Photoelectric element

Abstract

The invention discloses a photoelectric element, which comprises a semiconductor lamination layer comprising a first semiconductor layer, an active layer and a second semiconductor layer; a contact electrode on the second semiconductor layer; the insulation reflection structure covers the contact electrode and comprises a plurality of insulation reflection structure openings to expose the contact electrode; the metal reflecting structure covers the plurality of insulating reflecting structure openings and is electrically connected with the contact electrode; the insulation structure comprises one or more first insulation structure openings which expose the first semiconductor layer and one or more second insulation structure openings which expose the metal reflection structure; the first extension electrode covers the semiconductor lamination layer and the one or more first insulation structure openings so as to be electrically connected with the first semiconductor layer; and the second extension electrode covers the semiconductor lamination layer and the one or more second insulation structure openings so as to be electrically connected with the metal reflection structure, and from the top view of the photoelectric element, the one or more second insulation structure openings are respectively positioned at any position in a polygon formed by the plurality of insulation reflection structure openings.

Description

Technical Field

[0001] The present invention relates to an optoelectronic device, and more particularly to a flip-chip optoelectronic device including a metal reflection structure and an insulating reflection structure. Background Art

[0002] A light-emitting diode (LED) is a solid-state semiconductor optoelectronic device, which has the advantages of low power consumption, low heat generation, long working life, shock resistance, small size, fast response speed, and good optoelectronic characteristics, such as a stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, device indicators, and optoelectronic products, etc. Summary of the Invention

[0003] An optoelectronic device includes a semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer; a contact electrode located on the second semiconductor layer; an insulating reflection structure covering the contact electrode and including a plurality of insulating reflection structure openings exposing the contact electrode; a metal reflection structure covering the plurality of insulating reflection structure openings and electrically connecting to the contact electrode; an insulating structure including one or more first insulating structure openings exposing the first semiconductor layer and one or more second insulating structure openings exposing the metal reflection structure; a first extension electrode covering the semiconductor stack and the one or more first insulating structure openings to electrically connect to the first semiconductor layer; and a second extension electrode covering the semiconductor stack and the one or more second insulating structure openings to electrically connect to the metal reflection structure, wherein, when viewed from a top view of the optoelectronic device, the one or more second insulating structure openings are respectively located at any position within a polygon formed by the plurality of insulating reflection structure openings. Brief Description of the Drawings

[0004] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that various feature components are not drawn to scale and are only used for illustration. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

[0005] Figure 1 A top view of an optoelectronic device 1 disclosed in an embodiment of the present invention;

[0006] Figure 2 A top view of an optoelectronic device 2 disclosed in an embodiment of the present invention;

[0007] Figure 3 A top view of an optoelectronic device 3 disclosed in an embodiment of the present invention;

[0008] Figure 4 A top view of an optoelectronic device 4 disclosed in an embodiment of the present invention;

[0009] Figure 5 The top view of an optoelectronic element 5 disclosed in an embodiment of the present invention;

[0010] Figure 6 The top view of an optoelectronic element 6 disclosed in an embodiment of the present invention;

[0011] Figure 7 The sectional view along the tangent line L1-L1' of Figure 1 , the tangent line L2-L2' of Figure 2 , the tangent line L3-L3' of Figure 3 , the tangent line L4-L4' of Figure 4 , the tangent line L5-L5' of Figure 5 or the tangent line L6-L6' of Figure 6 as disclosed in an embodiment of the present invention;

[0012] Figure 8 The sectional view along the tangent line X1-X1' of Figure 1 , the tangent line X2-X2' of Figure 2 , the tangent line X3-X3' of Figure 3 , the tangent line X4-X4' of Figure 4 , the tangent line X5-X5' of Figure 5 or the tangent line X6-X6' of Figure 6 as disclosed in an embodiment of the present invention;

[0013] Figure 9 The sectional view along the tangent line Y1-Y1' of Figure 1 , the tangent line Y2-Y2' of Figure 2 , the tangent line Y3-Y3' of Figure 3 , the tangent line Y4-Y4' of Figure 4 , the tangent line Y5-Y5' of Figure 5 or the tangent line Y6-Y6' of Figure 6 as disclosed in an embodiment of the present invention;

[0014] Figure 10 The top view of the opening distribution of the insulating reflection structure in the optoelectronic element disclosed in an embodiment of the present invention;

[0015] Figure 11 The top view of the opening distribution of the insulating reflection structure in the optoelectronic element disclosed in an embodiment of the present invention;

[0016] Figure 12 The current distribution diagram of the optoelectronic element disclosed in an embodiment of the present invention;

[0017] Figure 13 The top view of the opening distribution of the insulating reflection structure disclosed in a comparative example of the present invention;

[0018] Figure 14Current distribution diagram of the comparative example of the present invention;

[0019] Figure 15 Schematic diagram of the light-emitting device 7 according to an embodiment of the present invention;

[0020] Figure 16 Schematic diagram of the light-emitting device 8 according to an embodiment of the present invention;

[0021] Figure 17 Schematic diagram of the backlight module 9 according to an embodiment of the present invention;

[0022] Figure 18 Schematic diagram of the display 100 according to an embodiment of the present invention;

[0023] Figure 19 Schematic diagram of the light-emitting device 1000 according to an embodiment of the present invention;

[0024] Figure 20 Schematic diagram of the light-emitting device 10000 according to an embodiment of the present invention.

[0025] Symbol description

[0026] 1 - 6: Photoelectric element

[0027] 7: Light-emitting device

[0028] 8: Light-emitting device

[0029] 9: Backlight module

[0030] 100: Display

[0031] 1000: Light-emitting device

[0032] 10000: Light-emitting device

[0033] 10: Substrate

[0034] 10s: Upper surface

[0035] 10t: Light-emitting surface

[0036] 11: First side

[0037] 12: Second side

[0038] 13: Third side

[0039] 14: Fourth side

[0040] 20: Semiconductor stack

[0041] 20b: Upper surface of the first exposed area E1

[0042] 20b’: Upper surface of the second exposed area E2

[0043] 20t: Upper surface of semiconductor platform M

[0044] 21: First semiconductor layer

[0045] 21t: First surface of the first semiconductor layer

[0046] 21t’: Second surface of the first semiconductor layer

[0047] 22: Active layer

[0048] 23: Second semiconductor layer

[0049] 23t: Second upper surface

[0050] 200: Through hole

[0051] 201: First frame

[0052] 202: Liquid crystal display panel

[0053] 2000: Bracket

[0054] 2001: First group of through holes

[0055] 2002: Second group of through holes

[0056] 2003: Third group of through holes

[0057] 2004: Fourth group of through holes

[0058] 2005: Fifth group of through holes 30: Contact electrode

[0059] 310: Brightness enhancement film

[0060] 3000: Light emitting panel

[0061] 40: Insulating reflection structure

[0062] 40s: Side wall

[0063] 400: Insulating reflection structure opening

[0064] 41: Insulating reflector

[0065] 410: First insulating reflection structure opening

[0066] 420: Second insulating reflection structure opening

[0067] 42: Insulating layer

[0068] 4100: First LED chip

[0069] 4200: Second LED chip

[0070] 430: Optical module

[0071] 4300: Long columnar lamp post

[0072] 4400: Drive power circuit board

[0073] 50: Encapsulation substrate

[0074] 51: Connection layer

[0075] 52: Metal reflection layer

[0076] 53: Insulation part

[0077] 54: Reflection structure

[0078] 500: Light-emitting module assembly

[0079] 501: First gasket

[0080] 502: Second gasket

[0081] 5000: Vehicle-mounted lighting lamp

[0082] 5100: Main lighting lamp

[0083] 5200: Combined lighting lamp

[0084] 60: Insulation structure

[0085] 600: Light-emitting module

[0086] 601: First insulation structure opening

[0087] 601s: First side wall

[0088] 602: Second insulation structure opening

[0089] 604: Reflector

[0090] 606: Carrying part

[0091] 608: Light-emitting unit

[0092] 610: Wavelength conversion structure

[0093] 611: Lamp socket

[0094] 612: Lamp cover

[0095] 614: Heat sink

[0096] 616: Connection part

[0097] 618: Electrical connection component

[0098] 71: First extended electrode

[0099] 72: Second extended electrode

[0100] 700: Second frame

[0101] 80: Protection structure

[0102] 800: Protection tabletop

[0103] 801: First opening of the protection structure

[0104] 802: Second opening of the protection structure

[0105] 91: First electrode pad

[0106] 92: Second electrode pad

[0107] B1: First boundary

[0108] B2: Second boundary

[0109] CT1: First contact first area

[0110] CT1’: First contact second area

[0111] CT2: Second contact area

[0112] D: Distance

[0113] D1: First direction

[0114] D2: Second direction

[0115] d1: First minimum distance

[0116] d2: Second minimum distance

[0117] D min 、d min : Minimum distance

[0118] E1: First exposed area

[0119] E2: Second exposed area

[0120] L 12 : Side length

[0121] L 34 : Side length

[0122] M: Semiconductor platform

[0123] P1: First pitch

[0124] P1 min : First minimum pitch

[0125] P2: Second pitch

[0126] P2 min : Second minimum pitch

[0127] P3: The third spacing

[0128] P3 min : The third minimum spacing

[0129] P4: The fourth spacing

[0130] P4 min : The fourth minimum spacing

[0131] P5: The fifth spacing

[0132] P5 min : The fifth minimum spacing

[0133] Smax: The minimum distance

[0134] S1: The first inclined plane

[0135] S2: The second inclined plane Detailed implementation manners

[0136] The following disclosure provides many different embodiments for implementing different features of the present case. The following disclosure describes specific examples of each component and its arrangement manner to simplify the description. Of course, these specific examples are not used for limitation. For example, if an embodiment of the present invention describes that a first feature component is formed on or above a second feature component, it means that it may include an embodiment in which the above first feature component and the above second feature component are in direct contact, and it may also include an embodiment in which an additional feature component is formed between the above first feature component and the above second feature component, so that the above first feature component and the second feature component may not be in direct contact.

[0137] It should be understood that additional operation steps can be implemented before, between, or after the method, and in other embodiments of the method, some operation steps can be replaced or omitted.

[0138] In addition, spatial-related terms may be used herein, such as "below", "beneath", "lower", "above", "over", "higher", and similar terms. These spatial-related terms are used to facilitate the description of the relationship between one or more elements or feature components in the drawings. These spatial-related terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 45 degrees or other orientations), the spatial-related adjectives used therein will also be interpreted according to the turned orientation. Furthermore, when referring to a first material layer being on or above a second material layer, it includes the case where the first material layer is in direct contact with the second material layer, or there may be one or more other material layers intervening therebetween. In this case, the first material layer and the second material layer may not be in direct contact. In some embodiments of the present invention, terms related to joining and connecting, such as "connect", "interconnect", etc., unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures disposed therebetween. And these terms related to joining and connecting may also include the case where both structures are movable, or both structures are fixed.

[0139] In the specification, terms such as "about", "approximately", "substantially", "generally", "essentially", "the same", "similar" typically mean that a characteristic value is within a range of plus or minus 15%, or plus or minus 10%, or plus or minus 5%, or plus or minus 3%, or plus or minus 2%, or plus or minus 1%, or plus or minus 0.5% of a given value. The given quantity is an approximate quantity, that is, the meaning of "about", "approximately", "substantially", "generally", "essentially" may still be implied even without specific mention of "about", "approximately", "substantially", "generally", "essentially".

[0140] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe different elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the technology of the present invention, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0141] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention. To make the description of the present invention more detailed and complete, please refer to the following description of the embodiments and the accompanying drawings. However, the embodiments shown below are used to illustrate the optoelectronic elements of the present invention and do not limit the present invention to the following embodiments. In addition, the dimensions, materials, shapes, relative configurations, etc. of the constituent parts described in the embodiments of this specification are not limited without specific descriptions, and the scope of the present invention is not limited thereto, but is merely for illustration. Moreover, the sizes or positional relationships of the components shown in the drawings may be exaggerated for clarity. In the following description, for the sake of appropriate omission of detailed descriptions, the same or similar components are denoted by the same reference numerals and symbols.

[0142] Figure 1 is a top view of an optoelectronic element 1 disclosed in an embodiment of the present invention. Figures 2 - 6 is Figure 1 a top view of optoelectronic elements 2 to 6 disclosed in different variant embodiments of the optoelectronic element 1. Figure 7 is along Figure 1 tangent line L1 - L1', Figure 2 tangent line L2 - L2', Figure 3 tangent line L3 - L3', Figure 4 tangent line L4 - L4', Figure 5 tangent line L5 - L5' or Figure 6 a sectional view along tangent line L6 - L6' of Figure 8 is along Figure 1 tangent line X1 - X1', Figure 2 tangent line X2 - X2', Figure 3 tangent line X3 - X3', Figure 4 tangent line X4 - X4', Figure 5 tangent line X5 - X5' or Figure 6 a sectional view along tangent line X6 - X6' of Figure 9 is along Figure 1 tangent line Y1 - Y1', Figure 2 tangent line Y2 - Y2', Figure 3 tangent line Y3 - Y3', Figure 4 tangent line Y4 - Y4', Figure 5 tangent line Y5 - Y5' or Figure 6Cross-sectional view of the tangent line Y6 - Y6'. The optoelectronic elements 1 - 6 of the present invention may include electroluminescent light-emitting elements, such as light-emitting diodes, laser diodes, or photoelectric photovoltaic elements, such as solar cells, photodetectors.

[0143] Reference Figures 1 - 6 And Figure 7 , according to an embodiment, each of the optoelectronic elements 1 - 6 includes a substrate 10 having an upper surface 10s, a first semiconductor layer 21 located on the upper surface 10s of the substrate 10 and including a first inclined surface S1 in contact with the upper surface 10s of the substrate 10, and a semiconductor platform M located on the first semiconductor layer 21. The semiconductor platform M includes an active layer 22 and a second semiconductor layer 23, and a second inclined surface S2 in contact with the first surface 21t of the first semiconductor layer 21.

[0144] Reference Figure 8 And Figure 9 , each of the optoelectronic elements 1 - 6 includes a contact electrode 30 located on the second semiconductor layer 23. An insulating reflective structure 40 is located on the contact electrode 30 and includes a plurality of insulating reflective structure openings 400 located on the second semiconductor layer 23. A connection layer 51 covers the insulating reflective structure 40 and fills the plurality of insulating reflective structure openings 400 to contact the contact electrode 30 and / or the second semiconductor layer 23. A metal reflective structure 52 is located on the connection layer 51 and fills the plurality of insulating reflective structure openings 400.

[0145] Reference Figures 7 - 9 , each of the optoelectronic elements 1 - 6 includes an insulating structure 60 located above the semiconductor platform M, covering the connection layer 51, the metal reflective structure 52, and the insulating reflective structure 40, and including one or more first insulating structure openings 601 located on the first semiconductor layer 21 and one or more second insulating structure openings 602 located on the metal reflective structure 52.

[0146] Reference Figure 7, each of the optoelectronic elements 1-6 includes a first extended electrode 71 covering the semiconductor platform M and electrically connected to the first semiconductor layer 21 through the opening 601 of the first insulating structure. A second extended electrode 72 covers the semiconductor platform M and covers the opening 602 of the second insulating structure, and is electrically connected to the metal reflection structure 52 through the opening 602 of the second insulating structure. The metal reflection structure 52 is electrically connected to the contact electrode 30 and / or the second semiconductor layer 23 through the covering insulating reflection structure opening 400. A protection structure 80 covers the first extended electrode 71 and the second extended electrode 72, and includes a first opening 801 of the protection structure located on the first extended electrode 71 and a second opening 802 of the protection structure located on the second extended electrode 72. A first electrode pad 91 covers the first opening 801 of the protection structure and is electrically connected to the first semiconductor layer 21 through the first extended electrode 71. A second electrode pad 92 covers the second opening 802 of the protection structure and is electrically connected to the second semiconductor layer 23 through the second extended electrode 72.

[0147] The substrate 10 can be a growth substrate for epitaxially growing a semiconductor stack 20. In an embodiment, the semiconductor stack 20 includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23. The substrate 10 includes a gallium arsenide (GaAs) wafer for epitaxially growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) wafer, a gallium nitride (GaN) wafer, a silicon carbide (SiC) wafer, or an aluminum nitride (AlN) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).

[0148] In an embodiment of the present invention, the optoelectronic elements 1-6 may not have the substrate 10. For example, the substrate 10 can be a growth substrate for growing the semiconductor stack 20, and then, the substrate 10 can be separated from the semiconductor stack 20 by methods such as laser lift off or chemical lift off.

[0149] In an embodiment of the present invention, a semiconductor stack 20 with optoelectronic properties, such as a light-emitting stack, is formed on the substrate 10 by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), physical vapor deposition (PVD), or ion plating methods, where the physical vapor deposition method includes sputtering or evaporation methods.

[0150] By changing the physical and chemical composition of one or more layers in the semiconductor stack 20, the wavelength of the light emitted or absorbed by the optoelectronic device 1 is adjusted. In this case, taking the light-emitting device as an example, the semiconductor stack 20 includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23. The material of the semiconductor stack 20 includes group III-V semiconductor materials, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, where 0 ≤ x, y ≤ 1; (x + y) ≤ 1. When the material of the semiconductor stack 20 is an AlInGaP series material, red light with a wavelength between 610 nm and 650 nm can be emitted. When the material of the semiconductor stack 20 is an InGaN series material, blue light with a wavelength between 400 nm and 490 nm, or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the semiconductor stack 20 is an AlGaN series or AlInGaN series material, ultraviolet light with a wavelength between 250 nm and 400 nm can be emitted.

[0151] The first semiconductor layer 21 and the second semiconductor layer 23 can be a cladding layer or a confinement layer, and the two have different conduction types, electrical properties, polarities, or provide electrons or holes according to the doped elements. For example, the first semiconductor layer 21 is an n-type semiconductor, and the second semiconductor layer 23 is a p-type semiconductor. The active layer 22 is formed between the first semiconductor layer 21 and the second semiconductor layer 23. Electrons and holes recombine in the active layer 22 under the drive of a current, converting electrical energy into light energy to emit a light ray, or converting light energy into electrical energy to absorb a light ray. The active layer 22 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (MQW). The material of the active layer 22 can be a neutral, p-type, or n-type semiconductor. The first semiconductor layer 21, the active layer 22, or the second semiconductor layer 23 can be a single layer or a structure including multiple sub-layers.

[0152] In an embodiment of the present invention, the semiconductor stack 20 may further include a buffer layer (not shown in the figures) located between the first semiconductor layer 21 and the substrate 10, which is used to release the stress generated between the substrate 10 and the semiconductor stack 20 due to the lattice mismatch of materials, so as to reduce dislocations and lattice defects, and further improve the epitaxial quality. The buffer layer can be a single layer or a structure including multiple sub-layers. In one embodiment, PVD aluminum nitride (AlN) can be selected as the buffer layer, which is formed between the semiconductor stack 20 and the substrate 10 to improve the epitaxial quality of the semiconductor stack 20. In one embodiment, the target for forming PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum can be used, and aluminum nitride is reactively formed with the aluminum target in an environment of a nitrogen source.

[0153] As Figures 7 - 9 shown, the semiconductor stack 20 includes a first exposed area E1, a second exposed area E2, and a semiconductor platform M surrounded by the first exposed area E1. In one embodiment, a part of the second semiconductor layer 23, the active layer 22, and the first semiconductor layer 21 can be removed by etching to form the first exposed area E1 and the second exposed area E2. In other words, the first exposed area E1 exposes the first surface 21t of the first semiconductor layer 21, and the second exposed area E2 exposes the second surface 21t' of the first semiconductor layer 21. In a top view of the optoelectronic device 1, as Figure 1 shown, the first exposed area E1 is located on at least one side of the semiconductor platform M, and the second exposed area E2 is located inside the semiconductor platform M and is surrounded by the semiconductor platform M. In Figure 7 , the label "B1" represents the first boundary B1 between the first exposed area E1 and the semiconductor platform M. In Figure 8 and Figure 9 , the label "B2" represents the second boundary B2 between the second exposed area E2 and the semiconductor platform M. The upper surface 20t (the second upper surface 23t of the second semiconductor layer 23) of the semiconductor platform M can be higher than the upper surface 20b (the first surface 21t of the first semiconductor layer 21) of the first exposed area E1 and the upper surface 20b' (the second surface 21t' of the first semiconductor layer 21) of the second exposed area E2. In one embodiment, the semiconductor platform M can be tapered towards its top. Therefore, the side surface of the semiconductor platform M can be an inclined surface, such as Figure 2 , Figure 8 and Figure 9 illustrated second inclined surface S2.

[0154] In one embodiment, as Figure 7 shown, a part of the upper surface 20b of the first exposed area E1 can be a first contact first area CT1. As Figure 8 and Figure 9As shown, a part of the upper surface 20b' of the second exposure region E2 can be a first contact second region CT1'. In one embodiment, at least a part of the upper surface 20t of the semiconductor platform M is defined as a second contact region CT2. The insulating structure 60 includes a plurality of first insulating structure openings 601 to expose the first contact first region CT1 and the first contact second region CT1'. The insulating reflective structure 40 includes a plurality of insulating reflective structure openings 400 located on the second contact region CT2 and exposing the contact electrode 30 and / or the second semiconductor layer 23. In one embodiment, a ratio (A1 / A2) between a first total area A1 included in the plurality of first contact second regions CT1' and a second total area A2 included in the plurality of first contact first regions CT1 is between 1 and 2 to improve the current distribution of the optoelectronic elements 1-6. If the ratio (A1 / A2) is less than 1, the brightness of the optoelectronic elements 1-6 will decrease; if the ratio (A1 / A2) is greater than 2, the voltage (Vf) of the optoelectronic elements 1-6 will increase.

[0155] As Figure 1 shown, the substrate 10 includes a first side 11, a second side 12, a third side 13, and a fourth side 14. The semiconductor platform M can be spaced apart from the first side 11 to the fourth side 14, and the first exposure region E1 can be distributively arranged between any one or more of the semiconductor platform M and the first side 11 to the fourth side 14. For example, the first exposure region E1 can be arranged between the semiconductor platform M and the first side 11 and between the semiconductor platform M and the second side 12, or between the semiconductor platform M and the third side 13 and between the semiconductor platform M and the fourth side 14. The first side 11 and the second side 12 can be opposite to each other or parallel to each other, and the third side 13 and the fourth side 14 can be opposite to each other or parallel to each other. In one embodiment, a plurality of second exposure regions E2 having a long strip shape, a rectangular shape, a circular shape, or an elliptical shape and spaced apart from each other can be arranged inside the semiconductor platform M.

[0156] Referring Figures 1 - 6 , each of the optoelectronic elements 1-6 includes a plurality of through holes 200 formed through the second semiconductor layer 23 and the active layer 22 in the second exposure region E2 to expose the second surface 21t' of the first semiconductor layer 21. The number of the through holes 200 includes a plurality, and the shapes include but are not limited to polygons such as circular, rectangular, or hexagonal, and can be distributed at a uniform or non-uniform pitch. In this embodiment, the shape of the through hole 200 is circular. After passing current through the optoelectronic elements 1-6, the external current is electrically connected to the first semiconductor layer 21 in the through hole 200 through the first extension electrode 71. The plurality of uniformly distributed through holes 200 can improve the current expansion ability and the uniformity of the current distribution, and at the same time increase the contact area between the first extension electrode 71 and the first semiconductor layer 21, thereby being able to reduce the voltage and improve the light emitting efficiency of the optoelectronic elements 1-6.

[0157] The number and distribution pattern of the through holes 200 can be designed according to the size of the optoelectronic element. The larger the size of the optoelectronic element, the greater the number of through holes 200 required accordingly.

[0158] As Figure 1 shown, the distribution directions of the multiple through holes 200 include a first direction D1 extending from the first side 11 of the substrate 10 to the second side 12 and a second direction D2 extending from the third side 13 of the substrate 10 to the fourth side 14. The multiple through holes 200 include a first group of through holes 2001 and a second group of through holes 2002. The first group of through holes 2001 and the second group of through holes 2002 are sequentially arranged in the first direction D1 extending from the first side 11 of the substrate 10 to the second side 12. The number of the first group of through holes 2001 or the second group of through holes 2002 can be one or more. In the first direction D1, a first pitch P1 between any one of the first group of through holes 2001 and the first side 11 is less than a second pitch P2 between any one of the second group of through holes 2002 and the first side 11 and / or the second side 12. The ratio P1 / L of the first pitch P1 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 1 34 is between 0.1 and 0.5. The ratio P2 / L of the second pitch P2 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 1 34 is between 0.3 and 0.7. In one embodiment, in the second direction D2, a minimum pitch among the pitches between any one of the first group of through holes 2001 and the third side 13 and the fourth side 14 is defined as a first minimum pitch P1 34 and the ratio P1 34 / L of the first minimum pitch P1 to the side length L of the first side 11 or the second side 12 min is between 0.3 and 0.7. A minimum pitch among the pitches between any one of the second group of through holes 2002 and the third side 13 and the fourth side 14 is defined as a second minimum pitch P2 min and the ratio P2 12 / L of the second minimum pitch P2 to the side length L of the first side 11 or the second side 12 min is between 0.1 and 0.5. In another embodiment, the first minimum pitch P1 12 is greater than the second minimum pitch P2 min . min . 12 . min . 12 . min . min .

[0159] As Figure 2As shown, a plurality of vias 200 include a first group of vias 2001, a second group of vias 2002, and a third group of vias 2003. The first group of vias 2001, the second group of vias 2002, and the third group of vias 2003 are sequentially arranged in a first direction D1 extending from a first side 11 of the substrate 10 to a second side 12. The number of vias in the first group 2001, the second group 2002, or the third group 2003 can be one or more. In the first direction D1, a first pitch P1 between any one of the vias in the first group 2001 and the first side 11 is less than a second pitch P2 between any one of the vias in the second group 2002 and the first side 11 or the second side 12, and / or less than a third pitch P3 between any one of the vias in the third group 2003 and the second side 12. The ratio P1 / L of the first pitch P1 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 2 34 is between 0.1 and 0.5. The ratio P2 / L of the second pitch P2 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 2 34 is between 0.3 and 0.7. The ratio P3 / L of the third pitch P3 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 2 34 is between 0.1 and 0.5. In one embodiment, in a second direction D2, there is a first minimum pitch P1 between one of the vias in the first group 2001 and the third side 13 or the fourth side 14 34 , and the ratio P1 34 / L of the first minimum pitch P1 to the side length L of the first side 11 or the second side 12 34 is between 0.3 and 0.7. There is a second minimum pitch P2 between any one of the vias in the second group 2002 and the third side 13 or the fourth side 14 min , and the ratio P2 min / L of the second minimum pitch P2 to the side length L of the first side 11 or the second side 12 12 is between 0.1 and 0.5. There is a third minimum pitch P3 between one of the vias in the third group 2003 and the third side 13 or the fourth side 14 min / L 12 , and the ratio P3 min / L of the third minimum pitch P3 to the side length L of the first side 11 or the second side 12 min is between 0.3 and 0.7. In another embodiment, the first minimum pitch P1 12 and the third minimum pitch P3 min / L 12 is between 0.1 and 0.5. In another embodiment, the first minimum pitch P1 min and the third minimum pitch P3 min are such that the ratio of the first minimum pitch P1 to the third minimum pitch P3 12 is between 0.1 and 0.5. In another embodiment, the first minimum pitch P1 min / L 12 is between 0.3 and 0.7. In another embodiment, the first minimum pitch P1 min and the third minimum pitch P3 minIncluding the same or different distances, the first minimum spacing P1 min and / or the third minimum spacing P3 min is greater than the second minimum spacing P2 min .

[0160] As Figure 3 shown, a plurality of through-holes 200 include a first group of through-holes 2001 and a third group of through-holes 2003. The first group of through-holes 2001 and the third group of through-holes 2003 are sequentially arranged in a first direction D1 extending from a first side 11 of the substrate 10 to a second side 12. The number of the first group of through-holes 2001 or the third group of through-holes 2003 can be one or more. In the first direction D1, a first spacing P1 between any one of the first group of through-holes 2001 and the first side 11 is less than a third spacing P3 between any one of the third group of through-holes 2003 and the second side 12. The ratio P1 / L of the first spacing P1 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 3 34 is between 0.1 and 0.5. The ratio P3 / L of the third spacing P3 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 3 34 is between 0.1 and 0.5. In one embodiment, in a second direction D2, a first minimum spacing P1 exists between one of the first group of through-holes 2001 and the third side 13 or the fourth side 14 34 , and the first minimum spacing P1 34 and the ratio P1 min / L of the side length L of the first side 11 or the second side 12 min is between 0.1 and 0.5. A third minimum spacing P3 exists between one of the third group of through-holes 2003 and the third side 13 or the fourth side 14 12 , and the third minimum spacing P3 min and the ratio P3 12 / L of the side length L of the first side 11 or the second side 12 min is between 0.1 and 0.5. In another embodiment, the first minimum spacing P1 min and the third minimum spacing P3 12 include the same or different distances. For example, the first minimum spacing P1 min can be greater than the third minimum spacing P3 12 . min min min min .

[0161] As Figure 4 ​​​As shown, a plurality of through-holes 200 include a first group of through-holes 2001 and a third group of through-holes 2003. The first group of through-holes 2001 and the third group of through-holes 2003 are sequentially arranged in a first direction D1 extending from a first side 11 of the substrate 10 to a second side 12. The number of the first group of through-holes 2001 or the third group of through-holes 2003 can be one or more. In the first direction D1, a first pitch P1 between any one of the first group of through-holes 2001 and the first side 11 is less than a third pitch P3 between any one of the third group of through-holes 2003 and the second side 12. The ratio P1 / L of the first pitch P1 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 4 34 is between 0.1 and 0.5. The ratio P3 / L of the third pitch P3 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 4 34 is between 0.1 and 0.5. In one embodiment, in a second direction D2, a first minimum pitch P1 exists between one of the first group of through-holes 2001 and the third side 13 or the fourth side 14 34 , and the ratio P1 / L of the first minimum pitch P1 to the side length L12 of the first side 11 or the second side 12 34 is between 0.1 and 0.5. A third minimum pitch P3 exists between one of the third group of through-holes 2003 and the third side 13 or the fourth side 14 min , and the ratio P3 / L of the third minimum pitch P3 to the side length L12 of the first side 11 or the second side 12 min is between 0.1 and 0.5. In another embodiment, the first minimum pitch P1 min / L 12 and the third minimum pitch P3 min include the same or different distances. In this embodiment, the pitch between two through-holes 200 in the first group of through-holes 2001 is greater than the pitch between two through-holes 200 in the third group of through-holes 2003, and the first minimum pitch P1 min is less than the third minimum pitch P3 min / L 12 . min min min min min min min .

[0162] Such as Figure 5As shown, a plurality of through holes 200 include a first group of through holes 2001, a second group of through holes 2002, and a third group of through holes 2003. The first group of through holes 2001, the second group of through holes 2002, and the third group of through holes 2003 are sequentially arranged in a first direction D1 extending from a first side 11 of the substrate 10 to a second side 12. The number of the first group of through holes 2001, the second group of through holes 2002, or the third group of through holes 2003 can be one or more. In the first direction D1, a first pitch P1 between any one of the first group of through holes 2001 and the first side 11 is less than a second pitch P2 between any one of the second group of through holes 2002 and the first side 11, and / or less than a third pitch P3 between any one of the third group of through holes 2003 and the second side 12. The ratio P1 / L of the first pitch P1 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 5 34 is between 0.1 and 0.5. The ratio P2 / L of the second pitch P2 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 5 34 is between 0.3 and 0.7. The ratio P3 / L of the third pitch P3 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 5 34 is between 0.1 and 0.5. In one embodiment, in a second direction D2, there is a first minimum pitch P1 between one of the first group of through holes 2001 and the third side 13 or the fourth side 14 34 and the ratio P1 34 / L of the first minimum pitch P1 to the side length L12 of the first side 11 or the second side 12 34 is between 0.1 and 0.5. There is a second minimum pitch P2 between any one of the second group of through holes 2002 and the third side 13 or the fourth side 14 min and the ratio P2 min / L of the second minimum pitch P2 to the side length L12 of the first side 11 or the second side 12 min is between 0.1 and 0.5. There is a third minimum pitch P3 between one of the third group of through holes 2003 and the third side 13 or the fourth side 14 12 and the ratio P3 min / L of the third minimum pitch P3 to the side length L12 of the first side 11 or the second side 12 min is between 0.1 and 0.5. In another embodiment, the first minimum pitch P1 min the second minimum pitch P2 12 and the third minimum pitch P3 min include the same distance. min min 12 / L 12 such as min min min

[0163]

[0163]

[0163] AsFigure 6 As shown, a plurality of through holes 200 include a first group of through holes 2001, a second group of through holes 2002, and a third group of through holes 2003. The number of the first group of through holes 2001, the second group of through holes 2002, or the third group of through holes 2003 can be one or more. In the first direction D1, a first distance P1 between any one of the first group of through holes 2001 and the first side 11 is less than a second distance P2 between any one of the second group of through holes 2002 and the first side 11, and / or less than a third distance P3 between any one of the third group of through holes 2003 and the second side 12. The ratio P1 / L of the first distance P1 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 6 34 is between 0.1 and 0.5. The ratio P2 / L of the second distance P2 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 6 34 is between 0.3 and 0.7. The ratio P3 / L of the third distance P3 to the side length L of the third side 13 or the fourth side 14 of the optoelectronic element 6 34 is between 0.1 and 0.5. In one embodiment, in the second direction D2, there is a first minimum distance P1 between one of the first group of through holes 2001 and the third side 13 or the fourth side 14 34 , and the ratio P1 34 / L of the first minimum distance P1 to the side length L12 of the first side 11 or the second side 12 34 is between 0.1 and 0.5. There is a second minimum distance P2 between any one of the second group of through holes 2002 and the third side 13 or the fourth side 14 min , and the ratio P2 min / L of the second minimum distance P2 to the side length L12 of the first side 11 or the second side 12 min is between 0.3 and 0.7. There is a third minimum distance P3 between one of the third group of through holes 2003 and the third side 13 or the fourth side 14 12 , and the ratio P3 min / L of the third minimum distance P3 to the side length L12 of the first side 11 or the second side 12 min is between 0.1 and 0.5. In another embodiment, the first minimum distance P1 min and the third minimum distance P3 12 include the same distance, the first minimum distance P1 min and / or the third minimum distance P3 min is greater than the second minimum distance P2 min / L 12 In another embodiment, the first minimum distance P1 min and the third minimum distance P3 min include the same distance, the first minimum distance P1 min and / or the third minimum distance P3 min is greater than the second minimum distance P2 minIn the present embodiment, the plurality of through holes 200 further include a fourth group of through holes 2004 and a fifth group of through holes 2005, and the number of the fourth group of through holes 2004 and the fifth group of through holes 2005 may be one or more. The first group of through holes 2001, the fourth group of through holes 2004, the second group of through holes 2002, the fifth group of through holes 2005, and the third group of through holes 2003 are sequentially arranged in a first direction D1 extending from the first side 11 to the second side 12 of the substrate 10. In the first direction D1, a first spacing P1 between any one of the first group of through holes 2001 and the first side 11 is smaller than a fourth spacing P4 between any one of the fourth group of through holes 2004 and the first side 11. A third spacing P3 between any one of the third group of through holes 2003 and the second side 12 is smaller than a fifth spacing P5 between any one of the fifth group of through holes 2005 and the second side 12. The fourth pitch P4, the fifth pitch P5 and the side length L of the third side 13 or the fourth side 14 of the photoelectric element 6 34 The ratio P4 / L 34 or P5 / L 34 In one embodiment, in the second direction D2, a fourth minimum spacing P4 is provided between one of the fourth group of through holes 2004 and the fifth group of through holes 2005 and the third side 13 or the fourth side 14. min The fifth minimum spacing P5 min , and the fourth minimum spacing P4 min The fifth minimum spacing P5 min The length L of the first side 11 or the second side 12 12 The ratio P4 min / L 12 With P5 min / L 12 In another embodiment, the fourth minimum spacing P4 min The fifth minimum spacing P5 min Contains the same distance.

[0164] The first pitch P1, the second pitch P2, the third pitch P3, the fourth pitch P4, the fifth pitch P5, the first minimum pitch P1 min , the second minimum spacing P2 min , the third minimum spacing P3 min , the fourth minimum spacing P4 min The fifth minimum spacing P5 min The measurement method can be as follows: (1) select the center of the through hole 200 for measurement; (2) select the outermost position of the through hole 200 for measurement. The measurement method is not limited to this, as long as the measurement can be performed at a consistent position of the through hole 200.

[0165] like Figures 7 - 9As shown, the contact electrode 30 can be directly disposed on the second semiconductor layer 23. The region where the contact electrode 30 contacts the second semiconductor layer 23 forms a second contact region CT2 and is electrically connected to the second semiconductor layer 23. The contact electrode 30 is used to disperse the current injected from the outside and then inject it into the second semiconductor layer 23 via the upper surface 20t of the semiconductor platform M (the second upper surface 23t of the second semiconductor layer 23).

[0166] In one embodiment, the insulating reflection structure 40 includes a plurality of insulating reflection structure openings 400 disposed on the semiconductor platform M. As Figures 1 - 6 shown, in a top view of the optoelectronic elements 1-6, the insulating reflection structure openings 400 include circles, semi-circles, ellipses, triangles, rectangles, polygons, arcs, or rings. The plurality of insulating reflection structure openings 400 can be arranged in a hexagonal closest-packed lattice pattern on the semiconductor platform M, but are not limited thereto. In another embodiment, the plurality of insulating reflection structure openings 400 can be arranged in various patterns. For example, a rectangular lattice pattern. As Figure 7 shown, the insulating reflection structure 40 is located above the contact electrode 30 and covers the second inclined surface S2 of the semiconductor platform M, and covers a part of the first semiconductor layer 21 and a part of the second semiconductor layer 23. For example, the insulating reflection structure 40 can cover a part of the first surface 21t of the first semiconductor layer 21 and a part of the second upper surface 23t of the second semiconductor layer 23.

[0167] In one embodiment of the invention, as Figures 7 - 9 shown, the insulating reflection structure 40 includes an insulating reflector 41 and / or an insulating layer 42. The insulating reflection structure opening 400 includes a first insulating reflection structure opening 410 passing through the insulating reflector 41. As Figure 8 and Figure 9 shown, the insulating reflector 41 of the insulating reflection structure 40 covers the second inclined surface S2 of the semiconductor platform M to reflect a light ray from the active layer 22 and increase the light extraction efficiency of the optoelectronic elements 1-6.

[0168] In one embodiment of the invention, as Figure 8 and Figure 9 shown, the insulating layer 42 of the insulating reflection structure 40 is located between the contact electrode 30 and the insulating reflector 41. The insulating reflection structure opening 400 includes a second insulating reflection structure opening 420 passing through the insulating layer 42. As Figures 1 - 6 shown, in a top view of the optoelectronic elements 1-6, the first insulating reflection structure opening 410 and the second insulating reflection structure opening 420 form a concentric circle pattern.

[0169] As Figure 8 and Figure 9As shown, the connection layer 51 covers the insulating reflective structure 40 and fills the first insulating reflective structure opening 410 and the second insulating reflective structure opening 420 to contact the contact electrode 30, where the connection layer 51 contains titanium (Ti), titanium oxide (TiO x ), titanium nitride (TiN x ), aluminum oxide (Al2O3), indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), indium zinc oxide (ZIO), indium gallium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) Mg x O, 0 ≤ x ≤ 1). The contact electrode 30 contains indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), indium zinc oxide (ZIO), indium gallium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) Mg x O, 0 ≤ x ≤ 1). In an embodiment of the invention, the connection layer 51 has a thickness less than that of the contact electrode 30. For example, the connection layer 51 has a thickness between 10 angstroms (Å) and 60 angstroms, and the contact electrode 30 has a thickness between 100 angstroms and 400 angstroms. In an embodiment of the invention, the contact electrode 30 and the connection layer 51 contain the same material. For example, the contact electrode 30 and the connection layer 51 contain indium tin oxide (ITO). In an embodiment of the invention, the contact electrode 30 and the connection layer 51 contain different materials. For example, the contact electrode 30 contains indium tin oxide (ITO), and the connection layer 51 contains titanium (Ti).

[0170] The metal reflective structure 52 is filled into the insulating reflective structure opening 400 of the insulating reflective structure 40 through the connection layer 51, where the connection layer 51 can improve the adhesion between the insulating reflective structure 40 and the metal reflective structure 52. In a side view of the optoelectronic elements 1 to 6, in an embodiment, the metal reflective structure 52 can be disposed on the connection layer 51 and conformal with the connection layer 51. For example, the metal reflective structure 52 and the connection layer 51 can completely overlap or partially overlap each other.

[0171] In an embodiment, the metal reflective structure 52 contains silver (Ag), chromium (Cr), nickel (Ni), titanium (Ti), aluminum (Al), rhodium (Rh), ruthenium (Ru), or a combination of the foregoing materials.

[0172] In an embodiment, each of the optoelectronic elements 1 to 6 includes a barrier layer (not shown in the figure) disposed on the metal reflective structure 52. The barrier layer has a multilayer structure. For example, a multilayer structure of alternately stacked Ti and Ni.

[0173] The insulating reflective structure 40, the connecting layer 51, and the metal reflective structure 52 can be configured as an Omni-Directional reflector (ODR). The omnidirectional reflector can increase the reflectivity of the light emitted from the active layer 22, thereby improving the light extraction efficiency of the optoelectronic elements 1-6.

[0174] In one embodiment, the insulating layer 42 of the insulating reflective structure 40 is used as an insulating film and has a single-layer structure, including oxides or nitrides, such as at least one oxide or nitride selected from the group consisting of metals such as silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), aluminum (Al), etc. In another embodiment, the insulating layer 42 can also have a multi-layer structure, such as a stack composed of any two or more of the above oxides or nitrides, such as a multi-layer structure composed of SiO2, TiO2, and Al2O3.

[0175] In one embodiment, the insulating mirror 41 can be formed of a material having a refractive index lower than that of the second semiconductor layer 23. The material of the insulating mirror 41 includes SiO2, SiN, SiO x N y , TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO, TaO2, Nb2O5, or MgF2. In one embodiment, the insulating mirror 41 has a multi-layer film structure in which insulating layers with different refractive indices are alternately stacked, such as a distributed Bragg reflector (DBR). The distributed Bragg reflector structure is formed by alternately stacking a plurality of first sub-layers having a first refractive index and a plurality of second sub-layers having a second refractive index, and the first refractive index is less than the second refractive index. For example, it can be stacked by SiO2 / TiO2 or SiO2 / Nb2O5, etc.

[0176] In one embodiment of the invention, when the insulating mirror 41 includes a distributed Bragg reflector structure with a stack of SiO2 / TiO2 or SiO2 / Nb2O5, the insulating layer 42 has a thickness greater than the thickness of each sub-layer included in the insulating mirror 41, but the thickness of the insulating layer 42 is less than the total thickness of each sub-layer included in the insulating mirror 41. In one embodiment of the invention, the thickness of the insulating layer 42 is between 3000 angstroms and 7000 angstroms.

[0177] At least one oxide or nitride selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), and aluminum (Al) can be used for the bottommost layer or the topmost layer of the insulating mirror 41. In one embodiment, the bottommost layer and / or the topmost layer of the insulating mirror 41 includes a material different from that of the intermediate layer therebetween and / or a thickness different from that of the intermediate layer and / or a formation process different from that of the intermediate layer.

[0178] In one embodiment, the insulating layer 42 may include the same material as the plurality of first sub-layers of the insulating mirror 41. For example, when the insulating mirror 41 is formed of a distributed Bragg reflector including SiO2 / TiO2 or SiO2 / Nb2O5, the insulating layer 42 may be formed of SiO2. Although the insulating layer 42 is formed of the same material as at least a part of the insulating mirror 41, it is not required to have a high film quality such as that of an insulating film like DBR. Therefore, the insulating mirror 41 and the insulating layer 42 can be formed by different processes. The interface of the insulating layer 42 with respect to the insulating mirror 41 can be visually distinguished (e.g., SEM photograph or TEM photograph). In one embodiment, the total thickness of the plurality of first sub-layers included in the insulating mirror 41 is less than the total thickness of the insulating layer 42.

[0179] In various embodiments of the present invention, in the plurality of insulating reflection structure openings 400, there is a minimum distance d between any two adjacent openings respectively. min For Figure 10 and Figure 11 taking the embodiment of the present invention as an example, a top view showing the distribution of the insulating reflection structure openings 400 in the optoelectronic elements 6a to 6b is disclosed. Similar Figures 1 to 6 to the embodiment, Figure 10 and Figure 11 the optoelectronic elements 6a to 6b disclosed also have a structure similar to that included in the optoelectronic elements 1 to 6. For the sake of convenience of explanation, Figure 10 and Figure 11 the first extension electrode 71, the second extension electrode 72, the second insulating structure 80, the first electrode pad 91, and the second electrode pad 92 are omitted, and only the substrate 10, the semiconductor stack 20, the through hole 200, the plurality of insulating reflection structure openings 400, the first insulating structure opening 601, and the second insulating structure opening 602 are disclosed. Figure 10 The sectional view of the tangent line L10 - L10' of Figure 11 and the tangent line L11 - L11' of Figure 7 can be referred to Figure 7 . The plurality of insulating reflection structure openings 400 includes a first group of openings 4001 on one side of the optoelectronic element and a second group of openings 4002 on the other side of the optoelectronic element to improve the uniformity of current diffusion in the optoelectronic element, wherein the minimum distance d between adjacent insulating reflection structure openings in the first group of openings 4001 and the second group of openings 4002min They are not equal. Specifically, a first minimum distance d1 is included between any two adjacent openings of the first group of openings 4001, which is greater than a second minimum distance d2 included between any two adjacent openings of the second group of openings 4004. In one embodiment, the first group of openings 4001 of the plurality of insulating reflective structure openings 400 is located below a first electrode pad 91 (not shown in the figure), and the second group of openings 4002 of the plurality of insulating reflective structure openings 400 is located below a second electrode pad 92 (not shown in the figure). In one embodiment, in the first group of openings 4001, the first minimum distances d1 between any two adjacent openings may be equal to or different from each other. In the second group of openings 4004, the second minimum distances d2 between any two adjacent openings may be equal to or different from each other. In a cross-sectional view (not shown in the figure) or a top view of the optoelectronic element, the first minimum distance d1 and the second minimum distance d2 can be measured in the following ways: (1) Select the centers of the insulating reflective structure openings 400 for measurement; (2) Select the outermost positions of the insulating reflective structure openings 400 for measurement. The measurement method is not limited to this, as long as it can be measured at a consistent position.

[0180] To improve the uniformity of current diffusion of the optoelectronic element, in one embodiment, as Figure 11 shown, a plurality of insulating reflective structure openings 400 are arranged in a ring along a second boundary B2 between a second exposed area E2 and a semiconductor platform M. The plurality of insulating reflective structure openings 400 are spaced apart from each other by a minimum distance D min around a via hole 200, and the plurality of insulating reflective structure openings 400 surrounding the via hole 200 are spaced apart from each other by a minimum distance d min and the minimum distance D between the insulating reflective structure opening 400 and the via hole 200 min is greater than the minimum distance d between the plurality of insulating reflective structure openings 400 min .

[0181] In one embodiment (not shown in the figure), Figure 10 the first minimum distance d1 included between the exemplified first group of openings 4001 and the second minimum distance d2 included between the second group of openings 4002 can be applied to Figure 11 the optoelectronic element in which the minimum distance D between the insulating reflective structure opening 400 and the via hole 200 min can be greater than the first minimum distance d1 included between the first group of openings 4001 and / or greater than the second minimum distance d2 included between the second group of openings 4002.

[0182] In one embodiment, Figure 10 and Figure 11 shown, the plurality of insulating reflective structure openings 400 can surround the second boundary B2 of the second exposed area E2 at equal intervals or non-equal intervals.

[0183] Figure 13 is a top view of the distribution of the openings 400 of the reflection structure disclosed in a comparative example of the present invention. As Figure 13 shown, the second insulating structure opening 602 includes an irregular shape or a rectangle, and includes a top view area, a width or a length greater than a top view area, a width or a length of the insulating reflection structure opening 400. In order to accommodate the second insulating structure opening 602 and prevent the second insulating structure opening 602 from overlapping with the insulating reflection structure opening 400, the insulating reflection structure openings 400 in a partial area close to the second insulating structure opening 602 can be arranged in an irregular pattern, and the insulating reflection structure openings 400 in other areas are arranged in a grid pattern of hexagons.

[0184] Figure 12 is a current distribution diagram of the optoelectronic elements 1-6 or 6a-6b disclosed in an embodiment of the present invention. Figure 14 is a current distribution diagram of a comparative example of the present invention. Figure 12 The dark area ratio in Figure 14 is less than the dark area in. Compared with the comparative example, the optoelectronic elements 1-6 or 6a-6b obtain a more uniform current distribution by disposing the second insulating structure opening at any position within the polygon formed by a plurality of insulating reflection structure openings.

[0185] As Figure 8 and Figure 9 shown, the insulating structure 60 can expose a side wall 40s of the insulating reflection structure 40. In another embodiment (not shown in the figure), the insulating structure 60 can cover the side wall 40s of the insulating reflection structure 40. In another embodiment, a minimum distance Smax between a first side wall 601s included in the first insulating structure opening 601 and the second inclined surface S2 of the semiconductor platform M is greater than 10 micrometers to ensure that the insulating structure 60 includes a thickness to cover the insulating reflection structure 40, and to avoid damaging the insulating reflection structure 40 when etching to remove the insulating structure 60 to form the first insulating structure opening 601 and reducing the reflectivity of the insulating reflection structure 40. The first extension electrode 71 is connected to the first semiconductor layer 21 exposed in the first exposure area E1 and the second exposure area E2 through the first insulating structure opening 601.

[0186] As Figures 7 - 9As shown, the insulating structure 60 continuously covers all the exposed surfaces of the metal reflective structure 52 and the connection layer 51 to protect the metal reflective structure 52, such as the upper surface and the side surfaces of the metal reflective structure 52 and the connection layer 51. The metal reflective structure 52 and the connection layer 51 can be encapsulated between the insulating structure 60 and the insulating reflective structure 40. In an embodiment of the invention, by forming the insulating structure 60, the reflectivity of the metal reflective structure 52 can be prevented from deteriorating due to subsequent manufacturing processes, and the migration of the metal elements contained in the metal reflective structure 52 can be suppressed.

[0187] In an embodiment of the invention, in order to increase the light extraction efficiency of the optoelectronic elements 1 to 6, the insulating structure 60 includes a first distributed Bragg reflector (DBR) structure formed by alternately stacking a plurality of non-metal oxide layers and a plurality of metal oxide layers. The material of the non-metal oxide layer includes SiO2, SiN, SiO x N y , Si3N4. The material of the metal oxide layer includes TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO, TaO2, Nb2O5, or MgF2. For example, it can be laminated by SiO2 / TiO2 or SiO2 / Nb2O5, etc. In order to improve the adhesion between the insulating structure 60, the first extended electrode 71, and the metal reflective structure 52, the metal reflective structure 52 can be in contact with the non-metal oxide layer of the insulating structure 60, such as SiO2, through a metal other than silver (Ag), such as platinum (Pt), and the insulating structure 60 is in contact with the first extended electrode 71 through the metal oxide layer, such as TiO2 or Nb2O5.

[0188] In an embodiment, as Figures 1 - 6 shown, the second insulating structure opening 602 and the plurality of insulating reflective structure openings 400 are arranged in a staggered manner, that is, the second insulating structure opening 602 does not overlap with the plurality of insulating reflective structure openings 400. In order to maintain the pattern of the plurality of insulating reflective structure openings 400 arranged at equal intervals, when viewed from a top view of the optoelectronic element, one or more second insulating structure openings 602 are respectively located at any position within the polygon formed by the arrangement of the plurality of insulating reflective structure openings 400. In an embodiment, the polygon arrangement formed by the plurality of insulating reflective structure openings 400 includes a triangular, rectangular, pentagonal, or hexagonal arrangement. In an embodiment, a rectangle includes a square, a rectangle, a trapezoid, or any quadrilateral. In an embodiment, a triangle can be an equilateral triangle or an isosceles triangle. In an embodiment, the position of the second insulating structure opening 602 can be located at the incenter, circumcenter, orthocenter, or centroid of a triangle.

[0189] In one embodiment, there is only one second insulating structure opening 602 within any polygon formed by a plurality of insulating reflection structure openings 400.

[0190] In one embodiment, as Figure 1 or Figure 4 shown, the second insulating structure opening 602 may be located within a rectangle formed by a plurality of insulating reflection structure openings 400. In another embodiment, as Figure 1 , Figure 2 or Figure 4 shown, the second insulating structure opening 602 may be located within a triangle formed by a plurality of insulating reflection structure openings 400.

[0191] In one embodiment, as Figure 1 shown, one of two adjacent second insulating structure openings 602 is located at any position within a rectangle formed by a plurality of insulating reflection structure openings 400, and the other of the two adjacent second insulating structure openings 602 is located at any position within a triangle formed by a plurality of insulating reflection structure openings 400.

[0192] In one embodiment, as Figure 5 or Figure 6 shown, there is only one second insulating structure opening 602 within a hexagon formed by a plurality of insulating reflection structure openings 400. In one embodiment, as Figure 3 shown, a hexagon formed by a plurality of insulating reflection structure openings 400 contains six second insulating structure openings 602.

[0193] In this embodiment, the second insulating structure opening 602 includes a width not greater than a width included in the insulating reflection structure opening 400. In another embodiment, one or more second insulating structure openings 602 each include a width greater than a width included in each of the plurality of insulating reflection structure openings 400.

[0194] As Figures 1 - 6 shown, one or more second insulating structure openings 602 are located in a region outside a projection area of the second electrode pad 92 and are covered by the second extended electrode 72. As Figure 1 , Figure 4 , Figure 5 and Figure 6 shown, a plurality of second insulating structure openings 602 are arranged along a periphery of the second electrode pad 92. A part of the plurality of second insulating structure openings 602 may overlap an edge of the second opening 802 of the protection structure and may be arranged at equal intervals or unequal intervals around the second electrode pad 92 or on one side of the second electrode pad 92. As Figure 2 and Figure 3As shown, a plurality of second insulating structure openings 602 can be changed to be only located at two opposite sides of the second electrode pad 92. In another embodiment, Figures 1 - 6 The illustrated pattern of the second insulating structure openings 602 can be changed to a rectangle, a triangle, or a regular or irregular polygon in addition to a circle.

[0195] In one embodiment, as Figures 1 - 3 and Figures 5 - 6 shown, a plurality of second insulating structure openings 602 have the same width or diameter. In one embodiment, as Figure 4 shown, a plurality of second insulating structure openings 602 have different widths or diameters.

[0196] As Figures 7 - 9 shown, the first extended electrode 71 can be disposed on the insulating structure 60 and extend through the first insulating structure opening 601 to contact and electrically connect to the first semiconductor layer 21 on the first contact first region CT1 and the first contact second region CT1' of the first semiconductor layer 21. In one embodiment, in order to improve the contact resistance characteristics between the first extended electrode 71 and the first semiconductor layer 21, a conductive contact layer (not shown in the figure) can be disposed between the first extended electrode 71 and the first semiconductor layer 21. The conductive contact layer can include indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), indium zinc oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) Mg x O, 0 ≤ x ≤ 1) and other conductive metal oxides. In one embodiment, a metal contact layer (not shown in the figure) can be disposed on the upper surface 20b of the first exposed region E1 and / or on the upper surface 20b' of the second exposed region E2, and a part of the upper surface of the metal contact layer can be the first contact first region CT1 and / or the first contact second region CT1'.

[0197] The second extended electrode 72 can be disposed on the insulating structure 60 and extend through the second insulating structure opening 602 to the metal reflection structure 52 to electrically connect to the second semiconductor layer 23.

[0198] Referring to Figures 1 - 6 and Figure 8, the first extended electrode 71 includes a first electrode connection portion 710 near the first side 11 of the substrate 10 and one or more first extended electrode protrusions 711 extending toward the second side 12 of the substrate 10. The second extended electrode 72 includes a second electrode connection portion 720 near the second side 12 of the substrate 10 and one or more second extended electrode recesses 722 extending toward the second side 12 of the substrate 10. When viewed from a top view, the second insulating structure opening 602 is located within the projected area of the second extended electrode 72, so that the second extended electrode 72 can fill the second insulating structure opening 602 and be electrically connected to the second semiconductor layer 23, and the edge 72e of the second extended electrode 72 covers the insulating reflection structure opening 400.

[0199] The first extended electrode 71 and the second extended electrode 72 are arranged staggeredly, and the width of the first extended electrode protrusion 711 is smaller than the width of the second extended electrode recess 722, so that the second extended electrode 72 can avoid the position of the through hole 200, and the upper surfaces of the second extended electrode 72 and the second electrode pad 92 are closer to or are a planarized surface.

[0200] Compared with the second extended electrode recess 722, the second extended electrode 72 includes a second extended electrode protrusion 721. Specifically, when viewed from the top view of the optoelectronic elements 1 to 6, with the edge of the first extended electrode protrusion 711 closest to the second side 12 as a reference, a reference line is drawn parallel to the second direction, and the second extended electrode recess 722 and the second extended electrode protrusion 721 are located on two opposite sides of the reference line. In an embodiment where the second insulating structure opening 602 is located within the polygon formed by a plurality of insulating reflection structure openings 400, one or more second insulating structure openings 602 are respectively located within the polygon formed by a plurality of insulating reflection structure openings 400 under the second extended electrode protrusion 721.

[0201] In one embodiment, the first extended electrode 71 and the second extended electrode 72 can be disposed on the insulating structure 60, formed of different materials, and spaced apart from each other. For example, the first extended electrode 71 and the second extended electrode 72 can be formed of a material including at least one of the following: aluminum (Al), gold (Au), tungsten (W), platinum (Pt), iridium (Ir), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), chromium (Cr), and alloys of the above materials.

[0202] The protection structure 80 includes a first protection structure opening 801 located on the first extended electrode 71 and a second protection structure opening 802 located on the second extended electrode 72. The first protection structure opening 801 can expose the first extended electrode 71, and the second protection structure opening 802 can expose the second extended electrode 71. Refer to Figures 1 - 6 and Figure 8, each of the optoelectronic elements 1-6 includes one or more protective mesa 800 covering one or more through holes 200 respectively. One or more protective mesa 800 are located in an area outside a projected area of the first electrode pad 91, so that the first electrode pad 91 can avoid the position of the through hole 200, and also make the upper surface of the first electrode pad 91 a planarized surface.

[0203] Reference Figures 1 - 6 , viewed from a top view, the projections of the first electrode pad 91 and the second electrode pad 92 do not overlap with the projection of the through hole 200, so that the surfaces of the optoelectronic elements 1-6 are planarized, which is beneficial to increasing the bonding area between the packaging substrate and the first electrode pad 91 and the second electrode pad 92 during the subsequent packaging process. Reference Figures 8 - 9 , a plurality of first insulating structure openings 601 are located in an area outside a projected area of the first electrode pad 91 and are covered by the first extended electrode 71.

[0204] Reference Figures 1 - 6 , a first group of through holes 2001 of the plurality of through holes 200 are surrounded by the first electrode pad 91, and / or a second group of through holes 2002 are surrounded by the second electrode pad 92. The first electrode pad 91 includes one or more first electrode pad recesses 912 to accommodate the first group of through holes 2001, and / or the second electrode pad 92 includes one or more second electrode pad recesses 922 to accommodate the second group of through holes 2002. In one embodiment, as Figure 1 and Figure 2 shown, the first electrode pad recess 912 extends towards the inside of the first electrode pad 91. In one embodiment, as Figures 3 - 5 shown, a plurality of first electrode pad recesses 912 are located on the same side of the first electrode pad 91 and extend towards the inside of the first electrode pad 91. In another embodiment, as Figure 6 shown, a plurality of first electrode pad recesses 912 are located on two opposite sides of the first electrode pad 91 and extend towards the inside of the first electrode pad 91.

[0205] The second electrode pad 92 has a top view area smaller than a top view area included by the second extended electrode 72. As Figure 1 shown, the morphology of the second electrode pad recess 922 does not have to correspond to the morphology of the second extended electrode recess 722. As Figures 2 - 6 shown, the morphology of the second electrode pad recess 922 can correspond to the morphology of the second extended electrode recess 722. Even if the morphology of the second electrode pad recess 922 does not correspond to the morphology of the second extended electrode recess 722, as Figure 1 shown, to expand the area of the second electrode pad 92, the distance D between one side of one or more second electrode pad recesses 922 and one side of the second extended electrode recess 722 is less than the minimum distance d between the plurality of insulating reflection structure openings 400 minMoreover, a plurality of second electrode pad recesses 922 are located on the same side of the second electrode pad 92.

[0206] The first electrode pad 91 can be disposed on the first extended electrode 71 through the first opening 801 of the protection structure, and the second electrode pad 92 can be disposed on the second extended electrode 72 through the second opening 802 of the protection structure. A first bonding pad (not shown) can be disposed on the first electrode pad 91, and a second bonding pad (not shown) can be disposed on the second electrode pad 92. The first bonding pad and the second bonding pad can be formed of a conductive material (e.g., Sn or AuSn). As Figures 1 - 6 shown, in a top view, the first electrode pad 91 can be adjacent to the first side 11, and the second electrode pad 92 can be adjacent to the second side 12.

[0207] The first electrode pad 91 and the second electrode pad 92 include a metal material, such as metals or alloys of chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag), etc. The first electrode pad 91 and the second electrode pad 92 can be composed of a single layer or multiple layers. For example, the first electrode pad 91 or the second electrode pad 92 can include a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, a Cr / Pt / Au layer, a Ni / Au layer, a Ni / Pt / Au layer, a Cr / Al / Cr / Ni / Au layer, or an Ag / NiTi / TiW / Pt layer. The first electrode pad 91 and the second electrode pad 92 can serve as current paths for supplying power from an external power source to the first semiconductor layer 21 and the second semiconductor layer 23. In one embodiment, each of the first electrode pad 91 and the second electrode pad 92 has a thickness ranging from 0.5 micrometers to 5 micrometers.

[0208] In one embodiment, an insulating layer 42, an insulating structure 60, and a protection structure 80 are disposed on a semiconductor stack 20 as a protective film for optoelectronic elements 1 to 6 and an interlayer insulating film for preventing electrostatic charge. In one embodiment, as the insulating film, the insulating layer 42, the insulating structure 60, and the protection structure 80 may be a single-layer structure containing a metal oxide or a metal nitride. For example, at least one oxide or nitride selected from the group consisting of silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), and aluminum (Al) may be preferably used. In another embodiment, the insulating layer 42, the insulating structure 60, and the protection structure 80 include two or more materials having different refractive indices stacked alternately to form a distributed Bragg reflector (DBR) structure that selectively reflects light of a specific wavelength. For example, a reflective structure with high reflectivity may be formed by stacking insulating layers of two or three materials such as SiO2, TiO2, Nb2O5, or Al2O3. For example, when a distributed Bragg reflector (DBR) structure is formed by stacking sub-layers such as SiO2 / TiO2 or SiO2 / Nb2O5, each sub-layer of the distributed Bragg reflector structure is designed to have an optical thickness that is one or an integral multiple of a quarter of the wavelength of the light emitted from the active layer 22. The optical thickness of each sub-layer of the distributed Bragg reflector (DBR) structure may have a deviation of ±30% based on one or an integral multiple of λ / 4. Since a change in the optical thickness of each sub-layer of the distributed Bragg reflector structure affects the reflectivity, the physical thickness of each sub-layer in the insulating layer 42, the insulating structure 60, and the protection structure 80 obtained based on the optical thickness of the distributed Bragg reflector structure may be formed by electron beam evaporation to stably control the thickness of each sub-layer in the insulating layer 42, the insulating structure 60, and the protection structure 80.

[0209] Figure 15 FIG. 4 is a schematic view of a light-emitting device 7 according to an embodiment of the present invention. One of the optoelectronic elements 1 to 6 in the foregoing embodiment is mounted on a first pad 501 and a second pad 502 of a package substrate 50 in a flip-chip form. Electrical insulation is provided between the first pad 501 and the second pad 502 by an insulating portion 53 containing an insulating material. In flip-chip mounting, the growth substrate side opposite to the electrode pad formation surface is set as the main light extraction surface. For example, the light extraction surface 10t of the substrate 10 of the optoelectronic elements 1 to 6 is the main light extraction surface of the optoelectronic elements 1 to 6. To increase the light extraction efficiency of the light-emitting device 7, a reflective structure 54 may be provided around the optoelectronic elements 1 to 6.

[0210] Figure 16It is a schematic diagram of a light-emitting device 8 according to an embodiment of the present invention. The light-emitting device 8 is a bulb lamp, and includes a lamp cover 612, a reflector 604, a light-emitting module 600, a lamp holder 611, a heat sink 614, a connecting portion 616, and an electrical connection element 618. The light-emitting module 600 includes a carrying portion 606, and a plurality of light-emitting units 608 are located on the carrying portion 606, wherein the plurality of light-emitting units 608 can be one of the optoelectronic elements 1 to 6 in the foregoing embodiments or the light-emitting device 7.

[0211] Figure 17 It is a schematic diagram of a backlight module 9 according to an embodiment of the present invention. The backlight module 9 includes a first frame 201, a liquid crystal display panel 202, a brightness enhancement film 310, an optical module 430, a light-emitting module assembly 500, and a second frame 700. The light-emitting module assembly 500 includes one of the plurality of optoelectronic elements 1 to 6 in the foregoing embodiments or the light-emitting device 7, and is arranged in the light-emitting module assembly 500 in an edge type or direct type light-emitting manner. In one embodiment, the backlight module 4 further includes a wavelength conversion structure 610, which is disposed on the light-emitting module assembly 500.

[0212] Figure 18 It is a schematic diagram of a display 100 according to an embodiment of the present invention. The display 100 includes an LED light-emitting panel 3000 and a current source (not shown). The bracket 2000 is used to support the LED light-emitting panel 3000. The LED light-emitting panel 3000 includes one of the plurality of optoelectronic elements 1 to 6 in the foregoing embodiments or any one of the light-emitting devices 7 or the backlight module 9. In one embodiment, the LED light-emitting panel 3000 includes a plurality of pixel units. Each pixel unit includes one of the plurality of optoelectronic elements 1 to 6 in the foregoing embodiments or the light-emitting device 7 to emit different colors respectively. For example, each pixel unit includes three optoelectronic elements 1 to 6 or the light-emitting device 7 that emit red light, green light, and blue light respectively.

[0213] Figure 19It is a schematic diagram of a light-emitting device 1000 according to an embodiment of the present invention. In one embodiment, the light-emitting device 1000 is an LED bulb for an automobile and can be plugged and fixed in an installation through-hole on the rear housing of an automobile headlight assembly. The light-emitting device 1000 includes a first LED chip 4100 for emitting light of a low beam or a second LED chip 4200 for emitting light of a high beam, a long-columnar lamp post 4300, a driving power circuit board 4400, heat dissipation fins (not shown in the figure), a fan (not shown in the figure) for heat dissipation, a fan cover (not shown in the figure) for covering the fan, a power cord (not shown in the figure) for electrically connecting to a vehicle-mounted battery, and a plug (not shown in the figure) provided at the end of the power cord. The first LED chip 4100 or the second LED chip 4200 in the light-emitting device 1000 may include any one or more of the foregoing optoelectronic elements 1 to 6 or the light-emitting device 7.

[0214] Figure 20 It is a schematic diagram of a light-emitting device 10000 according to an embodiment of the present invention. In one embodiment, the light-emitting device 10000 may be a vehicle lighting lamp 5000 and can be applied to a daytime running light, a headlight, a tail light, or a turn signal. The main lighting lamp 5100 may be the main light-emitting lamp in the vehicle lighting lamp 5000. For example, when the vehicle lighting lamp 5000 is used as a headlight in front of a vehicle, the main lighting lamp 5100 may have the function of illuminating the front of the vehicle. The combined lighting lamp 5200 may have at least two functions. For example, when the vehicle lighting lamp is used as a headlight in front of a vehicle, the combined lighting lamp 5200 may perform the functions of a daytime running light (DRL) and a turn indicator. The main lighting lamp 5100 or the combined lighting lamp 5200 may include any one or more of the foregoing optoelectronic elements 1 to 6 or the light-emitting device 7.

[0215] The components of some of the above embodiments are provided so that those of ordinary skill in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those of ordinary skill in the technical field to which the present invention pertains should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments introduced herein. Those of ordinary skill in the technical field to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims. Additionally, although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention.

[0216] References throughout this specification to features, advantages, or similar language do not imply that all of the features and advantages that can be realized by the present invention should or can be realized in any single embodiment of the invention. Rather, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

[0217] Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. As will be recognized by one of ordinary skill in the art in light of the disclosure herein, the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.

Claims

1. An optoelectronic device, comprising: A semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer; A contact electrode located on the second semiconductor layer; An insulating reflective structure covering the contact electrode and including a plurality of insulating reflective structure openings exposing the contact electrode; A metal reflective structure covering the plurality of insulating reflective structure openings and electrically connecting to the contact electrode; An insulating structure including one or more first insulating structure openings exposing the first semiconductor layer and one or more second insulating structure openings exposing the metal reflective structure; A first extension electrode covering the semiconductor stack and the one or more first insulating structure openings to electrically connect to the first conductivity type semiconductor layer; And A second extension electrode covering the semiconductor stack and the one or more second insulating structure openings to electrically connect to the metal reflective structure, wherein when viewed from a top view of the optoelectronic device, the one or more second insulating structure openings are respectively located at any position within a polygon formed by the plurality of insulating reflective structure openings.

2. The optoelectronic element according to claim 1, wherein the contact electrode comprises indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), indium zinc oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) Mg x O, where 0 ≤ x ≤ 1).

3. The optoelectronic element according to claim 2 further includes a connection layer covering the openings of the plurality of insulating reflection structures, wherein the connection layer includes titanium (Ti), aluminum oxide (Al2O3), indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), indium zinc oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or zinc magnesium oxide (Zn (1-x) Mg x O, where 0 ≤ x ≤ 1).

4. The optoelectronic device according to claim 3, wherein the connecting layer has a thickness less than that of the contact electrode.

5. The optoelectronic device according to claim 3, wherein the contact electrode and the connecting layer are made of the same material.

6. The optoelectronic device according to claim 3, wherein the contact electrode and the connecting layer are made of different materials.

7. The optoelectronic device according to claim 1, wherein the polygon includes a triangle, a rectangle, a pentagon, or a hexagon.

8. The optoelectronic device according to claim 7, wherein the position is located at the incenter, circumcenter, orthocenter, or centroid of the triangle.

9. The optoelectronic device according to claim 7, wherein the triangle is an equilateral triangle.

10. The optoelectronic device according to claim 1, wherein the second insulating structure opening has a width not greater than the width of each of the plurality of insulating reflective structure openings.

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