Solid state switch-based high speed pulse generator with plasma IEDF modification capability through multi-layer output function

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating a waveform for plasma processing a substrate in a processing chamber. One embodiment includes a waveform generator having three MOSFETs and three capacitors connected in series. The capacitors are connected to the DC power source, and the voltage across each capacitor may vary depending on the value of the capacitor. And a diode is connected behind each of the two capacitors at the top. The bottom capacitor is grounded. A drain terminal of each MOSFET is connected to a higher potential terminal of a series connected capacitor. A diode is connected behind each MOSFET, and the cathode ends of the diodes are connected together. The electrode is connected between the common cathode and the ground.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a system used in semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a plasma processing system for processing a substrate. Background Art

[0002] Low-temperature, non-equilibrium glow discharge plasmas are powerful tools in semiconductor device manufacturing, mainly used for various applications such as etching and deposition of thin films and ion implantation. As the semiconductor industry enters the sub-10nm regime, high aspect ratio features are becoming increasingly desirable in the semiconductor industry. Reactive ion etching (RIE) is one of the popular methods for achieving high aspect ratios and reliable throughput. In this process, the plasma is traditionally formed using a radio frequency (RF) source, and the ions inside the plasma are accelerated towards the substrate surface under the influence of a bias voltage applied to a metal plate called the cathode. The cathode can be capacitively coupled to the plasma through a dielectric layer.

[0003] The RF voltage bias applied to the chamber cathode creates an electron-repelling plasma sheath above the substrate surface, which acts like a non-linear diode, resulting in a negative cathode potential relative to the positive plasma potential. The RF cathode bias produces a bimodal ion energy distribution function (IEDF). The ions with lower energy contribute to its isotropic nature, resulting in sidewall bowing of high aspect ratio features, while the high-energy ions reach the bottom of the feature with greater sputtering. The increase in the sputtering level may compromise the etch selectivity and may cause unnecessary etching of the mask layer. Therefore, additional control knobs associated with the bias source are needed to fine-tune the selectivity features while producing high aspect ratio features.

[0004] To this end, multiple RF bias sources have been incorporated in some of the latest chamber designs to achieve an additional level of etch control. However, multiple RF bias sources may lead to arc problems and crosstalk problems. Pulsed plasma sources provide a unique platform that can alleviate the above problems associated with RF bias sources and help improve etch selectivity, throughput, and uniformity.

[0005] Traditionally, a pulsed power supply provides a pulsed DC bias voltage to a cathode. For these designs, the switching frequency and power consumption capabilities must be considered. As device sizes decrease, the complexity of semiconductor tools increases exponentially. The DC bias power supplies, which are crucial for semiconductor manufacturing tools employing plasma etching processes, are undergoing changes, including increased peak amplitudes and switching frequencies, multi-level pulses, and robust cooling mechanisms. Induction adder-based and metal-oxide-semiconductor field-effect transistor (MOSFET)-based DC power supplies are the two main types of DC power supplies suitable for semiconductor tools. However, due to the limited flux density swing of the magnetic core, induction adder-based DC power supplies are limited in terms of operating switching frequencies. Additionally, the weight of the magnetic core results in a bulky power supply with a large footprint. However, MOSFET-based power supplies have excellent switching capabilities, specifically silicon carbide (SiC) and gallium nitride (GaN) MOSFETs. Moreover, due to the compact size of MOSFETs, these solid-state switching-based power supplies can offer similar or better performance with a smaller footprint. However, as the switching frequency increases, the switching losses also increase proportionally, leading to complex cooling mechanisms.

[0006] Accordingly, there is a need for a pulsed DC bias voltage source with a high enough switching frequency to control critical high aspect ratio features, etch selectivity, and the uniformity of RIE. SUMMARY OF THE INVENTION

[0007] Embodiments described herein generally relate to a system used in semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a plasma processing system for processing a substrate using a bias pulse scheme to generate micro-pulses.

[0008] In one embodiment, a system for reactive ion etching includes: a chamber body; a substrate holder within the chamber body; a bias electrode within the substrate holder; and a bias voltage source configured to supply a pulsed bias voltage to the electrode. The bias voltage source includes: a DC voltage source; a first capacitor connected to the DC voltage source; ground; a first diode in series between the first capacitor and ground; a first resistor connected to the DC voltage source; a first metal-oxide-semiconductor field-effect transistor (MOSFET) in series with the first resistor; a first gate voltage source connected to the gate of the first MOSFET; a first blocking diode connected to the source of the first MOSFET; a second capacitor in series between the first diode and ground; a second diode in series between the second capacitor and ground; a second resistor connected between the first diode and the second capacitor; a second MOSFET in series with the second resistor; a second gate voltage source connected to the gate of the second MOSFET; and a second blocking diode connected to the source of the second MOSFET.

[0009] In another embodiment, a method of etching using a pulsed waveform is provided. The method includes: generating a plasma in a chamber body; applying a pulsed DC voltage to the plasma using a bias electrode capacitively coupled to the plasma through a dielectric layer, wherein the pulsed DC voltage includes a plurality of pulses, each pulse of the plurality of pulses further includes a plurality of signals, and wherein each signal of the plurality of signals has a turn-off time, a pulse width, and an amplitude; and etching a substrate in the chamber body using the pulsed DC voltage applied to the plasma. The DC voltage source is connected in series to a second capacitor, a second diode, a second resistor, a second MOSFET, a second gate voltage source, and a second blocking diode. The second capacitor is connected in series between the first diode and ground. The second diode is connected in series between the second capacitor and ground. The second resistor is connected in parallel with the second capacitor. The second MOSFET is connected in series to the second resistor. The second gate voltage source is connected to the gate terminal of the second MOSFET. The second blocking diode is connected to the source terminal of the MOSFET. The DC voltage source is connected in series to a second capacitor, a second diode, a second resistor, a second MOSFET, a second gate voltage source, and a second blocking diode. The second capacitor is connected in series between the first diode and ground. The second diode is connected in series between the second capacitor and ground. The second resistor is connected in parallel with the second capacitor. The second MOSFET is connected in series to the second resistor. The second gate voltage source is connected to the gate terminal of the second MOSFET. The second blocking diode is connected to the source terminal of the second MOSFET. The first MOSFET receives a first strobe signal from a first gate voltage source. The first strobe signal has a first pulse width. And wherein the second MOSFET receives a second strobe signal from a second gate voltage source. The second strobe signal has a second pulse width.

[0010] In yet another embodiment, a pulsed signal source device for etching is provided. The pulsed signal source device includes: a controller; a bias electrode; and a bias voltage source configured to supply a pulsed bias voltage to the bias electrode. The bias voltage source includes: a DC voltage source; a first capacitor connected in series with the DC voltage source; a first diode connected to the first capacitor; a ground connected in series with the first diode; a first resistor connected in parallel with the first capacitor; a first MOSFET connected in series to the first resistor; a first gate voltage source connected to the gate terminal of the first MOSFET; a second capacitor connected in series between the first diode and the ground; a second diode connected in series between the second capacitor and the ground; a second resistor connected in parallel with the second capacitor; a second MOSFET connected in series to the second resistor; a second gate voltage source connected to the gate terminal of the second MOSFET; a second blocking diode connected to the source terminal of the second MOSFET; a third capacitor connected in series between the second diode and the ground; a third resistor connected in parallel with the third capacitor; a third MOSFET connected in series to the third resistor; a third gate voltage source connected to the gate terminal of the third MOSFET; and a third blocking diode connected to the source terminal of the third MOSFET. Brief Description of the Drawings

[0012] To understand in detail the manner in which the above-described features of the present disclosure are utilized, a more specific description of the present disclosure briefly summarized above may be referred to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit other equivalent embodiments.

[0013] Figure 1 is a schematic cross-sectional view of a processing system according to one or more embodiments, the processing system being configured to practice the methods set forth herein.

[0014] Figure 2A is a diagram showing a solid-state-switching-based high-speed pulse generator according to an embodiment of the present disclosure.

[0015] Figure 2B is a diagram showing a solid-state-switching-based high-speed pulse generator according to an embodiment of the present disclosure.

[0016] Figure 3 is a schematic cross-sectional view of a device according to one or more embodiments, the device being configured to practice the methods set forth herein.

[0017] Figure 4 Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrode of the processing chamber.

[0018] Figure 5 Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrodes of the processing chamber.

[0019] Figure 6A Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrodes of the processing chamber.

[0020] Figure 6B Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrodes of the processing chamber.

[0021] Figure 7 Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrodes of the processing chamber.

[0022] Figure 8A Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrodes of the processing chamber.

[0023] Figure 8B Shows the voltage waveform established on the substrate due to the voltage waveform applied to the electrodes of the processing chamber.

[0024] Figure 9 Is a process flow diagram showing a method for waveform generation.

[0025] For the sake of facilitating understanding, the same element symbols have been used as much as possible to indicate the same elements common in the drawings. It is expected that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further recitation. Detailed Description

[0026] Embodiments herein generally relate to the manufacture of electronic devices, and more particularly to systems and methods for forming low resistivity tungsten features in semiconductor device manufacturing schemes.

[0027] The present disclosure includes a three-stage topology based on a metal oxide semiconductor field effect transistor (MOSFET), which is configured to generate a customizable multi-level output waveform and increase the effective output frequency while masking the switching frequency limitations of current generation MOSFETs. Embodiments of the present disclosure generate a customizable voltage output waveform that caters to the dynamic ion energy distribution function (IEDF) to add a unique tuning knob to the plasma etch recipe. In addition, the effective output efficiency of the pulse generator is increased based on the number of stages and the strobe signal pattern. Embodiments in the present disclosure also mask the switching frequency limitations of the current generation MOSFETs and reduce the corresponding cooling requirements, while generating pulses with different widths in a single output burst, and generating a lighter and faster alternative for an induction adder-based pulse generator.

[0028] Figure 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods set forth herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process. However, it should be noted that the embodiments described herein may also be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes, such as plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma processing treatments, or plasma-based ion implantation treatments (such as plasma doping (PLAD) treatments).

[0029] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP) and includes a processing chamber 100 that includes an upper electrode (e.g., chamber lid 123) disposed adjacent to a processing space 129 facing a lower electrode (e.g., substrate support assembly 136), the lower electrode being disposed in the processing space 129 opposite the upper electrode. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrodes ( Figure 1 in this case, the lower electrode), and transmits an RF signal configured to ignite and sustain a plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and is disposed in the processing space 129 between the upper and lower electrodes. Typically, one of the upper or lower electrodes ( Figure 1 in this case, the upper electrode) is coupled to ground or a second RF power source. In one embodiment as Figure 1 shown, one or more components of the substrate support assembly 136 (e.g., support base 107) are electrically coupled to a plasma generator assembly 163 that includes an RF generator 118, and the chamber lid 123 is electrically coupled to ground. As shown, the processing system 10 includes a processing chamber 100, a support assembly 136, and a system controller 126.

[0030] The processing chamber 100 generally includes a chamber body 113, which includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which together define a processing space 129. The one or more sidewalls 122 and the chamber base 124 generally include a material, the size and shape of which are designed to form the structural support of the elements of the processing chamber 100, and the material is configured to withstand the pressure and increased energy applied to the material while generating a plasma 101 within the vacuum environment maintained in the processing space 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed of a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0031] A gas inlet 128 disposed through the chamber lid 123 is configured to convey one or more processing gases from a processing gas source 119 in fluid communication therewith to the processing space 129. A substrate 103 is loaded into and removed from the processing space 129 through an opening (not shown) in one of the one or more sidewalls 122, the opening being sealed by a slit valve (not shown) during plasma processing of the substrate 103. The substrate 103 is supported by a substrate support assembly 136. The substrate support assembly 136 includes a substrate holder 105 configured to support the substrate 103 thereon, a support base 107 disposed below the substrate holder 105, an insulator plate 111 disposed below the support base 107, and a ground plate 112 disposed below the insulator plate 111.

[0032] In some embodiments, the processing chamber 100 further includes a quartz tube 110 or sleeve that at least partially surrounds portions of the substrate support assembly 136 to prevent the substrate holder 105 and the support base 107 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or by-products of the foregoing. Generally, the quartz tube 110, the insulator plate 111, and the ground plate 112 are surrounded by a gasket 108. In some embodiments, a plasma screen 109 is positioned between the gasket 108 and the one or more sidewalls 122 to prevent a plasma from forming in the space between the gasket 108 and the one or more sidewalls 122 below the plasma screen 109.

[0033] The system controller 126, also referred to herein as the process chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuitry 135. The system controller 126 is used to control the processing sequence for processing the substrate 103, including the substrate biasing methods described herein. The CPU is a general-purpose computer processor configured for an industrial environment to control the process chamber and associated sub-processors. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, a floppy disk or hard disk drive, or other suitable forms of local or remote digital memory. The support circuitry 135 is coupled to the CPU 133 in a conventional manner and includes a cache, clock circuitry, input / output subsystems, power supplies, etc., and combinations of the above. Software instructions (programs) and data can be encoded and stored in the memory 134 to direct the processors within the CPU 133. The software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks can be performed by the components in the processing system 10.

[0034] Generally, the programs readable by the CPU 133 in the system controller 126 include code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing scenarios described herein. The programs may include instructions for controlling various hardware and electronic components within the processing system 10 to perform various processing tasks and for implementing various processing sequences of the methods described herein.

[0035] The processing system may include a plasma generator assembly 163 and a first pulse voltage (PV) source assembly 196 for establishing a first PV waveform at a bias electrode 104 disposed within a substrate support 105, as described in more detail herein with reference to Figures 4 to 8B In some embodiments, the plasma generator assembly 163 transmits an RF signal to a support base 107 (e.g., a power electrode or cathode), and the RF signal can be used to generate (maintain or ignite) a plasma 101 in a processing space 129 disposed between a substrate support assembly 136 and a chamber lid 123. The bias electrode 104 is capacitively coupled to the plasma 101 through a dielectric layer 105B of the substrate support 105. In some embodiments, the RF generator 118 is configured to transmit an RF signal having a frequency greater than 1 MHz or higher, or about 2 MHz or higher, such as about 13.56 MHz or higher.

[0036] As discussed above, in some embodiments, the plasma generator assembly 163, including the RF generator 118 and the RF generator assembly 160, is generally configured to deliver a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to the support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to deliver RF power (e.g., an RF signal) to the support base 107 disposed near the substrate support 105 and within the substrate support assembly 136. The RF power delivered to the support base 107 is configured to ignite and sustain the processing plasma 101 using the processing gas disposed in the processing space 129 and the fields generated by the RF power (RF signal) delivered from the RF generator 118 to the support base 107.

[0037] In some embodiments, the support base 107 is an RF electrode electrically coupled to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, both of which are disposed within the RF generator assembly 160.

[0038] The processing space 129 is fluidly connected via a vacuum outlet 120 to one or more dedicated vacuum pumps that maintain the processing space 129 at sub-atmospheric conditions and evacuate processing and other gases therefrom. In some embodiments, the substrate support assembly 136 disposed in the processing space 129 is disposed on a support shaft 138 that is grounded and extends through the chamber base 124.

[0039] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an electrostatic chuck substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may additionally include an insulator plate 111 and a ground plate 112, as further discussed below. The support base 107 is electrically isolated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is inserted between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and is disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0040] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), a mixture of the foregoing, or a combination of the foregoing. In the embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material.

[0041] In one configuration, the bias electrode 104 is an adsorption rod for fixing (i.e., adsorbing) the substrate 103 to the substrate support surface 105A of the substrate support 105 and for biasing the substrate 103 relative to the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive parts, such as one or more metal meshes, foils, plates, or a combination of the foregoing.

[0042] In some embodiments, the bias electrode 104 is electrically coupled to a bias voltage source 150 using an electrical conductor such as a coaxial power transmission line 106 (e.g., a coaxial cable), and the bias voltage source 150 supplies an adsorption voltage or a pulsed bias voltage 153 to the bias electrode 104, such as a pulsed DC voltage between approximately -5000V and approximately 5000V.

[0043] A power transmission line 157 electrically connects the output of the bias voltage source 150 of the first bias voltage source assembly 196 to an optional filter assembly 151 and the bias electrode 104. The electrical conductors within the various parts of the power transmission line 157 may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) an insulated high-voltage corona-resistant connection line; (c) a bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical components in (a)-(e). The optional filter assembly 151 includes one or more electrical components configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power transmission line 157 and damaging the bias voltage source 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118 and thus inhibits current flow to the bias voltage source 150.

[0044] Figure 2A is a schematic diagram of the bias voltage source 150. As Figure 2AAs shown, the bias voltage source 150 includes a DC voltage source 210, a first capacitor 220 connected to the positive terminal of the DC voltage source 210, and a first diode 230 connected to the first capacitor 220. The bias voltage source 150 further includes a first resistor 240 connected to the positive terminal of the DC voltage source 210, a first MOSFET 250 connected in series to the first resistor 240, a first gate voltage source 260 connected to the gate terminal of the first MOSFET 250, and a first blocking diode 270 connected to the source terminal 251 of the first MOSFET 250. The bias voltage source 150 may also include a second capacitor 222 connected in series between the first diode 230 and ground 228 and a second diode 232 connected in series between the second capacitor 222 and ground 228. As shown, the second capacitor 222 is connected in series between the first diode 230 and the second diode 232. A second resistor 242 may be connected to the common point of the first diode 230 and the second capacitor 222. A second MOSFET 252, a second gate voltage source 262, and a second blocking diode 272 may also be connected in series with the second resistor 242, wherein the cathode of the second blocking diode 272 is connected to the cathode of the first blocking diode 270. As shown, the bias voltage source 150 may also include a third capacitor 224 connected in series between the second diode 232 and ground 228. In addition, a third resistor 244 may be connected to the common point of the second diode 232 and the third capacitor 224. A third MOSFET 254, a third gate voltage source 264, and a third blocking diode 274 may also be connected in series with the third resistor 244, wherein the cathode of the third blocking diode 274 is connected to the bias electrode 104. When all the MOSFETs are gated simultaneously and the gate signal widths are the same, the full supply voltage will be applied to the load.

[0045] By turning on the MOSFETs (such as 250, 252, and 254) at different timestamps, the effective output frequency can be increased by three times. Although this scheme is used to increase the effective output frequency, the operation switching frequency of each MOSFET is one-third of the effective output switching frequency. In addition, by combining the width and delay of the gate signal, various multi-level output voltage waveforms corresponding to a unique IEDF can be generated, and the IEDF can be a unique addition in the plasma etching recipe. By utilizing these features provided by the present disclosure, the selectivity, uniformity, and throughput of RIE can be significantly improved.

[0046] Alternatively, as Figure 2BAs shown, the bias voltage source 150 may include a first resistor 240 to the positive terminal of the DC voltage source 210, a first MOSFET 250 connected in series to the first resistor 240, a first gate voltage source 260 connected to the gate terminal of the first MOSFET 250, and a first blocking diode 270 connected to the source terminal 251 of the first MOSFET 250. In addition, a second capacitor 222 may be connected in series between the first diode 230 and ground 228. The bias voltage source 152 may further include a second resistor 242 connected to the common point of the first diode 230 and the second capacitor 222. A second MOSFET 252 may be connected in series to the second resistor 242, a second gate voltage source 262 connected to the gate terminal of the second MOSFET 252, and a second blocking diode 272 connected to the source terminal 253 of the second MOSFET 252. In this embodiment, the electrode 140 is electrically coupled to the second blocking diode 272 of the bias voltage source 152.

[0047] Figure 3It is a schematic diagram of the pulse signal source device 300. The pulse signal source device 300 includes a substrate support (e.g., an electrostatic chuck) 305, which is made of a dielectric material and is configured to support the substrate 303 on the substrate support surface 305A, the support base 307, the insulator plate, the ground plate 312, and the support shaft 338. The pulse signal source device 300 further includes an electrode 304 and a bias voltage source 301. The electrode 304 is disposed in the substrate support 305 and is configured to be capacitively coupled to the plasma through the dielectric layer 305B. The bias voltage source 301 is configured to supply a pulsed bias voltage to the electrode 304. The bias voltage source 301 includes a DC voltage source 310, a first capacitor 320 connected in series with the DC voltage source 310, a first diode 330 connected to the first capacitor 320, a first resistor 340 connected at one end to the positive terminal of the DC voltage source 310, a first MOSFET 350 connected in series to the first resistor 340, a first gate voltage source 360 connected to the gate terminal of the first MOSFET 350, and a first blocking diode 370 connected to the source terminal 351 of the first MOSFET 350. The bias voltage source 301 further includes a second capacitor 322 connected in series between the first diode 330 and the second diode 332 (the second diode 332 is connected in series between the second capacitor 322 and the ground 328), a second resistor 342 connected at the common connection point between the first diode 330 and the second capacitor 322, a second MOSFET 352 connected in series to the second resistor 342, a second gate voltage source 362 connected to the gate terminal of the second MOSFET 352, and a second blocking diode 372 connected to the source terminal 353 of the second MOSFET 352. In addition, a third capacitor 324 is connected in series between the second diode 332 and the ground 328, and a third resistor 344 is connected at the common connection point between the second diode 332 and the third capacitor 324. Further, a third MOSFET 354 is connected in series to the third resistor 344, a third gate voltage source 364 is connected to the gate terminal of the third MOSFET 354, and a third blocking diode 374 is connected to the source terminal of the third MOSFET 354. The memory 334, the CPU 333, and the support circuit 335 of the system controller 326 (similar to the system controller 126) can change the pulse width, duration, and amplitude according to the present disclosure, as further described below.

[0048] Figure 4A pulsed voltage biasing scheme using waveform 400 in accordance with certain embodiments of the present disclosure is shown. As shown, waveform 400 includes a plurality of pulses 410. Each of the plurality of pulses 410 includes a total pulse width 412. Within each of the plurality of pulses 410, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 420 having a first pulse width 421, a second signal 422 having a second pulse width 423, and a third signal 424 having a third pulse width 425. Each signal also includes an off-time (T off ), during which each signal is in an off state, such as a first T off 430 of the first signal 420, a second T off 432 of the second signal 422, and a third T off 434 of the third signal 424. The first T off 430 can be the duration between pulses or before the start of the initial pulse, during which at least the first MOSFET is selectively turned off, and typically all MOSFETs are selectively turned off. Additionally, each signal has its own amplitude, such as a first amplitude 440, a second amplitude 442, and a third amplitude 444.

[0049] In Figure 4 , each MOSFET is selectively turned on simultaneously and provides the same voltage, resulting in the first signal 420, the second signal 422, and the third signal 424 having the same amplitude (e.g., 440, 442, and 444 are equal), T off (e.g., 430, 432, and 434 are equal), and pulse width (e.g., 421, 423, and 425 are equal).

[0050] Figure 5 A pulsed voltage biasing scheme using waveform 500 in accordance with certain embodiments of the present disclosure is shown. As shown, waveform 500 includes a plurality of pulses 510. The plurality of pulses 510 includes a total pulse width 512. Within the plurality of pulses 510, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 520 having a first pulse width 521, a second signal 522 having a second pulse width 523, and a third signal 524 having a third pulse width 525. Each signal also includes a T off , such as a first T off 530 for the first signal 520, a second T off 532 for the second signal 522, and a third T off 534 for the third signal 524. Additionally, each signal has its own amplitude, such as a first amplitude 540, a second amplitude 542, and a third amplitude 544.

[0051] InFigure 5 In this case, each MOSFET is sequentially gated and then turned off, but each MOSFET provides the same voltage with the same pulse width. This results in the first signal 520, the second signal 522, and the third signal 524 having the same amplitude (e.g., 540, 542, and 544 are equal) and the same pulse width (e.g., 521, 523, and 525 are equal), but each T off gradually increases (e.g., 534 is greater than 532, and 532 is greater than 530). Each consecutive T off is also greater than the previous pulse width. For example, the second T off 532 is greater than the sum of the first T off 530 and the first pulse width 521. Additionally, the third T off 534 is greater than the sum of the first T off 530, the first pulse width 521, the second T off 532, and the second pulse width 523.

[0052] Figure 6A FIG. shows a pulsed voltage biasing scheme using waveform 600 according to certain embodiments of the present disclosure. As shown, waveform 600 includes a plurality of pulses 610. The plurality of pulses 610 includes a total pulse width 612. Within the plurality of pulses 610, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 620 having a first pulse width 621, a second signal 622 having a second pulse width 623, and a third signal 624 having a third pulse width 625. Each signal also includes a T off , such as a first T off 630 for the first signal 620, a second T off 632 for the second signal 622, and a third T off 634 for the third signal 624. Additionally, each signal has its own amplitude, such as a first amplitude 640, a second amplitude 642, and a third amplitude 644.

[0053] In Figure 6A , each MOSFET is sequentially gated and then turned off, and each MOSFET provides a different voltage, but the pulse widths are the same. This results in the first signal 620, the second signal 622, and the third signal 624 having the same pulse width (e.g., 621, 623, and 625 are equal), but each T off gradually increases (e.g., 634 is greater than 632, and 632 is greater than 630), and in this embodiment, each amplitude gradually decreases (e.g., 640 is greater than 642, and 642 is greater than 644). Each consecutive T off is also greater than the previous pulse width. For example, the second Toff 632 is greater than the first T off the sum of 630 and the first pulse width 621. Additionally, the third T off 634 is greater than the first T off 630, the first pulse width 621, the second T off the sum of 632 and the second pulse width 623.

[0054] Figure 6B A pulse voltage biasing scheme using waveform 650 according to certain embodiments of the present disclosure is shown. As shown, waveform 650 includes a plurality of pulses 660. The plurality of pulses 660 includes a total pulse width 662. Within the plurality of pulses 660, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 670 having a first pulse width 671, a second signal 672 having a second pulse width 673, and a third signal 674 having a third pulse width 675. Each signal also includes a T off , such as a first T off 680 for the first signal 670, a second T off 682 for the second signal 672, and a third T off 684 for the third signal 674. Additionally, each signal has its own amplitude, such as a first amplitude 690, a second amplitude 692, and a third amplitude 694.

[0055] In Figure 6B , each MOSFET is gated in sequence and then turned off, but each MOSFET provides a different voltage and has a different pulse width. This results in the first signal 670, the second signal 672, and the third signal 674 having different pulse widths (e.g., 671, 673, and 675 are not equal), each T off gradually increases (e.g., 684 is greater than 682, and 682 is greater than 680), and in this embodiment, each amplitude gradually decreases (e.g., 690 is greater than 692, and 692 is greater than 694). Each successive T off is also greater than the previous pulse width. For example, the second T off 682 is greater than the sum of the first T off 680 and the first pulse width 671. Additionally, the third T off 684 is greater than the sum of the first T off 680, the first pulse width 671, the second T off 682, and the second pulse width 673.

[0056] Figure 7A pulse voltage biasing scheme using waveform 700 in accordance with certain embodiments of the present disclosure is shown. As shown, waveform 700 includes a plurality of pulses 710. Each of the plurality of pulses 710 includes a total pulse width 712. Within the plurality of pulses 710, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 720 having a first pulse width 721, which may be equal to the total pulse width 712 (e.g., the first MOSFET is gated during the duration of the pulse), a second signal 722 having a second pulse width 723, and a third signal 724 having a third pulse width 725. As shown, the second pulse width 723 and the third pulse width 725 may be equal. Each signal also includes a T off , e.g., a first T off 730 for the first signal 720, a second T off 732 for the second signal 722, and a third T off 734 for the third signal 724. Additionally, each signal has its own amplitude, e.g., a first amplitude 740, a second amplitude 742, and a third amplitude 744.

[0057] In Figure 7 , the first MOSFET is gated before the second and third MOSFETs. As shown, the first MOSFET is gated at the start of the pulse. The second and third MOSFETs are gated simultaneously after the first MOSFET and then gated off before the first MOSFET such that their entire pulse widths 723, 725 are within the first pulse width 721 of the first signal 720. In this embodiment, the first, second, and third amplitudes 740, 742, 744 produce an output signal 726 whose amplitude 746 is equal to the sum of the first, second, and third amplitudes 740, 742, 744 while the second and third MOSFETs are gated. In this embodiment, the second pulse width 723 and the third pulse width 725 overlap due to their respective T off 732, 734 being equal to and greater than the first T off 730.

[0058] Figure 8A A pulse voltage biasing scheme using waveform 800 in accordance with certain embodiments of the present disclosure is shown. As shown, waveform 800 includes a plurality of pulses 810. The plurality of pulses 810 includes a total pulse width 812. Within the plurality of pulses 810, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 820 having a first pulse width 821, a second signal 822 having a second pulse width 823, and a third signal 824 having a third pulse width 825. Each signal also includes a T off, for example, the first T for the first signal 820 off 830, the second T for the second signal 822 off 832, and the third T for the third signal 824 off 834. Additionally, each signal has its own amplitude, such as the first amplitude 840, the second amplitude 842, and the third amplitude 844.

[0059] In Figure 8A , each MOSFET is sequentially gated and then simultaneously gated off at the end of the pulse. As shown, the first signal 820, the second signal 822, and the third signal 824 have different pulse widths (e.g., 821, 823, and 825 are not equal). Each T off gradually increases (e.g., 834 is greater than 832, and 832 is greater than 830), and in this embodiment, the output voltage amplitude (e.g., the combination of 840, 842, and 844) increases in a stepwise manner as the second and third MOSFETs are gated. For example, when the second MOSFET is gated after T off 832, the first signal 820 and the second signal 822 combine to produce a first output voltage signal 826. The first output voltage signal 826 has an amplitude 843 equal to the sum of the first amplitude 840 and the second amplitude 842. Similarly, when the third MOSFET is gated, the combination of the first signal 820, the second signal 822, and the third signal 824 produces a second output voltage signal 828, whose amplitude 845 is equal to the sum of the first amplitude 840, the second amplitude 842, and the third amplitude 844.

[0060] Figure 8B shows a pulsed voltage biasing scheme using a waveform 850 according to certain embodiments of the present disclosure. As shown, the waveform 850 includes a plurality of pulses 860. The plurality of pulses 860 includes a total pulse width 862. Within the plurality of pulses 860, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 870 having a first pulse width 871, a second signal 872 having a second pulse width 873, and a third signal 874 having a third pulse width 875. Each signal also includes T off , for example, the first T for the first signal 870 off 880, the second T for the second signal 872 off 882, and the third T for the third signal 874 off 884. Additionally, each signal has its own amplitude, such as the first amplitude 890, the second amplitude 892, and the third amplitude 894.

[0061] In Figure 8BAmong them, each MOSFET is simultaneously gated and then sequentially gated and turned off. In this embodiment, the first signal 870, the second signal 872, and the third signal 874 have different pulse widths (for example, 871, 873, and 875 are not equal), and in this embodiment, the output voltage amplitudes (for example, combinations 890, 892, and 894) gradually decrease. For example, all three MOSFETs are gated at the start of the pulse, thereby generating a first output voltage signal 878 by combining the first signal 870, the second signal 872, and the third signal 874. The first output voltage signal has an amplitude 895 equal to the sum of the first amplitude 890, the second amplitude 892, and the third amplitude 894. Since the first output voltage signal is a combination of all three signals 870, 872, and 873, the pulse width of the first output voltage signal is equal to the shortest pulse width among the three signals (for example, the third pulse width 875). When the third MOSFET is gated and turned off, a second output voltage signal 876 is generated by combining the first signal 870 and the second signal 874. The second output voltage signal has an amplitude 893 equal to the sum of the first amplitude 890 and the second amplitude 892. Since the second output voltage 876 is a combination of the first signal 870 and the second signal 872, the pulse width of the second output voltage 876 is equal to the shortest pulse width between the first signal 870 and the second signal 872 (for example, the second pulse width 873).

[0062] Figure 9 is a process flow diagram showing a method 900 for etching using a pulse waveform. In operation 910, a plasma 101 is generated in the chamber body 124. In operation 920, a pulsed DC voltage 153 is applied to the plasma 101 using a bias electrode 104 capacitively coupled to the plasma 101 through a dielectric layer 105B.

[0063] Applying a pulsed DC voltage in operation 920 may include using a DC voltage source (e.g., DC voltage source 210) connected to a first capacitor (e.g., first capacitor 220) via its positive terminal and a first diode (e.g., first diode 230), the positive terminal of the DC voltage source (e.g., DC voltage source 210) being further connected to a first resistor (e.g., first resistor 240), a first MOSFET (e.g., first MOSFET 250), and a first blocking diode (e.g., first blocking diode 270). A second capacitor (e.g., second capacitor 222) may be connected in series between the first diode (e.g., first diode 230) and ground (e.g., ground 228). The DC voltage source (e.g., DC voltage source 210) may also be coupled to a second diode (e.g., second diode 232) connected in series between the second capacitor (e.g., second capacitor 222) and ground (e.g., ground 228). A second resistor (e.g., second resistor 242) may be connected at the common point of the first diode (e.g., first diode 230) and the second capacitor (e.g., second capacitor 222). A second MOSFET (e.g., second MOSFET 252), a second gate voltage source (e.g., second gate voltage source 262) connected to the gate terminal of the second MOSFET (e.g., second MOSFET 252), and a second blocking diode (e.g., second blocking diode 272) connected to the source terminal (e.g., 253) of the second MOSFET (e.g., second MOSFET 252) may be connected in series to the second resistor (e.g., second resistor 242). Additionally, a third resistor (e.g., third resistor 244) may be connected at the common point of the second diode (e.g., second diode 232) and a third capacitor (third capacitor 224) between the second diode (e.g., second diode 232) and the third capacitor (e.g., third capacitor 224). A third MOSFET (e.g., third MOSFET 254), a third gate voltage source (e.g., third gate voltage source 264), and a third blocking diode (e.g., third blocking diode 274) may also be connected in series with the third resistor (e.g., third resistor 244), wherein the cathode of the third blocking diode (e.g., third blocking diode 274) is connected to a bias electrode (e.g., bias electrode 104). When all the MOSFETs are gated simultaneously and the gate signal widths are the same, the full supply voltage will be applied to the load.

[0064] In operation 920, applying a pulsed DC voltage source (e.g., DC voltage source 210) may further include switching a first MOSFET (e.g., first MOSFET 250) to an on state for a first duration (e.g., first duration 620), switching a second MOSFET (e.g., second MOSFET 252) to an on state for a second duration (e.g., second duration 622), and switching a third MOSFET (e.g., third MOSFET 254) to an on state for a third duration (e.g., third duration 624). In some embodiments, the first duration (e.g., first duration 420), the second duration (e.g., second duration 622), the third duration (e.g., third duration 624), or a combination of the foregoing terms may overlap. Alternatively, the first duration (e.g., first duration 620), the second duration (e.g., second duration 422), and the third duration (e.g., third duration 624) may not overlap. In operation 920, a first gate voltage source (e.g., first gate voltage source 260) may provide a first T off (e.g., first T off 630), a second gate voltage source (e.g., second gate voltage source 262) may provide a second T off (e.g., second T off 632), and a third gate voltage source (e.g., third gate voltage source 264) may provide a third T off (e.g., third T off634). In operation 920, the first MOSFET (e.g., the first MOSFET 250) receives a first strobe signal from the first gate voltage source (e.g., the first gate voltage source 260), where the first strobe signal has a first pulse width (e.g., the first pulse width 620). Additionally, the second MOSFET (e.g., the second MOSFET 252) may receive a second strobe signal from the second gate voltage source (e.g., the second gate voltage source 262), where the second strobe signal has a second pulse width (e.g., the second pulse width 622). Additionally, the third MOSFET (e.g., the third MOSFET 254) may receive a third strobe signal from the third gate voltage source (e.g., the third gate voltage source 264), where the third strobe signal has a third pulse width (e.g., the third pulse width 624). In some embodiments, the first pulse width (e.g., the first pulse width 620), the second pulse width (e.g., the second pulse width 622), and the third pulse width (e.g., the third pulse width 624) are different. The memory 134, the CPU 133, and the support circuitry 135 of the system controller 126 may implement the method 900 in the embodiments of the present disclosure. In operation 930, the substrate 103 is etched in the chamber body 124 using the pulsed DC voltage 153 applied to the plasma 101.

[0065] The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered to be coupled to each other—even if objects A and C do not directly physically contact each other. For example, a first object may be coupled to a second object even if the first object has never directly physically contacted the second object.

[0066] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisioned without departing from its basic scope, and its scope is determined by the following claims.

Claims

1. A system for reactive ion etching, comprising: A chamber body; A substrate holder, within the chamber body; A bias electrode, within the substrate holder; And A bias voltage source configured to supply a pulsed bias voltage to the bias electrode, the bias voltage source comprising: A DC voltage source; A first capacitor, connected to the DC voltage source; Ground; A first diode, connected in series between the first capacitor and ground; A first resistor, connected to the DC voltage source; A first metal oxide semiconductor field effect transistor, connected in series with the first resistor; A first gate voltage source, connected to the gate of the first metal oxide semiconductor field effect transistor; A first blocking diode, connected to the source of the first metal oxide semiconductor field effect transistor; A second capacitor, connected in series between the first diode and ground; A second diode, connected in series between the second capacitor and ground; A second resistor, connected between the first diode and the second capacitor; A second metal oxide semiconductor field effect transistor, connected in series with the second resistor; A second gate voltage source, connected to the gate of the second metal oxide semiconductor field effect transistor; and A second blocking diode, connected to the source of the second first metal oxide semiconductor field effect transistor.

2. The system according to claim 1, wherein the bias voltage source further comprises a third capacitor, the third capacitor being connected in series between the second diode and ground.

3. The system according to claim 2, wherein the bias voltage source further comprises a third resistor, a third metal oxide semiconductor field effect transistor, a third gate voltage source, and a third blocking diode, the third resistor being connected in parallel with the third capacitor, the third metal oxide semiconductor field effect transistor being connected in series with the third resistor, the third gate voltage source being connected to the gate terminal of the third metal oxide semiconductor field effect transistor, and the third blocking diode being connected to the source terminal of the third metal oxide semiconductor field effect transistor.

4. The system according to claim 1, wherein the bias electrode is electrically coupled to the second blocking diode of the bias voltage source.

5. The system according to claim 2, wherein the anode of the first blocking diode is connected to the source of the first metal oxide semiconductor field effect transistor.

6. The system according to claim 3, wherein the cathode of the first blocking diode is connected to the cathode of the second blocking diode.

7. The system according to claim 6, wherein the cathode of the third blocking diode is connected to the cathode of the first blocking diode and the cathode of the second blocking diode.

8. The system according to claim 7, wherein the cathode of the third blocking diode, the cathode of the second blocking diode, and the cathode of the third blocking diode are connected to the bias electrode.

9. The system according to claim 1, the system further comprising a controller configured to cause the bias voltage source to transmit pulses to the bias electrode, the pulses comprising a plurality of signals, and the plurality of signals comprising different pulse widths or different amplitudes.

10. The system according to claim 9, wherein the plurality of signals further comprises different off-times.

11. A method for etching using a pulse waveform, the method comprising: generating a plasma in a chamber body; applying a pulsed DC voltage to the plasma using a bias electrode capacitively coupled to the plasma through a dielectric layer, wherein the pulsed DC voltage comprises a plurality of pulses, each of the plurality of pulses further comprising a plurality of signals, and wherein each of the plurality of signals has an off-time, a pulse width, and an amplitude; and etching a substrate in the chamber body using the pulsed DC voltage applied to the plasma.

12. The method according to claim 11, wherein two or more of the off-time, the pulse width, and the amplitude of the plurality of signals are different.

13. The method according to claim 12, wherein applying the pulsed DC voltage comprises using a DC voltage source connected to a first capacitor and a first diode, the DC voltage source being further connected in parallel to a first resistor, a first metal oxide semiconductor field effect transistor, a first gate voltage source, and a first blocking diode, the first gate voltage source being connected to the gate of the first metal oxide semiconductor field effect transistor.

14. The method according to claim 13, wherein the DC voltage source is connected in series to a second capacitor, a second diode, a second resistor, a second metal oxide semiconductor field effect transistor, a second gate voltage source, and a second blocking diode, the second capacitor being connected in series between the first diode and ground, the second diode being connected in series between the second capacitor and ground, the second resistor being connected in parallel to the second capacitor, the second metal oxide semiconductor field effect transistor being connected in series to the second resistor, the second gate voltage source being connected to the gate terminal of the second metal oxide semiconductor field effect transistor, and the second blocking diode being connected to the source terminal of the second metal oxide semiconductor field effect transistor.

15. The method according to claim 14, wherein applying the pulsed DC voltage source further comprises switching the first metal oxide semiconductor field effect transistor to conduction for a first duration, and switching the second metal oxide semiconductor field effect transistor to conduction for a second duration.

16. The method according to claim 15, wherein the first duration and the second duration do not overlap.

17. The method according to claim 14, wherein the first gate voltage source comprises a first off-time, and the second gate voltage source comprises a second off-time.

18. The method according to claim 14, wherein the first metal-oxide semiconductor field-effect transistor receives a first strobe signal from the first gate voltage source, the first strobe signal having a first pulse width, and wherein the second metal-oxide semiconductor field-effect transistor receives a second strobe signal from the second gate voltage source, the second strobe signal having a second pulse width.

19. A pulsed signal source device for etching, comprising: a controller; a bias electrode; and a bias voltage source configured to supply a pulsed bias voltage to the bias electrode, the bias voltage source comprising: a DC voltage source; a first capacitor connected in series with the DC voltage source; a first diode connected to the first capacitor; ground connected in series with the first diode; a first resistor connected in parallel with the first capacitor; a first metal-oxide semiconductor field-effect transistor connected in series with the first resistor; a first gate voltage source connected to the gate terminal of the first metal-oxide semiconductor field-effect transistor; a second capacitor connected in series between the first diode and ground; a second diode connected in series between the second capacitor and ground; a second resistor connected in parallel with the second capacitor; a second metal-oxide semiconductor field-effect transistor connected in series with the second resistor; a second gate voltage source connected to the gate terminal of the second metal-oxide semiconductor field-effect transistor; a second blocking diode connected to the source terminal of the second metal-oxide semiconductor field-effect transistor; a third capacitor connected in series between the second diode and ground; a third resistor connected in parallel with the third capacitor; a third metal-oxide semiconductor field-effect transistor connected in series with the third resistor; a third gate voltage source connected to the gate terminal of the third metal-oxide semiconductor field-effect transistor; and a third blocking diode connected to the source terminal of the third metal-oxide semiconductor field-effect transistor.

20. The pulsed signal source device according to claim 19, wherein the controller causes the first metal-oxide semiconductor field-effect transistor to receive a first strobe signal from the first gate voltage source, the first strobe signal having a first pulse width, wherein the controller causes the second metal-oxide semiconductor field-effect transistor to receive a second strobe signal from the second gate voltage source, the second strobe signal having a second pulse width, wherein the controller causes the third metal-oxide semiconductor field-effect transistor to receive a third strobe signal from the third gate voltage source, the third strobe signal having a third pulse width, and wherein the first pulse width, the second pulse width, and the third pulse width are different.

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