Contact layer formation by microwave annealing for NMOS devices

Abstract

A method of forming an electrical contact in a semiconductor structure includes performing a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer having a trench within the dielectric layer, the selective deposition process including epitaxially forming a contact layer on the semiconductor region within the trench of the dielectric layer, and performing a microwave annealing process to activate dopants in the epitaxially formed contact layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 432,620, filed on December 14, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming electrical contacts within a semiconductor structure. Background Art

[0004] Multi - gate metal - oxide - semiconductor field - effect transistors (MOSFETs), such as complementary metal - oxide - semiconductor (CMOS) devices, face challenges in terms of manufacturability due to their three - dimensional (3D) design and small size. In n - type MOS (n - MOS) devices, to reduce contact resistivity, a silicon (Si) contact layer doped with phosphorus (P) at a high content (e.g., 3×10 21 cm −3 ) is typically utilized and epitaxially formed at the bottom of a trench contact. However, during epitaxial formation of the contact layer at low temperatures, sufficient diffusion of dopants within the contact layer may be hindered, and thus the activation of dopants is at a low level (e.g., 8×10 10 cm −3 or lower).

[0005] Therefore, there is a need for methods and systems capable of activating dopants in an epitaxially formed contact layer of an n - MOS device. Summary of the Invention

[0006] Embodiments of the present disclosure provide a method for forming an electrical contact in a semiconductor structure. The method includes: performing a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer with trenches therein, the selective deposition process including epitaxially forming a contact layer on the semiconductor region within the trenches of the dielectric layer; and performing a microwave annealing process to activate dopants in the epitaxially formed contact layer.

[0007] Embodiments of the present disclosure also provide a method for forming an electrical contact in a semiconductor structure. The method includes: performing a pre - cleaning process on a semiconductor structure having a semiconductor region and a dielectric layer with trenches therein, the pre - cleaning process including removing contaminants formed on the exposed surface of the semiconductor region within the trenches; performing a cavity shaping process to form a cavity on the exposed surface of the semiconductor region within the trenches; performing a selective deposition process, the selective deposition process including epitaxially forming a contact layer in the cavity of the dielectric layer semiconductor region within the trenches; and performing a microwave annealing process to activate dopants in the epitaxially formed contact layer.

[0008] Embodiments of the present disclosure further provide a processing system. The processing system includes: a first processing chamber; a second processing chamber; and a system controller configured to cause the processing system to perform a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer with trenches therein in the first processing chamber, the selective deposition process including epitaxially forming a contact layer on the semiconductor region within the trenches of the dielectric layer; and performing a microwave annealing process in the second processing chamber to activate dopants in the epitaxially formed contact layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To be able to understand the above features of the present disclosure in detail, the present disclosure briefly summarized above may be described in more detail with reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not considered to limit its scope, as the present disclosure may admit other equally effective embodiments.

[0010] Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0011] Figure 2A is a cross-sectional view of a processing chamber according to one or more embodiments.

[0012] Figure 2B is Figure 2A an enlarged view of a portion of the processing chamber.

[0013] Figure 3 is a cross-sectional view of a processing chamber according to one or more embodiments.

[0014] Figure 4 is a cross-sectional view of a processing system according to one or more embodiments.

[0015] Figure 5 depicts a process flow diagram of a method for forming a contact layer in a semiconductor structure according to a first embodiment of the present disclosure.

[0016] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E are Figure 5 cross-sectional views of portions of the semiconductor structure corresponding to various states of the method.

[0017] Figure 7 depicts an example of the resistivity of a phosphorus (P)-doped silicon (Si) sample as a function of microwave annealing dwell time.

[0018] For ease of understanding, the same reference numerals are used, whenever possible, to identify the same elements common to the figures. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. Detailed Description

[0019] Embodiments described herein provide methods and systems for forming contacts that include an epitaxial layer of a silicon-containing material (e.g., phosphorous-doped silicon) on a selected portion of a structure for forming an n-MOS device (e.g., on an epitaxial surface of silicon). These methods and systems may be particularly applicable for selectively forming an epitaxial layer of silicon that is doped with a P-type dopant (e.g., phosphorous (P)) at a high concentration on an exposed surface of a semiconductor region within an opening or feature (e.g., a contact trench) formed in a dielectric layer in a semiconductor structure that includes a semiconductor region of silicon and a dielectric layer formed thereon. The dopants in the epitaxial layer are activated by microwave annealing, thereby reducing the resistivity of the epitaxial layer.

[0020] Figure 1 is a schematic top view of a multi-chamber processing system 100 in accordance with one or more embodiments of the present disclosure. Processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in processing system 100 may be processed in the various chambers and transferred between the chambers without exposing the substrates to the environment external to processing system 100 (e.g., the ambient atmosphere that may exist in a wafer fab). For example, substrates may be processed in and transferred between various chambers that maintain a low pressure (e.g., less than or equal to about 300 Torr) or a vacuum environment without breaking the low pressure or vacuum environment between the various processes performed on the substrates in processing system 100. Thus, processing system 100 may provide an integrated solution for certain processes of substrates.

[0021] Processing systems that may be suitably modified in accordance with the teachings provided herein include Endura ® , Producer ® or Centura ® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc. of Santa Clara, California, USA. It is contemplated that other processing systems (including processing systems from other manufacturers) may be adapted to benefit from the aspects described herein.

[0022] In Figure 1In the example, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 can be adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of the corresponding factory interface robot 134, and the blade is adapted to transfer the substrate from the factory interface 102 to the load lock chambers 104, 106.

[0023] The load lock chambers 104, 106 have corresponding ports 140, 142 connected to the factory interface 102 and corresponding ports 144, 146 connected to the transfer chamber 108. The transfer chamber 108 also has corresponding ports 148, 150 coupled to the holding chambers 116, 118 and corresponding ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has corresponding ports 156, 158 coupled to the holding chambers 116, 118 and corresponding ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, openings with slit valves for the transfer robots 112, 114 to transfer the substrate therethrough and provide a seal between the corresponding chambers to prevent gas from passing between the corresponding chambers. Generally, any port is open for the transfer of the substrate through it. Otherwise, the port is closed.

[0024] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (such as turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the chambers. In the operation process, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 through the port 140 or 142. Then, the gas and pressure control system pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains a low internal pressure or vacuum environment (which can include inert gas) in the transfer chambers 108, 110 and the holding chambers 116, 118. Therefore, the pumping down of the load lock chamber 104 or 106 facilitates the passage of the substrate between the atmospheric environment of, for example, the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0025] When the substrate in the load lock chamber 104 or 106 has been pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 through the port 144 or 146. Then, the transfer robot 112 can transfer the substrate to any one of the processing chambers 120, 122 through the corresponding ports 152, 154 for processing, and transfer the substrate to any one of the holding chambers 116, 118 through the corresponding ports 148, 150 for holding, waiting for further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 through the port 156 or 158, and can transfer the substrate to any chamber among the processing chambers 124, 126, 128, 130 and / or transfer between any chamber among the processing chambers 124, 126, 128, 130 and the holding chambers 116, 118, and hold through the corresponding ports 156, 158 waiting for further transfer. The transfer and holding of the substrate inside and between the chambers can be carried out in a low-pressure or vacuum environment provided by the gas and pressure control system.

[0026] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing the substrate. In some examples, the processing chamber 120 can be capable of performing an etching process, the processing chamber 122 can be capable of performing a cleaning process, the processing chamber 124 can be capable of performing a selective removal process, and the processing chambers 126, 128 can be capable of performing corresponding epitaxial growth processes. The processing chamber 120 can be a Selectra™ etching chamber, available from Applied Materials, Inc., Santa Clara, California, USA. The processing chamber 122 can be a SiCoNi™ pre-cleaning chamber, available from Applied Materials, Inc., Santa Clara, California, USA. The processing chamber 126 or 128 can be a Centura™ Epi chamber commercially available from Applied Materials, Inc., Santa Clara, California, USA. The processing chamber 130 can be a microwave annealing (MWA) chamber.

[0027] The system controller 168 is connected to the processing system 100 for controlling the processing system 100 or its components. For example, the system controller 168 can control the execution of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling the controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 can implement data collection and feedback from each chamber to coordinate the performance of the processing system 100.

[0028] The system controller 168 generally includes a central processing unit 170, a memory 172, and support circuitry 174. The central processing unit 170 can be any form of general-purpose processor suitable for an industrial environment. The memory 172 or non-transitory computer-readable medium can be accessed by the CPU 170 and can be one or more of random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital memory. The support circuitry 174 is connected to the CPU 170 and can include a cache, frequency circuitry, input / output subsystems, power supplies, etc. The various methods disclosed herein can generally be implemented under the control of the CPU 170 by the CPU 170 executing a computer instruction program code stored in the memory 172 (or the memory of a specific processing chamber), for example, as software routines. When the computer instruction program code is executed by the CPU 170, the CPU 170 controls the chamber to perform a processing operation according to the various methods.

[0029] Other processing systems can also be configured differently. For example, more or fewer processing chambers can be coupled to the transfer device. In the example shown, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0030] Figure 2A is a cross-sectional view of a processing chamber 200 according to one or more embodiments, which is adapted to perform a pre-cleaning process detailed below. The processing chamber 200 can be Figure 1 the processing chamber 122 shown in Figure 2B is Figure 2A an enlarged view of a portion of the processing chamber 200 in

[0031] The processing chamber 200 can be particularly used to perform heat- or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at the upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum pump port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling the processes within the processing chamber 200.

[0032] The cover assembly 204 includes stacked components and is adapted to provide precursor gas and / or plasma to the processing region 214 within the processing chamber 200. The first plate 216 is coupled to the second plate 218. The third plate 220 is coupled to the second plate 218. The cover assembly 204 may be coupled to a power source (not shown) for supplying plasma to the tapered chamber 222 formed in the cover assembly 204. The cover assembly 204 may also be coupled to a remote plasma source 224 that generates plasma upstream of the cover stack. The remote plasma chamber (e.g., Figure 2A - 2B the processing region 214, the first plate 216, and the second plate 218 therein) is coupled to a gas source 226 by the remote plasma source 224 (or, in the absence of the remote plasma source 224, the gas source 226 is directly coupled to the cover assembly 204). The gas source 226 may include a gas source adapted to provide helium, argon, or other inert gas. In certain configurations, the gas provided by the gas source 226 may be energized into plasma and supplied to the cover assembly 204 using the remote plasma source 224. In another embodiment, the gas source 226 may provide processing gases that may be activated by the remote plasma source 224 before being introduced to the substrate surface disposed within the processing chamber 200. Referring to Figure 2B , the tapered chamber 222 has an opening 228 that allows the shaped plasma to flow from the remote plasma source 224 to the space 230 formed in the fourth plate 232 of the cover assembly 204.

[0033] In certain configurations of the cover assembly 204, plasma occurs within the tapered chamber 222 by applying energy from a plasma source. In one example, energy may be provided by biasing the cover assembly 204 to capacitively couple radio frequency, very high frequency, and / or ultra-high frequency energy to the gas disposed within the tapered chamber 222. In this configuration of the cover assembly 204, the remote plasma source 224 may not be used or may not be installed within the cover assembly 204.

[0034] A central conduit 234 formed in the fourth plate 232 is adapted to provide the material generated by the plasma provided from the volume 230 to a mixing chamber 238 formed in the sixth plate 240 of the cover assembly 204 through the fifth plate 236. The central conduit 234 communicates with the mixing chamber 238 through an opening 242 in the fifth plate 236. The diameter of the opening 242 may be less than, greater than, or equal to the diameter of the central conduit 234. In Figure 2B the embodiment, the diameter of the opening 242 is the same as the diameter of the central conduit 234.

[0035] The fourth plate 232 also includes inlets 244 and 246 that are adapted to supply gas to the mixing chamber 238. Inlet 244 is connected to a first gas source 248, and inlet 246 is connected to a second gas source 250. The first gas source 248 and the second gas source 250 may include process gases as well as inert gases, such as inert gases like argon and / or helium used as carrier gases. The first gas source 248 may include ammonia (NH3) and argon (Ar). The second gas source 250 may contain a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) and argon (Ar).

[0036] As Figure 2B shown, in some configurations, inlet 244 is connected to the mixing chamber 238 through a cylindrical channel 252 (shown in dashed lines) and a hole 254 formed in the fifth plate 236. Inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in dashed lines) and a hole 258 formed in the fifth plate 236. The sizes of the holes 254, 258 formed in the fifth plate 236 are generally such that gas can flow into the mixing chamber 238 uniformly, and these gases are provided from their respective gas sources 248, 250. In one configuration, the diameter of hole 258 is less than the opening width defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232. The holes 258 are typically distributed on the circumference of the centerline of the cylindrical channel 256 to enable fluid to flow into the mixing chamber 238 uniformly. In one configuration, the diameter of hole 254 is less than the opening width defined by the opposing sidewalls of the cylindrical channel 252 forming the fourth plate 232. The holes 254 are typically distributed on the circumference of the centerline of the cylindrical channel 252 to enable fluid to flow into the mixing chamber 238 uniformly.

[0037] Inlets 244 and 246 provide corresponding fluid flow paths that traverse the fourth plate 232 laterally, turn to the fifth plate 236, and pass through the fifth plate 236 to reach the mixing chamber 238. The cover assembly 204 also includes a seventh plate or a first gas distributor 260, which may be a gas distribution plate, such as a showerhead, through which the various gases mixed in the cover assembly 204 flow through the perforations 262 formed therein. The perforations 262 are in fluid communication with the mixing chamber 238 to provide a gas flow path from the mixing chamber 238 through the first gas distributor 260. Please refer back to Figure 2A , below the cover assembly 204, a baffle plate 264 and a second gas distributor 266 are provided, and the second gas distributor 266 may be a gas distribution plate, such as a showerhead.

[0038] Alternatively, different cleaning processes can also be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) can be introduced into the processing chamber 200 through the lid assembly 204, while ammonia (NH3) can be directly injected into the processing chamber 200 through a separate gas inlet 268, which is disposed on one side of the chamber body 202 and coupled to a gas source (not shown).

[0039] The susceptor assembly 206 can include a substrate susceptor 270 for supporting the substrate 272 thereon during the processing operation. The substrate susceptor 270 can be coupled to an actuator 274 through a shaft 276, and the shaft 276 passes through a central opening formed at the bottom of the chamber body 202. The actuator 274 can be flexibly sealed to the chamber body 202 through a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 can vertically move the substrate susceptor 270 between a processing chamber position and a loading position within the chamber body 202. The loading position is slightly lower than the opening of a channel (not illustrated) formed on the sidewall of the chamber body 202.

[0040] The substrate susceptor 270 has a flat or substantially flat substrate support surface for supporting the substrate 272 to be processed thereon. The substrate susceptor 270 can be vertically moved within the chamber body 202 by the actuator 274, and the actuator 274 is coupled to the substrate susceptor 270 through the shaft 276. For certain processing operations, the substrate susceptor 270 can be lifted to a position close to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated by radiation emitted by the second gas distributor 266 or another radiation source, or by convection or conduction of an intermediate gas through the second gas distributor 266. In certain process steps, the substrate can be placed on the lift rod 278 to perform additional heat treatment operations, such as performing an annealing step.

[0041] Figure 3 is a cross-sectional view of a processing chamber 300 according to one or more embodiments, which is adapted to perform an epitaxial (Epi) deposition process detailed below. The processing chamber 300 can be Figure 1 the processing chamber 126 or 128 shown in

[0042] The processing chamber 300 includes a housing structure 302, which is made of a resistive material, such as aluminum or stainless steel, such as 316L stainless steel. The housing structure 302 encloses various functional elements of the processing chamber 300, such as a quartz chamber 304, which includes an upper quartz chamber 306 and a lower quartz chamber 308, and the lower quartz chamber 308 houses a processing space 310. Active species are provided to the quartz chamber 304 through a gas distribution assembly 312, and processing by-products are discharged from the processing space 310 through an outlet 314, which is generally in communication with a vacuum source (not shown).

[0043] The substrate support 316 is adapted to receive a substrate 318 that is transferred into the processing space 310. The substrate support 316 is arranged along the longitudinal axis 320 of the processing chamber 300. The substrate support 316 can be made of a ceramic material or a graphite material coated with a silicon material such as silicon carbide or other resistive materials. Active species from precursor reactants are applied to the surface 322 of the substrate 318, and by-products can subsequently be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing space 310 can be provided by radiation sources such as the upper lamp module 324A and the lower lamp module 324B.

[0044] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. The non-thermal energy or radiation of the lamp modules 324A and 324B passes through the upper quartz window 326 of the upper quartz chamber 306 and through the lower quartz window 328 of the lower quartz chamber 308. If needed, the cooling gas for the upper quartz chamber 306 enters through the inlet 330 and exits through the outlet 332. The precursor reactants as well as the dilution gas, purge gas, and vent gas for the processing chamber 300 enter through the gas distribution assembly 312 and exit through the outlet port 314. Although the upper quartz window 326 is shown as arcuate or convex, the upper quartz window 326 can be planar or concave since the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0045] The low-wavelength radiation in the processing space 310 is used to excite the active species and assist in the adsorption of reactants and the desorption of by-products from the surface 322 of the substrate 318, which generally ranges from about 0.8 µm to about 1.2 µm, for example, between about 0.95 µm and about 1.05 µm, and various combinations of wavelengths can be provided, for example, depending on the composition of the film being epitaxially grown.

[0046] The component gases enter the processing space 310 through the gas distribution assembly 312. The gases flow out of the gas distribution assembly 312 and exit through the outlet port 314, as shown by the flow path 334. The combination of component gases for cleaning / passivating the substrate surface or forming a silicon- and / or germanium-containing epitaxial film is typically mixed before entering the processing space 310. The overall pressure in the processing space 310 can be adjusted by a valve (not shown) on the outlet port 314. At least a portion of the inner surface of the processing space 310 is covered by a liner 336. In one embodiment, the liner 336 includes an opaque quartz material. In this way, the chamber wall is thermally insulated from the heat in the processing space 310.

[0047] The temperature of the surface in the processing space 310 can be controlled within a temperature range of about 200 °C to about 600 °C or higher by the flow rate of the cooling gas, which enters from the inlet 330 and exits from the outlet 332, in combination with the radiation from the upper lamp module 324A located above the upper quartz window 326. The temperature in the lower quartz chamber 308 can be controlled within a temperature range of about 200 °C to about 600 °C or higher by adjusting the speed of a blower device (not shown) and by the radiation from the lower lamp module 324B disposed below the lower quartz chamber 308. The pressure in the processing space 310 can be between about 0.1 Torr and about 600 Torr, for example, between about 5 Torr and about 30 Torr.

[0048] The temperature on the surface 322 of the substrate 318 can be controlled by adjusting the power of the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power of both the upper lamp module 324A covering the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing space 310 can be between about 40 W / cm 2 to about 400 W / cm 2 and, for example, between about 80 W / cm 2 to about 120 W / cm 2 .

[0049] In one aspect, the gas distribution assembly 312 is disposed normal to the longitudinal axis 320 or the radial direction 338 of the processing chamber 300 or the substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow the processing gas across or parallel to the surface 322 of the substrate 318 in the radial direction 338. In an applicator application, the processing gas is preheated at the location where it is introduced into the processing chamber 300 in order to initiate gas preheating and / or break specific bonds in the gas before it is introduced into the processing space 310. In this way, the surface reaction kinetics can be modified independently of the thermal temperature of the substrate 318.

[0050] In operation, precursors for forming silicon (Si) and silicon germanium (SiGe) blanket or selective epitaxial films are provided from one or more gas sources 340A and 340B to the gas distribution assembly 312. An IR lamp 342 ( Figure 3 only one is shown therein) can be used to heat the precursors within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B can be coupled to the gas distribution assembly 312 in such a way as to facilitate the introduction zones (such as the radially outer zones and the radially inner zones between these outer zones as viewed from a top view) within the gas distribution assembly 312. The gas sources 340A, 340B can include valves (not shown) for controlling the rate of introduction into the zones.

[0051] The gas sources 340A, 340B may include silicon precursors such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher-order silanes, their derivatives, and combinations thereof. The gas sources 340A, 340B may also include germanium-containing precursors such as germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), their derivatives, and combinations thereof. The silicon- and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine gas (Cl2), hydrogen bromide (HBr), and combinations thereof. The gas sources 340A, 340B may include one or more silicon- and germanium-containing precursors in one or both of the gas sources 340A, 340B.

[0052] The precursor enters the processing space 310 through the openings or holes 344 in the perforated plate 346 ( Figure 3 only one is shown in the figure) in this excited state. In one embodiment, the perforated plate 346 is made of quartz material, and the holes 344 are formed thereon. The perforated plate 346 is transparent to infrared energy and can be made of transparent quartz material. In other embodiments, the perforated plate 346 can be any material that is transparent to infrared energy and can resist the processing chemicals and other processing chemicals. The energized precursor material flows through the holes 344 in the perforated plate 346 into the processing space 310 and through the channel 348 ( Figure 3 only one is shown in the figure). Part of the photons and non-thermal energy from the IR lamp 342 also pass through the holes 344, the perforated plate 346, and the channel 348 with the facilitation of the reflective material and / or surface provided on the inner surface of the gas distribution assembly 312, thereby illuminating the flow path 334 of the precursor. In this way, the vibrational energy of the precursor can be maintained along the flow path from the point where it is introduced into the processing space 310.

[0053] Figure 4 is a cross-sectional view of the processing system 400. According to one or more embodiments, the processing system 400 includes a processing chamber 402 that is adapted to perform the microwave annealing process detailed below. The processing chamber 402 can be Figure 1 the processing chamber 130 shown in the figure.

[0054] The processing chamber 402 includes a chamber body 404. The chamber body 404 at least partially defines a processing space 406. In some embodiments, the chamber body 404 includes a top wall 408 (such as a top plate or a cover), a bottom wall 410 (such as a floor) opposite to the top wall 408, a first side wall 412 coupling the top wall 408 and the bottom wall 410, and a second side wall 414 opposite to the first side wall 412. The chamber body 404 can be or include any material suitable for the processing process performed in the processing chamber 402. For example, materials suitable for the chamber body 404 include aluminum, stainless steel, ceramic materials, or combinations thereof.

[0055] The processing system 400 further includes a microwave source 416. The microwave source 416 can be continuous or pulsed. The microwave source 416 can be coupled to the chamber body 404 through a waveguide 418. The electromagnetic energy generated by the microwave source 416 can be fed into the processing space 406 from the waveguide emission port 420, which is fluidly coupled to the processing space 406 through the waveguide 418. Although Figure 4 the waveguide emission port 420 is shown disposed along the first side wall 412 of the chamber body 404, the waveguide emission port 420 can also be disposed at other locations, such as the bottom wall 410, the second side wall 414, the top wall 408, or a combination of different locations.

[0056] At least one substrate support base 422 is disposed in the processing space 406 to support one or more substrates 424 thereon during the processing process. The substrate 424 can be brought into the processing space 406 through a loading port 426. The substrate 424 can include a main surface 428 on which devices are formed and / or depositions are performed. The substrate support base 422 can be any support base for fixing one or more semiconductor substrates and can include components for physically positioning and fixing the substrate, such as an electrostatic chuck, a fixing clamp, an edge ring, a guiding pin, etc. In some embodiments, the substrate support base 422 is configured to rotate during the processing process. In some embodiments, the substrate support base 422 includes additional components for processing the substrate 424, such as an electrode for supplying DC or RF bias power, a system for uniformly supplying or removing heat from the surface of the substrate 424 or the substrate support base 422, or similar components.

[0057] In some embodiments, the processing system 400 further includes a substrate temperature sensor 430. The substrate temperature sensor 430 can be embedded in the substrate support base 422. The substrate temperature sensor 430 is connected to a system controller 432. In some embodiments, the substrate temperature monitored by the substrate temperature sensor 430 is used to control the operation of the microwave source 416 according to the monitored substrate temperature. A pyrometer (not shown) can be used to measure the radiation emitted by the substrate 424 through a hole at the upper end of the chamber body 202.

[0058] In some embodiments, the microwave source 416 is positioned to heat the entire substrate 424. The microwave source 416 can be positioned to transmit electromagnetic energy 434 parallel to the main surface 428 of the substrate 424 positioned on the substrate support base 422.

[0059] In some embodiments, the microwave source 416 is a microwave generator that can generate fixed-frequency or variable-frequency microwaves. The microwaves generated in the microwave generator are fed into the processing space 406 through the waveguide emission port 420 from the waveguide 418. In one embodiment, the provided microwave frequency is in the range of approximately 1 GHz to approximately 30 GHz. In another embodiment, the frequency of the fed microwaves is in the range of about 1 GHz to about 10 GHz, or in the range of about 2 GHz to about 5 GHz, such as 2.45 GHz. However, other applicable frequencies can also be used. The power of the microwaves can be in the range of about 1000 watts to about 7000 watts, or in the range of about 1000 watts to about 3000 watts. In one example, the microwave generator outputs up to 20 kilowatts of power at a frequency of about 2.54 gigahertz (GHz).

[0060] The system controller 432 can control the phase, frequency, and other parameters of the transmitted electromagnetic energy 434. For example, in some embodiments where the microwave source 416 is a microwave signal generator, the system controller 432 can control the phase, frequency, and other parameters of the microwave signal output by the microwave signal generator.

[0061] In some embodiments, the processing system 400 further includes a phase frequency detector 436 for detecting the phase and / or frequency of the electromagnetic energy 434 emitted by the microwave source 416. The phase frequency detector 436 can be connected to the microwave source 416 and the system controller 432. The phase frequency detector 436 can be used for feedback processing, where the phase frequency detector 436 detects the phase, frequency, and / or other parameters of the transmitted electromagnetic energy 434, and the system controller 432 adjusts the microwave source 416 according to the input of the phase frequency detector 436.

[0062] In some embodiments, the processing system 400 further includes a gas supplier 438. The gas supplier 438 may be fluidly coupled to the processing space through a gas inlet 440. The gas supplier 438 provides one or more suitable processing gases (such as annealing gas, deposition gas, etching gas, cleaning gas or similar gases) for processing the substrate 424 and / or maintaining the processing space 406. These gases can be reactive, such as precursors for deposition processes, or non-reactive, such as inert gases commonly used in conventional heat treatment processes. In a processing operation, the processing space 406 in which the substrate 424 is located may be evacuated or may contain a gas suitable for the target processing operation. In one embodiment, the gas supplier 438 includes a plurality of gas sources for supplying one or more processing gases to the processing space 406. Each processing gas may be supplied independently or in combination with other processing gases. For simplicity, other components for controlling the gas flow rate to the processing space 406, such as flow controllers, valves or similar components, are not shown.

[0063] In some embodiments, the execution of the system controller 432 facilitates the control and automation of aspects such as thermal annealing techniques, method 500, and the processing system 400. The system controller 432 facilitates the control and automation of the processing system 400 and may include a central processing unit (CPU), a memory, and support circuitry (or I / O). The CPU may be one of any form of computer processor used in an industrial environment to control various processing operations and hardware (such as conventional electromagnetic radiation detectors, motors, laser hardware, microwave hardware), and to monitor processing operations (such as substrate temperature, substrate support temperature, energy from a microwave source, energy from a pulsed laser, detector signals). Software instructions and data may be encoded and stored in the memory for instructing the central processing unit. The system controller 432 may communicate with one or more components of the processing system 400 through, for example, a system bus. Programs (or computer instructions) readable by the system controller 432 determine which tasks may be performed on the substrate. In some embodiments, the program is software readable by the controller and includes program code for monitoring and controlling substrate position, the amount of energy transfer in the emitted continuous electromagnetic energy, the amount of energy transfer in each electromagnetic pulse, the timing of one or more electromagnetic pulses, the intensity and wavelength of each pulse as a function of time, the temperature of various regions of the substrate, or any combination thereof. Although the system controller 432 is shown as a single system controller, it should be understood that the embodiments described herein may use multiple system controllers.

[0064] In some embodiments, the processing system 400 further includes an exhaust system 442. In one embodiment, the exhaust system 442 is coupled to the processing chamber 402 through an exhaust port 444. The exhaust system 442 can be coupled to the processing chamber 402 at any suitable location for exhausting the processing space 406, such as along the bottom wall 410 of the chamber body 404, as Figure 4 shown. For example, depending on the chamber design and considerations of the processing gas flow, the exhaust port 444 can be located at any suitable location in the processing chamber 402, such as in the side walls 412, 414 of the processing chamber 402, below the top or bottom surface of the substrate support base 422, in the top wall 408 of the processing chamber 402, in the bottom wall 410 of the processing chamber 402, or any other suitable location.

[0065] Figure 5 FIG. 500 is a process flow diagram of a method 500 for forming a contact layer in a semiconductor structure 600 formed on a substrate according to an embodiment of the present disclosure. Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E FIGS. 501-505 are cross-sectional views of a portion of the semiconductor structure 600 corresponding to various states of the method 500. It should be understood that Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E only illustrate partial schematic views of the semiconductor structure 600, and the semiconductor structure 600 can include any number of transistor portions and additional materials having the aspects shown in the figures. It should also be noted that although Figure 5 the methods illustrated in FIGS. 501-505 are described sequentially, including one or more operations that have been omitted and / or added, and / or other process sequences that have been rearranged in another desired order, all fall within the scope of the embodiments of the present disclosure provided herein.

[0066] As used herein, the term "substrate" refers to a material layer that serves as a basis for subsequent processing operations, including the surface to be cleaned. The substrate can be a silicon-based material or any suitable insulator material or conductive material as needed. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, doped silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0067] As Figure 6AAs shown, semiconductor structure 600 includes a semiconductor region 602 formed on a substrate (not shown). The semiconductor region 602 may be formed of a first material such as silicon (Si), and is doped with an n-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb) at a concentration between about 10 19 cm −3 and 5×10 21 cm −3 .

[0068] Semiconductor structure 600 further includes a dielectric layer 604 having a trench 606 formed in the semiconductor region 602. The dielectric layer 604 may be formed of a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0069] The semiconductor region 602 and the dielectric layer 604 may be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The trench 606 may be formed by patterning techniques such as lithography and etching processes.

[0070] Method 500 starts with a pre-clean process in block 510. The pre-clean process may be performed in an etch chamber, such as the processing chamber 122 shown in Figure 1 or the processing chamber 200 shown in Figure 2. The pre-clean process in block 510 may be performed in a non-break vacuum environment in a multi-chamber processing system, such as Figure 1 the multi-chamber processing system 100 shown.

[0071] The pre-clean process can remove contaminants, such as a native oxide layer, or pattern residues (such as fluorocarbons) formed on the exposed surface of the semiconductor region 602 within the trench 606. The pre-clean process is used to prepare the exposed surface of the semiconductor region 602 within the trench 606, on which an epitaxial layer can be formed in a subsequent epitaxial deposition process.

[0072] The pre-clean process may include an anisotropic remote plasma-assisted dry etching process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluent is directed to bombard and remove the remaining dielectric layer within the trench 606.

[0073] The pre-clean process may include an isotropic plasma etching process, such as a SiCoNi™ dry chemical etching process, using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. The dry chemical etching process is selective to the silicon oxide layer and thus is not likely to etch silicon, germanium, or silicon nitride layers, whether these layers are amorphous, crystalline, or polycrystalline. The dry chemical etching process has a selectivity of at least about 3:1 for silicon oxide to silicon or germanium, typically 5:1 or better, and sometimes 10:1. The dry chemical etching process also has a high selectivity for oxide to nitride. The selectivity of the dry chemical etching process relative to nitride is at least about 3:1, typically 5:1 or better, and sometimes 10:1.

[0074] The pre-clean process may include an inductively coupled plasma (ICP) etching process using a plasma formed from a gas including chlorine (Cl2) and hydrogen (H2) and a carrier gas including argon (Ar) and helium (He).

[0075] In block 520, as Figure 6B shown, a cavity shaping process is performed to form a cavity 602A on the exposed surface of the semiconductor region 602 within the trench 606. The cavity shaping process may be performed in an etching chamber, such as Figure 1 the processing chamber 120 shown. The cavity shaping process in block 520 may be performed in a multi-chamber processing system, such as Figure 1 the multi-chamber processing system 100 shown, without breaking the vacuum environment.

[0076] The cavity shaping process in block 520 includes an etching process using an etching gas including a halogen-containing gas such as chlorine (Cl2), hydrogen chloride (HCl), or hydrogen fluoride (HF), and a carrier gas such as argon (Ar) or helium (He).

[0077] The cavity 602A may have a V shape, a U shape, or any other shape, with a width between about 5 nm and about 15 nm and a depth between about 5 nm and about 15 nm, and expands the contact area between the semiconductor region 602 and the contact plug to be formed within the trench 606 to minimize parasitic resistivity and thus improve device performance.

[0078] In block 530, as Figure 6C shown, a selective epitaxial deposition process is performed to epitaxially form a contact layer 608 in the cavity 602A of the semiconductor region 602 within the trench 606. The selective epitaxial deposition chamber process may be performed in an epitaxial chamber, such as Figure 1 the processing chamber 126 or 128 shown, or Figure 3The processing chamber 300 shown. The selective epitaxial deposition process in block 530 can be performed in a multi-chamber processing system without breaking the vacuum environment, such as Figure 1 the multi-chamber processing system 100 shown.

[0079] The contact layer 608 is formed as an interface between the semiconductor region 602 and the metal contact plug to be formed in the trench 606 to minimize the parasitic resistivity. The contact layer 608 can be formed of a second material, such as silicon (Si), doped with an n-type dopant at a concentration between about 10 19 cm −3 and 5×10 21 cm −3 such as phosphorus (P), arsenic (As), or antimony (Sb), depending on the desired conductive characteristics of the contact layer 608.

[0080] In some embodiments, the selective epitaxial deposition process includes a deposition process and an etching process. The deposition process is an epitaxial deposition process. The selectivity in the selective epitaxial deposition process may result from the difference in the nucleation of the second material on the exposed surface of the semiconductor region 602 (such as silicon (Si)) and the nucleation on the exposed surface of the dielectric layer 604 (such as silicon dioxide (SiO2) or silicon nitride (Si3N4)). The nucleation rate on the exposed surface of the semiconductor region 602 (such as silicon (Si)) may be faster compared to the exposed surface of the dielectric layer 604 (such as silicon dioxide (SiO2) or silicon nitride (Si3N4)), so in the semiconductor region 602 (such as silicon (Si)), when the semiconductor structure 600 is exposed to the deposition gas during the deposition process, an amorphous layer of the second material can be formed on the exposed surface of the dielectric layer 604 (such as silicon dioxide (SiO2) or silicon nitride (Si3N4)). In the subsequent etching process, through an appropriate etching gas, the amorphous layer of the second material formed on the exposed surface of the dielectric layer 604 can be removed at a faster rate than the epitaxial layer of the second material formed on the exposed surface of the semiconductor region 602. Therefore, the overall result of combining the deposition process and the etching process can be the epitaxial growth of the second material on the exposed surface of the semiconductor region 602 while minimizing the growth (if any) of the second material on the exposed surface of the dielectric layer 604.

[0081] In some embodiments, the deposition gas includes a silicon-containing precursor and a dopant gas source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10 ), or a combination thereof. The dopant source may include precursor phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), arsine (AsH3), arsenic trichloride (AsCl3), tertiary butylarsine (AsC4H 11), antimony trichloride (SbCl3), Sb(C2H5)5. The etch gas includes an etchant gas and a carrier gas. The etch gas may include a halogen-containing gas such as hydrogen chloride (HCl), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0082] The deposition process and the etch process may be carried out at a low temperature of about 200 °C to about 800 °C and a pressure of 5 Torr to 600 Torr. Due to the low-temperature epitaxial deposition of the contact layer 608 and the high concentration of dopants such as phosphorus (P) (e.g., 3×10 21 cm −3 ), the dopants may be active only at one level (e.g., 8×10 10 cm −3 ) or lower levels in the deposited contact layer 608 in the frame 530. The clustering of dopants in the silicon (Si) lattice defects in the deposited contact layer 608 may cause the dopants to be deactivated. The clustering of the dopants will be separated by a subsequent microwave annealing process to activate the dopants.

[0083] The cycle of the deposition process and the etch process may be repeated as needed to obtain the desired thickness of the contact layer 608. The thickness of the contact layer 608 may be between about 30 Å and about 100 Å.

[0084] In the frame 540, a microwave annealing process is performed to activate the dopants in the contact layer 608. The microwave annealing process may be carried out in a microwave annealing chamber, such as Figure 1 the processing chamber 130 shown or Figure 4 the processing chamber 402 shown. In some embodiments, the microwave annealing process may be performed in an epitaxial chamber, such as Figure 1 the processing chamber 126 or 128 shown, or Figure 3 the processing chamber 300 shown, which is connected to a microwave source through a waveguide, such as Figure 4 the microwave source 416 and the waveguide 418 shown. In a multi-chamber processing system, such as Figure 1 the multi-chamber processing system 100 shown, the microwave annealing process in the frame 540 may be performed without breaking the vacuum environment.

[0085] In the microwave annealing process, the surface of the contact layer 608 is exposed to microwave radiation with a frequency of about 2.54 GHz and thermally annealed by the microwave radiation, and the processing time can reach about 1000 seconds. The microwave power may be higher than 20 kW. The surface of the contact layer 608 may be heated at a temperature of about 700 °C.

[0086] Through a microwave annealing process, dopants (such as phosphorus (P)) in the contact layer 608 deposited in the block 530 may be activated. This activation of the dopants may be due to the cluster separation of the dopants aggregated in the silicon (Si) lattice defects. The clustering of the dopants in the deposited contact layer 608 may cause the dopants to be deactivated. Therefore, separating the clusters of the dopants can activate the dopants and reduce the resistivity. The inventors of the present disclosure have shown that, as Figure 7 shown, by microwave annealing with an annealing dwell time of about 60 seconds, the resistivity of a phosphorus (P)-doped silicon (Si) sample (a 300-mm silicon wafer doped with phosphorus at a concentration between about 10 20 cm −3 and 510 21 cm −3 is reduced by about 8%. This result indicates that the microwave annealing process activates the dopants.

[0087] In some embodiments, the microwave annealing process is also used to repair the dielectric layer 604 that may be damaged in the selective epitaxial deposition process in the block 530.

[0088] In the block 550, as Figure 6D shown, a blanket deposition process is performed to form a metal layer 610 on the contact layer 608. The blanket deposition process can be performed in a processing chamber different from the epitaxial chamber in the block 530 or the microwave annealing chamber in the block 540, such as Figure 1 the processing chambers 126 or 128 shown in Figure 3 or the processing chamber 300 shown in Figure 1 The blanket deposition process in the block 550 can be carried out in a multi-chamber processing system without breaking the vacuum environment, such as

[0089] The metal layer 610 contacts the contact layer 608 and provides an electrical connection between the contact plug formed in the trench 606 and the semiconductor region 602 while maintaining the electrical connection therebetween. The metal layer 610 can be formed of a metal material, such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), or tantalum (Ta) or their silicides.

[0090] In some embodiments, the metal source may include a precursor that includes titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo) or a combination thereof. The blanket deposition process can be carried out at a temperature of about 300 °C to about 800 °C and a pressure of 1 °Torr to 50 °Torr.

[0091] The blanket deposition process performed in block 550 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or similar processes, at a temperature between about 100 °C and about 300 °C.

[0092] In block 560, a metal filling process is performed to form contact plugs 612 in trenches 606, as Figure 6E shown. The contact plugs 612 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The contact plugs 612 may include a metal having desired functionality. The metal filling process in block 560 may include a chemical vapor deposition (CVD) process using a tungsten precursor (such as WF6) or a cobalt precursor in a processing chamber (such as Figure 1 processing chambers 126 or 128 shown therein).

[0093] After the metal filling process, the semiconductor structure 600 may be planarized by using a chemical mechanical planarization (CMP) process.

[0094] The embodiments described herein provide methods and systems for forming a contact epitaxial layer within a trench on a semiconductor device. The contact trench structure includes metal contact plugs formed within the trench and a contact that forms an interface between the contact plugs and the silicon-based trench in the semiconductor device. The contact layer is formed of silicon doped with a high concentration of n-type dopants (such as phosphorus (P)), and the dopants are activated by microwave annealing, reducing the parasitic resistivity.

[0095] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from its basic scope, the scope of which is determined by the claims that follow.

Claims

1. A method of forming an electrical contact in a semiconductor structure, the method comprising: Performing a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer with a trench therein, the selective deposition process including epitaxially forming a contact layer on the semiconductor region within the trench of the dielectric layer; And Performing a microwave annealing process to activate dopants in the epitaxially formed contact layer.

2. The method of claim 1, wherein The selective deposition process and the microwave annealing process are performed without breaking a vacuum environment.

3. The method of claim 1, wherein The semiconductor region comprises silicon doped with an n-type dopant, and The contact layer comprises silicon doped with an n-type dopant.

4. The method of claim 3, wherein The contact layer comprises silicon doped with phosphorus (P) at a concentration between 10 19 cm −3 and 5×10 21 cm −3 .

5. The method of claim 1, wherein The selective deposition process is performed at a temperature of 200°C to 800°C.

6. The method of claim 1, the method further comprising: Before performing the selective deposition process, Performing a pre-cleaning process to remove contaminants formed on the exposed surface of the semiconductor region within the trench; And Performing a cavity shaping process to form a cavity on the exposed surface of the semiconductor region within the trench.

7. The method of claim 1, the method further comprising: After performing the microwave annealing process, Performing a blanket deposition process to form a metal layer on the contact layer; And Performing a metal filling process to form a contact plug in the trench.

8. A method of forming an electrical contact in a semiconductor structure, the method comprising: Performing a pre-cleaning process on a semiconductor structure having a semiconductor region and a dielectric layer with a trench therein, the pre-cleaning process including removing contaminants formed on the exposed surface of the semiconductor region within the trench; Performing a cavity shaping process to form a cavity on the exposed surface of the semiconductor region within the trench; Performing a selective deposition process, the selective deposition process including epitaxially forming a contact layer in the cavity of the semiconductor region within the trench of the dielectric layer; And Performing a microwave annealing process to activate dopants in the epitaxially formed contact layer.

9. The method of claim 8, wherein The pre-cleaning process, the cavity shaping process, the selective deposition process, and the microwave annealing process are all performed without breaking a vacuum environment.

10. The method of claim 8, wherein The semiconductor region comprises silicon doped with an n-type dopant, and The contact layer comprises silicon doped with an n-type dopant.

11. The method of claim 10, wherein The contact layer comprises silicon doped with phosphorus (P) at a concentration between 10 19 cm −3 and 5×10 21 cm −3 .

12. The method of claim 8, wherein The selective deposition process is performed at a temperature of 200°C to 800°C.

13. The method of claim 8, the method further comprising: After performing the microwave annealing process, Performing a blanket deposition process to form a metal layer on the contact layer; And Performing a metal filling process to form a contact plug in the trench.

14. A processing system, the processing system comprising: A first processing chamber; A second processing chamber; And A system controller configured to cause the processing system to: In the first processing chamber, perform a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer, the dielectric layer having trenches therein, the selective deposition process including epitaxially forming a contact layer on the semiconductor region within the trenches of the dielectric layer; And In the second processing chamber, perform a microwave annealing process to activate dopants in the epitaxially formed contact layer.

15. The processing system according to claim 14, wherein The semiconductor region comprises silicon doped with an n-type dopant, and The contact layer comprises silicon doped with an n-type dopant.

16. The processing system according to claim 15, wherein The contact layer comprises silicon doped with phosphorus (P) at a concentration between 10 19 cm −3 and 5×10 21 cm −3 .

17. The processing system according to claim 14, wherein The selective deposition process is performed at a temperature of 200 °C to 800 °C.

18. The processing system according to claim 14, the processing system further comprising: A third processing chamber; and A fourth processing chamber, wherein the system controller is further configured to cause the processing system to: Before performing the selective deposition process, In the third processing chamber, perform a pre-cleaning process to remove contaminants formed on the exposed surface of the semiconductor region within the trenches; And In the fourth processing chamber, perform a cavity shaping process to form a cavity on the exposed surface of the semiconductor region within the trenches.

19. The processing system according to claim 18, the processing system further comprising: A fifth processing chamber; and A sixth processing chamber, wherein the system controller is further configured to cause the processing system to: After performing the microwave annealing process, In the fifth processing chamber, perform a blanket deposition process to form a metal layer on the contact layer; And In the sixth processing chamber, perform a metal filling process to form a contact plug in the trenches.

20. The processing system according to claim 14, wherein the system controller is further configured to cause the processing system to perform the selective deposition process and the microwave annealing process without breaking the vacuum environment.

Images