Sampling resistor fault detection method and system

Abstract

The invention provides a sampling resistor fault detection method and system, and the method comprises the steps: obtaining the duty ratio of each phase in a circuit, and obtaining the number of times that the sum of the current values of each phase exceeds a set current threshold value after the duty ratio of each phase exceeds a set duty ratio; and judging whether the three-phase sampling resistor in the circuit breaks down after the number of times exceeds a set threshold value. Whether the circuit breaks down or not can be directly judged according to the sum of the current values of the three-phase sampling current and the duty ratio, so that monitoring and early warning for the circuit are realized. The problem that in the prior art, a mode of monitoring and early warning through a pre-drive chip cannot judge whether the circuit breaks down or not according to the obtained feedback current, and consequently the pre-drive chip cannot conduct early warning in time when the circuit breaks down is solved, and the safety of the system is improved.

Description

Technical Field

[0001] The present invention relates to the field of current sampling, and in particular to a sampling resistor fault detection method and system. Background Art

[0002] The steer-by-wire system is a vehicle steering control system that realizes steering operations through electronic signals and electric power assist devices. In the existing steer-by-wire system, the electric power assist motor is the actuator of the steer-by-wire system, directly responding to the steering performance of the steer-by-wire system and the safety of the driver. In the existing current closed-loop control scheme for controlling the electric power assist motor, when system fault judgment is required, the pre-driver chip is needed to sample the current and then execute the corresponding fault judgment process. However, in the existing pre-driver chips, the pre-driver chip can only obtain its own fault status by reading the chip register, that is, the pre-driver chip cannot judge whether the circuit is faulty based on the sampled current obtained, resulting in the pre-driver chip being unable to give a timely warning when the circuit fails. Therefore, how to implement a fault judgment method that can judge whether the system circuit fails according to the sampled current in the steer-by-wire system has become an urgent problem to be solved. Summary of the Invention

[0003] Based on this, in view of the above problems, it is necessary to propose a sampling resistor fault detection method and system that can sample the three-phase feedback current in the system in the steer-by-wire system and judge whether the system fails according to the sampled current.

[0004] The present application provides a sampling resistor fault detection method for detecting faults of the three-phase current sampling resistor in the SBW system, including the following steps:

[0005] S1, judging whether the sum of the sampled current values of the three phases of the feedback current in the SBW at the current time is greater than a preset first current threshold;

[0006] S2, if the sum of the sampled current values of the three phases at the current time is greater than the preset first current threshold, then increase the record of the fault signal by one;

[0007] S3, judging whether the total number of the recorded fault signals exceeds a preset fault signal record threshold. If so, it is judged that the three-phase current sampling resistor fails; if not, return to the step S1.

[0008] Further, before the step S1, it further includes:

[0009] S1a, obtaining the duty cycle of the three phases of the feedback current in the SBW;

[0010] S1b. Obtain the sampled current values of the three phases of the feedback current in the SBW at the current time according to the duty cycle.

[0011] Further, the step S1b specifically includes:

[0012] S1c. If all three duty cycles exceed the preset duty cycle threshold, after obtaining the sampled current values of the three phases of the feedback current in the SBW at the current time, execute step S1.

[0013] Further, after the step S2, the following steps are further included:

[0014] S3a. If the sum of the sampled current values of the three phases at the current time is not greater than the first current threshold, reduce the fault signal record by one time, and then enter the step S3.

[0015] Further, after the step S1b, it includes:

[0016] S2a. If the duty cycle of at least one phase among the three phases does not exceed the duty cycle threshold, and the duty cycle of at least one phase exceeds the duty cycle threshold, set the phase with the duty cycle not exceeding the duty cycle threshold as the estimated phase, and set the phase with the duty cycle exceeding the duty cycle threshold as the standard phase;

[0017] S2b. Estimate the current value of the estimated phase to obtain an estimated current value corresponding to the estimated phase;

[0018] Record the current value of the standard phase as the standard current value corresponding to the standard phase;

[0019] S2c. Denote the estimated current value as the sampled current value of the estimated phase at the current time, and denote the standard current value as the sampled current value of the standard phase at the current time.

[0020] Further, the step S1b specifically includes:

[0021] S2d. If the duty cycle of one phase among the three phases does not exceed the duty cycle threshold, while the duty cycles of the other two phases exceed the duty cycle threshold, set the phase with the duty cycle less than the duty cycle threshold as the first estimated phase, and set the remaining two phases as the first standard phase and the second standard phase respectively;

[0022] S2e. Set the historical current sampled value of the first estimated phase at the preset time as the first estimated current value;

[0023] Set the current values of the first standard phase and the second standard phase to the first standard current value and the second standard current value respectively;

[0024] S2f, Denote the first estimated current value as the sampled current value of the first estimated phase, and denote the first standard current value and the second standard current value as the sampled current values of the first standard phase and the second standard phase respectively;

[0025] Update the first current threshold to a preset second current threshold.

[0026] Further, the step S2e specifically includes:

[0027] S2g, Obtain a first historical estimated current set that matches the first estimated phase, where the first historical estimated current set is a set of current values obtained by the first estimated phase at several historical time nodes;

[0028] Obtain the historical time node closest to the current time node from the first historical estimated current set, and denote it as the first node to be obtained;

[0029] S2h, Obtain the current value that matches the first node to be obtained, and denote it as the first estimated current value.

[0030] Further, the step S1b specifically includes:

[0031] S2i, If the duty cycles of two of the three phases do not exceed the duty cycle threshold, while the duty cycle of the other phase exceeds the duty cycle threshold, then set the phases with duty cycles less than the duty cycle threshold as the second estimated phase and the third estimated phase respectively, and set the remaining one phase as the third standard phase;

[0032] S2j, Set the historical current sampled values of the second estimated phase and the third estimated phase at a preset time to the second estimated current value and the third estimated current value respectively;

[0033] Set the current value of the third standard phase to the third standard current value;

[0034] S2k, Denote the second estimated current value as the sampled current value of the second estimated phase, and denote the third estimated current value as the sampled current value of the third estimated phase;

[0035] Denote the third standard current value as the sampled current value of the third standard phase;

[0036] Update the first current threshold to a preset third current threshold.

[0037] Further, the step S2j specifically includes:

[0038] S2l, obtaining a second set of historical estimated currents matching the second estimated phase, where the second set of historical estimated currents is a set of current values obtained at several historical time nodes for the second estimated phase

[0039] Obtaining a third set of historical estimated currents matching the third estimated phase, where the third set of historical estimated currents is a set of current values obtained at several historical time nodes for the third estimated phase

[0040] S2m, obtaining, from the second set of historical estimated currents, the historical time node closest to the current time node, denoted as the second node to be obtained;

[0041] Obtaining, from the third set of historical estimated currents, the historical time node closest to the current time node, denoted as the third node to be obtained;

[0042] S2n, obtaining the current values matching the second node to be obtained and the third node to be obtained, and respectively denoting them as the second estimated current value and the third estimated current value.

[0043] The present invention also provides a sampling resistor fault detection system for detecting faults of three-phase current sampling resistors in an SBW system, which is characterized by including:

[0044] A current analysis unit for determining whether the sum of the sampled current values of the three phases of the feedback current in the SBW at the current time is greater than a preset first current threshold;

[0045] A fault recording unit for determining that if the sum of the sampled current values of the three phases at the current time is greater than the preset first current threshold, then incrementing a fault signal record;

[0046] A fault judgment unit for determining whether the total number of the fault signal records exceeds a preset fault signal record threshold. If so, it is determined that the three-phase current sampling resistor has a fault; if not, it returns to the step of determining whether the duty ratios of the three phases all exceed the duty ratio threshold.

[0047] A computer device includes a memory and a processor. When a computer program stored in the memory is executed by the processor, the processor performs the following steps:

[0048] S1, determining whether the sum of the sampled current values of the three phases of the feedback current in the SBW at the current time is greater than a preset first current threshold;

[0049] S2. If the sum of the sampled current values of the three phases at the current time is greater than a preset first current threshold, increment the fault signal record count by one.

[0050] S3. Determine whether the total number of fault signal records exceeds a preset fault signal record threshold. If so, determine that the three-phase current sampling resistor is faulty; if not, return to step S1.

[0051] A computer-readable medium stores a computer program. When the computer program is executed by a processor, the processor performs the following steps:

[0052] S1. Determine whether the sum of the sampled current values of the three phases of the feedback current in SBW at the current time is greater than a preset first current threshold.

[0053] S2. If the sum of the sampled current values of the three phases at the current time is greater than a preset first current threshold, increment the fault signal record count by one.

[0054] S3. Determine whether the total number of fault signal records exceeds a preset fault signal record threshold. If so, determine that the three-phase current sampling resistor is faulty; if not, return to step S1.

[0055] The above sampling resistor fault detection method and system can directly determine whether a circuit is faulty based on the sum of the current values of the three-phase sampled currents and the duty cycle by obtaining the number of times the sum of the current values of each phase in the circuit exceeds the set current threshold and determining that the three-phase sampling resistor in the circuit is faulty after this number exceeds the set threshold. This realizes the monitoring and early warning of the circuit, solves the problem in the prior art that the method of monitoring and early warning through a pre-driver chip cannot determine whether the circuit is faulty based on the obtained feedback current, resulting in the pre-driver chip being unable to give an early warning in a timely manner when the circuit fails, and improves the safety of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0057] Figure 1 Is a flowchart of the sampling resistor fault detection method in one embodiment;

[0058] Figure 2 Is a flowchart of the sampling resistor fault detection method in another embodiment;

[0059] Figure 3 It is a flowchart of a sampling resistor fault detection method in another embodiment;

[0060] Figure 4 It is a schematic diagram for obtaining the duty cycle of each phase in an embodiment;

[0061] Figure 5 It is a schematic structural diagram of a sampling resistor fault detection system in an embodiment;

[0062] Figure 6 It is a structural block diagram of a computer device in an embodiment Specific implementation manners

[0063] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0064] Refer to Figure 1 , the present invention provides a sampling resistor fault detection method for detecting faults of three-phase current sampling resistors in an SBW system, which is characterized by including the following steps:

[0065] S1. Determine whether the sum of the sampled current values of the three phases at the current time is greater than a preset first current threshold;

[0066] As described in the above step S1, the background system obtains the sampled current values of each phase at the current time. It can be understood that the background system can also be a pre-driver chip set in the circuit. In addition, since the current being sampled is a three-phase sampled current, the pre-driver chip can obtain the phase A current value, phase B current value, and phase C current value. After that, the pre-driver chip determines whether the sum of the phase A current value, the phase B current value, and the phase C current value is greater than the first set current threshold. It can be understood that when the resistance values of the three-phase sampling resistors in the circuit are normal, according to Kirchhoff's current law, the phase A current value ia, the phase B current value ib, and the phase C current value ic sampled by the pre-driver chip at the current time node should satisfy ia + ib + ic = 0. However, when the resistance values of the three-phase sampling resistors change or there is a short circuit / break, that is, when a current fault occurs in the current sampling circuit, ia + ib + ic will no longer be equal to 0. In this embodiment, to prevent misjudgment, the set threshold of ia + ib + ic is set as the first set current threshold, and in this embodiment, the first set current threshold is 10A. Therefore, in this step S3, the pre-driver chip is actually determining whether there is ia + ib + ic > 10A.

[0067] S2. If the sum of the sampled current values of the three phases at the current time is greater than the preset first current threshold, then increase the record of the fault signal by one.

[0068] As described in the above step S2, when the pre-driver chip determines that ia + ib + ic > 10A, the pre-driver chip determines that a current fault has occurred in the current sampling circuit, and then increases the record of the fault signal by one.

[0069] S3. Determine whether the total number of the fault signal records exceeds the preset fault signal record threshold. If so, determine that the three-phase current sampling resistor has a fault; if not, return to the step S1.

[0070] As described in the above step S3, the pre-driver chip determines whether the fault signal record exceeds the preset fault signal record threshold. It can be understood that in this embodiment, the pre-driver chip obtains the phase A current value, the phase B current value, and the phase C current value every 0.1 ms. Therefore, under the premise of multiple acquisitions and judgments during the sampling period, the fault statistical value will keep increasing. In this embodiment, the preset threshold is 240. Then, at this time, the pre-driver chip is actually determining whether the value of the fault signal record exceeds 240 on the premise of judging whether ia + ib + ic > 10A every 0.1 ms.

[0071] When the pre-driver chip determines that the value of the current fault signal record exceeds the fault signal record threshold, the pre-driver chip determines that the three-phase sampling resistors in the circuit are faulty. At this time, the pre-driver chip can send a corresponding warning message or control the external assist motor to perform a set warning operation;

[0072] When the pre-driver chip U1 determines that the current value of v does not exceed the preset threshold, it returns to execute step S1.

[0073] In this embodiment, through the above method, by obtaining the number of times that the sum of the current values of each phase in the circuit exceeds the set current threshold, and determining that the three-phase sampling resistors in the circuit are faulty after this number exceeds the set threshold, it is possible to directly determine whether the circuit is faulty based on the sum of the current values and the duty cycle of the three-phase sampling current, thereby realizing the monitoring and warning of the circuit, solving the problem in the prior art that the method of monitoring and warning through the pre-driver chip cannot determine whether the circuit is faulty based on the obtained feedback current, resulting in the pre-driver chip being unable to give a timely warning when the circuit fails, and improving the safety of the system.

[0074] In one embodiment, before step S1, it further includes:

[0075] S1a, obtaining the duty cycles of the three phases of the feedback current in the SBW;

[0076] S1b, obtaining the sampling current values of the three phases of the feedback current in the SBW at the current time according to the duty cycles.

[0077] As described in the above embodiment, the pre-driver chip obtains the duty cycles of each phase of the three-phase feedback current, and records them as the duty cycle of phase A, the duty cycle of phase B, and the duty cycle of phase C. Then, the pre-driver chip determines whether the duty cycle of phase A, the duty cycle of phase B, and the duty cycle of phase C all exceed the set duty cycle threshold. It can be understood that only when the duty cycle is higher than a set duty cycle threshold, the current values of phase A, phase B, and phase C can be obtained by the pre-driver chip. At this time, the pre-driver chip records the obtained duty cycles as the duty cycle of phase A, the duty cycle of phase B, and the duty cycle of phase C respectively. At this time, the duty cycle of phase A, the duty cycle of phase B, and the duty cycle of phase C can be specifically referred to Figure 4 as shown.

[0078] In one embodiment, step S1b specifically includes:

[0079] S1c, if all three duty cycles exceed the preset duty cycle threshold, after obtaining the sampling current values of the three phases of the feedback current in the SBW at the current time, execute step S1.

[0080] As described in the above embodiments, the duty cycle threshold is 12%. Therefore, in this embodiment, the pre-driver chip actually determines whether the duty cycles of the A-phase current value, the B-phase current value, and the C-phase current value all exceed 12%. If so, after the pre-driver chip obtains the sampled current values of the three phases of the feedback current in the SBW at the current time, it returns to step S1 to determine whether the sum of the A-phase current value, the B-phase current value, and the C-phase current value is greater than a preset first current threshold.

[0081] In one embodiment, after the step S2, the following steps are further included:

[0082] S3a, if the sum of the sampled current values of the three phases at the current time is not greater than the first current threshold, reduce the fault signal record by one time, and then enter the step S3.

[0083] As described in the above embodiments, when the pre-driver chip determines that ia + ib + ic < 10A, the pre-driver chip determines that the current sampling circuit has no current fault, and reduces the fault signal record by one time.

[0084] In one embodiment, the step S1b specifically includes:

[0085] S2a, if the duty cycle of at least one phase among the three phases does not exceed the duty cycle threshold, and the duty cycle of at least one phase exceeds the duty cycle threshold, set the phase with the duty cycle not exceeding the duty cycle threshold as the estimated phase, and set the phase with the duty cycle exceeding the duty cycle threshold as the standard phase;

[0086] S2b, estimate the current value of the estimated phase to obtain an estimated current value corresponding to the estimated phase;

[0087] Record the current value of the standard phase as the standard current value corresponding to the standard phase;

[0088] S2c, record the estimated current value as the sampled current value of the estimated phase at the current time, and record the standard current value as the sampled current value of the standard phase at the current time.

[0089] As described in the above embodiments, when the pre-driver chip determines that there is at least one duty cycle among the duty cycles of the A phase, the duty cycle of the B phase, and the duty cycle of the C phase that is less than 12%, and there is at least one duty cycle that is greater than 12%, the phase with a duty cycle less than the duty cycle threshold is recorded as the estimated phase, and the phase with a duty cycle greater than the duty cycle threshold is recorded as the standard phase. Then, the pre-driver chip estimates the current value of the estimated phase to obtain an estimated current value that matches the estimated phase. At the same time, the pre-driver chip also obtains the current value of the standard phase, which is recorded as the standard current value. After that, the pre-driver chip re-labels the estimated current value and the standard current value as the A-phase current value, the B-phase current value, and the C-phase current value according to the corresponding phases.

[0090] Reference Figure 2 , in one embodiment, step S1b specifically includes:

[0091] S2d, if the duty cycle of one of the three phases does not exceed the duty cycle threshold, while the duty cycles of the other two phases exceed the duty cycle threshold, the phase with a duty cycle less than the duty cycle threshold is set as the first estimated phase, and the other two phases are respectively set as the first standard phase and the second standard phase;

[0092] S2e, set the historical current sampling value of the first estimated phase within a preset time as the first estimated current value;

[0093] Set the current values of the first standard phase and the second standard phase as the first standard current value and the second standard current value respectively;

[0094] S2f, record the first estimated current value as the sampling current value of the first estimated phase, and record the first standard current value and the second standard current value as the sampling current values of the first standard phase and the second standard phase respectively;

[0095] Update the first current threshold to a preset second current threshold.

[0096] As described in the above embodiments, when the pre-driver chip determines that any one of the duty ratios of the A phase, the duty ratio of the B phase, and the duty ratio of the C phase is less than 12%, the pre-driver chip records the phase with the duty ratio less than the duty ratio threshold as the first estimated phase, and records the other two phases with the duty ratios greater than the duty ratio threshold as the first standard phase and the second standard phase. For example, when the duty ratios of the A phase and the B phase are greater than 12% and the duty ratio of the C phase is less than 12%, the pre-driver chip records the C phase as the first estimated phase, and records the A phase and the B phase as the first standard phase and the second standard phase respectively. After that, the pre-driver chip obtains the first historical current value of the C phase and updates the first historical current value to the first estimated current value. It can be understood that at this time, the first estimated current value is regarded as the C-phase current value ic in the subsequent steps;

[0097] After that, the pre-driver chip obtains the current values of the first standard phase and the second standard phase (i.e., the A-phase current value ia and the B-phase current value ib). Then, the pre-driver chip updates the current values of the first standard phase and the second standard phase to the first standard current value and the second standard current value respectively, and replaces the first set current threshold with the second set current threshold. It can be understood that the second current threshold is used to judge the current fault when the step is executed to S1 in the case where the current value of a single phase is an estimated value;

[0098] It can be understood that the second set current threshold is 20A. Therefore, on the premise that the current value of any phase is an estimated value, when the pre-driver chip determines that ia + ib + ic > 20A, the pre-driver chip can execute the step of increasing the record of the fault signal once.

[0099] In one embodiment, the step S2e specifically includes:

[0100] S2g, obtaining a first historical estimated current set matching the first estimated phase, where the first historical estimated current set is a set of current values obtained by the first estimated phase at several historical time nodes;

[0101] Obtaining the historical time node closest to the current time node from the first historical estimated current set and recording it as the first node to be obtained;

[0102] S2h, obtaining the current value matching the first node to be obtained and recording it as the first estimated current value.

[0103] As described in the above embodiments, the pre-driver chip obtains a first set of historical estimated currents that match the first estimated phase. The first set of historical estimated currents is a set of current values obtained at the first estimated phase at a plurality of historical time nodes. After that, the pre-driver chip obtains the historical time node closest to the current time node and records it as the first node to be obtained, and then records the historical current value that matches the first node to be obtained as the first estimated current value.

[0104] Reference Figure 3 , in one embodiment, step S1b specifically includes:

[0105] S2i, if the duty cycles of two of the three phases do not exceed the duty cycle threshold, while the duty cycle of the other phase exceeds the duty cycle threshold, then set the phases with duty cycles less than the duty cycle threshold as the second estimated phase and the third estimated phase respectively, and set the remaining one phase as the third standard phase;

[0106] S2j, set the historical current sampling values of the second estimated phase and the third estimated phase at a preset time as the second estimated current value and the third estimated current value respectively;

[0107] Set the current value of the third standard phase as the third standard current value;

[0108] S2k, record the second estimated current value as the sampling current value of the second estimated phase, and record the third estimated current value as the sampling current value of the third estimated phase;

[0109] Record the third standard current value as the sampling current value of the third standard phase.

[0110] As described in the above embodiments, when the pre-driver chip determines that any two of the duty ratios of the A phase, the B phase, and the C phase are less than 12%, the pre-driver chip records the two phases with duty ratios less than the duty ratio threshold as the third estimated phase and the fourth estimated phase, and records the remaining phases with duty ratios greater than the duty ratio threshold as the third standard phase. For example, when the duty ratios of the A phase and the B phase are less than 12% and the duty ratio of the C phase is greater than 12%, the pre-driver chip records the C phase as the third standard phase, and records the A phase and the B phase as the second estimated phase and the third estimated phase respectively. Then, the pre-driver chip obtains the second historical current value of the A phase and the third historical current value of the B phase, updates the second historical current value to the second estimated current value, and updates the third historical current value to the third estimated current value. It can be understood that at this time, the second estimated current value is regarded as the A-phase current value ia in the subsequent steps, and similarly, the third estimated current value is regarded as the B-phase current value ib in the subsequent steps;

[0111] Then, the pre-driver chip obtains the current value of the third standard phase and records it as the third standard current value (i.e., the C-phase current value ic). Then, the pre-driver chip updates the current value of the third standard phase to the third standard current value and replaces the first set current threshold with the third set current threshold. It can be understood that the third current threshold is used to judge the current fault when the step reaches S1 in the case where the current values of two phases are estimated values;

[0112] It can be understood that the third set current threshold is 30A. Therefore, on the premise that the current values of any two phases are estimated values, when the pre-driver chip judges that ia + ib + ic > 30A, the pre-driver chip can execute the step of increasing the record of the fault signal once.

[0113] In one embodiment, the step S2j specifically includes:

[0114] S2g, obtaining a second historical estimated current set matching the second estimated phase, where the second historical estimated current set is a set of current values obtained by the second estimated phase at several historical time nodes

[0115] Obtaining a third historical estimated current set matching the third estimated phase, where the third historical estimated current set is a set of current values obtained by the third estimated phase at several historical time nodes

[0116] S2h, obtain the historical time node closest to the current time node from the second historical estimated current set, and denote it as the second node to be obtained;

[0117] Obtain the historical time node closest to the current time node from the third historical estimated current set, and denote it as the third node to be obtained;

[0118] S2i, obtain the current values matching the second node to be obtained and the third node to be obtained, and denote them as the second estimated current value and the third estimated current value respectively.

[0119] As described in the above embodiments, the pre-driver chip obtains the second historical estimated current set matching the second estimated phase and the third historical estimated current set matching the third estimated phase. It can be understood that the second historical estimated current set is the set of current values obtained by the second estimated phase at several historical time nodes. Similarly, the third historical estimated current set is the set of current values obtained by the third estimated phase at several historical time nodes. Then, after the pre-driver chip obtains the historical time node closest to the current time node from the second historical estimated current set and denotes it as the second node to be obtained, and then the pre-driver chip obtains the current value matching the second node to be obtained and denotes it as the second historical current value. Similarly, the pre-driver chip obtains the historical time node closest to the current time node from the third historical estimated current set and denotes it as the third node to be obtained. Then, the pre-driver chip obtains the current value matching the third node to be obtained and denotes it as the third historical current value.

[0120] Reference Figure 5 , this application also provides a sampling resistor fault detection system for detecting faults of three-phase current sampling resistors in the SBW system, which is characterized by including:

[0121] The current analysis unit 10 is used to judge whether the sum of the sampled current values of the three phases of the feedback current in the SBW at the current time is greater than a preset first current threshold;

[0122] The fault recording unit 20 is used to judge that if the sum of the sampled current values of the three phases at the current time is greater than the preset first current threshold, then increase the recording of a fault signal once;

[0123] The fault judgment unit 30 is used to judge whether the total number of the fault signal records exceeds a preset fault signal record threshold. If so, judge that the three-phase current sampling resistor has a fault; if not, return to the step of judging whether the duty ratios of the three phases all exceed the duty ratio threshold.

[0124] The above-mentioned units are for implementing the above-mentioned sampling resistor fault detection system, which will not be introduced one by one here.

[0125] Figure 6 The internal structure diagram of a computer device in an embodiment is shown. The computer device may specifically be a server, and the server includes but is not limited to high-performance computers and high-performance computer clusters. As Figure 6 shown, the computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor can implement the sampling resistor fault detection method. The internal memory may also store a computer program. When the computer program is executed by the processor, the processor can execute the sampling resistor fault detection method.

[0126] In an embodiment, the sampling resistor fault detection method provided by the present invention can be implemented in the form of a computer program, and the computer program can run on a computer device as Figure 6 shown. Each program template constituting the sampling resistor fault detection system can be stored in the memory of the computer device. For example: 10 - current analysis unit, 20 - fault recording unit, 30 - fault judgment unit.

[0127] A computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0128] S1, determining whether the sum of the sampled current values of the three phases of the feedback current in SBW at the current time is greater than a preset first current threshold;

[0129] S2, if the sum of the sampled current values of the three phases at the current time is greater than the preset first current threshold, increasing the number of recorded fault signals by one;

[0130] S3, determining whether the total number of recorded fault signals exceeds a preset fault signal recording threshold. If so, it is determined that the three-phase current sampling resistor has a fault; if not, returning to step S1.

[0131] As can be seen from the above embodiments, the greatest beneficial effect of the present invention is that by obtaining the number of times that the sum of the current values of each phase in the circuit exceeds the set current threshold, and determining that the three-phase sampling resistors in the circuit are faulty after this number exceeds the set threshold, it is possible to directly determine whether the circuit is faulty based on the sum of the current values of the three-phase sampling currents and the duty cycle, thereby realizing the monitoring and early warning of the circuit, solving the problem in the prior art that the method of monitoring and early warning through the pre-driver chip cannot determine whether the circuit is faulty based on the obtained feedback current, resulting in the inability of the pre-driver chip to give an early warning in a timely manner when the circuit fails, and improving the safety of the system.

[0132] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A sampling resistor fault detection method for detecting faults of three-phase current sampling resistors in the SBW system, characterized in that, It includes the following steps: S1. Determine whether the sum of the sampled current values of the three phases of the feedback current in the SBW at the current time is greater than a preset first current threshold; S2. If the sum of the sampled current values of the three phases at the current time is greater than the preset first current threshold, increase the fault signal record count by one; S3. Determine whether the total number of the fault signal records exceeds a preset fault signal record threshold. If so, determine that the three-phase current sampling resistor is faulty; if not, return to step S1.

2. The sampling resistor fault detection method according to claim 1, wherein, Before step S1, it further includes: S1a. Obtain the duty cycles of the three phases of the feedback current in the SBW; S1b. Obtain the sampled current values of the three phases of the feedback current in the SBW at the current time according to the duty cycles.

3. The sampling resistor fault detection method according to claim 3, wherein, Step S1b specifically includes: S1c. If all three duty cycles exceed a preset duty cycle threshold, after obtaining the sampled current values of the three phases of the feedback current in the SBW at the current time, execute step S1.

4. The sampling resistor fault detection method according to claim 1, characterized in that, After step S2, it further includes the following steps: S3a. If the sum of the sampled current values of the three phases at the current time is not greater than the first current threshold, reduce the fault signal record count by one, and then enter step S3.

5. The sampling resistor fault detection method according to claim 3, characterized in that, Step S1b specifically includes: S2a. If at least one of the three phases has a duty cycle that does not exceed the duty cycle threshold and at least one phase has a duty cycle that exceeds the duty cycle threshold, set the phase with a duty cycle that does not exceed the duty cycle threshold as the estimated phase, and set the phase with a duty cycle that exceeds the duty cycle threshold as the standard phase; S2b. Estimate the current value of the estimated phase to obtain an estimated current value corresponding to the estimated phase; Record the current value of the standard phase as the standard current value corresponding to the standard phase; S2c. Denote the estimated current value as the sampled current value of the estimated phase at the current time, and denote the standard current value as the sampled current value of the standard phase at the current time.

6. The sampling resistor fault detection method according to claim 5, characterized in that, Step S1b specifically includes: S2d. If one of the three phases has a duty cycle that does not exceed the duty cycle threshold while the other two phases have duty cycles that exceed the duty cycle threshold, set the phase with a duty cycle less than the duty cycle threshold as the first estimated phase, and set the other two phases as the first standard phase and the second standard phase respectively; S2e. Set the historical current sampled value of the first estimated phase at a preset time as the first estimated current value; Set the current values of the first standard phase and the second standard phase as the first standard current value and the second standard current value respectively; S2f. Denote the first estimated current value as the sampled current value of the first estimated phase, and denote the first standard current value and the second standard current value as the sampled current values of the first standard phase and the second standard phase respectively; Update the first current threshold to a preset second current threshold.

7. The sampling resistor fault detection method according to claim 6, wherein Step S2e specifically includes: S2g, obtain a first set of historical estimated currents that match the first estimated phase, where the first set of historical estimated currents is a set of current values obtained by the first estimated phase at a number of historical time nodes; Obtain the historical time node closest to the current time node from the first set of historical estimated currents, and denote it as the first node to be obtained; S2h, obtain the current value that matches the first node to be obtained, and denote it as the first estimated current value.

8. The sampling resistor fault detection method according to claim 5, characterized in that The step S1b specifically includes: S2i, if the duty cycles of two of the three phases do not exceed the duty cycle threshold, while the duty cycle of the other phase exceeds the duty cycle threshold, then set the phases with duty cycles less than the duty cycle threshold as the second estimated phase and the third estimated phase respectively, and set the remaining one phase as the third standard phase; S2j, set the historical current sampling values of the second estimated phase and the third estimated phase at a preset time as the second estimated current value and the third estimated current value respectively; Set the current value of the third standard phase as the third standard current value; S2k, denote the second estimated current value as the sampling current value of the second estimated phase, and denote the third estimated current value as the sampling current value of the third estimated phase; Denote the third standard current value as the sampling current value of the third standard phase; Update the first current threshold to a preset third current threshold.

9. The sampling resistor fault detection method according to claim 8, wherein The step S2j specifically includes: S2l, obtain a second set of historical estimated currents that match the second estimated phase, where the second set of historical estimated currents is a set of current values obtained by the second estimated phase at a number of historical time nodes Obtain a third set of historical estimated currents that match the third estimated phase, where the third set of historical estimated currents is a set of current values obtained by the third estimated phase at a number of historical time nodes S2m, obtain the historical time node closest to the current time node from the second set of historical estimated currents, and denote it as the second node to be obtained; Obtain the historical time node closest to the current time node from the third set of historical estimated currents, and denote it as the third node to be obtained; S2n, obtain the current values that match the second node to be obtained and the third node to be obtained, and denote them as the second estimated current value and the third estimated current value respectively.

10. A sampling resistor fault detection system for detecting faults of three-phase current sampling resistors in an SBW system, characterized in that, Includes: A current analysis unit, configured to determine whether the sum of the sampling current values of the three phases of the feedback current in the SBW at the current time is greater than a preset first current threshold; A fault recording unit, configured to determine that if the sum of the sampling current values of the three phases at the current time is greater than the preset first current threshold, then increase the recording of a fault signal once; A fault judgment unit, configured to determine whether the total number of the recorded fault signals exceeds a preset fault signal recording threshold. If so, it is determined that the three-phase current sampling resistor fails; if not, return to the step of determining whether the duty cycles of the three phases all exceed the duty cycle threshold.

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