Voltage detection circuit, circuit system and electronic equipment

Abstract

The invention provides a voltage detection circuit, a circuit system and electronic equipment, and the circuit system comprises a voltage shift module which has a first input end connected with a first reference voltage and a second input end connected with a first to-be-detected voltage, and is used for carrying out the first voltage shift of the first reference voltage and outputting a second reference voltage from a first output end; performing second voltage shift on the first to-be-detected voltage and outputting a second to-be-detected voltage from a second output end; the comparator is used for comparing the second reference voltage with the second voltage to be detected and outputting a comparison result signal; the current mirror module is used for inputting a first current to the first input end from the first output end and inputting a second current to the second input end from the second output end when a first reference voltage is smaller than zero, the first current is equal to the second current, and the first current is used for ensuring that the second reference voltage is smaller than zero when the second reference voltage is smaller than zero; the second reference voltage is greater than or equal to zero.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a voltage detection circuit, a circuit system, and an electronic device. Background Art

[0002] Currently, in the electronic industry, a comparator is often used to detect voltages such as the resistance voltage of a load in high-voltage applications or the source-drain voltage of an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor). Since the voltage to be detected and the reference voltage for detection often exceed the voltage withstand limit of the comparator, a level shift circuit needs to be set to step down the voltage to be detected and the reference voltage respectively, so that the input voltage of the comparator is less than the voltage withstand limit of the comparator, thereby enabling the comparator to work properly.

[0003] However, in some application scenarios, the voltage to be detected and the reference voltage may also be negative voltages, causing the input voltage of the comparator to exceed the common-mode input level range of the comparator, resulting in the comparator being unable to work and thus unable to detect the voltage to be detected. Summary of the Invention

[0004] Embodiments of the present invention provide a voltage detection circuit, a circuit system, and an electronic device, so that the first voltage to be detected can also be detected when both the first reference voltage and the first voltage to be detected are negative voltages.

[0005] To solve the above technical problems, the technical solution of the present invention provides a voltage detection circuit, which includes:

[0006] A voltage shift module, configured to perform a first voltage shift on the received first reference voltage and output a second reference voltage, and also configured to perform a second voltage shift on the received first voltage to be detected and output a second voltage to be detected. The first input terminal of the voltage shift module receives the first reference voltage, the first output terminal of the voltage shift module outputs the second reference voltage, the second input terminal of the voltage shift module receives the first voltage to be detected, and the second output terminal of the voltage shift module outputs the second voltage to be detected;

[0007] A comparator, configured to compare the second reference voltage and the second voltage to be detected and output a comparison result signal;

[0008] A current mirror module is configured to output a first current to the first output terminal of the voltage shift module when the first reference voltage is less than zero, and is further configured to output a second current to the second output terminal of the voltage shift module when the first reference voltage is less than zero. The first current is equal to the second current, and the minimum value of the first current and the first reference voltage is set to be proportional to each other, so that the second reference voltage is greater than or equal to zero.

[0009] The voltage shift module is further configured to output the first current from its first input terminal and output the second current from its second input terminal.

[0010] Optionally, the current mirror module includes a current source, a first current mirror, and a second current mirror. The anode of the current source is connected to the power supply voltage, the cathode of the current source is connected to the first input terminal of the first current mirror, the second input terminal of the first current mirror is connected to the first output terminal of the second current mirror, the output terminal of the first current mirror is connected to the first output terminal of the voltage shift module. The first current mirror is configured to output the first current to the first output terminal of the voltage shift module when the first reference voltage is less than zero. The second output terminal of the second current mirror is connected to the second output terminal of the voltage shift module. The second current mirror is configured to mirror the first current and output the second current to the second output terminal of the voltage shift module.

[0011] Optionally, the first current mirror includes a first NMOS transistor and a second NMOS transistor. The drain of the first NMOS transistor serves as the first input terminal of the first current mirror. The gate of the first NMOS transistor is connected to its own drain and the gate of the second NMOS transistor respectively. The source of the first NMOS transistor is connected to the ground terminal. The source of the second NMOS transistor serves as the output terminal of the first current mirror to output the first current. The drain of the second NMOS transistor serves as the second input terminal of the first current mirror.

[0012] Optionally, the second current mirror includes a first PMOS transistor and a second PMOS transistor. The drain of the first PMOS transistor serves as the first output terminal of the second current mirror and is connected to the drain of the second NMOS transistor. The gate of the first PMOS transistor is connected to its own drain and the gate of the second PMOS transistor respectively. The drain of the second PMOS transistor serves as the second output terminal of the second current mirror to output the second current. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage.

[0013] Optionally, the voltage shift module includes a third current mirror, a first voltage shift unit, and a second voltage shift unit. The third current mirror is configured to output a first bias current and a second bias current. A first end of the first voltage shift unit serves as a first input end of the voltage shift module, and a second end of the first voltage shift unit serves as a first output end of the voltage shift module. The first voltage shift unit is configured to perform a first voltage shift on the first reference voltage according to the first bias current and output the second reference voltage. A first end of the second voltage shift unit serves as a second input end of the voltage shift module, and a second end of the second voltage shift unit serves as a second output end of the voltage shift module. The second voltage shift unit is configured to perform a second voltage shift on the first voltage to be detected according to the second bias current and output the second voltage to be detected.

[0014] Optionally, the first voltage shift unit includes: a first resistor, a first end of the first resistor serving as the first end of the first voltage shift unit, and a second end of the first resistor serving as the second end of the first voltage shift unit;

[0015] The second voltage shift unit includes: a second resistor, a first end of the second resistor serving as the first end of the second voltage shift unit, and a second end of the second resistor serving as the second end of the second voltage shift unit.

[0016] Optionally, the third current mirror includes a third NMOS transistor and a fourth NMOS transistor. A drain of the third NMOS transistor is connected to a second end of the first resistor; a gate of the third NMOS transistor is connected to its own drain and a gate of the fourth NMOS transistor. A drain of the fourth NMOS transistor is connected to a second end of the second resistor. Sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to a ground terminal.

[0017] Optionally, the voltage shift module further includes a first overvoltage protection unit and a second overvoltage protection unit. The first overvoltage protection unit is coupled between a second end of the second voltage shift unit and the third current mirror, and is configured to perform overvoltage protection on the third current mirror. The second overvoltage protection unit is coupled between a second end of the second voltage shift unit and the comparator, and is configured to perform overvoltage protection on the comparator.

[0018] Optionally, the first overvoltage protection unit includes a fifth NMOS transistor with high breakdown voltage. A gate of the fifth NMOS transistor with high breakdown voltage is connected to the power supply voltage. A source of the fifth NMOS transistor with high breakdown voltage is connected to the third current mirror. A drain of the fifth NMOS transistor with high breakdown voltage is connected to a second end of the second voltage shift unit;

[0019] The second overvoltage protection unit includes a sixth high-voltage-resistant NMOS transistor. The gate of the sixth high-voltage-resistant NMOS transistor is connected to the power supply voltage. The source of the sixth high-voltage-resistant NMOS transistor is connected to the comparator. The drain of the sixth high-voltage-resistant NMOS transistor is connected to the second end of the second voltage shift unit.

[0020] The technical solution of the present invention also provides a circuit system, which is characterized by including the voltage detection circuit.

[0021] The technical solution of the present invention also provides an electronic device, which is characterized by including the circuit system.

[0022] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0023] In the voltage detection circuit provided by the technical solution of the present invention, when the first reference voltage is less than zero, the current mirror module inputs a first current from the first output end of the voltage shift module to the first input end of the voltage shift module. Since the first current is proportional to the minimum value of the first reference voltage, so that the second reference voltage is greater than or equal to zero, it ensures that the comparator can work normally. At the same time, the current mirror module also inputs a second current from the second output end of the voltage shift module to the second input end of the voltage shift module, and the first current is equal to the second current, so as to realize the normal detection of the first voltage to be detected on the basis that the comparator can work normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic circuit structure diagram of the voltage detection circuit provided by an embodiment of the present invention Figure 1 ;

[0025] Figure 2 is a schematic circuit structure diagram of the voltage detection circuit provided by an embodiment of the present invention Figure 2 ;

[0026] Figure 3 is a schematic circuit structure diagram of the voltage detection circuit provided by an embodiment of the present invention Figure 3 . DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] As described in the background art, in a voltage detection circuit, when the voltage to be detected and the reference voltage are negative voltages, the comparator in the circuit cannot work because the input exceeds the common-mode input level, and thus the voltage to be detected cannot be detected.

[0028] In view of this, an embodiment of the present invention provides a new voltage detection circuit, so that when both the reference voltage and the voltage to be detected are negative voltages, the voltage to be detected can also be detected.

[0029] To make the above objects, features, and advantages of the present invention more apparent and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0030] Figure 1 Schematic circuit structure of the voltage detection circuit provided by the embodiment of the present invention Figure 1 。

[0031] Please refer to Figure 1 , the voltage detection circuit provided by the embodiment of the present invention includes:

[0032] A voltage shift module 10, configured to perform a first voltage shift on the received first reference voltage Vref1 and output a second reference voltage Vref2, and further configured to perform a second voltage shift on the received first voltage to be detected Vsense1 and output a second voltage to be detected Vsense2. The first input terminal in1 of the voltage shift module 10 receives the first reference voltage Vref1, the first output terminal out1 of the voltage shift module 10 outputs the second reference voltage Vref2, the second input terminal in2 of the voltage shift module 10 receives the first voltage to be detected Vsense1, and the second output terminal out2 of the voltage shift module 10 outputs the second voltage to be detected Vsense2;

[0033] A comparator, configured to compare the second reference voltage Vref2 and the second voltage to be detected Vsense2 and output a comparison result signal Vout;

[0034] The current mirror module 20 is configured to output a first current I1 to the first output terminal out1 of the voltage shift module 10 when the first reference voltage Vref1 is less than zero, and is further configured to output a second current I2 to the second output terminal out2 of the voltage shift module 10 when the first reference voltage Vref1 is less than zero. The first current I1 is equal to the second current I2, and the minimum value of the first current I1 is set to be proportional to the first reference voltage Vref1, so that the second reference voltage Vref2 is greater than or equal to zero.

[0035] The voltage shift module 10 is further configured to output the first current I1 from its first input terminal in1, and output the second current I2 from its second input terminal in2.

[0036] When detecting the voltage drop across an external resistor or the drain-source voltage of an LDMOS, the source of the external resistor or LDMOS needs to be connected to the power ground terminal. If the voltage of the power ground terminal is lower than the ground voltage of the comparator CMP, then the voltage drop across the external resistor or the drain-source voltage of the LDMOS, i.e., the first voltage to be detected Vsense1, may be less than 0V. Or the current flowing through the LDMOS flows from the source to the drain due to half-bridge driving, and since the source of the LDMOS is connected to the ground voltage, the drain-source voltage of the LDMOS, i.e., the first voltage to be detected Vsense1, is less than 0V. If the first voltage to be detected Vsense1 is less than 0V, then the first reference voltage Vref1 may be less than 0V. If both the first voltage to be detected Vsense1 and the first reference voltage Vref1 are less than 0V, the comparator CMP cannot work because the input exceeds the common-mode input level, and thus cannot detect all the first voltages to be detected Vsensel with negative voltages.

[0037] When the first voltage to be detected Vsensel and the first reference voltage Vrefl are both less than 0V, for the comparator CMP to work properly, the current mirror module 20 outputs a first current I1 to the first output terminal outl of the voltage shift module 10 when the first reference voltage Vrefl is less than zero, and the first current I1 flows from the first output terminal outl of the voltage shift module 10 to the first input terminal in1 of the voltage shift module 10. Since the first current I1 ensures that when the second reference voltage Vref2 is less than zero, the second reference voltage Vref2 is greater than or equal to zero, thus enabling the comparator CMP to work properly. The current mirror module 20 also outputs a second current I2 to the second output terminal out2 of the voltage shift module 10, and the second current I2 flows from the second output terminal out2 of the voltage shift module 10 to the second input terminal in2 of the voltage shift module 10. Since the first current I1 is equal to the second current I2, the difference between the second voltage to be detected Vsense2 and the first voltage to be detected Vsense1 is equal to the difference between the second reference voltage Vref2 and the first reference voltage Vref1, thereby ensuring that the difference between the second voltage to be detected Vsense2 and the second reference voltage Vref2 is equal to the difference between the first voltage to be detected Vsensel and the first reference voltage Vref1, that is, the normal detection of the first voltage to be detected Vsense1 is realized.

[0038] Figure 2 Schematic diagram of the circuit structure of the voltage detection circuit provided by the embodiment of the present invention Figure 2 。

[0039] Please refer to Figure 1 and Figure 2 In an embodiment, the current mirror module 20 includes a current source Isource, a first current mirror 21, and a second current mirror 22. The anode of the current source Isource is connected to the power supply voltage VCC, the cathode of the current source Isource is connected to the first input terminal of the first current mirror 21, the second input terminal of the first current mirror 21 is connected to the first output terminal of the second current mirror 22, the output terminal of the first current mirror 21 is connected to the first output terminal outl of the voltage shift module 10. The first current mirror 21 is configured to output the first current I1 to the first output terminal outl of the voltage shift module 10 when the first reference voltage Vref1 is less than zero. The second output terminal of the second current mirror 22 is connected to the second output terminal out2 of the voltage shift module 10. The second current mirror 22 is configured to mirror the first current I1 and output the second current I2 to the second output terminal out2 of the voltage shift module 10.

[0040] The voltage shift module 10 includes a third current mirror 13, a first voltage shift unit 11, and a second voltage shift unit 12. The third current mirror 13 is configured to output a first bias current and a second bias current. The first end of the first voltage shift unit 11 serves as the first input terminal in1 of the voltage shift module 10, and the second end of the first voltage shift unit 11 serves as the first output terminal outl of the voltage shift module 10. The first voltage shift unit 11 is configured to perform a first voltage shift on the first reference voltage Vref1 according to the first bias current and output the second reference voltage Vref2. The first end of the second voltage shift unit 12 serves as the second input terminal in2 of the voltage shift module 10, and the second end of the second voltage shift unit 12 serves as the second output terminal out2 of the voltage shift module 10. The second voltage shift unit 12 is configured to perform a second voltage shift on the first voltage to be detected Vsensel according to the second bias current and output the second voltage to be detected Vsense2.

[0041] Specifically, the first current mirror 21 includes a first NMOS transistor MN1 and a second NMOS transistor MN2. The drain of the first NMOS transistor MN1 serves as the first input terminal of the first current mirror 21. The gate of the first NMOS transistor MN1 is connected to its own drain and the gate of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is connected to the ground terminal. The source of the second NMOS transistor MN2 serves as the output terminal of the first current mirror 21 to output the first current I1, and the drain of the second NMOS transistor MN2 serves as the second input terminal of the first current mirror 21.

[0042] The second current mirror 22 includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The drain of the first PMOS transistor MP1 serves as the first output terminal of the second current mirror 22 and is connected to the drain of the second NMOS transistor MN2. The gate of the first PMOS transistor MP1 is connected to its own drain and the gate of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 serves as the second output terminal of the second current mirror 22 to output the second current I2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage VCC.

[0043] The first voltage shift unit 11 includes a first resistor R1. The first end of the first resistor R1 serves as the first end of the first voltage shift unit 11, and the second end of the first resistor R1 serves as the second end of the first voltage shift unit 11. The second voltage shift unit 12 includes a second resistor R2. The first end of the second resistor R2 serves as the first end of the second voltage shift unit 12, and the second end of the second resistor R2 serves as the second end of the second voltage shift unit 12. Of course, in addition to resistors, the first voltage shift unit and the second voltage shift unit can also select other resistive devices or buck circuits, which are not limited herein.

[0044] The third current mirror 13 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The drain of the third NMOS transistor MN3 is connected to the second end of the first resistor R1; the gate of the third NMOS transistor MN3 is connected to its own drain and the gate of the fourth NMOS transistor MN4. The drain of the fourth NMOS transistor MN4 is connected to the second end of the second resistor R2. The sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are respectively connected to the ground terminal.

[0045] The following Figure 2 will detail the working principle of the shown circuit:

[0046] When both the first reference voltage Vref1 and the first voltage to be detected Vsense1 are less than zero, the third current mirror 13 composed of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 does not work. The second NMOS transistor MN2 and the first PMOS transistor MP1 are turned on, and the first current I1 flows from the first PMOS transistor MP1 through the second NMOS transistor MN2 and is output from the source of the second NMOS transistor MN2. The formula for the first current I1 is as follows:

[0047] I1 = 0.5 * kn * (W / L) * (VGS - VTH)^2 Formula (1)

[0048] Where, I1 is used to represent the first current I1, kn is used to represent the average mobility of the second NMOS transistor MN2, W / L is used to represent the aspect ratio of the second NMOS transistor MN2, VGS is used to represent the gate-source voltage of the second NMOS transistor MN2, and VTH is used to represent the threshold voltage of the second NMOS transistor MN2.

[0049] When the first current I1 flows from the first output terminal out1 to the first input terminal in1 and passes through the first resistor R1, the formula for the second reference voltage Vref2 is as follows:

[0050] Vref2 = I1 * R1 + Vref1 Equation (2)

[0051] Since the voltage range of the first reference voltage Vref1 has been determined, the magnitude of the first current I1 can be adjusted by adjusting the aspect ratio of the second NMOS transistor MN2 according to the minimum value of the first reference voltage Vref1, so as to ensure that the second reference voltage Vref2 is greater than or equal to zero regardless of the value of the first reference voltage Vref1, thereby ensuring that the comparator CMP can normally output the comparison result signal Vout when both the first reference voltage Vref1 and the first voltage to be detected Vsense1 are negative values.

[0052] Since the first PMOS transistor MP1 and the second PMOS transistor MP2 form a current mirror structure, the first current I1 is mirrored to the drain of the second PMOS transistor MP2, and the second current I2 is output. In order to ensure that the difference between the second voltage to be detected Vsense2 and the first voltage to be detected Vsense1 is equal to the difference between the second reference voltage Vref2 and the first reference voltage Vref1, it is necessary to set the first resistor R1 equal to the second resistor R2, and the first current I1 equal to the second current I2. In order to make the first current I1 equal to the second current I2, it is necessary to set the aspect ratio of the first PMOS transistor MP1 equal to the aspect ratio of the second PMOS transistor MP2. Since the difference between the second voltage to be detected Vsense2 and the first voltage to be detected Vsensel is equal to the difference between the second reference voltage Vref2 and the first reference voltage Vref1, the difference between the second voltage to be detected Vsense2 and the second reference voltage Vref2 is equal to the difference between the first voltage to be detected Vsensel and the first reference voltage Vref1, thereby realizing the normal detection of the first voltage to be detected Vsense1.

[0053] When both the first reference voltage Vref1 and the first voltage to be detected Vsense1 are greater than zero, the first current mirror 21 and the second current mirror 22 in the current mirror module 20 do not work. The third NMOS transistor MN3 in the third current mirror 13 outputs a first bias current. The first resistor R1 combines with the first bias current to perform a first voltage shift on the first reference voltage Vref1 and output the second reference voltage Vref2. The fourth NMOS transistor MN4 outputs a second bias current. The second resistor R2 combines with the second bias current to perform a second voltage shift on the first voltage to be detected Vsense1 and output the second voltage to be detected Vsense2. To ensure that the difference between the second voltage to be detected Vsense2 and the first voltage to be detected Vsense1 is equal to the difference between the second reference voltage Vref2 and the first reference voltage Vref1, it is necessary to set the first resistor R1 equal to the second resistor R2, and the first bias current equal to the second bias current. To make the first bias current equal to the second bias current, it is necessary to set the aspect ratio of the third NMOS transistor MN3 equal to the aspect ratio of the fourth NMOS transistor MN4. Since the difference between the second voltage to be detected Vsense2 and the first voltage to be detected Vsense1 is equal to the difference between the second reference voltage Vref2 and the first reference voltage Vref1, the difference between the second voltage to be detected Vsense2 and the second reference voltage Vref2 is equal to the difference between the first voltage to be detected Vsense1 and the first reference voltage Vref1, thus realizing the normal detection of the first voltage to be detected Vsense1.

[0054] Figure 3 Schematic diagram of the circuit structure of the voltage detection circuit provided by the embodiment of the present invention Figure 3 。

[0055] Please refer to Figure 3 In another embodiment, the comparator CMP and the current mirror module 20 are the same as those in the previous embodiment. The voltage shift module 30 is further provided with a first overvoltage protection unit 34 and a second overvoltage protection unit 35. The first overvoltage protection unit 34 is coupled between the second end of the second voltage shift unit 32 and the third current mirror 33. The first overvoltage protection unit 34 is used to perform overvoltage protection on the third current mirror 33. The second overvoltage protection unit 35 is coupled between the second end of the second voltage shift unit 32 and the comparator CMP. The second overvoltage protection unit 35 is used to perform overvoltage protection on the comparator CMP.

[0056] Specifically, the first overvoltage protection unit 34 includes a fifth high-voltage withstand NMOS transistor MN5. The gate of the fifth high-voltage withstand NMOS transistor MN5 is connected to the power supply voltage VCC. The source of the fifth high-voltage withstand NMOS transistor MN5 is connected to the third current mirror 33. The drain of the fifth high-voltage withstand NMOS transistor MN5 is connected to the second end of the second voltage shift unit 32.

[0057] The second overvoltage protection unit 35 includes a sixth high-voltage withstand NMOS transistor MN6. The gate of the sixth high-voltage withstand NMOS transistor MN6 is connected to the power supply voltage VCC. The source of the sixth high-voltage withstand NMOS transistor MN6 is connected to the comparator CMP. The drain of the sixth high-voltage withstand NMOS transistor MN6 is connected to the second end of the second voltage shift unit 32.

[0058] In summary, the voltage detection circuit provided by the embodiment of the present invention, when the first reference voltage is less than zero, the current mirror module inputs a first current from the first output end of the voltage shift module to the first input end of the voltage shift module. Since the first current is used to ensure that when the second reference voltage is less than zero, the second reference voltage is greater than or equal to zero, the normal operation of the comparator is ensured. At the same time, the current mirror module also inputs a second current from the second output end of the voltage shift module to the second input end of the voltage shift module, and the first current is equal to the second current, so as to realize the normal detection of the first voltage to be detected on the basis of the normal operation of the comparator.

[0059] The embodiment of the present invention also provides a circuit system, including the voltage detection circuit.

[0060] The embodiment of the present invention also provides an electronic device, including the circuit system.

[0061] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage detection circuit, characterized in that, Comprising: A voltage shift module, configured to perform a first voltage shift on a received first reference voltage and output a second reference voltage, and further configured to perform a second voltage shift on a received first voltage to be detected and output a second voltage to be detected. A first input terminal of the voltage shift module receives the first reference voltage, a first output terminal of the voltage shift module outputs the second reference voltage, a second input terminal of the voltage shift module receives the first voltage to be detected, and a second output terminal of the voltage shift module outputs the second voltage to be detected; A comparator, configured to compare the second reference voltage and the second voltage to be detected and output a comparison result signal; A current mirror module, configured to output a first current to the first output terminal of the voltage shift module when the first reference voltage is less than zero, and further configured to output a second current to the second output terminal of the voltage shift module when the first reference voltage is less than zero. The first current is equal to the second current, and the minimum value of the first current and the first reference voltage is set to be proportional, so that the second reference voltage is greater than or equal to zero; The voltage shift module is further configured to output the first current from its first input terminal and output the second current from its second input terminal.

2. The voltage detection circuit according to claim 1, wherein The current mirror module includes a current source, a first current mirror, and a second current mirror. An anode of the current source is connected to a power supply voltage, a cathode of the current source is connected to a first input terminal of the first current mirror, a second input terminal of the first current mirror is connected to a first output terminal of the second current mirror, an output terminal of the first current mirror is connected to the first output terminal of the voltage shift module. The first current mirror is configured to output the first current to the first output terminal of the voltage shift module when the first reference voltage is less than zero. A second output terminal of the second current mirror is connected to the second output terminal of the voltage shift module. The second current mirror is configured to mirror the first current and output the second current to the second output terminal of the voltage shift module.

3. The voltage detection circuit according to claim 1, characterized in that, The first current mirror includes a first NMOS transistor and a second NMOS transistor. A drain of the first NMOS transistor serves as the first input terminal of the first current mirror. A gate of the first NMOS transistor is connected to its own drain and a gate of the second NMOS transistor. A source of the first NMOS transistor is grounded. A source of the second NMOS transistor serves as the output terminal of the first current mirror to output the first current, and a drain of the second NMOS transistor serves as the second input terminal of the first current mirror.

4. The voltage detection circuit according to claim 3, wherein The second current mirror includes a first PMOS transistor and a second PMOS transistor. A drain of the first PMOS transistor serves as the first output terminal of the second current mirror and is connected to the drain of the second NMOS transistor. A gate of the first PMOS transistor is connected to its own drain and a gate of the second PMOS transistor. A drain of the second PMOS transistor serves as the second output terminal of the second current mirror to output the second current. Sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage.

5. The voltage detection circuit according to claim 4, wherein The voltage shift module includes a third current mirror, a first voltage shift unit, and a second voltage shift unit. The third current mirror is configured to output a first bias current and a second bias current. The first end of the first voltage shift unit serves as the first input end of the voltage shift module, and the second end of the first voltage shift unit serves as the first output end of the voltage shift module. The first voltage shift unit is configured to perform a first voltage shift on the first reference voltage according to the first bias current and output the second reference voltage. The first end of the second voltage shift unit serves as the second input end of the voltage shift module, and the second end of the second voltage shift unit serves as the second output end of the voltage shift module. The second voltage shift unit is configured to perform a second voltage shift on the first voltage to be detected according to the second bias current and output the second voltage to be detected.

6. The voltage detection circuit according to claim 5, wherein The first voltage shift unit includes: a first resistor, where the first end of the first resistor serves as the first end of the first voltage shift unit, and the second end of the first resistor serves as the second end of the first voltage shift unit; The second voltage shift unit includes: a second resistor, where the first end of the second resistor serves as the first end of the second voltage shift unit, and the second end of the second resistor serves as the second end of the second voltage shift unit.

7. The voltage detection circuit according to claim 6, wherein The third current mirror includes a third NMOS transistor and a fourth NMOS transistor. The drain of the third NMOS transistor is connected to the second end of the first resistor; the gate of the third NMOS transistor is connected to its own drain and the gate of the fourth NMOS transistor. The drain of the fourth NMOS transistor is connected to the second end of the second resistor. The sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the ground terminal.

8. The voltage detection circuit according to claim 5, characterized in that, The voltage shift module further includes a first overvoltage protection unit and a second overvoltage protection unit. The first overvoltage protection unit is coupled between the second end of the second voltage shift unit and the third current mirror. The first overvoltage protection unit is configured to perform overvoltage protection on the third current mirror. The second overvoltage protection unit is coupled between the second end of the second voltage shift unit and the comparator. The second overvoltage protection unit is configured to perform overvoltage protection on the comparator.

9. The voltage detection circuit according to claim 8, wherein The first overvoltage protection unit includes a fifth high-voltage-resistant NMOS transistor. The gate of the fifth high-voltage-resistant NMOS transistor is connected to the power supply voltage. The source of the fifth high-voltage-resistant NMOS transistor is connected to the third current mirror. The drain of the fifth high-voltage-resistant NMOS transistor is connected to the second end of the second voltage shift unit; The second overvoltage protection unit includes a sixth high-voltage-resistant NMOS transistor. The gate of the sixth high-voltage-resistant NMOS transistor is connected to the power supply voltage. The source of the sixth high-voltage-resistant NMOS transistor is connected to the comparator. The drain of the sixth high-voltage-resistant NMOS transistor is connected to the second end of the second voltage shift unit.

10. A circuit system, characterized in that, Including the voltage detection circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that, Including the circuit system according to claim 10.

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