Micro-nano processing method and transistor

Abstract

The invention provides a micro-nano machining method and a transistor, and relates to the technical field of micro-nano machining. The method comprises the following steps: exposing a structural body by using ultraviolet light with a preset wavelength under the condition that the surface of the structural body is spin-coated with photoresist; wherein the surface of the structural body is a two-dimensional material layer; attaching the metal electrode layer to the surface of the two-dimensional material layer on the surface of the structural body under the condition that the exposure is finished; under the condition that the metal electrode layer is attached to the structural body, the structural body is spin-coated with the photoresist again, and secondary exposure is conducted through ultraviolet light with the preset wavelength; wherein the preset wavelength is determined according to the structural line width and the structural strength of the two-dimensional material layer. According to the method, the damage condition of the two-dimensional material in the exposure process can be improved, so that the defect density of the two-dimensional material is effectively reduced, and the contact performance of the two-dimensional material is optimized. Meanwhile, the method can be combined with a traditional CMOS process to be further applied to large-scale manufacturing of other two-dimensional material transistors.

Description

Technical Field

[0001] This application relates to the field of micro-nano processing technology. Specifically, it relates to a micro-nano processing method and a transistor. Background Art

[0002] In recent years, with the rapid development of artificial intelligence and mobile terminals, the requirements for high computing power and low energy consumption of chips have become increasingly high. Two-dimensional semiconductor materials with atomic layer thickness (such as transition metal sulfide MoS2, etc.) have great potential in future large-scale integrated circuits. However, the performance of a single device based on MoS2 still cannot be compared with that of traditional silicon-based field-effect transistors. The contact resistance of two-dimensional material transistors is generally one to two orders of magnitude higher than that of silicon-based transistors, far from meeting the requirements of the latest IRDS for the contact resistance index of traditional field-effect transistors.

[0003] There are two main factors affecting the contact resistance of MoS2 transistors. One of them is the defect-induced state caused by material defects. The defects will further lead to the Fermi level pinning effect, thus affecting the contact performance between the semiconductor and the metal. Therefore, continuously improving the device structure or processing technology to make the contact resistance between the two-dimensional material and the metal approach the level of traditional transistors is one of the important research directions in the current research field.

[0004] Traditional micro-nano processing means include electron beam lithography and optical lithography, etc. Some studies have shown that primary electrons, secondary electrons in electron beam lithography, and ultraviolet exposure in optical lithography can damage two-dimensional materials from graphene to transition metal sulfide films. Therefore, improving the micro-nano processing technology is also one of the means to effectively reduce the contact resistance of two-dimensional material transistors. In 2019, the team of Elisa Riedo at New York University studied the combination of a dual-polymer stack chemical etching / lift off process and a thermal scanning probe lithography (t-SPL) process. Using the t-SPL technology, different metals were used as the contact electrodes of single-layer MoS2 transistors, and top-gate and bottom-gate field-effect transistors were fabricated, and the electrical properties of the transistors were characterized. Although the t-SPL micro-nano processing technology can avoid defects caused by irradiation to the material, the processing time of a single device is long, and it is not suitable for large-scale fabrication of transistors in combination with the CMOS process. Summary of the Invention

[0005] In view of this, the purpose of the embodiments of the present application is to provide a micro-nano processing method to improve the following problems existing in the prior art: First, in the process of fabricating electronic devices with small line widths in traditional technologies, the light sources used, such as primary electrons and secondary electrons in electron beam lithography, and ultraviolet exposure in optical lithography, have high energy, which causes MoS2 to be easily irradiated, increasing the defect density of the material and affecting its intrinsic electrical properties. However, low-energy light sources have large processing line widths. Second, the existing t-SPL technology that can improve the damage to two-dimensional materials has a long processing cycle and is not suitable for large-scale fabrication of transistors in combination with CMOS technology.

[0006] The method includes: when spin-coating a photoresist on the surface of a structure, exposing the structure with ultraviolet light of a preset wavelength; wherein, the surface of the structure is a two-dimensional material layer; when the exposure ends, attaching a metal electrode layer to the surface of the two-dimensional material layer on the surface of the structure; when the metal electrode layer is attached to the structure, spin-coating the photoresist on the structure again and performing secondary exposure with ultraviolet light of a preset wavelength; wherein, the preset wavelength is determined according to the structural line width and structural strength of the two-dimensional material layer.

[0007] In the above implementation process, when there is a basic structure of a structure, it is processed. The preset wavelength of ultraviolet light is used to perform fine processing on it, so that the structure can have good electrical properties. In addition, this method improves the damage condition of the two-dimensional material during the exposure process, effectively reduces the defect density of the two-dimensional material, optimizes its contact performance, and enables it to better combine with the traditional CMOS process and be applied to the large-scale manufacturing of other two-dimensional material transistors.

[0008] Optionally, the structure is composed of a base layer, a dielectric layer, and an excitation metal layer; the preparation method of the structure includes: attaching the excitation metal layer to the surface of the base layer; when the excitation metal layer is attached to the surface of the base layer, attaching the dielectric layer to the surface of the excitation metal layer; when the dielectric layer is attached to the surface of the excitation metal layer, attaching the two-dimensional material layer to the surface of the dielectric layer.

[0009] In the above implementation process, first, the excitation metal layer is attached to the surface of the base layer, providing a stable attachment foundation for subsequent layers and enhancing the conductivity or optical properties of the structure. Next, the attachment of the dielectric layer not only plays an insulating role but also effectively isolates the excitation metal layer from the two-dimensional material layer, preventing unnecessary interactions and possibly improving the generation of defects in the two-dimensional material layer. Finally, the two-dimensional material layer is attached to the surface of the dielectric layer, and the properties of the dielectric layer are used to optimize the performance of the two-dimensional material layer, such as improving its carrier mobility or stability. The entire preparation process requires precise control of the material selection, attachment method, and process parameters of each layer to ensure good bonding between the layers and excellent performance of the overall structure.

[0010] Optionally, when the excitation metal layer is attached to the surface of the base layer, attaching the dielectric layer to the surface of the excitation metal layer includes: when the excitation metal layer is attached to the surface of the base layer, cleaning the base layer with the attached excitation metal layer using a variety of cleaning media; when drying the cleaned base layer with the attached excitation metal layer, evacuating the base layer with the attached excitation metal layer to a preset vacuum degree and heating the base layer with the attached excitation metal layer to the preparation temperature.

[0011] In the above implementation process, first, after the excitation metal layer is attached to the surface of the base layer, the base layer with the attached excitation metal layer is cleaned using a variety of cleaning media to remove surface impurities and contaminants. Then, the cleaned base layer is dried to eliminate residual moisture or solvents to prevent them from affecting the attachment quality and performance of subsequent layers; the base layer with the attached excitation metal layer is evacuated until the preset vacuum degree is reached, which helps to exclude factors such as oxygen and water vapor in the air that may interfere with the attachment of the dielectric layer and reduces defects in the dielectric layer during the preparation process. Finally, the base layer with the attached excitation metal layer is heated to the preparation temperature to further improve the adhesion between the dielectric layer and the excitation metal layer and promote the uniform deposition and curing of the dielectric layer material, thus ensuring the quality and performance of the dielectric layer and laying the foundation for the attachment of the subsequent two-dimensional material layer and the stability and electrical performance of the entire structure.

[0012] Optionally, when the dielectric layer is attached to the surface of the excitation metal layer, attaching the two-dimensional material layer to the surface of the dielectric layer includes: when a PMMA solution is coated on the surface of the two-dimensional material layer, heating the two-dimensional material layer; transferring the two-dimensional material layer to the surface of the dielectric layer using deionized water.

[0013] In the above implementation process, first, a PMMA (polymethyl methacrylate) solution is coated on the surface of the two-dimensional material layer. This step is to protect the two-dimensional material layer during the transfer process, preventing it from being damaged or contaminated during the transfer. At the same time, PMMA, as a commonly used transfer auxiliary material, can effectively help the two-dimensional material layer transfer from the original substrate to the surface of the target dielectric layer. Then, the two-dimensional material layer is heated. This step helps to cure the PMMA, improve its adhesion to the two-dimensional material layer, and ensure that the two-dimensional material layer can be transferred to the surface of the dielectric layer completely and evenly during the subsequent transfer process. Subsequently, deionized water is used to transfer the two-dimensional material layer to the surface of the dielectric layer. The use of deionized water can reduce the interference of ions in the water on the two-dimensional material layer and the surface of the dielectric layer, ensuring the purity of the transfer process, and thus achieving good contact and adhesion between the two-dimensional material layer and the dielectric layer. The entire transfer process requires precise control of parameters such as the concentration of the PMMA solution, the coating thickness, the heating temperature and time, as well as the purity and transfer speed of the deionized water, to ensure that the integrity and performance of the two-dimensional material layer after transfer are not affected, laying a foundation for subsequent processing steps and the performance of the final device.

[0014] Optionally, the spin-coated photoresist includes: the thickness of the photoresist is 40 to 80 nm, the spin-coating speed is 1500 to 2500 r / s, and the spin-coating duration is 30 to 60 s; in the case of completing the spin-coating of the photoresist, the photoresist on the structure is baked; wherein, the baking temperature is 80 to 120 °C, and the baking time is 3 to 5 minutes.

[0015] In the above implementation process, on the premise of ensuring that the photoresist is evenly coated on the structure, this temperature and time range are based on the chemical properties of the photoresist and the thermal stability of the structure, ensuring the full curing of the photoresist and not causing thermal damage or performance degradation to the two-dimensional material layer, dielectric layer, etc. in the structure. By precisely controlling these process parameters, this method can improve the quality and performance of the photoresist film, thus providing guarantee for the subsequent exposure step and the smooth progress of the entire micro-nano processing process.

[0016] Optionally, the use of ultraviolet light with a preset wavelength for exposure includes: the ultraviolet exposure time is 10 to 30 seconds, and the ultraviolet exposure power is 5 to 20 mW.

[0017] In the above implementation process, by controlling the exposure time and power of the ultraviolet light, the exposure effect of the photoresist can be effectively improved, ensuring the precise transfer of the pattern, and thus providing strong guarantee for the subsequent processing steps and the performance of the final device.

[0018] Optionally, the method further includes: spin-coating a photoresist on the surface of the structure, and in the case of the end of exposure, developing and fixing the structure; wherein, the developing and fixing times are 30 to 60 seconds respectively.

[0019] In the above implementation process, by controlling the development and fixing time, the clarity and accuracy of the photoresist pattern are ensured, providing a delicate template for the subsequent attachment of the metal electrode layer and other processing steps, thereby guaranteeing the performance and quality of the final device.

[0020] Optionally, the method further includes: when the development and fixing operations of the structure are completed, performing channel etching on the developed structure; wherein, the etching plasma is one of oxygen or argon; the etching power is 30 to 80 w; the etching time is 1 to 3 minutes.

[0021] In the above implementation process, after the development and fixing operations of the structure are completed, channel etching is further performed on the developed structure to form the required channel structure. By controlling the type of etching plasma, etching power, and etching time, high-precision channel etching can be achieved, providing a strong guarantee for the subsequent attachment of the metal electrode layer and the final performance of the device.

[0022] Optionally, the wavelength range of the preset wavelength includes 355 nm to 370 nm.

[0023] In the above implementation process, under specific illumination conditions, metals can excite surface plasmons to achieve super-resolution lithography. When ultraviolet light with a preset wavelength is incident on the surface of the excited metal layer at a specific angle, the free electrons in the metal interact with the light field to excite surface plasmon waves. The excited surface plasmon waves interfere with each other to form intensity fringes with a periodic distribution in space. These fringes can be transferred to the photoresist to form nanoscale periodic patterns.

[0024] The embodiment of the present application also provides a transistor, which is made by the aforementioned micro-nano processing method; the transistor includes: a base layer, a dielectric layer, a two-dimensional material layer, a metal electrode layer, and an excited metal layer; the base layer is placed at the bottom; the excited metal layer is disposed on the surface of the base layer; the excited metal layer connects the base layer and the dielectric layer; the two-dimensional material layer is disposed on the surface of the dielectric layer; the metal electrode layer is connected to the two-dimensional material layer.

[0025] In the above implementation process, the structural settings and manufacturing processes of the entire transistor cooperate with each other. By controlling the material selection, thickness, attachment method, and processing parameters of each layer, the high performance and stability of the transistor are achieved. It can not only effectively reduce the defect density of two-dimensional materials during the preparation process and optimize their contact performance, but also combine with traditional CMOS processes to achieve large-scale manufacturing, providing a feasible solution for the application of two-dimensional materials. Description of the Drawings

[0026] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0027] Figure 1 Schematic diagram of the micro-nano processing method provided by the embodiment of the present application;

[0028] Figure 2 The first schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0029] Figure 3 The second schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0030] Figure 4 The third schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0031] Figure 5 The fourth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0032] Figure 6 The fifth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0033] Figure 7 The sixth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0034] Figure 8 The seventh schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0035] Figure 9 The eighth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0036] Figure 10 The ninth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0037] Figure 11 The tenth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0038] Figure 12 The eleventh schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application;

[0039] Figure 13a and Figure 13bRaman scanning imaging diagram of the MoS2 thin film provided by the embodiment of the present application after irradiation with 365 nm and 193 nm ultraviolet light;

[0040] Figure 14 Statistical chart of doping and strain changes of the MoS2 thin film provided by the embodiment of the present application after irradiation with 365 nm and 193 nm ultraviolet light;

[0041] Figure 15 Raman scanning imaging diagram of the MoS2 thin film provided by the embodiment of the present application after irradiation with electron beam and 365 nm ultraviolet light;

[0042] Figure 16 SEM image of a 100 nm linewidth device realized by the micro-nano processing method provided by the embodiment of the present application.

[0043] Icon: 10 - base layer; 20 - excitation metal layer; 30 - dielectric layer; 40 - two-dimensional material layer; 50 - photoresist; 60 - metal electrode layer. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the embodiments of the present application.

[0045] Optionally, please refer to Figure 1 , Figure 1 Schematic diagram of the micro-nano processing method provided by the embodiment of the present application.

[0046] This micro-nano processing method includes: when spin-coating the photoresist 50 on the surface of the structure body, exposing the structure body with ultraviolet light of a preset wavelength; wherein, the surface of the structure body is the two-dimensional material layer 40; when the exposure is completed, attaching the metal electrode layer 60 to the surface of the two-dimensional material layer 40 on the surface of the structure body; when the metal electrode layer 60 is attached to the structure body, spin-coating the photoresist 50 on the structure body again and performing secondary exposure with ultraviolet light of a preset wavelength; wherein, the preset wavelength is determined according to the structural linewidth and structural strength of the two-dimensional material layer 40.

[0047] In the above implementation process, the first spin coating of the photoresist 50 and the exposure to ultraviolet light with a preset wavelength are to form a specific pattern on the two-dimensional material layer 40 on the surface of the structure, providing position and shape guidance for the subsequent attachment of the metal electrode layer 60. The selection of the preset wavelength needs to match the optical and physical properties of the two-dimensional material layer 40 to ensure that the photoresist 50 can be correctly cured during the exposure process, thereby forming the required pattern. For example, the structural line width is usually referred to as the "critical dimension" (CD), which is the smallest line width in the device structure, usually referring to the length of the transistor gate. At this time, the selection of the preset wavelength needs to consider matching the structural line width that can be fabricated by the two-dimensional material layer 40. Furthermore, the structural strength mainly measures the ability of a material or component not to be damaged (such as fractured) or undergo excessive deformation under the action of external forces. In the case of processing the two-dimensional material layer 40, its structural strength needs to be considered to avoid unexpected deformation of the material. After the attachment of the metal electrode layer 60, the second spin coating of the photoresist 50 and the exposure to ultraviolet light with a preset wavelength refine the structure, ensuring the precise connection between the metal electrode layer 60 and the two-dimensional material layer 40, while enhancing the overall stability and electrical performance of the structure.

[0048] Optionally, please combine Figures 2 to 11 , the foregoing drawings are all schematic diagrams of the specific operations of the micro-nano processing method provided by the embodiments of the present application. Next, the micro-nano processing method will be specifically described according to the steps.

[0049] Figures 2 to 4 The formation process of the structure is described. It can be seen that the structure is composed of a base layer 10, a dielectric layer 30, and an excitation metal layer 20; and the preparation method of the structure includes: attaching the excitation metal layer 20 to the surface of the base layer 10; in the case where the excitation metal layer 20 is attached to the surface of the base layer 10, attaching the dielectric layer 30 to the surface of the excitation metal layer 20; in the case where the dielectric layer 30 is attached to the surface of the excitation metal layer 20, attaching the two-dimensional material layer 40 to the surface of the dielectric layer 30.

[0050] In the above implementation process, the substrate serves as the foundation of the entire structure, providing mechanical support for the upper-layer materials, ensuring the structural stability of the entire device, and preventing deformation or damage during processing and use. Under specific light conditions, the excitation metal layer 20 can excite surface plasmons (SP), thereby realizing functions such as super-resolution lithography, enhancing the light field intensity, and achieving sub-wavelength scale lithography. The presence of the excitation metal layer 20 can enhance the interaction between light and the photoresist 50, improving the light absorption efficiency, photocatalytic performance, etc. When the excitation metal layer 20 is plated on the base layer 10, the dielectric layer 30 is plated on the surface of the excitation metal layer 20. After plating the dielectric layer 30, the two-dimensional material layer 40 is transferred above the base layer 10 plated with the dielectric layer 30.

[0051] The dielectric layer 30 can isolate the excited metal layer 20 from the two-dimensional material layer 40, preventing problems such as chemical reactions and charge transfer caused by direct contact between the metal and the two-dimensional material, and protecting the performance of the two-dimensional material. The dielectric layer 30 can change the propagation and distribution of light in the structure, such as forming an optical resonator, waveguide, etc., further enhancing the light field intensity, prolonging the interaction time of light and matter, and improving the light utilization efficiency.

[0052] Two-dimensional materials have unique physical properties, such as high mobility, strong light-matter interaction, rich electronic states, etc., and can be used to prepare high-performance transistors, sensors, photodetectors and other devices. Two-dimensional materials can work together with the substrate, the excited metal layer 20, the dielectric layer 30, etc., giving play to their respective advantages and realizing more complex functions and performances.

[0053] Specifically, as Figure 2 shown, when the excited metal layer 20 is attached to the surface of the base layer 10, attaching the dielectric layer 30 to the surface of the excited metal layer 20 includes: when the excited metal layer 20 is attached to the surface of the base layer 10, cleaning the base layer 10 with the attached excited metal layer 20 using a variety of cleaning media; when drying the cleaned base layer 10 with the attached excited metal layer 20, evacuating the base layer 10 with the attached excited metal layer 20 to a preset vacuum degree and heating the base layer 10 with the attached excited metal layer 20 to the preparation temperature.

[0054] Optionally, silver can be selected as the material for the excited metal layer 20, or gold or aluminum can be selected as the material; the thickness of the excited metal layer 20 is controlled between 10 nm and 30 nm.

[0055] Optionally, magnetron sputtering, electron beam deposition, or thermal evaporation in physical vapor deposition (PVD) can be used to deposit the excited metal layer 20 on the base layer 10.

[0056] Optionally, the variety of cleaning media can be acetone, ethanol, and deionized water. Acetone and ethanol can be miscible with organic solvents and have strong volatility, and deionized water can wash away residual ions and can also wash away residual organic solvents.

[0057] In an embodiment of the present application, the selected substrate here is silicon, and other substances with relatively stable physical and chemical properties can also be selected according to needs. The material selected for the excitation metal layer 20 is silver. It is processed by magnetron sputtering. First, substrate pretreatment is carried out. The substrate is ultrasonically cleaned with acetone, ethanol, and deionized water for 10 minutes each in sequence, and then dried with nitrogen gas. Under the condition of completing the cleaning, a high-purity silver target (above 99.99%) is used, and the distance between the target and the substrate is set to 50 to 100 mm, and specifically needs to be adjusted according to the actual situation of the equipment. The parameter settings during sputtering are a background vacuum less than 5×10 -6 Torr to ensure a high-vacuum environment. High-purity Ar (99.999%) is used as the sputtering gas, and its flow rate is 20 to 30 sccm. The set value of the working pressure is 3 to 5 mTorr. A DC power supply is used, and the sputtering power is set to 50 to 100 W. The continuous sputtering time is about 20 to 100 seconds, and specifically adjusted to the coating thickness according to the rate. In the present application, the thickness of the excitation metal layer 20 is controlled between 10 nm and 30 nm.

[0058] In an embodiment of the present application, the excitation metal layer 20 can also be deposited on the surface of the base layer 10 by electron beam evaporation. The selected substrate here is also silicon, and other substances with relatively stable physical and chemical properties can also be selected according to needs. Similarly, the material selected for the excitation metal layer 20 is silver. The pretreatment of the substrate is the same as that processed by magnetron sputtering. In this step, the surface oxide needs to be completely removed to avoid the influence of impurities in the subsequent steps. The high-purity silver particles (99.999%) are placed in a molybdenum or graphite crucible, and at the same time, the substrate temperature is ensured to be at room temperature or low temperature (<100 °C). The evaporation parameters for it are a ultra-high vacuum environment less than 1×10 -6 Torr. The electron beam current is 50 to 150 mA (adjusted according to the melting requirement of the silver source). The acceleration voltage is set to 5 to 10 kV, the deposition rate is 0.1 to 0.3 nm / s (here, it needs to be monitored in real time by a quartz crystal microbalance), and the deposition time is 30 to 100 seconds (here is the case of depositing the excitation metal layer 20 to 10 nm).

[0059] In an embodiment of the present application, thermal evaporation can also be selected to process the excitation metal layer 20. Without changing the selected materials, the base layer 10 is pretreated to avoid the decomposition of residual organic substances at high temperature in the subsequent process. The silver wire or silver foil is wound in a tungsten boat or tantalum boat. The substrate temperature is set to room temperature. Set less than 1×10 -5A high-vacuum environment of Torr. The heating current is adjusted according to the resistance of the tungsten boat, which can be set to 30 to 50 A here; and the excitation metal layer 20 needs to be slowly evaporated to improve uniformity, so its deposition rate is set to 0.05 to 0.1 nm / s, and the deposition time is set to 100 to 200 seconds (this is the case where the excitation metal layer 20 is deposited to 10 nm).

[0060] Optionally, please refer to Figure 3 , Figure 3 which is the second schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application. Figure 3 It describes that in the case where the excitation metal layer 20 is attached to the surface of the base layer 10, the dielectric layer 30 is attached to the surface of the excitation metal layer 20. The dielectric layer 30 can isolate the excitation metal layer 20 from the two-dimensional material layer 40, preventing problems such as chemical reactions and charge transfer caused by direct contact between the metal and the two-dimensional material, thereby protecting the performance of the two-dimensional material. In electronic devices such as transistors, the dielectric layer 30 serves as a gate dielectric, and its properties such as dielectric constant will affect the concentration and mobility of carriers, thereby regulating the electrical performance of the device.

[0061] Optionally, the dielectric layer 30 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0062] In an embodiment of the present application, about 10 to 20 nm of Al2O3 is deposited as the dielectric layer 30 on a silver-plated substrate using an atomic layer deposition (ALD) device. In the case where the excitation metal layer 20 is attached to the surface of the base layer 10, the substrate (the base layer 10 and the excitation metal layer 20) is pretreated: the substrate is ultrasonically cleaned with acetone, ethanol, and deionized water for 10 minutes each to remove organic substances and particles. After being dried with nitrogen, it is treated with oxygen plasma to enhance surface hydrophilicity. The power of the oxygen plasma is set to 100 W and it is treated for 5 minutes; the environment where the substrate is located is evacuated (or purged with high-purity nitrogen) until the base pressure is less than or equal to 10-3 Torr, and the substrate is heated to 200 to 250 °C to balance the film quality and the thermal stability of the substrate; the Al2O3 film is deposited by ALD, and the thickness of the Al2O3 film increases by about 0.1 nanometer for one deposition cycle. By controlling the number of cycles, the film thickness can be controlled, and after the treatment is completed, a sample is taken from the chamber.

[0063] Optionally, please refer to Figure 4 , Figure 4 which is the third schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application.

[0064] Figure 4Describes the process of attaching the two-dimensional material layer 40 to the surface of the dielectric layer 30 when the dielectric layer 30 is attached to the surface of the excitation metal layer 20. This process includes: heating the two-dimensional material layer 40 when a PMMA solution is coated on the surface of the two-dimensional material layer 40; transferring the two-dimensional material layer 40 to the surface of the dielectric layer 30 using deionized water.

[0065] In the above implementation process, the detailed steps are as follows. First, configure a KOH solution with a concentration of 4 to 5 mol / L using deionized water. Then, set the rotation speed of the spin coater to 3000 r / min and spin coat the PMMA solution on the substrate (different from the aforementioned base layer 10) with the CVD-grown two-dimensional material layer 40 thin film. Generally, spin coating needs to be performed 4 to 6 times. Then, place the sample substrate with spin-coated PMMA on a heating plate at 120 °C and heat for 10 s. After that, use a blade to gently scratch around the substrate once to facilitate the subsequent etching of the sample substrate with spin-coated PMMA by the KOH solution. Subsequently, place the sample substrate with spin-coated PMMA solution in the configured KOH solution and soak it until the sample after spin-coating the PMMA solution, that is, the PMMA thin film (the grown two-dimensional material layer 40 thin film), completely detaches from the substrate. At this time, use a blank substrate to lift the PMMA thin film from the bottom up. After that, transfer the lifted PMMA thin film to deionized water and rinse it 2 times. After rinsing, lift the PMMA thin film again using the same method. Finally, transfer the cleaned PMMA thin film to the base layer 10 coated with the dielectric layer 30.

[0066] In an embodiment of the present application, the two-dimensional material layer 40 is a MoS2 thin film; the substrate for growing the two-dimensional material layer 40 is a silicon wafer.

[0067] Please refer to Figure 5 , Figure 5 which is the fourth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application.

[0068] Optionally, the spin-coated photoresist 50 includes: the thickness of the photoresist 50 is 40 to 80 nm, the spin coating rotation speed is 1500 to 2500 r / s, and the spin coating duration is 30 to 60 s; after the spin coating of the photoresist 50 is completed, bake the photoresist 50 on the structure; wherein, the baking temperature is 80 to 120 °C and the baking time is 3 to 5 minutes.

[0069] In the above implementation process, during the spin coating process of the photoresist 50, the thickness of the photoresist 50 needs to be such that the photoresist 50 maintains good photosensitivity and resolution during the subsequent exposure process, and can also effectively cover the fine structures on the surface of the structure, providing a basis for the accurate transfer of patterns. The control of the spin coating speed and time can enable the photoresist 50 to be evenly distributed on the surface of the structure under the action of centrifugal force, so that the photoresist 50 reaches a stable thickness distribution on the surface of the structure, avoiding problems such as uneven thickness or pattern transfer defects, and taking into account the spin coating efficiency and the consumption of the photoresist 50. After the spin coating of the photoresist 50 is completed, the photoresist 50 on the structure is baked. The purpose of baking is to remove the solvent in the photoresist 50, improve the viscosity and mechanical strength of the photoresist 50, and enable it to maintain good adhesion and pattern fidelity during the subsequent exposure and development processes.

[0070] In an embodiment of the present application, a positive photoresist 50 with a thickness of 40 nm is spin coated on the surface of the two-dimensional material layer 40 of the structure. The spin coating parameters are set to a rotation speed of 1500 r / s for 30 s, and after spin coating, it is baked on a hot plate at 100 °C for 3 minutes.

[0071] Please refer to Figure 6 , Figure 6 which is the fifth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application. It describes the exposure of the structure after spin coating the photoresist 50, and after development and fixing, the device as shown in Figure 6 is obtained.

[0072] Optionally, ultraviolet light with a preset wavelength is used for exposure, including: the ultraviolet exposure time is 10 to 30 seconds, and the ultraviolet exposure power is 5 to 20 mW.

[0073] In the above implementation process, when using ultraviolet light with a preset wavelength for exposure, the photoresist 50 needs to fully undergo a chemical reaction under the action of the ultraviolet light, so as to achieve the expected pattern transfer effect. At the same time, it is necessary to ensure the full exposure of the photoresist 50 without causing damage to the photoresist 50 or other materials due to excessive power, which affects the final processing quality.

[0074] Optionally, the wavelength range of the preset wavelength includes 355 nm to 370 nm.

[0075] In the above implementation process, because metal can excite surface plasmons under specific conditions, thereby achieving super-resolution lithography. Therefore, when ultraviolet light with a preset wavelength is incident on the surface of the excitation metal layer 20 at a specific angle, the free electrons in the metal interact with the light field to excite surface plasmon waves. The excited surface plasmon waves interfere with each other to form intensity fringes with a periodic distribution in space. These fringes can be transferred to the photoresist 50 to form nano-scale periodic patterns.

[0076] In one embodiment of the present application, ultraviolet light source with a wavelength of 355 nm is used for irradiation to excite the surface plasmon mode of the excitation metal layer 20, enabling the photoresist 50 to denature and form a pattern beyond the diffraction limit, so that the lithography pattern can present a line width of 100 nm.

[0077] Preferably, the wavelength of the preset wavelength is 365 nm.

[0078] In the above implementation process, to achieve the manufacturing of small line widths, electron beams or deep ultraviolet light are usually used. However, electron beams or deep ultraviolet light are prone to cause irradiation damage to the two-dimensional material layer 40 during the processing, resulting in defects. These defects will cause the Fermi level pinning effect between the two-dimensional material layer 40 and the metal, thereby affecting its contact performance. To avoid this situation, using ultraviolet light with a wavelength of 365 nm can achieve a feature size far smaller than the incident light wavelength on the photoresist 50, providing a basis for the preparation of high-density nano-devices. During the lithography process, the enhanced light field can expose the photoresist 50 on a smaller scale, thereby breaking through the diffraction limit of traditional optical lithography and improving the lithography resolution. At the same time, it can effectively avoid the irradiation effect on the two-dimensional material layer 40 during the exposure process, thereby reducing the defect density of the two-dimensional material layer 40 during the processing.

[0079] In one embodiment of the present application, the substrate with the spin-coated photoresist 50 is placed on the first mask plate, and exposed using 365 nm ultraviolet light. The exposure intensity and time are controlled, and after the exposure is completed, it is baked on a hot plate at 100 °C for 1 minute. Using 365 nm ultraviolet light can achieve a line width of 100 nm. In addition, this method can be combined with traditional CMOS processes and is expected to be further applied to the large-scale manufacturing of other two-dimensional material transistors.

[0080] Optionally, the method further includes: spin-coating the photoresist 50 on the surface of the structure body, and developing and fixing the structure body in the case of the exposure being completed; wherein, the developing and fixing times are 30 to 60 seconds respectively.

[0081] In the above implementation process, after spin-coating the photoresist 50 on the surface of the structure body and completing the exposure, the structure body is developed. The developing time is 30 to 60 seconds. The purpose of developing is to remove the unexposed part of the photoresist 50, so that the predetermined pattern appears in the photoresist 50 layer. Subsequently, a fixing process is carried out, and the fixing time is also 30 to 60 seconds, aiming to solidify the developed photoresist 50 pattern so that it will not deform or be damaged due to chemical reactions or physical effects during subsequent processing.

[0082] In one embodiment of the present application, after exposure, at a temperature of 25 °C, develop for 30 s using a developer solution with a concentration of 50%, fix in deionized water for 30 s, and observe the developed graphic structure under a microscope.

[0083] Please refer to Figure 7 , Figure 7 which is the sixth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application. In the case of the end of development, deposit a metal electrode layer 60 on the structure body.

[0084] Optionally, magnetron sputtering, electron beam deposition, or thermal evaporation in physical vapor deposition can also be used to deposit an excitation metal layer 20 on the base layer 10.

[0085] In one embodiment of the present application, electron beam evaporation is also used. Similarly, the steps are to ensure that the substrate temperature is at room temperature or low temperature (<100 °C), evacuate the gas in the working chamber to create a high-vacuum environment, and set its evaporation parameters to less than 1×10 -6 Torr ultra-high vacuum environment to reduce the influence of impurities on the film quality. Clean and surface-treat the substrate to remove contaminants and increase surface roughness, which helps film adhesion. Heat the substrate to the set temperature to improve film adhesion and nucleation efficiency. Place the material to be evaporated in the electron beam bombardment area, sublime it by electron beam heating, and deposit it on the substrate surface to form a film. The electron beam current is 50 to 150 mA (adjusted according to the metal melting requirement). Set the acceleration voltage to 5 to 10 kV, and the deposition rate to 0.1 to 0.3 nm / s (here, it needs to be monitored in real time by a quartz crystal microbalance), and the deposition time is 30 to 100 seconds (here is the case of depositing the metal electrode layer 60 to 10 nm). After the film deposition is completed, gradually reduce the substrate temperature to solidify and stabilize the film structure.

[0086] Optionally, the deposition thickness of the metal electrode layer 60 can be in the range of 20 to 60 nm.

[0087] In one embodiment of the present application, the selected metal electrode can be a mixed metal of chromium and gold. Among them, the thickness of chromium is 5 nm and the thickness of gold is 15 nm.

[0088] In another embodiment of the present application, the selected metal electrode can also be a mixed metal of titanium and gold. Among them, the thickness of titanium is 5 nm and the thickness of gold is 15 nm.

[0089] In one embodiment of the present application, as Figure 8 shown, Figure 8 which is the seventh schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application.

[0090] Since metals are deposited using processes such as electron beam evaporation or sputtering, and a photoresist layer 50 after lithography is retained thereon, the substrate with the deposited metal can be placed in a remover (such as acetone or N-Methyl-2-pyrrolidone, NMP) for lift-off stripping, or with the assistance of ultrasonic waves or other means to ensure complete stripping of the electrodes and the integrity of the pattern, and finally a patterned metal electrode is obtained. During lift-off stripping, the photoresist 50 can be removed while the metal on the photoresist 50 is also completely stripped off, so that only the metal of the originally etched pattern remains on the substrate.

[0091] Next, please refer to Figure 9 , Figure 9 which is the eighth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application.

[0092] In the case of stripping the excess photoresist 50 and the deposited metal, photoresist 50 is spin-coated again. The spin-coating parameters of photoresist 50 this time are as follows: the spin-coated thickness is 40 to 80 nm; the spin-coating speed is 1500 to 2500 r / s; the spin-coating time is 30 to 60 s. Similarly, baking is required after spin-coating, and the baking parameters after spin-coating are as follows: the baking temperature is 80 to 120 °C and the baking time is 3 to 5 min.

[0093] After the second spin-coating of photoresist 50 is completed, then as Figure 10 shown, it is subjected to secondary exposure. The substrate with spin-coated photoresist 50 is placed on the second mask plate, and ultraviolet light with a wavelength of 365 nm is used. The exposure time of the ultraviolet light is 10 to 30 s, and the ultraviolet light power is 5 to 20 mW. After the exposure is completed, it is baked on a heating plate at 100 °C for 1 minute. The baking parameters after exposure are as follows: the baking temperature is 80 to 120 °C, and the baking time is 1 to 3 min. Similarly, after the exposure is completed, it is developed. Under the condition of a temperature of 25 °C, it is developed with a developer with a concentration of 50% for 30 s to make the predetermined pattern appear in the photoresist layer 50. Subsequently, a fixing process is carried out, and it is fixed in deionized water for 30 s to solidify the developed photoresist 50 pattern.

[0094] Optionally, please refer to Figure 11 , Figure 11 which is the tenth schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application. The method further includes: when the structure is completed with the development and fixing operations, channel etching is performed on the developed structure; wherein, the etching plasma is one of oxygen or argon; the etching power is 30 to 80 w; the etching time is 1 to 3 minutes.

[0095] In the above implementation process, by controlling various parameters during the etching process, a high-quality channel structure can be achieved, thereby improving the performance and reliability of the device. When manufacturing semiconductor devices such as transistors, an accurate channel structure is formed through channel etching to control the conductivity of the device.

[0096] Optionally, the channel etching can be wet etching or dry etching. In dry etching, it can be ion beam etching (IBE) or reactive ion etching (RIE).

[0097] In an embodiment of the present application, dry etching is used for the developed device, and oxygen plasma is used for channel etching. The etching parameters are set as follows: the etching power is 30w, the etching gas is O2 and the gas flow rate is 30 sccm, and the etching time is 120s.

[0098] According to the above embodiment, please refer to Figure 12 , Figure 12 , which is the eleventh schematic diagram of the specific operation of the micro-nano processing method provided by the embodiment of the present application, mainly showing a schematic diagram of a MoS2 transistor finally obtained by removing the photoresist. The specific operation method is that after the etching is completed, the photoresist 50 is removed by hot acetone to obtain the finished device. When the two-dimensional material layer 40 is MoS2, the finished device is a MoS2 transistor.

[0099] The embodiment of the present application also provides a transistor, which is made by the aforementioned micro-nano processing method; the transistor includes: a base layer 10, a dielectric layer 30, a two-dimensional material layer 40, a metal electrode layer 60, and an excitation metal layer 20; the base layer 10 is placed at the bottom; the excitation metal layer 20 is disposed on the surface of the base layer 10; the excitation metal layer 20 is connected to the base layer 10 and the dielectric layer 30; the two-dimensional material layer 40 is disposed on the surface of the dielectric layer 30; the metal electrode layer 60 is connected to the two-dimensional material layer 40.

[0100] In the above implementation process, a transistor with a specific structure is fabricated using the aforementioned micro-nano processing method. The transistor is composed of a base layer 10, an excitation metal layer 20, a dielectric layer 30, a two-dimensional material layer 40, and a metal electrode layer 60. The base layer 10 is placed at the bottom of the entire structure, providing mechanical support and a basic platform for the entire transistor. The excitation metal layer 20 is disposed on the surface of the base layer 10, connecting the base layer 10 and the dielectric layer 30. While enhancing the structural stability, it serves as an excitation metal for exciting surface plasmons. The dielectric layer 30 is located above the excitation metal layer 20, not only acting as an insulating layer to isolate the excitation metal layer 20 from the two-dimensional material layer 40, but also providing a suitable environment for the two-dimensional material layer 40 to reduce defects and optimize its performance. The two-dimensional material layer 40 is disposed on the surface of the dielectric layer 30, serving as the core part of the transistor, responsible for the transport of carriers and the main electrical characteristics of the device. The metal electrode layer 60 is connected to the two-dimensional material layer 40 to form a good ohmic contact, ensuring that current can be efficiently injected into and out of the two-dimensional material layer 40, realizing the conductive and switching functions of the transistor. By this micro-nano processing method, small line-width transistors based on two-dimensional materials can be mass-produced, and during the manufacturing process, damage to the two-dimensional materials caused by ultraviolet light irradiation can be effectively avoided. Further, this method provides a new idea for the manufacturing of transistors of other two-dimensional materials.

[0101] In addition, due to the traditional process for fabricating small line-width transistor devices, the high energy of the electron beam or deep ultraviolet light source used results in the easy irradiation of MoS2, thereby increasing the defect density of the material and affecting its intrinsic electrical properties, while the processing line width of the low-energy light source is large. To achieve patterning with a line width of 100 nm, an electron beam or a 193 nm deep ultraviolet light with higher energy is generally used. However, the electron beam or 193 nm deep ultraviolet light is likely to cause irradiation damage to MoS2 during the processing, generating defects. The defects in the material will cause a Fermi level pinning effect between it and the metal, affecting its contact performance.

[0102] Please refer to Figures 13a - 13b , Figure 13a which is the Raman scanning imaging diagram of the MoS2 thin film provided by the embodiment of the present application at 365 nm. Figure 13b which is the Raman scanning imaging diagram of the MoS2 thin film provided by the embodiment of the present application after irradiation with 193 nm ultraviolet light.

[0103] It can be seen from the figure that the strain imaging diagram of the MoS2 thin film after irradiation with 193 nm shows obvious changes compared with that before irradiation. After irradiation, obvious compressive strain appears in the thin film, which will lead to a decrease in the uniformity of the thin film, thereby reducing its carrier transport performance in the device. However, the influence on the material after exposure to 365 nm ultraviolet light is relatively small.

[0104] Similarly, Figure 14Statistical chart of doping and strain changes of MoS2 thin film provided by the embodiment of the present application after irradiation with 365nm and 193nm ultraviolet light. It can also be seen that compared with exposure using 365nm, the overall strain defects of the MoS2 thin film after exposure using 193nm increase by 0.2%. This change will significantly affect the intrinsic properties of the thin film. For the MoS2 thin film after exposure using 365nm, its strain and doping basically do not change significantly, and its intrinsic characteristics are better retained.

[0105] Furthermore, Figure 15 Raman scanning imaging diagram of the MoS2 thin film provided by the embodiment of the present application after electron beam and 365nm ultraviolet light irradiation. In the figure, the intensity of the Raman characteristic peaks of the MoS2 thin film after electron beam irradiation has significantly decreased, indicating that the electron beam has a significant impact on the structure of the thin film. However, there is no obvious change in the MoS2 thin film after 365nm ultraviolet light irradiation, indicating that the 365nm ultraviolet light does not affect its structure.

[0106] Please refer to Figure 16 , Figure 16 SEM image of a 100nm linewidth device realized by the micro-nano processing method provided by the embodiment of the present application. As Figure 16 shown, it proves that the use of low-energy 365nm ultraviolet light combined with the excitation of a silver layer can realize the fabrication of a 100nm linewidth transistor. Then it can also be known that the operation of this micro-nano processing method is feasible and can have the ability of large-scale processing.

[0107] In summary, the micro-nano processing method, namely the SP lithography method, is adopted to replace the traditional EBL lithography to realize the fabrication of low-damage small linewidth MoS2 transistors. Using 365nm ultraviolet light in the SP processing to achieve a 100nm linewidth can effectively avoid the influence of irradiation on MoS2 during the exposure process, thereby reducing the defect density of MoS2 during the processing.

[0108] The above are only the embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0109] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

[0110] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "comprising..." do not exclude the presence of additional identical elements in the process, method, article or device comprising the said elements.

Claims

1. A micro-nano processing method, characterized in that, The method includes: When spin - coating a photoresist on the surface of the structure, exposing the structure with ultraviolet light of a preset wavelength; wherein, the surface of the structure is a two - dimensional material layer; When the exposure ends, attaching a metal electrode layer to the surface of the two - dimensional material layer on the surface of the structure; When the metal electrode layer is attached to the structure, spin - coating the photoresist on the structure again and performing secondary exposure with ultraviolet light of a preset wavelength; Wherein, the preset wavelength is determined according to the structural line width and structural strength of the two - dimensional material layer.

2. The method according to claim 1, wherein Wherein, The structure is composed of a base layer, a dielectric layer, and an excitation metal layer; The preparation method of the structure includes: Attaching the excitation metal layer to the surface of the base layer; When the excitation metal layer is attached to the surface of the base layer, attaching the dielectric layer to the surface of the excitation metal layer; When the dielectric layer is attached to the surface of the excitation metal layer, attaching the two - dimensional material layer to the surface of the dielectric layer.

3. The method according to claim 2, wherein When attaching the dielectric layer to the surface of the excitation metal layer in the case where the excitation metal layer is attached to the surface of the base layer, it includes: When the excitation metal layer is attached to the surface of the base layer, cleaning the base layer with the attached excitation metal layer with a variety of cleaning media; When drying the cleaned base layer with the attached excitation metal layer, evacuating the base layer with the attached excitation metal layer to a preset vacuum degree and heating the base layer with the attached excitation metal layer to the preparation temperature.

4. The method according to claim 2, wherein When attaching the two - dimensional material layer to the surface of the dielectric layer in the case where the dielectric layer is attached to the surface of the excitation metal layer, it includes: When coating a PMMA solution on the surface of the two - dimensional material layer, heating the two - dimensional material layer; Transferring the two - dimensional material layer to the surface of the dielectric layer using deionized water.

5. The method according to claim 1, characterized in that The spin - coating of the photoresist includes: The thickness of the photoresist is 40 to 80 nm, the spin - coating speed is 1500 to 2500 r / s, and the spin - coating duration is 30 to 60 s; When the spin - coating of the photoresist is completed, baking the photoresist on the structure; Wherein, the baking temperature is 80 to 120 °C and the baking time is 3 to 5 minutes.

6. The method according to claim 1, characterized in that, The exposure using ultraviolet light of a preset wavelength includes: The ultraviolet exposure time is 10 to 30 seconds, and the ultraviolet exposure power is 5 to 20 mW.

7. The method according to claim 1, wherein The method further includes: When spin - coating a photoresist on the surface of the structure and the exposure ends, developing and fixing the structure; wherein, the developing and fixing times are 30 to 60 seconds respectively.

8. The method according to claim 7, wherein The method further includes: When the structure completes the developing and fixing operations, performing channel etching on the developed structure; Wherein, the etching plasma is one of oxygen or argon; the etching power is 30 to 80 w; the etching time is 1 to 3 minutes.

9. The method according to any one of claims 1 to 8, characterized in that, Wherein, The wavelength value range of the preset wavelength includes 355 nm to 370 nm.

10. A transistor, characterized in that, The transistor is fabricated by the micro-nano processing method described in any one of claims 1 to 9; the transistor includes: a base layer, a dielectric layer, a two-dimensional material layer, a metal electrode layer, and an excitation metal layer; The base layer is placed at the bottom; the excitation metal layer is disposed on the surface of the base layer; The excitation metal layer connects the base layer and the dielectric layer; The two-dimensional material layer is disposed on the surface of the dielectric layer; the metal electrode layer is connected to the two-dimensional material layer.

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