Interface resistor calibration circuit

Abstract

The invention provides an interface resistance calibration circuit, which comprises a current mirror circuit, two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage and output to an interface resistance circuit to generate a calibration voltage, and a plurality of resistance branches are connected in parallel in the interface resistance circuit. The reference voltage and the calibration voltage are connected to a comparator for comparison, and a comparison result is output to control the interface resistance circuit to change the resistance value; the comparator is provided with a first switch between the accessed reference voltage and the accessed calibration voltage, the first switch is controlled to be closed before the system starts resistance calibration, and the comparator outputs an initial comparison result; based on the initial comparison result, after resistance calibration is started, when the comparison result output by the comparator skips, the resistance value of the access interface resistance circuit is selected, and the accuracy of resistance calibration can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of resistance calibration, and particularly relates to an interface resistance calibration circuit. Background Art

[0002] An interface resistance calibration circuit is an electronic system used to dynamically adjust or compensate the resistance value in an interface circuit, aiming to solve the problem of resistance mismatch caused by environmental changes, device aging, or process deviations, thereby ensuring signal integrity, improving measurement accuracy, or optimizing system performance.

[0003] The interface resistance calibration circuit in the prior art generally includes a comparator, a reference voltage, and a calibration voltage of a resistance circuit. By comparing the reference voltage with the calibration voltage through the comparator, when the ratio between the reference voltage and the calibration voltage meets a set value, the comparator will jump, indicating the end of the comparison process. At this time, the resistance value in the resistance circuit is the calibrated resistance value required.

[0004] A comparator is a commonly used component in electronic circuits, mainly for comparing the magnitudes of two voltages or currents. In practical applications, the noise of the comparator is inevitable and will have a certain impact on the performance of the system. The offset voltage of the comparator refers to a fixed voltage deviation existing at the input end of the comparator under the condition of zero input. This deviation will affect the output result of the comparator. Specifically, the offset voltage of the comparator can be divided into input offset voltage and output offset voltage. The offset voltage existing in the comparator can be greater than zero or less than zero. When the offset voltage of the comparator is greater than zero, it means that when the same common-mode voltage is connected to the input end, the output is high. Or, when a voltage V0 with a negative pole greater than the positive pole (theoretically, the output should be low) is input at this time, but when V0 is less than the offset voltage of the comparator, the output is still high. That is, when the offset voltage of the comparator is greater than zero, it will contribute a positive equivalent resistance to the resistance to be calibrated.

[0005] The equivalent resistance contributed by the offset voltage of the comparator may be positive or negative. If it is superimposed on the basis of the inherent error, there may be a situation of error superposition or a situation of error cancellation. When the situation of error superposition occurs, the accuracy of the calibrated resistance will be reduced. Therefore, it is necessary to improve the interface resistance calibration circuit to improve the accuracy of resistance calibration. Summary of the Invention

[0006] The present invention provides an interface resistance calibration circuit, which reduces the additional error caused by the offset voltage of the comparator and improves the accuracy of resistance calibration.

[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides 1. An interface resistance calibration circuit. The interface resistance calibration circuit includes a current mirror circuit. Two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage. A plurality of parallel resistance branches are connected in parallel in the interface resistance circuit. The reference voltage and the calibration voltage are connected to a comparator for comparison, and the comparison result is output to control the interface resistance circuit to change the resistance value. A first switch is arranged between the accessed reference voltage and the accessed calibration voltage in the comparator. Before the system starts resistance calibration, the first switch is controlled to close, and the comparator outputs an initial comparison result. Based on the initial comparison result, after starting resistance calibration, when the comparison result output by the comparator jumps, the resistance value connected to the interface resistance circuit is selected.

[0009] The interface resistance circuit includes a plurality of parallel resistance branches. A second switch and a MOS transistor are arranged on each parallel resistance branch. The second switch is closed before starting resistance calibration. After the resistance calibration starts, the comparator outputs a comparison result. The gates of the MOS transistors on the parallel resistance branches are connected to a resistance selection signal, and the resistance selection signal changes according to the comparison result of the comparator to perform a resistance value traversal operation of the interface resistance circuit.

[0010] The resistance selection signal is a multi-bit binary selection signal. Each bit signal of the binary selection signal controls the conduction and opening of the corresponding resistance branch. Based on the comparison result of the comparator, each bit signal is assigned a value in sequence according to the resistance traversal order, and the number of branch resistances incorporated into the interface resistance circuit is increased or decreased in sequence. When the comparison result of the comparator jumps, the comparison process ends.

[0011] The calibration voltage is connected to the negative electrode of the comparator. When the resistance value of the interface resistance circuit starts to traverse from high to low, if the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result. If the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

[0012] When the resistance value of the interface resistance circuit starts to traverse from low to high, if the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result. If the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

[0013] Before the interface resistance circuit starts calibration, the first switch connects both input terminals of the comparator to the reference voltage, and the initial comparison result output by the comparator is used to characterize the equivalent internal resistance of the comparator.

[0014] A third switch is provided between the current mirror circuit and the interface resistance calibration circuit; the first switch is controlled by a comparator initialization control signal, and the second switch and the third switch are controlled by a switch control signal; the control signals of the first switch, the second switch, and the third switch are generated by a signal control circuit; the signal control circuit includes a plurality of delay circuits and an inverter circuit. After the external enable signal is input to the signal control circuit, a switch control signal is obtained after delay processing. The switch control signal is obtained after delay processing and inversion processing to obtain a comparator initialization control signal. The comparator initialization control signal is obtained after delay processing and inversion processing to obtain a system working signal; when the system working signal is pulled high, the system starts to work normally.

[0015] After the comparator outputs the initial comparison result, the initial comparison result is saved, and after the interface resistance circuit calibration is completed, the resistance selection signal is selected based on the initial comparison result, and then the resistance value connected to the interface resistance circuit is selected.

[0016] The initial comparison result is saved to the D input terminal of the D flip-flop.

[0017] The clock signal input terminal of the D flip-flop inputs a switch control signal, and the initial comparison result is input to the D input terminal of the D flip-flop.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. Before calibrating the resistance circuit, the present invention connects both ends of the comparator to the reference voltage, and the initial comparison result output by the comparator is used to characterize the equivalent internal resistance of the offset voltage when comparing the calibration voltage with the reference voltage, and the number of resistors connected to the final resistance circuit is selected based on the output initial comparison result to improve the comparison accuracy and reduce errors.

[0019] 2. The present invention generates a plurality of switch control signals through a signal control circuit to realize the offset voltage equivalent internal resistance test and comparison result output of the resistance calibration circuit before calibration, and saves the output initial comparison result through a D flip-flop. The circuit has a simple structure, does not increase the area overhead of the interface resistance calibration circuit too much, and can efficiently output comparison results.

[0020] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the drawings, is described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of the interface resistance calibration circuit of the present invention.

[0023] Figure 2 It is a schematic diagram of the signal control circuit and the timing control diagram of the present invention. Specific Embodiments

[0024] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0025] Embodiment 1 Embodiment 1 provides an interface resistance calibration circuit. The interface resistance calibration circuit includes a current mirror circuit. Two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage. A plurality of resistor branches are connected in parallel in the interface resistance circuit. The reference voltage and the calibration voltage are input to a comparator for comparison, and the comparison result is output to control the interface resistance circuit to change the resistance value. A first switch is set between the input reference voltage and the input calibration voltage of the comparator, and before the system starts resistance calibration, the first switch is controlled to close, and the comparator outputs an initial comparison result. Based on the initial comparison result, after starting resistance calibration, when the comparison result output by the comparator jumps, the resistance value connected to the interface resistance circuit is selected.

[0026] In Embodiment 1, the same voltage is input to the input terminals of the comparator before resistance calibration, and the initial comparison result is output. The initial comparison result can be used to characterize the equivalent internal resistance of the comparator offset voltage. Then, based on the characterized equivalent internal resistance of the comparator offset voltage, the resistance value connected to the interface resistance circuit is selected.

[0027] The following combines the attached Figure 1 A detailed explanation of the interface resistance calibration circuit of the present invention will be given.

[0028] As Figure 1As shown in the figure, the interface resistance calibration circuit of the first embodiment includes a current mirror circuit and an interface resistance circuit. The current mirror circuit includes two output branches. One output branch is connected to an external standard resistor rext to generate a reference voltage compA, and the other output branch is connected to an external interface resistance circuit to generate a calibration voltage compB. The generated reference voltage compA and the standard voltage cb_vref are input into a differential amplifier for operation, and the operation result is input into the gates of two transistor circuits P5 and P6 in the current mirror circuit. The differential amplifier adjusts the gate outputs of the transistor circuits P5 and P6 until the reference voltage compA and the standard voltage cb_vref are the same. At the same time, the mirror ratio of the current mirror circuit can be set as needed. For different setting ratios, by adjusting the resistance values of the standard resistor rext and the interface resistance circuit to be calibrated, finally the reference voltage compA and the calibration voltage compB are made consistent. Generating the current ratio of the current mirror circuit is a conventional technique in the art, and this application will not elaborate on it in detail here.

[0029] See Figure 1 , the interface resistance circuit includes multiple parallel resistor branches. Each resistor branch includes a mos transistor circuit (P0, P1, P2, P3, P4), a resistor (S3, S6, S12, S24, S48,), and a second switch k2. The second switch k2 can be a transmission transistor, and the second switch k2 is controlled to be turned off and on by a switch control signal en1. Wherein, the total resistance value of the interface resistance circuit will change when each resistor branch is sequentially connected to the interface resistance circuit.

[0030] When the switch control signal en1 is pulled high, the second switch k2 closes, and the resistor branch of the interface resistance circuit is turned on. At this time, the connected resistor branch is controlled by the mos transistor circuit (P0, P1, P2, P3, P4).

[0031] When performing resistance calibration, it is necessary to control the number of connected resistor branches in the interface resistance circuit based on a resistance selection signal. The resistance selection signal is a binary signal and is input into the gates of the mos transistor circuits to perform a traversal operation of the resistors. Specifically, when the resistance selection signal is set to "1", the mos transistor circuit conducts, and the resistor branch where the mos transistor is located is connected to the interface resistance circuit. Taking Figure 1 as an example, Figure 1The interface resistance circuit therein has 5 resistor branches. When traversing the resistors from high to low, the first resistor is connected in the initial state, and the resistance value of the interface resistance circuit is the largest. At this time, the resistance selection signal is "00001". Then, starting from the low bit, the signal "0" is sequentially set to "1". For example, when the first and the second resistor branches are connected, the resistance selection signal is "00011". When traversing the resistors from low to high, all resistor branches are connected to the interface resistance circuit in the initial state. At this time, the circuit selection signal is "11111". During the traversal, the resistance selection signal starts from the highest bit and is gradually set to "0", making the resistance value of the interface resistance circuit gradually increase.

[0032] The reference voltage compA and the calibration voltage compB are input into the comparator for comparison. The calibration voltage compB is input to the negative terminal of the comparator. By comparing the proportional relationship between the reference voltage compA and the calibration voltage compB, when the proportional relationship meets the pre-set proportional relationship, the comparison result comp_out output by the comparator will jump (taking the current mirror current ratio of 1:1 and traversing the resistor values from high to low as an example, in the initial state, the calibration voltage compB is higher than the reference voltage compA. When traversing to the point where the calibration voltage compB is lower than the reference voltage compA, the comparison result comp_out output by the comparator jumps). At this time, it is prompted that the comparison result meets the expectation and the comparison process ends. If the comparison result comp_out output by the comparator does not jump, at this time, the number of resistor branches connected to the interface resistance circuit is changed through the d resistance selection signal (sw<0,4>) input to the gate of the mos tube circuit until the comparator jumps. Since the total resistance of the parallel resistor circuit does not change regularly after each resistor is connected, the resistance value of each resistor branch can be designed so that when the interface resistance circuit traverses the resistance value, the total resistance value of the interface resistance circuit changes regularly after each resistor branch is connected or a connected resistor branch is removed. And each equal change in resistance value is called a single resistor calibration step value.

[0033] Ideally, the resistance value of the interface resistance circuit when the comparator makes a signal jump is the calibrated resistance value. Since the comparator itself has an offset voltage (the offset voltage existing in the comparator is equivalent to contributing an equivalent resistance, and the equivalent resistance contributed by the offset voltage can be positive or negative, which will affect the comparison of the resistance value when the comparison results are wrongly superimposed), in order to solve the influence of the offset voltage existing in the comparator on the comparison result, the solution of the first embodiment sets a first switch k1 on the two input terminals of the comparator, which is controlled to be opened and closed by the comparator initialization control signal enn. Before calibrating the interface resistance circuit, the comparator is initialized, and both input terminals of the comparator are connected to the reference voltage compA (since the current mirror circuit can only stably output when the reference voltage compA is finally equal to the standard voltage cb_vref, this is equivalent to both ends of the comparator being connected to the standard voltage cb_vref). The initial comparison result comp_out_vdd output is used to characterize the offset voltage existing in the comparator (that is, the equivalent resistance contributed by the comparator offset voltage). Connecting both input terminals to the reference voltage compA to characterize the offset voltage existing in the comparator is also because the calibration voltage compB ultimately needs to be compared with the reference voltage compA. At this time, when the comparator is initialized and the inputs of the comparator are all the reference voltage compA, the comparison result output is used to calibrate the result of the voltage comparison with the reference voltage compA.

[0034] Among them, in order to facilitate the characterization of the offset voltage existing in the comparator, a third switch is also set between the current mirror circuit and the interface resistance circuit, and the third switch is controlled to be disconnected and closed by the switch control signal en1.

[0035] The first embodiment selects the resistance value connected to the interface resistance circuit based on the initial comparison result. The specific selection method is as follows: The calibration voltage is connected to the negative terminal of the comparator. When the resistance value of the interface resistance circuit traverses from high to low; if the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the current resistance selection signal is the calibration resistance result; if the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the previous resistance selection signal is the calibration resistance result.

[0036] The specific reasons are as follows: When the initial comparison result output by the comparator is high, it means that the offset voltage of the comparator at this time is a number greater than 0 (equivalent to the offset voltage contributing an equivalent resistance greater than zero). When the comparison result output by the comparator jumps, for the resistor connected to compB, if the resistor value of the previous gear (the resistor value corresponding to the previous resistor selection signal) is taken at this time, the actual resistor connected to compB will be larger (the equivalent resistor value with the offset voltage superimposed). Therefore, the current gear value should be taken to avoid expanding the error. When the initial comparison result output by the comparator is low, it means that the offset voltage of the comparator at this time is a number less than 0 (equivalent to the offset voltage contributing an equivalent resistance less than zero). When the comparison result output by the comparator jumps, it means that the resistor connected to compB is not only smaller than the resistor connected to compA, but also additionally smaller by the equivalent resistance of the offset voltage (the equivalent resistance is negative, and superimposing the offset voltage is equivalent to subtracting the equivalent resistance). Therefore, the resistor value corresponding to the previous gear (the resistor value corresponding to the previous resistor selection signal) should be taken to offset the error caused by the offset voltage.

[0037] When the resistance value of the interface resistance circuit starts to be traversed from low to high; if the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the current resistor selection signal is the calibration resistance result. If the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the previous resistor selection signal is the calibration resistance result. The resistance value starts to be traversed from low to high, and the selection situation of its resistor selection signal is just the opposite of the traversal of the resistance value from high to low as described above. The specific reasons are similar to those above and will not be specifically explained here.

[0038] To facilitate the storage of the initial comparison result comp_out_vdd, Embodiment 1 also sets a D flip-flop. The output initial comparison result comp_out_vdd is input to the D input terminal of the D flip-flop, and a switch control signal en1 is input to the clock interface of the D flip-flop. The D flip-flop collects the input initial comparison result comp_out_vdd at the rising edge of the input clock signal and outputs a sel signal. The output sel signal can be used to represent the selection of the resistor selection signal, and then the resistance value connected to the interface resistance circuit is selected. Taking the example of the resistors being gradually connected to the interface resistance circuit (the total resistance value of the interface resistance circuit is traversed from high to low), if sel is high, it means taking the total resistance value of the current interface resistance circuit. If sel is low, take the total resistance value of the previous gear of the interface resistance circuit (the resistor value corresponding to the previous resistor selection signal).

[0039] To facilitate the generation of the switch control signal en1, the comparator initialization control signal enn, and the system working signal enok, a signal control circuit is set up. The signal control circuit and the control timing change as Figure 2As shown, the signal control circuit includes a plurality of delay circuits and an inverter circuit. The switch control signal en1 is a signal obtained by delaying the external enable signal en. The comparator initialization control signal enn is an inverted signal obtained by delaying the switch control signal en1. The system operating signal enok is an inverted signal obtained by delaying the comparator initialization control signal enn. The system operating signal enok indicates the end of the characterization of the comparator offset voltage, the end of system initialization, and the start of the resistor calibration operation of the system. For the comparator initialization control signal en and the switch control signal en1, when the above two signals are low, the corresponding controlled switches are turned off, and when the control signals are high, the corresponding controlled switches are turned on.

[0040] Combined with Figure 2 With the timing changes in , the present invention will be further explained. The external enable signal en is input to the signal control circuit. At time to, the external enable signal en is pulled high. At this time, the switch control signal en1 is low, and all the switches controlled by the switch control signal en1 are turned off, while the comparator initialization control signal enn is high, and the first switch is turned on. At this time, the voltage of compA is equal to the voltage of compB and equal to cb_vref. At this time, the initialization of the comparator starts, and the comparator outputs an initial comparison result of high or low. High represents that the offset voltage of the comparator is positive, and low represents that the offset voltage of the comparator is negative. At time t1, the switch control signal en1 jumps, and the switch control signal en1 is input to the clock signal port of the D flip-flop. At time t1, the D flip-flop reads the input initial comparison result of the comparator, and the D flip-flop latches the comparison output result onto the sel signal, and the switch controlled by en1 is turned on and conducts. At time t2, the comparator initialization control signal enn is pulled low, and the controlled first switch is turned off. At this time, the initialization of the comparator ends, and the entire circuit can operate normally. When the system operating signal enok signal is pulled high at time t3, it represents that the system starts to operate normally. By reading the sel signal later, it can be known whether the current gear or the previous gear can reduce the error more.

[0041] The comparator error control method of the present invention can greatly reduce the design and comparison difficulties, has extremely high comparison operation efficiency, and very low error.

[0042] The above has introduced in detail an interface resistor calibration circuit provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. An interface resistance calibration circuit, the interface resistance calibration circuit includes a current mirror circuit, two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage, characterized in that ； A plurality of resistor branches are connected in parallel within the interface resistance circuit. The reference voltage and the calibration voltage are input to a comparator for comparison, and the comparison result is output to control the interface resistance circuit to change its resistance value. A first switch is provided between the input reference voltage and the input calibration voltage of the comparator. Before the resistor calibration of the system starts, the first switch is controlled to close, and the comparator outputs an initial comparison result. Based on the initial comparison result, after the resistor calibration starts, when the comparison result output by the comparator jumps, the resistance value connected to the interface resistance circuit is selected.

2. The interface resistance calibration circuit according to claim 1, wherein The interface resistance circuit includes a plurality of parallel resistor branches, and a second switch and a MOS transistor are provided on each parallel resistor branch. The second switch closes before the resistor calibration starts. After the resistor calibration starts, the comparator outputs a comparison result. The gates of the MOS transistors on the parallel resistor branches are connected to a resistor selection signal, and the resistor selection signal changes according to the comparison result of the comparator to perform a traversal operation on the resistance value of the interface resistance circuit.

3. The interface resistance calibration circuit according to claim 2, wherein The resistor selection signal is a multi-bit binary selection signal, and each bit of the binary selection signal controls the conduction and opening of the corresponding resistor branch. Based on the comparison result of the comparator, the resistor selection signal assigns values to each bit in sequence according to the resistor traversal order, controlling the number of parallel branch resistors in the interface resistance circuit to increase or decrease sequentially. When the comparison result of the comparator jumps, the comparison process ends.

4. An interface resistance calibration circuit according to claim 3, wherein The calibration voltage is input to the negative terminal of the comparator. When the resistance value of the interface resistance circuit starts to traverse from high to low; If the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the current resistor selection signal is the calibration resistance result. If the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the previous resistor selection signal is the calibration resistance result.

5. An interface resistance calibration circuit according to claim 3, characterized in that When the resistance value of the interface resistance circuit starts to traverse from low to high; If the initial comparison result output by the comparator is low, the resistance value of the interface resistance circuit corresponding to the current resistor selection signal is the calibration resistance result. If the initial comparison result output by the comparator is high, the resistance value of the interface resistance circuit corresponding to the previous resistor selection signal is the calibration resistance result.

6. The interface resistance calibration circuit according to claim 1, wherein Before the interface resistance circuit starts calibration, the first switch connects both input terminals of the comparator to the reference voltage, and the initial comparison result output by the comparator is used to characterize the equivalent internal resistance of the comparator.

7. An interface resistance calibration circuit according to claim 2, characterized in that, A third switch is provided between the current mirror circuit and the interface resistance calibration circuit. The first switch is controlled by a comparator initialization control signal, and the second switch and the third switch are controlled by a switch control signal. The control signals of the first switch, the second switch, and the third switch are generated by a signal control circuit. The signal control circuit includes a plurality of delay circuits and an inversion circuit. After an external enable signal is input to the signal control circuit, a switch control signal is obtained after delay processing. The switch control signal is processed through delay processing and inversion processing to obtain a comparator initialization control signal. The comparator initialization control signal is processed through delay processing and inversion processing to obtain a system working signal; When the system working signal is pulled high, the system starts to work normally.

8. An interface resistance calibration circuit according to claim 7, wherein After the comparator outputs the initial comparison result, the initial comparison result is saved. After the calibration of the interface resistance circuit is completed, the resistance selection signal is selected based on the initial comparison result, and then the resistance value connected to the interface resistance circuit is selected.

9. The interface resistance calibration circuit according to claim 8, wherein The initial comparison result is saved to the D input terminal of the D flip-flop.

10. An interface resistance calibration circuit according to claim 9, wherein, The clock signal input terminal of the D flip-flop inputs the switch control signal, and the initial comparison result is input to the D input terminal of the D flip-flop.

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