Tracking capability detection device for digital image processor

Abstract

The invention relates to a device for detecting the tracking capability of a digital image processor, belongs to the technical field of image processing, and solves the problems of limited efficiency and accuracy of a data processing and arbitration system and poor data synchronism in the existing related technologies for detecting the tracking capability of optical measurement equipment. The system comprises a multi-target image source board card which generates a multi-target image with superposition information, transmits the multi-target image to an upper computer and a detected digital image processor, and outputs the superposition information to a tracking capability arbiter; the tracking capability arbiter is used for resolving a cyclic code and a target miss distance in the collected superposed information, judging the tracking capability of the digital image processor according to a resolving result, obtaining arbitration information and sending the arbitration information to the upper computer; and the upper computer is used for integrating and visually displaying the multi-target image and the arbitration information. The efficiency and accuracy of data processing and arbitration are improved, the stability and reliability of the detection device are improved, and meanwhile data transmission is complete and accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and particularly to a device for detecting the tracking ability of a digital image processor. Background Art

[0002] With the evolution of modern weapon systems, new challenges have been posed to the tracking ability test of optical measurement equipment in the shooting range. Higher requirements are placed on measurement accuracy and real-time performance, and more efficient data processing and analysis are also needed. The existing related technologies for detecting the tracking ability of optical measurement equipment mainly have the following disadvantages:

[0003] The efficiency and accuracy of the data processing and arbitration system are limited. Delays, errors, or the inability to effectively distinguish the performance differences of image processors under different complex tracking tasks occur when processing high-speed and large amounts of image data and related information, thus unable to provide a detailed and reliable basis for the performance evaluation of the image processor;

[0004] The cooperation among components is poor. Problems such as poor data synchronization may occur during data transmission and interaction, affecting the stability and reliability of the entire detection device, prone to faults such as data loss and misinterpretation, and reducing the credibility of the detection results. Summary of the Invention

[0005] Aiming at the problems of limited efficiency and accuracy of the data processing and arbitration system and poor data synchronization existing in the existing related technologies for detecting the tracking ability of optical measurement equipment, the present invention provides a device for detecting the tracking ability of a digital image processor. In this device, a multi-target image source board uses an FPGA chip to generate pseudo-random numbers to plan multi-image target trajectories, thus being able to simulate complex scenarios; a tracking ability arbiter can accurately calculate cyclic codes and target miss distances to evaluate the tracking ability; combined with the collaborative work of the upper computer, network switch, and the digital image processor to be detected, it ensures data transmission and system stability, makes up for the existing deficiencies, and provides an effective solution for the tracking ability evaluation of optical measurement equipment in the shooting range.

[0006] The specific technical solution adopted by the present invention is as follows:

[0007] A device for detecting the tracking ability of a digital image processor, comprising:

[0008] A multi-target image source board, which generates a multi-target image with superimposed information including target miss distance and cyclic code based on an FPGA chip, transmits the multi-target image to the host computer through a Camera Link interface and to the digital image processor to be detected through an optical fiber interface respectively, and outputs the superimposed information to a tracking ability arbiter through a serial interface at the same frequency. The FPGA chip plans independent trajectories of multi-image targets with randomly dynamic changes in target trajectories through pseudo-random numbers and supports multi-type camera simulation functions with adjustable resolution and image frequency;

[0009] A tracking ability arbiter, which adopts a cooperative architecture of an FPGA and a GD32 microcontroller, collects the superimposed information output by the multi-target image source board and the superimposed information extracted from the multi-target image transmitted by the digital image processor to be detected through a network switch, resolves the cyclic code and target miss distance in the collected superimposed information, judges the tracking ability of the digital image processor to be detected according to the resolution result, obtains arbitration information, and sends the arbitration information to the host computer in a network form through the network switch;

[0010] A host computer, which integrates and visually displays the received multi-target image and the arbitration information.

[0011] The beneficial effects of the present invention are as follows:

[0012] Through the cooperative architecture of the FPGA and the GD32 microcontroller adopted by the tracking ability arbiter, as well as serial port data transceiver, network data transceiver, data resolution processing, etc., the present invention realizes efficient collection and accurate resolution of the superimposed information in the image source board and the digital image processor to be detected, effectively distinguishes the performance of the image processor under different tracking tasks, provides a detailed and reliable basis for its performance evaluation, and improves the efficiency and accuracy of data processing and arbitration;

[0013] The present invention optimizes the hardware design of the entire detection device, including the electrical interfaces, communication interfaces and data transmission processes of each board, ensures good cooperation between components, solves problems such as poor data synchronization in existing detection technologies, improves the stability and reliability of the detection device, ensures the integrity and accuracy of data transmission, and enhances the credibility of detection results. Description of the Drawings

[0014] Figure 1 It is a principle block diagram of a digital image processor tracking ability detection device according to an embodiment of the present invention;

[0015] Figure 2 It is a data flow diagram of a digital image processor tracking ability detection device according to an embodiment of the present invention;

[0016] Figure 3Data processing flowchart of the digital image processor tracking ability detection device according to the embodiments of the present invention;

[0017] Figure 4 Timing diagram of the digital image processor tracking ability detection device according to the embodiments of the present invention. Detailed implementation manners

[0018] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0019] The present invention provides a set of highly integrated tracking ability detection devices, which are centered around the detection of the tracking ability of the image processor. The device mainly consists of a multi-target image source board, a tracking ability arbiter, a network switch, and a host computer. Among them, the multi-target image source board uses an XC7K160T FPGA chip for core logic control, generates multiple pseudo-random numbers to realize the random and independent planning of the trajectories of multiple image targets, and then converts the digital images generated by the FPGA into differential digital signals that conform to the Camera Link protocol standard through a serial-to-parallel conversion interface. The hardware of the multi-target image source board covers modules such as an external clock, FLASH storage, and various interfaces, and functional modules such as the internal clock of the FPGA and the line / field signals cooperate with each other; the tracking ability arbiter uses the method of FPGA+GD32 for core logic control, including modules such as serial ports and network data transceiver and related peripheral circuits, and judges the tracking ability of the detected digital image processor by collecting the superimposed information of the multi-target image source board and the digital image processor and resolving the cyclic code and target miss distance information therein; the host computer is used to receive and visually display the images and arbitration information; the network switch ensures data transmission; the detected digital image processor receives the image containing the superimposed information, extracts relevant information, and then sends it to the network switch. Each part of the entire system cooperates with each other to accurately detect the tracking ability of the image processor and provide a reliable performance evaluation basis.

[0020] Specifically, as Figure 1 shown, the multi-target image source board generates multi-target images with superimposed information including target miss distance and cyclic code based on the FPGA chip, and transmits the generated multi-target images to the host computer through the Camera Link interface and to the detected digital image processor through the optical fiber interface respectively, and outputs the superimposed information to the tracking ability arbiter through the serial interface at the same frequency. The FPGA chip in the multi-target image source board plans the independent trajectories of multiple image targets with randomly dynamic changes in the target trajectories through pseudo-random numbers, and can support the simulation functions of multiple types of cameras with adjustable resolution and image frequency.

[0021] The hardware of the multi-target image source board mainly consists of an FPGA and its peripheral circuits. Among them, the external clock provides the clock reference for the entire system of the multi-target image source board; the FLASH storage module is responsible for storing the program data files of the system and logically initializing the FPGA chip every time it is powered on; the power supply module powers the entire system and ensures that different levels are powered on in the correct order during the power-on process. In addition, there is an in-circuit debugging interface (JTAG interface) that can achieve program burning and in-circuit simulation; the serial output interface can use an interface chip to convert the TTL digital signal output by the FPGA chip into a standard 422 differential signal and output it to the data processor at the backend; the Camera Link output interface uses a standard Full mode interface, including two independent MDR26 physical interfaces, Base and Medium / Full, and can achieve digital image data output of up to 6.8 Gbps.

[0022] As the core logic processing unit of the system, the FPGA chip contains multiple functional modules.

[0023] (1) The preset target generation module is used to generate targets in the form of point targets and surface targets.

[0024] Targets are generated in the form of point targets and surface targets, where the surface target can input a preset image as the target. The preset image target can more comprehensively detect the target extraction ability of the image processing module and better restore the characteristics of the real image.

[0025] (2) The background generation module is used to fill the lower n bits of the image pixels with the generated random numbers to simulate complex scene noise, so as to detect the filtering ability and anti-interference ability of the tracking ability detection device.

[0026] The background generation module uses a random number generator to generate random numbers and fills the lower n bits of the image pixels with the random numbers, and the other positions of the image pixels are 0.

[0027] (3) The trajectory planning module is used to randomly and dynamically generate multiple targets with the center pixel point of the image as the origin, and output the center points of the multiple targets as the true values of the miss distances of each target.

[0028] The target trajectories generated by the trajectory planning module change randomly and dynamically. The center points of the targets are output as the true values of the miss distances transmitted in the superimposed information, and multiple targets can be generated for multi-target detection by the processor. When the tracking ability arbiter performs position conversion, the center pixel point of the image is used as the origin of the target miss distance, and the calculation is performed according to the transmitted true value of the target miss distance and the origin information.

[0029] At the same time, the FPGA chip has the function of simulating multiple types of cameras:

[0030] Simulate different camera image output modes, using a method with adjustable resolution and adjustable image frequency to adapt to the camera. The superimposed time information is obtained from the time synchronization board at the front end through the serial port. At the same time, the image output frequency can also be adapted according to different frame rates given by the time synchronization board. In addition, the output image resolution can also be customized using a timer counter, including image resolutions such as 1920×1080 and 640×480, and the specific line number corresponding to the current line / field signal and the relative position of each line can also be synchronously output, providing a basis for the target superimposition position for subsequent modules.

[0031] The tracking ability arbiter adopts a cooperative architecture of FPGA and GD32 microcontroller, collects the superimposed information output by the multi-target image source board and the superimposed information extracted from the multi-target images transmitted by the detected digital image processor through the network switch, and resolves the cyclic code and target miss distance in the collected superimposed information. According to the resolution result, the tracking ability of the detected digital image processor is judged, and finally the arbitration information is obtained, and the obtained arbitration information is sent to the upper computer in the form of a network through the network switch. The communication between the network switch and the tracking ability arbiter and the upper computer is realized through the network interface. The network interface (abbreviated as network port) adopts the UDP protocol to transmit the extracted superimposed information and arbitration information. The detected digital image processor also communicates with the network switch through the network port to transmit the superimposed information extracted by the digital image processor from the multi-target images.

[0032] The hardware of the tracking ability arbiter is mainly composed of a cooperative architecture of field programmable gate array (FPGA) and GD32 microcontroller and its peripheral circuits. Among them, the temperature compensated crystal oscillator provides a clock reference for the entire system of the tracking ability arbiter; the storage module is responsible for storing the program data files of the system and initializing the logic of the FPGA every time it is powered on; the power module can effectively suppress and adjust the voltage fluctuation of the input power supply and output a stable voltage to meet the voltage accuracy and stability requirements of different components in the system. The serial interface converts the input standard 422 differential signal into a TTL digital signal and outputs it to the data processor at the back end. The network communication module provides the FPGA with efficient, stable and reliable network connection and data transmission capabilities.

[0033] For high-speed serial communication, the FPGA can achieve a very high data transmission rate. It can directly process high-speed clock signals and data signals, and can reduce the transmission delay by optimizing the logic design. The serial communication speed of the GD32 microcontroller is usually limited by its internal hardware resources and clock frequency, and may not meet the requirements when processing high-speed data. Therefore, after the tracking ability arbiter uses the FPGA to receive the serial port data, it is transmitted to the GD32 microcontroller through SPI for processing to ensure accurate and high-speed data transmission.

[0034] The network communication module can utilize its characteristic of fast data transmission to achieve efficient data exchange. It can quickly send small data packets, and can implement unicast and multicast functions based on the User Datagram Protocol (UDP), sending data to multiple receivers simultaneously to improve the efficiency of information dissemination. Moreover, it can perform simple encapsulation and decapsulation of UDP data packets, process the header information of the data packets, and extract key data content.

[0035] The data flow of the digital image processor tracking ability detection device is as Figure 2 shown. The multi-target image source board has one input interface and three output interfaces. The input interface receives the real-time serial port time information and the external trigger signal transmitted by the time synchronization board. The output interfaces are the optical fiber interface, the serial interface (referred to as the serial port for short), and the Camera Link interface respectively. Among them, the optical fiber interface outputs an image with superimposed information to the digital image processor to be detected. This interface can adopt the SFP optical module interface to realize the functions of optical signal transceiver. The SFP optical module interface supports high-speed data transmission and has the advantages of small size and hot pluggability. The serial interface outputs the superimposed information to the tracking ability arbiter at the same frequency as the optical fiber interface. The serial interface has the characteristics of simplicity and reliability and is suitable for low-speed data transmission scenarios. For example, the serial interface uses the RS-422 standard for one-to-one communication with external devices to transmit the superimposed information. The Camera Link interface outputs an image with superimposed information to the host computer. The Camera Link interface adopts the standard Full mode interface, including two independent MDR26 physical interfaces of Base and Medium / Full, and can achieve a digital image data output of up to 6.8 Gbps. The tracking ability arbiter accesses the superimposed information from the serial port and the network port respectively, and the superimposed information extracted by the digital image processor to be detected from the multi-target image. After comparing and processing the information, the arbitration information is sent to the host computer in the form of a network via a network switch. The digital image processor to be detected receives the image with superimposed information transmitted by the optical fiber, extracts the superimposed information including the target miss distance and the cyclic code in the image, and then sends it to the network switch via the network port. The host computer, as the terminal display and monitoring platform for the entire data processing process, will finally integrate and visually present the received images and arbitration information. Through this intuitive display method, the real-time calculation performance indicators of the board to be tested can be obtained more conveniently and accurately, thus providing a strong basis for evaluating the working efficiency of the board.

[0036] The data processing process of the digital image processor tracking ability detection device is as Figure 3As shown in the figure. The multi-target image source board receives the external trigger signal from the time synchronization board through the serial port as the trigger for the image, and at the same time superimposes the received time information onto the image. The multi-target image source board generates multi-target images and corresponding superimposed information, where the superimposed information includes the target miss distance and the cyclic code. Subsequently, the multi-target images are respectively transmitted to the digital image processor to be detected and the host computer, and the superimposed information is transmitted to the tracking ability arbiter. After extracting the superimposed information in the image, the digital image processor transmits it to the tracking ability arbiter in the format of network information. The tracking ability arbiter judges the correctness of the target miss distance and the cyclic code in the superimposed information of each frame of image transmitted by the multi-target image source board and the superimposed information extracted by the digital image processor. If the judgment result shows that both the target miss distance and the cyclic code are correct, it indicates that the tracking ability of the digital image processor meets the qualified standard; otherwise, if the judgment result shows that the target miss distance or the cyclic code is incorrect, it is determined that the tracking ability of the digital image processor is unqualified, which means that the tracking ability of the digital image processor fails to meet the requirements. At this time, the judgment of the current frame of image is ended and waiting for the next frame of image to enter. Finally, this judgment result information, that is, the arbitration information, will be transmitted to the host computer for clear display, so that relevant technical personnel can obtain the tracking ability evaluation result of the image processor in a timely and intuitive manner, and thus provide key data support and decision-making basis for subsequent system optimization, fault troubleshooting, and performance improvement work.

[0037] The timing relationship between the image and the superimposed information is as Figure 4 shown, and all data uses the image sent by the multi-target image source board as the synchronous source reference T0. T TRANS is the time delay on the optical fiber link, T PRO is the time delay for the digital image processor to process data, T NETA 、T NETB 、T NETC are all network delays, where T NETA is the network delay from the network switch to the tracking ability arbiter, T NETB is the network delay from the tracking ability arbiter to the network switch, T NETC is the network delay from the network switch to the host computer.

[0038] Therefore, the time delay from the multi-target image source board to the final display on the host computer is:

[0039] T2 - T0 = T TRANS + T PRO + T NETA + T NETB + T NETC ;

[0040] The time delay from the multi-target image source board to the tracking ability arbiter is:

[0041] T1 - T0 = T TRANS + T PRO + T NETA ;

[0042] To obtain a more accurate delay time T for the digital image processor to process data PRO , the function of the data processing part of the digital image processor can be masked to calculate a delay difference T from the multi-target image source board to the tracking ability arbiter DIF , and then use this delay difference T DIF to inversely deduce T PRO , to obtain the true delay time of the digital image processor, and a more accurate comparison can be made for the detected digital image processor. The formula is as follows:

[0043] T DIF = T TRANS + T NETA ;

[0044] T PRO = T1 - T0 - T DIF .

[0045] In the multi-target image source board of the present invention, an FPGA chip is used as the core to generate pseudo-random numbers to achieve precise random and independent planning of multi-image target trajectories, which can highly simulate the complex movements of multiple targets in the shooting range. And with the help of the internal function modules of the FPGA, the target characteristics and scene parameters can be flexibly adjusted, greatly enriching the diversity of test scenarios; the tracking ability arbiter adopts an FPGA + GD32 microcontroller cooperative architecture, and combined with multiple modules, it can efficiently and accurately collect and solve the cyclic codes and target miss distances in the superimposed information of the digital image processors in the multi-target image source board and the optical measurement equipment, and accurately evaluate the tracking ability; the upper computer, network switch and each processor cooperate to ensure stable data transmission and efficient operation of the system, which can not only provide realistic test conditions for the optical measurement equipment in the shooting range to comprehensively verify its adaptability and accuracy, but also achieve accurate evaluation and stable operation.

[0046] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0047] The above-described embodiments merely represent several implementation manners of the present invention. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A detection device for the tracking ability of a digital image processor, characterized in that, Comprising: A multi-target image source board, which generates a multi-target image with superimposed information including target miss distance and cyclic code based on an FPGA chip, transmits the multi-target image to a host computer through a Camera Link interface and to a digital image processor to be detected through an optical fiber interface respectively, and outputs the superimposed information to a tracking ability arbiter through a serial interface at the same frequency. The FPGA chip plans independent trajectories of multi-image targets with randomly dynamic changes in target trajectories through pseudo-random numbers, and supports multi-type camera simulation functions with adjustable resolution and image frequency; A tracking ability arbiter, adopting a cooperative architecture of FPGA and GD32 microcontroller, collects the superimposed information output by the multi-target image source board and the superimposed information extracted from the multi-target image transmitted by the digital image processor to be detected through a network switch, resolves the cyclic code and target miss distance in the collected superimposed information, judges the tracking ability of the digital image processor to be detected according to the resolution result to obtain arbitration information, and sends the arbitration information to the host computer in a network form through the network switch; A host computer, which integrates and visually displays the received multi-target image and the arbitration information.

2. The digital image processor tracking ability detection device according to claim 1, characterized in that, The multi-target image source board includes an FPGA chip and its peripheral circuits. Among them, an external clock provides a clock reference for the multi-target image source board; a FLASH storage module is responsible for storing the program data files of the system and logically initializing the FPGA chip every time it is powered on; a power module supplies power to the multi-target image source board and ensures that different levels are powered on in the correct order during the power-on process; an in-circuit debugging interface is used to implement program burning and in-circuit simulation; a serial output interface uses an interface chip to convert the TTL digital signal output by the FPGA chip into a standard 422 differential signal; a Camera Link output interface adopts a standard Full mode interface, including two independent MDR26 physical interfaces of Base and Medium / Full, and can output digital image data up to 6.8 Gbps.

3. The digital image processor tracking ability detection device according to claim 2, wherein, The FPGA chip includes: A preset target generation module, which is used to generate targets in the form of point targets and surface targets; A background generation module, which is used to fill the lower n bits of image pixels with generated random numbers to simulate complex scene noise; A trajectory planning module, which is used to randomly and dynamically generate multi-targets with the center pixel point of the image as the origin, and output the center points of the multi-targets as the true values of their respective miss distances.

4. A digital image processor tracking ability detection device according to claim 1, characterized in that The tracking ability arbiter includes a cooperative architecture of FPGA and GD32 microcontroller and its peripheral circuits. After the FPGA receives serial port data, it is transmitted to the GD32 microcontroller through SPI for processing. Among them, a temperature-compensated crystal oscillator provides a clock reference for the tracking ability arbiter; a storage module is responsible for storing the program data files of the system and logically initializing the FPGA every time it is powered on; The power supply module outputs a stable voltage to meet the requirements of different components within the system for voltage accuracy and stability; the serial interface converts the input standard 422 differential signal into a TTL digital signal; the network communication module provides the FPGA with network connection and data transmission capabilities.

5. The detection device for the tracking ability of a digital image processor according to claim 4, wherein, The network communication module supports unicast and multicast functions based on the User Datagram Protocol, and sends data to multiple receivers simultaneously.

6. The detection device for the tracking ability of a digital image processor according to claim 1, characterized in that, Taking the multi-target image sent by the multi-target image source board as the synchronization source reference T0, the delay time T of the data processed by the digital image processor to be detected PRO is calculated by the following formula: T PRO = T1 - T0 - T DIF Among them, T1 - T0 is the time delay from the multi-target image source board to the tracking ability arbiter, and its value is equal to the sum of the time delay on the optical fiber link, the time delay for the detected digital image processor and the tracking ability arbiter to process data, and the network delay from the network switch to the tracking ability arbiter, T DIF is the delay difference from the multi-target image source board to the tracking ability arbiter calculated after masking the data processing part function of the detected digital image processor.

7. A digital image processor tracking ability detection device according to claim 1, characterized in that, The fiber optic interface uses an SFP optical module interface.

8. The detection device for the tracking ability of a digital image processor according to claim 1, characterized in that, The serial interface uses the RS-422 standard to transmit superimposed information.

9. A digital image processor tracking ability detection device according to claim 1, characterized in that The Camera Link interface uses a standard Full mode interface, including two independent MDR26 physical interfaces, Base and Medium / Full.

10. The digital image processor tracking ability detection device according to claim 9, characterized in that The data transmission rate of the Camera Link interface is less than or equal to 6.8 Gbps.

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