A digital image processor tracking capability detection device

Abstract

The present invention relates to a digital image processor tracking capability detection device, which belongs to the field of image processing technology and solves the problems of limited efficiency and accuracy of data processing and arbitration systems and poor data synchronization in existing technologies related to the tracking capability detection of optical measurement equipment. The present invention includes: a multi-target image source board, which generates multi-target images with superimposed information, and transmits them to a host computer and a digital image processor to be detected, respectively, and outputs the superimposed information to a tracking capability arbitrator; the tracking capability arbitrator solves the cyclic code and target miss distance in the collected superimposed information, judges the tracking capability of the digital image processor based on the solution result, obtains arbitration information and sends it to the host computer; the host computer integrates and visualizes the multi-target images and arbitration information. The present invention improves the efficiency and accuracy of data processing and arbitration, improves the stability and reliability of the detection device, and at the same time, the data transmission is complete and accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to a device for detecting the tracking capability of a digital image processor. Background Art

[0002] The evolution of modern weapon systems has posed new challenges to the tracking capability testing of optical measurement equipment at the target range, requiring higher measurement accuracy and real-time performance, as well as more efficient data processing and analysis. Existing technologies for testing the tracking capability of optical measurement equipment have the following main shortcomings:

[0003] The data processing and arbitration system has limited efficiency and accuracy. When processing high-speed, large amounts of image data and related information, delays and errors may occur, or the system cannot effectively distinguish the performance differences of image processors under tracking tasks of different complexity. This makes it impossible to provide a detailed and reliable basis for image processor performance evaluation.

[0004] The coordination between the various components is poor, and there may be problems such as poor data synchronization during data transmission and interaction, which affects the stability and reliability of the entire detection device, and is prone to failures such as data loss and misinterpretation, reducing the credibility of the detection results. Summary of the Invention

[0005] To address the problems of limited efficiency and accuracy of data processing and arbitration systems and poor data synchronization in existing technologies related to the tracking capability detection of optical measurement equipment, the present invention provides a digital image processor tracking capability detection device. In this device, a multi-target image source board uses an FPGA chip to generate pseudo-random numbers to plan multi-image target trajectories, thereby simulating complex scenarios. A tracking capability arbitrator can accurately resolve cyclic codes and target miss distances to evaluate tracking capability. Combined with the coordinated operation of a host computer, network switch, and the digital image processor being tested, data transmission and system stability are guaranteed, thus overcoming existing deficiencies and providing an effective solution for evaluating the tracking capability of optical measurement equipment at a shooting range.

[0006] The specific technical solutions adopted by the present invention are as follows:

[0007] A digital image processor tracking capability detection device, comprising:

[0008] A multi-target image source board generates multi-target images with superimposed information including target miss distances and cyclic codes based on an FPGA chip, transmits the multi-target images to a host computer via a Camera Link interface and to a detected digital image processor via an optical fiber interface, and outputs the superimposed information to a tracking capability arbitrator via a serial interface at the same frequency. The FPGA chip plans independent multi-image target trajectories with randomly changing target trajectories using pseudo-random numbers, and supports multi-type camera simulation functions with adjustable resolution and image frequency.

[0009] The tracking capability arbitrator adopts a collaborative architecture of FPGA and GD32 microcontroller, collects the superposition information output by the multi-target image source board and the superposition information extracted from the multi-target image transmitted by the detected digital image processor via a network switch, calculates the cyclic code and target miss distance in the collected superposition information, determines the tracking capability of the detected digital image processor based on the calculation result, obtains arbitration information, and sends the arbitration information to the host computer via the network switch in a network form;

[0010] The host computer integrates and visualizes the received multi-target images and the arbitration information.

[0011] The beneficial effects of the present invention are:

[0012] The present invention uses the FPGA and GD32 microcontroller collaborative architecture adopted by the tracking capability arbitrator, as well as serial port data transmission and reception, network data transmission and reception, and data resolution processing, to achieve efficient collection and accurate resolution of the superimposed information in the image source board and the detected digital image processor. This effectively distinguishes the performance of the image processor under different tracking tasks, provides a detailed and reliable basis for its performance evaluation, and improves the efficiency and accuracy of data processing and arbitration.

[0013] The present invention optimizes the hardware design of the entire detection device, including the electrical interface, communication interface and data transmission process of each board, ensuring good coordination between the components, solving problems such as poor data synchronization of existing detection technologies, improving the stability and reliability of the detection device, ensuring the integrity and accuracy of data transmission, and enhancing the credibility of the detection results. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a principle block diagram of a device for detecting the tracking capability of a digital image processor according to an embodiment of the present invention;

[0015] Figure 2 This is a data flow diagram of the digital image processor tracking capability detection device according to an embodiment of the present invention;

[0016] Figure 3This is a data processing flow chart of the digital image processor tracking capability detection device according to an embodiment of the present invention;

[0017] Figure 4 This is a timing diagram of the digital image processor tracking capability detection device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0019] The present invention provides a highly integrated tracking capability detection device, which focuses on detecting the tracking capability of an image processor. The device mainly consists of a multi-target image source board, a tracking capability arbitrator, a network switch, and a host computer. The multi-target image source board uses an XC7K160T FPGA chip for core logic control, generating multiple pseudo-random numbers to achieve random and independent planning of multiple image target trajectories. The FPGA-generated digital images are then converted into differential digital signals compliant with the Camera Link protocol via a serial-to-parallel conversion interface. The multi-target image source board's hardware includes modules such as an external clock, FLASH storage, and various interfaces. Functional modules such as the FPGA's internal clock and line / field signals operate collaboratively. The tracking capability arbiter utilizes an FPGA + GD32 approach for core logic control, including serial ports, network data transceiver modules, and related peripheral circuits. It collects overlay information from the multi-target image source board and the digital image processor, and calculates the cyclic code and target miss distance information. The results determine the tracking capability of the digital image processor being tested. The host computer receives and visually displays images and arbitration information. A network switch ensures data transmission. The digital image processor being tested receives the images containing the overlay information, extracts relevant information, and sends it to the network switch. The various components of the entire system work together to accurately test the image processor's tracking capability and provide a reliable basis for performance evaluation.

[0020] Specifically, if Figure 1 As shown, the multi-target image source board generates multi-target images with superimposed information including target miss distance and cyclic code based on the FPGA chip, and transmits the generated multi-target images to the host computer through the Camera Link interface and to the detected digital image processor through the optical fiber interface, and outputs the superimposed information to the tracking capability arbitrator through the serial interface at the same frequency. The FPGA chip in the multi-target image source board plans the independent trajectories of multiple image targets with random and dynamic changes in target trajectories through pseudo-random numbers, and can support multi-type camera simulation functions with adjustable resolution and image frequency.

[0021] The hardware of the multi-target image source board primarily consists of an FPGA and its peripheral circuits. An external clock provides the clock reference for the entire system. The FLASH memory module is responsible for storing the system's program data files and performing logic initialization on the FPGA chip during each power-up. The power supply module provides power to the entire system, ensuring that different voltage levels are powered up in the correct sequence during the power-up process. In addition, there is an online debugging interface (JTAG interface) that enables program burning and online simulation. The serial output interface uses an interface chip to convert the TTL digital signal output by the FPGA chip into a standard 422 differential signal for output to the back-end data processor. The Camera Link output interface uses a standard Full Mode interface, consisting of two independent MDR26 physical interfaces: Base and Medium / Full, capable of outputting digital image data at a rate of up to 6.8Gbps.

[0022] As the core logic processing unit of the system, the FPGA chip contains multiple functional modules.

[0023] (1) Preset target generation module, used to generate targets in the form of point targets and surface targets.

[0024] Targets are generated in the form of point targets and surface targets. Surface targets can be input as preset images. Preset image targets can more comprehensively test the target extraction capabilities of the image processing module and better restore the characteristics of real images.

[0025] (2) Background generation module, which is used to fill the lower n bits of the image pixels with generated random numbers to simulate complex scene noise in order to detect the filtering ability and anti-interference performance of the tracking capability detection device.

[0026] The background generation module uses a random number generator to generate random numbers, fills the lower n bits of the image pixels with random numbers, and the other positions of the image pixels are 0.

[0027] (3) Trajectory planning module, which is used to randomly and dynamically generate multiple targets with the center pixel of the image as the origin, and output the center point of the multiple targets as the true value of their respective miss distances.

[0028] The target trajectory generated by the trajectory planning module changes randomly and dynamically, outputting the target center point as the true value of the target miss distance transmitted in the overlay information. Multiple targets can be generated for multi-target detection by the processor. The tracking capability arbitrator uses the center pixel of the image as the target miss distance origin when performing position conversion, and solves the problem based on the transmitted target miss distance true value and origin information.

[0029] At the same time, the FPGA chip has multiple types of camera simulation functions:

[0030] The system simulates different camera image output modes, adopting adjustable resolution and image frequency to adapt to the camera. Overlay time information is obtained from the front-end timing board via the serial port, and the image output frequency can also be adapted to the different frame rates provided by the timing board. Furthermore, the output image resolution can be customized using the timing counter, including image resolutions such as 1920×1080 and 640×480. The system also synchronously outputs the specific line number and relative position of each line corresponding to the current line / field signal, providing a basis for the position of target overlay for subsequent modules.

[0031] The tracking capability arbitrator utilizes a collaborative architecture of an FPGA and a GD32 microcontroller. It collects overlay information output by the multi-target image source board and overlay information extracted from the multi-target imagery transmitted via a network switch by the digital image processor under test. It then calculates the cyclic codes and target miss distances in the collected overlay information, determines the tracking capability of the digital image processor under test based on the results, and ultimately generates arbitration information. This information is then transmitted to the host computer via the network switch. Communication between the network switch, the tracking capability arbitrator, and the host computer is achieved via a network interface (referred to as the network port) that uses the UDP protocol to transmit the extracted overlay information and arbitration information. The network port also communicates between the digital image processor under test and the network switch to transmit the overlay information extracted from the multi-target imagery.

[0032] The tracking capability arbiter's hardware primarily consists of a field-programmable gate array (FPGA) integrated with a GD32 microcontroller and its peripheral circuits. A temperature-compensated crystal oscillator provides the clock reference for the entire tracking capability arbiter system. The storage module stores the system's program data files and initializes the FPGA logic upon each power-up. The power module effectively suppresses and regulates input power voltage fluctuations, outputting a stable voltage that meets the voltage accuracy and stability requirements of various system components. The serial interface converts the input standard 422 differential signal into a TTL digital signal for output to the backend data processor. The network communication module provides the FPGA with efficient, stable, and reliable network connectivity and data transmission capabilities.

[0033] For high-speed serial communication, FPGAs can achieve very high data transmission rates. They can directly process high-speed clock and data signals and reduce transmission delays through optimized logic design. However, the serial communication speed of the GD32 microcontroller is often limited by its internal hardware resources and clock frequency, which may not meet the requirements when processing high-speed data. Therefore, the tracking capability arbiter uses the FPGA to receive serial port data and transmits it to the GD32 microcontroller via SPI for processing, ensuring accurate and high-speed data transmission.

[0034] The network communication module leverages its fast data transmission capabilities to achieve efficient data exchange. It can quickly send small data packets and implement unicast and multicast capabilities based on the User Datagram Protocol (UDP), sending data simultaneously to multiple recipients and improving information dissemination efficiency. Furthermore, it can perform simple encapsulation and decapsulation of UDP packets, process packet header information, and extract key data content.

[0035] The data flow of the digital image processor tracking capability detection device is as follows Figure 2 As shown in the figure, the multi-target image source board has one input interface and three output interfaces. The input interface receives real-time serial time information and external trigger signals transmitted by the time control board. The output interfaces are fiber optic, serial, and Camera Link. The fiber optic interface outputs an image with overlay information to the digital image processor under inspection. This interface can use an SFP optical module interface to transmit and receive optical signals. The SFP optical module interface supports high-speed data transmission and has advantages such as small size and hot swappability. The serial interface outputs overlay information to the tracking capability arbitrator at the same frequency as the fiber optic interface. The serial interface is simple and reliable and is suitable for low-speed data transmission scenarios. For example, the serial interface uses the RS-422 standard for one-to-one communication with external devices to transmit overlay information. The Camera Link interface outputs the image with overlay information to the host computer. The Camera Link interface uses a standard full-mode interface, including two independent MDR26 physical interfaces: Base and Medium / Full, capable of outputting digital image data at a maximum rate of 6.8 Gbps. The tracking capability arbitrator receives the overlay information from the serial port and the overlay information extracted from the multi-target image by the digital image processor under test through the network port, respectively. After comparing and processing the information, the arbitration information is sent to the host computer via the network switch. The digital image processor under test receives the image containing the overlay information transmitted via the optical fiber, extracts the overlay information from the image, including the target miss distance and cyclic code, and then sends it to the network switch through the network port. The host computer, serving as the terminal display and monitoring platform for the entire data processing process, ultimately integrates and visualizes the received images and arbitration information. This intuitive display method can more conveniently and accurately obtain the real-time computing performance indicators of the tested board, providing a strong basis for evaluating the board's working efficiency.

[0036] The data processing flow of the digital image processor tracking capability detection device is as follows: Figure 3As shown in the figure, the multi-target image source board receives an external trigger signal from the timing board via the serial port as an image trigger and simultaneously overlays the received time information onto the image. The multi-target image source board generates a multi-target image and corresponding overlay information, which includes the target miss distance and cyclic code. The multi-target image is then transmitted to the digital image processor being tested and the host computer, respectively, and the overlay information is transmitted to the tracking capability arbitrator. The digital image processor extracts the overlay information from the image and transmits it to the tracking capability arbitrator in the form of a network message. The tracking capability arbitrator verifies the accuracy of the overlay information of each frame transmitted by the multi-target image source board, as well as the target miss distance and cyclic code extracted from the overlay information by the digital image processor. If the judgment result indicates that both the miss distance and cyclic code are correct, the digital image processor's tracking capability meets the qualified standard. Conversely, if the judgment result indicates that either the miss distance or the cyclic code is incorrect, the digital image processor's tracking capability is deemed unqualified, indicating that the digital image processor's tracking capability does not meet the requirements. The current frame image judgment is terminated and the next frame image is awaited. Finally, this judgment result information, namely the arbitration information, will be transmitted to the host computer for clear display, so that relevant technical personnel can obtain the image processor's tracking capability evaluation results in a timely and intuitive manner, thereby providing key data support and decision-making basis for subsequent system optimization, troubleshooting, and performance improvement.

[0037] The temporal relationship between the image and the superimposed information is as follows Figure 4 As shown, all data uses the image sent by the multi-target image source board as the synchronization source reference T0. TRANS is the time delay on the fiber link, T PRO is the time delay of the digital image processor in processing data, T NETA 、T NETB 、T NETC All are network delays, where T NETA is the network delay from the network switch to the tracking capacity arbitrator, T NETB is the network delay from the tracking capacity arbitrator to the network switch, T NETC It is the network delay from the network switch to the host computer.

[0038] Therefore, the time delay from the multi-target image source board to the final host computer display is:

[0039] T2- T0= T TRANS + T PRO + T NETA + T NETB + T NETC ;

[0040] The time delay from the multi-target image source board to the tracking capability arbitrator is:

[0041] T1 - T0 = T TRANS + T PRO + T NETA ;

[0042] To obtain a more accurate data processing delay time T of the digital image processor, PRO The data processing function of the digital image processor can be shielded to calculate a delay difference T from the multi-target image source board to the tracking capability arbitrator. DIF , and then use the delay difference T DIF Inversely deduce T PRO , we can get the real delay time of the digital image processor and make a more accurate comparison of the digital image processors being tested. The formula is as follows:

[0043] T DIF = T TRANS + T NETA ;

[0044] T PRO = T1- T0- T DIF .

[0045] The multi-target image source board in the present invention uses an FPGA chip as its core to generate pseudo-random numbers to achieve precise, random, and independent planning of multi-image target trajectories. This allows for highly simulated, complex multi-target motions at a target range, and with the help of the FPGA's internal functional modules, it can flexibly adjust target characteristics and scene parameters, greatly enriching the diversity of test scenarios. The tracking capability arbitrator utilizes an FPGA + GD32 microcontroller collaborative architecture. Combining multiple modules, it can efficiently and accurately collect and resolve cyclic codes and target miss distances in the superimposed information of the multi-target image source board and the digital image processor in the optical measurement equipment, accurately evaluating tracking capabilities. The host computer, network switch, and processors collaborate to ensure stable data transmission and efficient system operation, providing realistic test conditions for the target range optical measurement equipment to fully verify its adaptability and accuracy, while also achieving precise evaluation and stable operation.

[0046] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A digital image processor tracking capability detection device, characterized in that: include: A multi-target image source board generates multi-target images with superimposed information including target miss distances and cyclic codes based on an FPGA chip, transmits the multi-target images to a host computer via a Camera Link interface and to a detected digital image processor via an optical fiber interface, and outputs the superimposed information to a tracking capability arbitrator via a serial interface at the same frequency. The FPGA chip uses pseudo-random numbers to plan independent multi-image target trajectories with randomly changing target trajectories and supports multi-type camera simulation functions with adjustable resolution and image frequency. The optical fiber interface uses an SFP optical module interface. The tracking capability arbitrator adopts a collaborative architecture of FPGA and GD32 microcontroller, collects the superposition information output by the multi-target image source board and the superposition information extracted from the multi-target image transmitted by the detected digital image processor via a network switch, calculates the cyclic code and target miss distance in the collected superposition information, determines the tracking capability of the detected digital image processor based on the calculation result, obtains arbitration information, and sends the arbitration information to the host computer via the network switch in a network form; The multi-target image sent by the multi-target image source board is used as the synchronization source reference T0, and the delay time T of the digital image processor to be detected in processing data is PRO Calculated by the following formula: T PRO =T1-T0-T DIF Wherein, T1-T0 is the time delay from the multi-target image source board to the tracking capability arbitrator, which is equal to the sum of the time delay on the optical fiber link, the time delay of the detected digital image processor and the data processing time of the tracking capability arbitrator, and the network delay from the network switch to the tracking capability arbitrator. DIF The delay difference from the multi-target image source board to the tracking capability arbitrator is calculated after the data processing function of the digital image processor to be detected is shielded; The host computer integrates and visualizes the received multi-target images and the arbitration information.

2. A digital image processor tracking capability detection device according to claim 1, characterized in that: The multi-target image source board includes an FPGA chip and its peripheral circuits, wherein an external clock provides a clock reference for the multi-target image source board; a FLASH storage module is responsible for storing the system's program data files and performing logic initialization on the FPGA chip each time it is powered on; a power supply module supplies power to the multi-target image source board and ensures that different voltage levels are powered on in the correct order during the power-on process; an online debugging interface is used to implement program burning and online simulation; a serial output interface uses an interface chip to convert the TTL digital signal output by the FPGA chip into a standard 422 differential signal; and a Camera Link output interface uses a standard Full mode interface, including two independent MDR26 physical interfaces, Base and Medium / Full, capable of achieving a maximum digital image data output of 6.8Gbps.

3. The digital image processor tracking capability detection device according to claim 2, characterized in that: The FPGA chip includes: A preset target generation module is used to generate targets in the form of point targets and area targets; Background generation module, used to fill the lower n bits of image pixels with generated random numbers to simulate complex scene noise; The trajectory planning module is used to randomly and dynamically generate multiple targets with the center pixel point of the image as the origin, and use the center point of the multiple targets as the true value output of their respective miss distances.

4. The digital image processor tracking capability detection device according to claim 1, characterized in that: The tracking capability arbiter includes a collaborative architecture of an FPGA and a GD32 microcontroller and its peripheral circuits. After receiving serial port data, the FPGA transmits it to the GD32 microcontroller via SPI for processing. The temperature-compensated crystal oscillator provides a clock reference for the tracking capability arbiter. The storage module is responsible for storing the system's program data files and performing logic initialization on the FPGA each time the power is turned on. The power module outputs a stable voltage to meet the voltage accuracy and stability requirements of different components in the system; the serial interface converts the input standard 422 differential signal into a TTL digital signal; and the network communication module provides network connection and data transmission capabilities for the FPGA.

5. The digital image processor tracking capability detection device according to claim 4, characterized in that: The network communication module supports unicast and multicast functions based on the User Datagram Protocol, and sends data to multiple receivers simultaneously.

6. The digital image processor tracking capability detection device according to claim 1, characterized in that: The serial interface adopts RS-422 standard to transmit superposition information.

7. The digital image processor tracking capability detection device according to claim 1, characterized in that: The Camera Link interface adopts a standard Full mode interface, including two independent MDR26 physical interfaces: Base and Medium / Full.

8. The digital image processor tracking capability detection device according to claim 7, characterized in that: The data transmission rate of the Camera Link interface is less than or equal to 6.8 Gbps.

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