Operation method of storage controller and storage device comprising storage controller

Abstract

An operating method of a memory controller configured to control a non-volatile memory device includes receiving, from an external host, a first write command of a first logical address included in a first logical address range corresponding to a first trim bit, the first trimming bit is in an active state, performs a first mapping invalidation for the first logical address range in response to the first write command, receives a second write command from the host corresponding to a second logical address included in the first logical address range before the first mapping invalidation is completed, and performs a second mapping invalidation for the second logical address range. A second mapping invalidation corresponding to the second write command is skipped, and after the first mapping invalidation is completed, a mapping update is performed for the second logical address.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0002419, filed with the Korean Intellectual Property Office on January 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concept described herein relate to a semiconductor memory, and more particularly, to a storage controller configured to control a non - volatile memory device, an operation method thereof, and a storage device including the storage controller. Background Art

[0004] Semiconductor memories are classified as volatile memories, which lose data stored therein when the power is turned off, such as static random access memory (SRAM) or dynamic random access memory (DRAM), or non - volatile memories, which retain data stored therein even when the power is turned off, such as flash memory, phase - change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0005] A host uses a memory and a storage device. When the host deletes a file, the host may not erase the data corresponding to the file and may mark the data to indicate an unused state. Even when the host marks the data to indicate an unused state, the storage device may recognize the data corresponding to the deleted file as valid data.

[0006] Accordingly, the host may transmit, provide, or send a trim command to the storage device. The trim command may be a command for providing a notification that the data corresponding to the deleted file is invalid data. The storage device may recognize the data corresponding to the deleted file as invalid data in response to the trim command. To improve performance, it may be advantageous to provide a storage device that processes trim commands at high speed. Summary of the Invention

[0007] Example embodiments of the inventive concept provide a storage controller configured to control a non - volatile memory device, an operation method thereof, and a storage device including the storage controller.

[0008] According to some example embodiments, an operating method of a storage controller configured to control a non-volatile memory device includes: receiving, from an external host, a first write command for a first logical address included in a first logical address range corresponding to a first trim bit, the first trim bit being in an active state when the first write command is received; in response to the first write command, performing a first mapping invalidation for the first logical address range; before the first mapping invalidation is completed, receiving, from the host, a second write command corresponding to a second logical address included in the first logical address range; skipping a second mapping invalidation corresponding to the second write command; and after the first mapping invalidation is completed, performing a mapping update for the second logical address.

[0009] According to some example embodiments, a storage device includes a non-volatile memory device and a storage controller configured to control the non-volatile memory device. The storage controller is configured to receive, from an external host, a first write command for a first logical address included in a first logical address range corresponding to a first trim bit, perform a first mapping invalidation for the first logical address range in response to the first write command, before the first mapping invalidation is completed, receive, from the host, a second write command corresponding to a second logical address included in the first logical address range, skip a second mapping invalidation corresponding to the second write command, and after the first mapping invalidation is completed, perform a mapping update for the second logical address.

[0010] According to some example embodiments, an operating method of a storage controller configured to communicate with a host and a non-volatile memory device includes: activating a first trim bit corresponding to a first logical address range in response to a trim command from the host; receiving, from the host, a first write command for a first logical address included in the first logical address range; initiating a first mapping invalidation of the first logical address range in response to the first write command; before the first mapping invalidation is completed, receiving, from the host, a second write command corresponding to a second logical address included in the first logical address range; when the second write command is received, skipping a second mapping invalidation corresponding to the second write command based on the first trim bit being in an active state and the first mapping invalidation not being completed; completing the first mapping invalidation and performing a first mapping update for the first logical address; and after the first mapping update is completed, performing a mapping update for the second logical address. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the inventive concept will become apparent by describing in detail some example embodiments of the inventive concept with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram of a storage system according to some example embodiments.

[0013] Figure 2 is a schematic diagram showing a Figure 1 storage controller according to some example embodiments.

[0014] Figure 3 is a schematic diagram depicting the operation of a Figure 2 storage controller associated with a trimming bitmap according to some example embodiments.

[0015] Figure 4A and Figure 4B is a schematic diagram depicting the operation of a Figure 1 storage controller when the storage controller receives a write command according to some example embodiments.

[0016] Figure 5A and 5B is a schematic diagram showing an example of the operation of a Figure 1 storage controller when the storage controller continuously receives write commands according to some example embodiments.

[0017] Figure 6 is a flowchart depicting the operation of a Figure 1 storage controller according to some example embodiments.

[0018] Figure 7 is a schematic diagram depicting the operation of a Figure 1 storage controller according to some example embodiments.

[0019] Figure 8 is a flowchart depicting the operation of a Figure 1 storage controller according to some example embodiments.

[0020] Figure 9A and Figure 9B is a schematic diagram showing an example of the operation of a Figure 1 storage controller 110 according to some example embodiments.

[0021] Figure 10 is a schematic diagram depicting the operation of Figure 8 operation S1100 according to some example embodiments.

[0022] Figure 11 is a block diagram depicting the operation of a Figure 1 mapping data manager according to some example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, some example embodiments of the inventive concept will be described in detail and clearly so that those skilled in the art can easily implement the inventive concept.

[0024] In the specification, functional blocks corresponding to terms such as "block", "unit", "logic", etc. can be implemented in the form of software, hardware, or a combination thereof.

[0025] Figure 1 is a block diagram of a storage system according to some example embodiments. Refer to Figure 1 , the storage system 10 may include a host 11 and a storage device 100. In some example embodiments, the storage system 10 may refer to a computing system configured to process various information, such as a personal computer (PC), a laptop, a notebook computer, a server, a workstation, a tablet PC, a smart phone, a digital camera, and a black box, but the example embodiments are not limited thereto.

[0026] The host 11 may control the overall operation of the storage system 10. For example, the host 11 may store data in the storage device 100, or may read data stored in the storage device 100.

[0027] The storage device 100 may include a storage controller 110, a non-volatile memory device (NVM) 120, and a volatile memory device 130. The non-volatile memory device 120 may store data. The storage controller 110 may store data in the non-volatile memory device 120, or may read data stored in the non-volatile memory device 120. The volatile memory device 130 may be used as an external buffer memory of the storage device 100. The non-volatile memory device 120 may operate under the control of the storage controller 110. For example, based on a command CMD indicating an operation and an address indicating a data location, the storage controller 110 may store data in the non-volatile memory device 120, or may read data stored in the non-volatile memory device 120.

[0028] Figure 1 shows an example where the volatile memory device 130 exists outside the storage controller 110, but the example embodiments are not limited thereto. For example, the volatile memory device 130 may exist in the storage controller 110.

[0029] In some example embodiments, the non-volatile memory device 120 may be a NAND flash memory device, but the example embodiments are not limited thereto. For example, the non-volatile memory device 120 may be one of various storage devices that retain data stored therein even when the power is turned off, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM).

[0030] The volatile memory device 130 may include a random access memory. For example, the volatile memory device 130 may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistive random access memory.

[0031] The volatile memory device 130 may include a trim bitmap TBMP. For example, the volatile memory device 130 may be configured to store the trim bitmap TBMP. In some example embodiments, the trim bitmap TBMP may include a plurality of trim bits. Each of the plurality of trim bits may indicate whether data corresponding to a relevant logical address range among a plurality of logical address ranges is invalid data. Each logical address range may include at least two logical addresses. The trim bitmap TBMP will be described in detail with reference to Figure 3 the following.

[0032] In some example embodiments, the host 11 may run an operating system (OS) that supports a file system. The host 11 may delete a file that is being used. When the file is deleted, the host 11 may send, transmit, or provide a trim command to the storage device 100, the trim command being for invalidating data in the non-volatile memory device 120 that corresponds to the deleted file. For example, the trim command may include information about a logical address (e.g., a trim target address) corresponding to the data of the deleted file. The storage device 100 may manage the data in the non-volatile memory device 120 (which corresponds to the data of the deleted file) as invalid data in response to the trim command.

[0033] In some example embodiments, the storage controller 110 may include a mapping data manager 114a and a hazard table HT.

[0034] The mapping data manager 114a may perform mapping invalidation for a trim target address in response to a trim command from the host 11. For example, the mapping invalidation may include an operation of removing (or unmapping) the mapping relationship between a logical address and a physical address.

[0035] The mapping invalidation operation may be referred to as an "unmapping operation". The mapping data manager 114a may identify a target logical address for mapping invalidation based on the trim bitmap TBMP and may perform mapping invalidation.

[0036] According to some example embodiments, the mapping data manager 114a may perform mapping update for a logical address corresponding to a write command in response to the write command. For example, the mapping data manager 114a may perform mapping update by mapping the logical address corresponding to the write command to the physical address where the write data is to be stored.

[0037] The hazard table HT may include information about logical addresses with a hazard occurrence probability. For example, the hazard table HT may include information about target logical addresses whose mapping is invalid via a write command. In some example embodiments, the storage device 100 may receive a write command for a logical address included in a trim target address before performing mapping invalidation for the trim target address. In some example embodiments, the mapping data manager 114a may store information about the trim target address in the hazard table HT.

[0038] For example, a logical address in a first logical address range among a plurality of logical address ranges may be a trim target address. The storage device 100 may receive a first write command from the host 11 before performing mapping invalidation for the trim target address. The write target logical address of the first write command may be the first logical address included in the first logical address range.

[0039] In some example embodiments, the mapping data manager 114a may initiate a first mapping invalidation of the first logical address range in response to the first write command. The first mapping invalidation may mean that the mapping of all logical addresses included in the first logical address range is invalidated. The logical addresses included in the first logical address range may include a second logical address.

[0040] The storage device 100 may receive the first write command and then may receive a second write command from the host 11 before completing the first mapping invalidation (e.g., before completing the first mapping invalidation). The second write command may correspond to the second logical address.

[0041] For example, the mapping data manager 114a may initiate a second mapping invalidation of the first logical address range in response to the second write command. In some example embodiments, the mapping invalidation of the logical addresses belonging to the first logical address range may be repeated and executed. In some example embodiments, a hazard may be caused by the second write command.

[0042] According to some example embodiments, the mapping data manager 114a may skip mapping invalidation in consideration of the probability that a hazard can be caused by the second write command wCMD2 (e.g., refer to Figure 4B ). For example, the mapping data manager 114a may check whether information about logical addresses belonging to the same logical address range as the second logical address corresponding to the second write command is included in the hazard table HT. In some example embodiments, when information about logical addresses belonging to the same logical address range as the second logical address is included in the hazard table HT and the trim bit corresponding to the second logical address is active, the mapping data manager 114a may determine that a hazard can be caused by the second write command.

[0043] For example, when a second write command is received, the first mapping invalidation of the first logical address range based on the first write command may not be completed. In some example embodiments, when a second write command is received, the hazard table HT may include information about the second logical address.

[0044] For example, when a hazard may occur, the mapping data manager 114a may perform a mapping update only for the second logical address, without performing a second mapping invalidation based on the second write command wCMD2. In some example embodiments, duplicate runs of mapping invalidation may be prevented. Accordingly, the performance of the storage device 100 may be improved.

[0045] In other words, according to some example embodiments, the storage device 100 may prevent duplicate execution of mapping invalidation by determining whether a hazard may occur by referring to the hazard table HT. Accordingly, in some example embodiments, a storage controller configured to control a non-volatile memory device, an operation method thereof, and a storage device including the storage controller may be provided with improved performance. Some example embodiments of the inventive concept will be described in detail with reference to the following drawings.

[0046] Figure 2 is a schematic diagram of a Figure 1 storage controller according to some example embodiments. Referring to Figure 1 and Figure 2 , the storage controller 110 may include a system bus 111, a host interface 112, a buffer memory 113, a flash translation layer (FTL) 114, a central processing unit (CPU) 115, a volatile memory controller 116, an error correction code (ECC) engine 117, and a memory interface 118.

[0047] The system bus 111 may provide a communication channel between components of the storage controller 110. The host interface 112 may receive various requests from an external host device and may parse the received requests. The host interface 112 may store the parsed requests in the buffer memory 113.

[0048] The host interface 112 may send, provide, or transmit various responses to an external host device. The host interface 112 may exchange signals with the external host device in accordance with a given communication protocol. For example, the communication protocol may include at least one of the protocols for various interfaces, such as an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, an External SATA (e-SATA) interface, a Small Computer System Interface (SCSI) interface, a Serial Attached SCSI (SAS) interface, a Peripheral Component Interconnect (PCI) interface, a PCI Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, IEEE 1394, a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, a Multimedia Card (MMC) interface, an Embedded Multimedia Card (eMMC) interface, a Universal Flash Storage (UFS) interface, an Embedded Universal Flash Storage (eUFS) interface, a Compact Flash (CF) card interface, a Compute Express Link (CXL) interface, and a network interface, but the example embodiments are not limited thereto.

[0049] The buffer memory 113 may include a random access memory. For example, the buffer memory 113 may include a static random access memory or a dynamic random access memory.

[0050] The FTL 114 may be configured to manage an address mapping between a logical address from the host 11 and a physical address of the storage device 100. In some example embodiments, the FTL 114 may include a mapping data manager 114a and a hazard table HT. In some example embodiments, the hazard table HT may be implemented through an internal register of the FTL 114.

[0051] The FTL 114 may perform a wear-leveling operation so as to prevent excessive deterioration of a specific memory block among the memory blocks of the non-volatile memory device 120. The lifespan of the non-volatile memory device 120 may be improved through the wear-leveling operation of the FTL 114. The FTL 114 may perform garbage collection for the non-volatile memory device 120 to protect free memory blocks.

[0052] In some example embodiments, the FTL 114 may be implemented in the form of software or hardware. For example, in the case where the FTL 114 is implemented in the form of software, the program code or information associated with the FTL 114 may be stored in the volatile memory device 130 and may be run by the CPU 115. In some example embodiments, when the FTL 114 is implemented in the form of hardware, a hardware accelerator configured to perform the operations of the FTL 114 may be provided independently of the CPU 115. In some example embodiments, the FTL 114 may include or be implemented as a processing circuit, such as hardware (e.g., logic circuit) or a combination of hardware and software (e.g., a computer-based electronic system, such as a processor running instruction code or program routines (e.g., software programs)).

[0053] The CPU 115 may control the overall operation of the storage controller 110. The FTL 114 may perform various operations for effectively using the non-volatile memory device 120.

[0054] Under the control of the CPU 115, the volatile memory controller 116 may write data into the volatile memory device 130 or may read data from the volatile memory device 130. In some example embodiments, the volatile memory device 130 may include a mapping table MT, physical address information PBI, and a trim bitmap TBMP.

[0055] In some example embodiments, the mapping table MT may include mapping information between a logical address and a physical address. For example, the logical address LA may indicate a logical page number LPN received from the host 11. The logical page number LPN may indicate the position of data that can be recognized by the host 11. For example, the physical address may indicate a physical page number PPN of a memory block of the non-volatile memory device 120. The physical page number PPN may indicate the position of the non-volatile memory device 120 where the data is stored.

[0056] In some example embodiments, the physical address information PBI may include information on whether the data stored at the physical address is valid data or invalid data. In some example embodiments, the physical address information PBI may include a valid page count, which indicates the number of valid pages among a plurality of pages included in each memory block of the non-volatile memory device 120. The trim bitmap TBMP will be described in detail with reference to Figure 3 be described in detail.

[0057] The ECC engine 117 may perform error detection and error correction on data read from the non-volatile memory device 120. In some example embodiments, the ECC engine 117 may be implemented as processing circuitry, such as hardware (e.g., logic circuitry) or a combination of hardware and software (e.g., a computer-based electronic system), such as a processor running instruction code or program routines (e.g., a software program). For example, the ECC engine 117 may generate an error correction code (or parity bits) for data to be written to the non-volatile memory device 120. The generated error correction code (or parity bits) may be stored in the non-volatile memory device 120 together with the data to be written. In some example embodiments, when reading the written data from the non-volatile memory device 120, the ECC engine 117 may detect and correct errors in the read data based on the read data and the corresponding error correction code (or the corresponding parity bits).

[0058] The memory interface 118 may be configured to communicate with the non-volatile memory device 120 in accordance with a given communication protocol. The memory interface 118 may provide data to be written to the non-volatile memory device 120, or may receive data read from the non-volatile memory device 120. The memory interface 118 may be implemented to comply with a standard such as a switching or Open NAND Flash Interface (ONFI).

[0059] In some example embodiments, the mapping data manager 114a may manage the hazard table HT, the mapping table MT, the physical address information PBI, and the trim bitmap TBMP. For example, the mapping data manager 114a may update the mapping table MT and the physical address information PBI based on the hazard table HT.

[0060] In some example embodiments, when deleting mapping information regarding a logical address in the mapping table MT, the mapping data manager 114a may perform mapping invalidation. When the mapping information is deleted, the data stored at the physical address corresponding to the deleted logical address may be processed (or managed) as invalid data. In some example embodiments, mapping invalidation may include marking the physical address information PBI such that the data stored at the physical address corresponding to the trim target address is invalid data and changing the valid page count.

[0061] In some example embodiments, the volatile memory device 130 and the volatile memory controller 116 may be omitted in the storage device 100. According to some example embodiments, when the volatile memory device 130 and the volatile memory controller 116 are omitted, the functions described as being performed by the volatile memory device 130 and the volatile memory controller 116 may be performed by the buffer memory 113.

[0062] Figure 3 is a schematic diagram describing the operation of a storage controller associated with a trimming bitmap according to some example embodiments. Referring to Figure 2 , a plurality of logical addresses LPN1 to LPN12 may be included in a plurality of logical address ranges LAR1 to LAR3. For example, the first logical address range LAR1 may include the first logical address LPN1 to the fourth logical address LPN4, the second logical address range LAR2 may include the fifth logical address LPN5 to the eighth logical address LPN8, and the third logical address range LAR3 may include the ninth logical address LPN9 to the twelfth logical address LPN12. Figure 3 An example in which one logical address range includes four logical addresses is shown in Figure 3 , but the example embodiments of the inventive concept are not limited thereto.

[0063] According to some example embodiments, the storage device 100 may include a trimming bitmap TBMP, which includes trimming bits corresponding to the logical address ranges LAR1 to LAR3, respectively. The trimming bits may indicate whether the corresponding logical address range is a target for which mapping is to be invalidated. For example, the first trimming bit may correspond to the first logical address range LAR1, the second trimming bit may correspond to the second logical address range LAR2, and the third trimming bit may correspond to the third logical address range LAR3.

[0064] The storage controller 110 may receive a trimming command TRIM CMD from the host 11. The trimming command TRIM CMD may include a trimming target address. Based on the trimming target address, the storage controller 110 may manage the trimming bitmap TBMP and may perform mapping invalidation.

[0065] For example, the trimming target address may include only the tenth logical address LPN10. For example, the trimming target address LPN10 may not include all the logical addresses (e.g., LPN9 to LPN12) included in one logical address range (e.g., LAR3). In some example embodiments, after the storage controller 110 receives the trimming command, the storage controller 110 may immediately perform mapping invalidation for the trimming target address (e.g., LPN10) without updating the trimming bitmap TBMP.

[0066] For example, the trimming target address may include the fifth logical address LPN5 to the eighth logical address LPN8. For example, the trimming target address LPN5 to LPN8 may include all the logical addresses LPN5 to LPN8 included in one logical address range LAR2.

[0067] In some example embodiments, after the storage controller 110 receives a trim command, the storage controller 110 may not immediately perform mapping invalidation for the trim target addresses LPN5 to LPN8. In some example embodiments, the storage controller 110 may change the trim bits corresponding to the trim target addresses LPN5 to LPN8 from "0" to "1" (or may activate the trim bits corresponding to the trim target addresses LPN5 to LPN8), and then may send, provide, or transmit a response indicating the completion of mapping invalidation to the host 11 without actually performing mapping invalidation.

[0068] After that, during the idle time, the storage controller 110 may perform mapping invalidation for the trim target addresses LPN5 to LPN8 corresponding to the activated trim bits. After the storage controller 110 completes mapping invalidation during the idle time, the storage controller 110 may deactivate the trim bits corresponding to the trim target addresses LPN5 to LPN8.

[0069] For example, the trim target addresses may include the fourth logical address LPN4 to the ninth logical address LPN9. For example, some of the trim target addresses (e.g., LPN5 to LPN8) among the trim target addresses (e.g., LPN4 to LPN9) may correspond to all the logical addresses included in a logical address range LAR2, and the remaining trim target addresses LPN4 and LPN9 may be the logical addresses included in the logical address ranges LAR1 and LAR3. In some example embodiments, after the storage controller 110 receives a trim command, the storage controller 110 may immediately activate the trim bits corresponding to the logical address range LAR2 and may perform mapping invalidation for the logical addresses LPN4 and LPN9. For example, the storage controller 110 may defer the processing of some (e.g., LPN5 to LPN8) of the trim target addresses (e.g., LPN4 to LPN9) and may immediately process the others (e.g., LPN4 and LPN9) of the trim target addresses.

[0070] For example, the storage controller 110 may reduce the number of logical addresses by using trim bits, and the mapping invalidation of the logical addresses will be performed immediately after receiving the trim command. Thus, the storage controller 110 may process the trim command quickly. Further, according to some example embodiments, one trim bit may correspond to at least two or more logical addresses. Thus, the capacity of the trim bitmap TBMP may be reduced. This may mean preventing or reducing an increase in the cost of manufacturing the storage device 100.

[0071] For example, when the trimming bit is "0", the logical address included in the logical address range corresponding to the trimming bit may be a target for which mapping is invalid. For ease of description, the trimming bit being "1" may refer to the activation of the trimming bit. In contrast, the trimming bit being "0" may refer to the deactivation of the trimming bit. However, the inventive concept is not limited thereto.

[0072] In some example embodiments, when the storage controller 110 receives a read command for a logical address corresponding to an activated trimming bit, even if the storage controller 110 does not actually perform mapping invalidation for the target logical address to be read, the storage controller 110 may notify the host 11 that the data corresponding to the logical address is invalid data. For example, when the trimming bit corresponding to the logical address range is activated, the storage controller 110 may manage the data corresponding to the logical address range as invalid data.

[0073] Figure 4A and Figure 4B is a schematic diagram describing the operation of the storage controller when the storage controller receives a write command according to some example embodiments Figure 1 will be described with reference to Figures 1 to 3 Description Figure 4A and Figure 4B . Referring to Figure 4A , for example, at a first time point, the trimming bits corresponding to the first logical address range LAR1 may be in an activated state based on a previously received trimming command (e.g., may be in a state of "1"), and the trimming bits corresponding to the second logical address range LAR2 and the third logical address range LAR3 may be in a deactivated state (e.g., may be in a state of "0").

[0074] After that, at a second time point, the storage controller 110 may receive a first write command wCMD1 for the first logical address LPN1. The first logical address LPN1 may be included in the first logical address range LAR1. The second time point may be a time point at which the storage controller 110 does not enter the idle time after the trimming bit is activated. For example, the second time point may be a time point at which mapping invalidation of the first logical address range LAR1 is not performed.

[0075] After that, at a third time point, the storage controller 110 may perform mapping invalidation for the first logical address range LAR1 including the first logical address LPN1. For example, the storage controller 110 may sequentially release the mapping relationships of the logical addresses LPN1 to LPN4 included in the first logical address range LAR1. After the storage controller 110 completes mapping invalidation of the first logical address range LAR1, the storage controller 110 may deactivate the trimming bit.

[0076] For example, at the fourth time point, the storage controller 110 may perform mapping update for the write target logical address LPN1. For example, the storage controller 110 may perform mapping update by mapping a new physical address to the write target logical address LPN1.

[0077] Meanwhile, in some example embodiments, referring to Figure 4B , for example, at the first time point, the storage controller 110 may receive a second write command wCMD2 for the fifth logical address LPN5 from an external host (e.g., 11).

[0078] After that, at the second time point, since the trim bit corresponding to the fifth logical address LPN5 is in the deactivated state, the storage controller 110 may perform mapping invalidation only for the fifth logical address LPN5. After the storage controller 110 completes the mapping invalidation of the fifth logical address LPN5, the storage controller 110 may perform mapping update for the fifth logical address LPN5.

[0079] As described above, the storage controller 110 may receive a write command (e.g., wCMD1) for a logical address (e.g., LPN1) corresponding to an activated trim bit. In some example embodiments, the storage controller 110 may perform mapping invalidation for all logical addresses in a logical address range (LAR1) including the write target logical address (e.g., LPN1), and perform mapping invalidation for the write target logical address (e.g., LPN1).

[0080] Conversely, in some example embodiments, the storage controller 110 may receive a write command (e.g., wCMD2) for a logical address (e.g., LPN5) corresponding to a deactivated trim bit. The logical addresses LPN5 to LPN8 corresponding to the deactivated trim bit may not be targets for mapping invalidation based on the trim command. Therefore, in some example embodiments, the storage controller 110 may not perform mapping invalidation for the remaining logical addresses (e.g., LPN6 to LPN8) in a logical address range (e.g., LAR2) other than the write target logical address (e.g., LPN5).

[0081] In some example embodiments, with Figure 4AUnlike the example shown, the storage controller 110 may perform mapping invalidation for the remaining logical addresses LPN2 to LPN4 except for the first logical address LPN1 corresponding to the first write command wCMD1, and may deactivate the trim bit. After the storage controller 110 deactivates the trim bit, the storage controller 110 may perform mapping invalidation for the first logical address LPN1. After that, the storage controller 110 may perform mapping update for the first logical address LPN1. For example, the storage controller 110 may continuously perform mapping update and mapping invalidation operations associated with the first logical address LPN1 corresponding to the first write command wCMD1. In some example embodiments, when the storage controller 110 performs mapping update and mapping invalidation operations, the number of times the storage controller 110 accesses the volatile memory device (e.g., Figure 1 130) may be reduced.

[0082] For ease of description and for simplicity of drawing, as described below Figure 4A will give a description of deactivating the trim bit after mapping invalidation of all logical addresses corresponding to the trim bit is completed. However, the inventive concept is not limited thereto.

[0083] Figure 5A and Figure 5B are diagrams illustrating examples of operations of a storage controller when the storage controller continuously receives write commands according to some example embodiments. Reference will be made to Figure 1 to describe Figures 1 to 4B . In Figure 5A and Figure 5B , in the graphs of Figure 5A and Figure 5B , the horizontal axis represents time and the vertical axis represents the task order. Referring to Figure 5A , at the 0th time point t0, the storage controller 110 may receive the first write command wCMD1 for the first logical address LPN1 corresponding to the activated trim bit. In some example embodiments, the storage controller 110 may perform the first process P1 during the time period from t0 to t6 in response to the first write command wCMD1.

[0084] In some example embodiments, during the time period from t0 to t1, the storage controller 110 may check the trim bitmap TBMP. For example, the storage controller 110 may read the trim bitmap TBMP stored in the volatile memory device (e.g., Figure 1 130), and may check that the trim bit corresponding to the first logical address LPN1 is in the activated state.

[0085] After that, during the time period from t1 to t5, the storage controller 110 may perform a first mapping invalidation in response to a first write command wCMD1. For example, the storage controller 110 may perform a first mapping invalidation for a logical address range including a first logical address LPN1 (e.g., Figure 4A LAR1).

[0086] The storage controller 110 may perform mapping invalidation for a second logical address LPN2 during the time period from t1 to t2, may perform mapping invalidation for a third logical address LPN3 during the time period from t2 to t3, may perform mapping invalidation for a fourth logical address LPN4 during the time period from t3 to t4, and may perform mapping invalidation for the first logical address LPN1 during the time period from t4 to t5.

[0087] In some example embodiments, the storage controller 110 may perform mapping invalidation for a second logical address LPN2 during the time period from t1 to t2, may perform mapping invalidation for a third logical address LPN3 during the time period from t2 to t3, may perform mapping invalidation for a fourth logical address LPN4 during the time period from t3 to t4, and may perform mapping invalidation for the first logical address LPN1 during the time period from t4 to t5. According to some example embodiments, different from the Figure 5A example shown, the order of the invalid logical addresses LPN1 to LPN4 may be changed.

[0088] In some example embodiments, at the fifth time point t5, when the storage controller 110 completes the mapping invalidation of the first logical address LPN1, the storage controller 110 may complete the first mapping invalidation. In some example embodiments, the storage controller 110 may deactivate the trim bit corresponding to the first logical address LPN1.

[0089] After that, during the time period from t5 to t6, the storage controller 110 may perform a mapping update for the first logical address LPN1.

[0090] In some example embodiments, at the first time point t1, the storage controller 110 may receive a second write command wCMD2 corresponding to a second logical address LPN2. In some example embodiments, as Figure 4A shown, both the first logical address LPN1 and the second logical address LPN2 may be included in the first logical address range LAR1.

[0091] For example, the storage controller 110 may execute a second process P2 during a time period from t1 to t7 in response to a second write command wCMD2. For example, even if a first process P1 based on a first write command wCMD1 is being executed, the storage controller 110 may execute a second process P2 based on the second write command wCMD2.

[0092] In some example embodiments, during a time period from t1 to t2, the storage controller 110 may check a trimming bitmap TBMP. The storage controller 110 may check whether a trimming bit corresponding to a second logical address LPN2 is in an active state. The trimming bit corresponding to the second logical address LPN2 may be the same as the trimming bit corresponding to a first logical address LPN1. As described above, the first mapping invalidation may be completed at a fifth time point t5. Therefore, the trimming bit may be in an active state during the time period from t1 to t2. For example, the storage controller 110 may check that the trimming bit corresponding to the second logical address LPN2 is in an active state.

[0093] In some example embodiments, during a time period from t2 to t6, the storage controller 110 may execute a second mapping invalidation for a logical address range (e.g., Figure 4A LAR1) including the second logical address LPN2 in response to the second write command wCMD2.

[0094] For example, the storage controller 110 may execute mapping invalidation for a first logical address LPN1 during a time period from t2 to t3, may execute mapping invalidation for a third logical address LPN3 during a time period from t3 to t4, may execute mapping invalidation for a fourth logical address LPN4 during a time period from t4 to t5, and may execute mapping invalidation for a second logical address LPN2 during a time period from t5 to t6. According to some example embodiments, different from the Figure 5A example shown, the order of invalid logical addresses LPN1 to LPN4 may be changed.

[0095] After that, during a time period from t6 to t7, the storage controller 110 may execute mapping update for the second logical address LPN2.

[0096] As described above, in some example embodiments, even when a first process P1 is running, the storage controller 110 may start running a second process P2. In some example embodiments, mapping invalidation for logical addresses LPN1 to LPN4 corresponding to trimming bits may be repeated and executed. Therefore, the consistency of the metadata of the storage controller 110 may be damaged.

[0097] Refer to Figure 5B, the write commands wCMD1 and wCMD2 corresponding to the activated trimming bits can be received continuously. In some example embodiments, different from the example shown in Figure 5A , until the first mapping invalidation based on the first write command wCMD1 is completed, the storage controller 110 can wait without processing the second write command wCMD2.

[0098] For example, when the storage controller 110 continuously receives the write commands wCMD1 and wCMD2 corresponding to the activated trimming bits, the storage controller 110 can determine that a data hazard has occurred. In some example embodiments, the storage controller 110 can generate a delay period DP associated with the second write command wCMD2. Therefore, until the first mapping invalidation is completed, the storage controller 110 can wait without processing the second write command wCMD2.

[0099] For example, at the fifth time point t5, the storage controller 110 can complete the first mapping invalidation and can deactivate the trimming bit corresponding to the first logical address LPN1.

[0100] After that, during the period from t5 to t6, the storage controller 110 can perform mapping update for the first logical address LPN1. In addition, the storage controller 110 can check the trimming bitmap TBMP in response to the second write command wCMD2. The storage controller 110 can check that the trimming bit corresponding to the second logical address LPN2 is in the deactivated state.

[0101] Since the trimming bit is in the deactivated state, as described in reference to Figure 4B , during the period from t6 to t7, the storage controller 110 can perform mapping invalidation only for the second logical address LPN2. For example, different from Figure 5A , in Figure 5B , the second mapping invalidation based on the second write command wCMD2 can include only the mapping invalidation of the second logical address LPN2.

[0102] After that, during the period from t7 to t8, the storage controller 110 can perform mapping update for the second logical address LPN2.

[0103] Referring to Figure 5B , after the first mapping invalidation based on the first write command wCMD1 is completed and the trimming bit is deactivated, the storage controller 110 can initiate the execution of the second process P2. In some example embodiments, the problem of repeated mapping invalidation of logical addresses due to the continuous input of the write commands wCMD1 and wCMD2 can be solved. However, in some example embodiments, such as in Figure 5B , the operation speed of the storage controller 110 may be slowed down due to the delay period DP.

[0104] When write commands wCMD1 and wCMD2 corresponding to logical addresses (e.g., LPN1 to LPN4) of activated trim bits are continuously received, a storage controller according to some example embodiments may skip second mapping invalidation based on the second write command wCMD2. Accordingly, a storage controller configured to control a non-volatile memory device, a method of operating the same, and a storage device including the storage controller are provided that have improved performance.

[0105] Figure 6 is a flowchart depicting the operation of a Figure 1 storage controller according to some example embodiments. Reference will be made to Figures 1 to 4B for a description of Figure 6 . Referring to Figure 6 , in operation S110, the storage controller 110 may receive a first write command wCMD1 corresponding to a first logical address LPN1 from the host 11. For example, the first logical address LPN1 may be included in a first logical address range (e.g., Figure 3 LAR1). In some example embodiments, when the storage device 100 receives the first write command wCMD1, the trim bits corresponding to the first logical address range (e.g., Figure 3 LAR1) may be in an activated state.

[0106] According to some example embodiments, prior to operation S110, the storage controller 110 may include receiving a trim command from the host 11 and activating the trim bits corresponding to the first logical address range LAR1 based on the trim command. In some example embodiments, the trim target address of the trim command may include all logical addresses LPN1 to LPN4 of the first logical address range LAR1.

[0107] In operation S120, the storage controller 110 may perform first mapping invalidation for the first logical address range (e.g., Figure 3 LAR1) in response to the first write command wCMD1. The first mapping invalidation may include invalidating the mappings of all logical addresses LPN1 to LPN4 belonging to the first logical address range (e.g., LAR1).

[0108] In operation S130, the storage controller 110 may receive a second write command wCMD2. For example, the storage controller 110 may receive the second write command wCMD2 before completion of the first mapping invalidation. The second write command wCMD2 may correspond to a second logical address LPN2. In some example embodiments, the second logical address LPN2 may be included in the first logical address range (e.g., Figure 3 LAR1).

[0109] In operation S140, the storage controller 110 may determine whether it is a hazard situation. For example, when it is determined that a hazard can be caused by the second write command wCMD2 (the "yes" in operation S140), the storage controller 110 may perform operation S150. When it is determined that a hazard cannot be caused by the second write command wCMD2 (the "no" in operation S140), the storage controller 110 may perform operation S160.

[0110] In some example embodiments, when the logical address LPN1 corresponding to the first write command wCMD1 and the logical address LPN2 corresponding to the second write command wCMD2 are included in the same logical address range LAR1 and the second write command wCMD2 is received before the completion of the invalidation of the first mapping, the storage controller 110 may determine that a hazard can be caused by the second write command wCMD2. In other words, in some example embodiments, the storage controller 110 may determine that this is a hazard situation.

[0111] In some example embodiments, when it is indicated that the trim bit corresponding to the second logical address LPN2 is in an active state and information included with the second logical address LPN2 in the first logical address range LAR1 exists in the hazard table (e.g., Figure 1 the HT of), the storage controller 110 may determine that a hazard can be caused by the second write command wCMD2. In other words, in some example embodiments, the storage controller 110 may determine that this is a hazard situation.

[0112] In other words, in some example embodiments, a hazard situation may refer to a situation where a write command corresponding to a logical address of an active trim bit is received before the completion of the invalidation of the mapping of the logical address corresponding to the active trim bit.

[0113] In operation S150, the storage controller 110 may skip the second mapping invalidation corresponding to the second write command wCMD2. The storage controller 110 may determine that a hazard can be caused by the second write command wCMD2. In some example embodiments, the storage controller 110 may not perform the second mapping invalidation corresponding to the second write command wCMD2 associated with all the logical addresses LPN1 to LPN4 included in the first logical address range LAR1.

[0114] In operation S160, the storage controller 110 may perform the second mapping invalidation in response to the second write command wCMD2. For example, when the trim bit is in a deactivated state when the second write command wCMD2 is received, the storage controller 110 may perform the mapping invalidation for the second logical address LPN2.

[0115] In operation S170, the storage controller 110 may perform a mapping update for the second logical address LPN2. The storage controller 110 may map a new physical address to the second logical address LPN2. In some example embodiments, after receiving mapping invalidation based on the first write command wCMD1, the storage controller 110 may perform a mapping update for the second logical address LPN2.

[0116] As described above, according to some example embodiments, when a hazard can be caused by a write command (e.g., wCMD2), the storage controller 110 may skip mapping invalidation based on the write command (e.g., wCMD2). Thus, according to some example embodiments, duplicate and execution of mapping invalidation can be prevented.

[0117] Figure 7 is a schematic diagram describing the operation of a Figure 1 storage controller according to some example embodiments. Reference will be made to Figures 1 to 6 for a description of Figure 7 . Referring to Figure 7 , at the 0th time point t0, the storage controller 110 may receive a first write command wCMD1 corresponding to a first logical address LPN1 included in a first logical address range LAR1, and the first logical address range LAR1 corresponds to an activated trim bit. As described with reference to Figure 5A and 5B , the storage controller 110 may perform a first process P1 during the time period from t0 to t6 in response to the first write command wCMD1.

[0118] For example, during the time period from t0 to t1, the storage controller 110 may check the trim bitmap TBMP. In addition, the storage controller 110 may check whether a hazard based on the first write command wCMD1 can be caused. For example, when the first write command wCMD1 is received, the mapping invalidation of the first logical address range LAR1 may not be in progress. In some example embodiments, the storage controller 110 may determine that a hazard based on the first write command wCMD1 cannot be caused.

[0119] Thus, during the time period from t1 to t5, the storage controller 110 may perform a first mapping invalidation for the logical addresses LPN1 to LPN4 included in the first logical address range LAR1. Thereafter, during the time period from t5 to t6, the storage controller 110 may perform a mapping update for the first logical address LPN1.

[0120] In some example embodiments, at a first time point t1, the storage controller 110 may receive a second write command wCMD2 corresponding to a second logical page number LPN2. The first logical page number LPN1 and the second logical page number LPN2 may be included in a first logical address range LAR1. For example, the first mapping invalidation may not be completed at the first time point t1. In response to the second write command wCMD2, the storage controller 110 may perform a second process P2 during a time period from t1 to t7.

[0121] During a time period from t1 to t2, the storage controller 110 may check the trim bitmap TBMP and may check whether an adventure based on the second write command wCMD2 can be caused. During the time period from t1 to t2, the trim bit corresponding to the second logical page number LPN2 may be in an active state. In addition, the first mapping invalidation may not be completed. In some example embodiments, the storage controller 110 may determine that an adventure based on the second write command wCMD2 can be caused.

[0122] Thus, in some example embodiments, different from the case of Figure 5A and Figure 5B , the storage controller 110 may skip the second mapping invalidation based on the second write command wCMD2. The storage controller 110 may wait until the mapping update of the first logical page number LPN1 is completed. After the mapping update of the first logical page number LPN1 is completed, the storage controller 110 may perform only the mapping update of the second logical page number LPN2. According to some example embodiments, the mapping invalidation of the logical page numbers LPN1 to LPN4 may not be repeated and executed. Thus, the performance of the storage controller 110 may be improved.

[0123] Figure 8 is a flowchart illustrating the operation of a storage controller according to some example embodiments. Reference will be made to Figure 1 to describe Figures 1 to 4B , Figure 6 and Figure 7 to describe Figure 8 . Referring to Figure 8 , in operation S1100, the storage controller 110 may receive a first write command wCMD1 from the host 11 and may manage the hazard table HT.

[0124] For example, the first write command wCMD1 may correspond to a first logical page number LPN1 included in the first logical address range LAR1. In addition, the trim bit corresponding to the first logical address range LAR1 may be in an active state. In some example embodiments, the storage controller 110 may update the hazard table HT. For example, the storage controller 110 may store information about the first logical page number LPN1 in the hazard table HT.

[0125] In operation S1200, the storage controller 110 may initiate a first mapping invalidation in response to a first write command wCMD1. The storage controller 110 may initiate a first mapping invalidation of a first logical address range LAR1. The first mapping invalidation may include invalidating the mapping of logical addresses LPN1 to LPN4.

[0126] In operation S1300, the storage controller 110 may receive a second write command wCMD2 and may manage a hazard table HT. For example, the second write command wCMD2 may correspond to a second logical address LPN2 included in the first logical address range (e.g., Figure 3 of LAR1). In some example embodiments, the storage controller 110 may store information about the second logical address LPN2 in the hazard table HT.

[0127] In some example embodiments, the storage controller 110 may check if information about the second logical address LPN2 exists in the hazard table HT. For example, the storage controller 110 may recognize that the running of a second mapping invalidation based on the second write command wCMD2 is not complete.

[0128] In operation S1400, the storage controller 110 may determine whether a trim bit is in an active state. For example, the storage controller 110 may determine whether a trim bit corresponding to the logical address associated with the second write command wCMD2 is in an active state. When the trim bit is not in an active state (''No'' in operation S1400), the storage controller 110 may perform operation S1500. When the trim bit is in an active state (''Yes'' in operation S1400), the storage controller 110 may perform operation S1600.

[0129] In operation S1500, the storage controller 110 may perform only a second mapping invalidation corresponding to the second write command wCMD2. For example, similar to Figure 4B the example, the second write command wCMD2 may correspond to a fifth logical address LPN5. Also, the trim bit corresponding to the fifth logical address LPN5 may be in a deactivated state. In some example embodiments, the storage controller 110 may perform a second mapping invalidation only for the fifth logical address LPN5.

[0130] In operation S1600, the storage controller 110 may determine whether it is a hazard situation. For example, the storage controller 110 may determine that the hazard can be caused by the second write command wCMD2. When it is determined that the hazard cannot be caused by the second write command wCMD2 ( "No" in operation S1600), the storage controller 110 may perform operation S1700. When it is determined that the hazard can be caused by the second write command wCMD2 ( "Yes" in operation 1600), the storage controller 110 may perform operation S1800.

[0131] In some example embodiments, a hazard situation may refer to a situation where a write command corresponding to the logical address of the activated trim bit is received before the mapping invalidation corresponding to the logical address of the activated trim bit is completed.

[0132] In some example embodiments, information about a logical address (e.g., the first logical address LPN1) included in the same logical address range (e.g., LAR1) as the logical address (e.g., LPN2) corresponding to the second write command wCMD2 may exist in the hazard table HT. In some example embodiments, the storage controller 110 may check that the first mapping invalidation associated with the logical address (e.g., LPN2) corresponding to the second write command wCMD2 is not completed. Therefore, the storage controller 110 may determine that the hazard can be caused by the second write command wCMD2.

[0133] In some example embodiments, information about a logical address (e.g., the sixth logical address LPN6) included in the same logical address range (e.g., LAR2) as the logical address (e.g., LPN5) corresponding to the second write command wCMD2 may not exist in the hazard table HT. In some example embodiments, the storage controller 110 may check that the first mapping invalidation associated with the logical address (e.g., LPN5) corresponding to the second write command wCMD2 is not in progress. Therefore, the storage controller 110 may determine that the hazard cannot be caused by the second write command wCMD2.

[0134] In operation S1700, the storage controller 110 may perform a second mapping invalidation for a logical address range corresponding to the trim bit. For example, the second write command wCMD2 may correspond to the fifth logical address LPN5. In addition, the trim bit corresponding to the fifth logical address LPN5 may be in an active state. In some example embodiments, when the second write command wCMD2 is received, information about the logical addresses (e.g., the sixth logical address LPN6) included in the same logical address range LAR2 as the fifth logical address LPN5 may not be present in the hazard table HT. In some example embodiments, for example, the storage controller 110 may determine that there is no hazard condition, and then may perform a second mapping invalidation for a second logical address range LAR2 corresponding to the active trim bit.

[0135] In operation S1800, the storage controller 110 may skip the second mapping invalidation corresponding to the second write command wCMD2. For example, the second write command wCMD2 may correspond to the second logical address LPN2. In addition, the trim bit corresponding to the second logical address LPN2 may be in an active state. In some example embodiments, when the second write command wCMD2 is received, information about the logical addresses (e.g., the first logical address LPN1) included in the same logical address range LAR1 as the second logical address LPN2 may be present in the hazard table HT. In some example embodiments, for example, the storage controller 110 may determine that a hazard can be caused by the second write command wCMD2. Therefore, the storage controller 110 may skip the second mapping invalidation based on the second write command wCMD2.

[0136] In operation S1900, the storage controller 110 may complete the first mapping invalidation. In addition, the storage controller 110 may perform a first mapping update for the first logical address LPN1 corresponding to the first write command wCMD1. In some example embodiments, after the storage controller 110 completes the first mapping update, the storage controller 110 may delete the information about the logical address (e.g., LPN1) corresponding to the first write command wCMD1 from the hazard table HT.

[0137] In operation S2000, the storage controller 110 may perform a second mapping update for the logical address (e.g., LPN2) corresponding to the second write command wCMD2. In some example embodiments, after the storage controller 110 completes the second mapping update, the storage controller 110 may delete the information about the logical address (e.g., LPN2) corresponding to the second write command wCMD2 from the hazard table HT.

[0138] For example, Figure 8 operation S1100 may correspond to Figure 6Operation S110; Figure 8 Operation S1200 can correspond to Figure 6 Operation S120; Figure 8 Operation S1300 can correspond to Figure 6 Operation S130; Figure 8 Operation S1600 can correspond to Figure 6 Operation S140; Figure 8 Operation S1800 can correspond to Figure 6 Operation S150; Figure 8 Operation S1700 can correspond to Figure 6 Operation S160; and, Figure 8 Operation S2000 can correspond to Figure 6 Operation S170.

[0139] Figure 9A and Figure 9B are schematic diagrams depicting examples of operations of the storage controller 110 according to some example embodiments. Reference will be made to Figure 1 to describe Figures 1 to 8 and Figure 9A and Figure 9B . Reference will be made to Figure 9A and Figure 9B . Before performing the first operation ①, the trim bits corresponding to the first logical address range LAR1 can be in a state activated by a trim command from the host 11. In some example embodiments, the first logical address range LAR1 can include the first logical address LPN1 to the fourth logical address LPN4.

[0140] For example, the first logical address LPN1 can correspond to the first physical address PPN1, the second logical address LPN2 can correspond to the second physical address PPN2, the third logical address LPN3 can correspond to the third physical address PPN3, and the fourth logical address LPN4 can correspond to the fourth physical address PPN4.

[0141] In the first operation ①, the storage controller 110 can receive the first write command wCMD1. After the storage controller 110 activates the trim bits and before the storage controller 110 enters the idle time, the storage controller 110 can receive the first write command wCMD1. The first write command wCMD1 can correspond to the first logical address LPN1. When the first write command wCMD1 is received, the hazard table HT may not include information about any logical address.

[0142] Therefore, in the second operation ②, the storage controller 110 can update the hazard table HT. The storage controller 110 can store information about the first logical address LPN1 corresponding to the first write command wCMD1 in the hazard table HT.

[0143] For example, the storage controller 110 may perform a second operation ② and then may check the trim bitmap TBMP. The storage controller 110 may initiate invalidation of the first mapping of the first logical address range LAR1 based on the trim bit corresponding to the first logical address LPN1 being in an active state.

[0144] After that, in a third operation ③, the storage controller 110 may receive a second write command wCMD2. The storage controller 110 may receive the second write command wCMD2 before completing the invalidation of the first mapping based on the first write command wCMD1. For example, the storage controller 110 may receive the second write command wCMD2 after receiving the first write command wCMD1 and before completing the invalidation of the first mapping.

[0145] In a fourth operation ④, the storage controller 110 may update the hazard table HT. The storage controller 110 may store information about the second logical address LPN2 corresponding to the second write command wCMD2 in the hazard table HT.

[0146] In a fifth operation ⑤, the storage controller 110 may skip the running of the mapping invalidation based on the second write command wCMD2. The storage controller 110 may determine a hazard that can be caused by the second write command wCMD2 based on the trim bitmap TBMP and the hazard table HT, and then may skip the running of the second mapping invalidation.

[0147] For example, when the second write command wCMD2 is received, the trim bit corresponding to the second logical address LPN2 may be in an active state. In addition, the hazard table HT may include information about the first logical address LPN1 included in the first logical address range LAR1 and the second logical address LPN2. In some example embodiments, the storage controller 110 may identify that the invalidation of the first mapping based on the first write command wCMD1 is not completed by checking the trim bitmap TBMP and the hazard table HT. Therefore, the storage controller 110 may determine a hazard that can be caused by the second write command wCMD2, and the storage controller 110 may skip the second mapping invalidation.

[0148] For example, the storage controller 110 may receive a first write command wCMD1 corresponding to the first logical physical address LPN1 of the activated trim bit (in the first operation ①). After the storage controller 110 receives the first write command wCMD1, the storage controller 110 may receive a second write command wCMD2 for the second logical physical address LPN2 before completing the first mapping invalidation (in the third operation ③). In some example embodiments, the storage controller 110 may determine that an adventure can be caused based on the second write command wCMD2 and may skip the second mapping invalidation (in the fifth operation ⑤).

[0149] In the sixth operation ⑥, the storage controller 110 may complete the running of the first mapping invalidation. Accordingly, the mapping relationships of the logical physical addresses LPN1 to LPN4 included in the first logical physical address range LAR1 can be released. This may mean that the data corresponding to the first physical addresses PPN1 to the fourth physical addresses PPN4 are invalid data.

[0150] Reference Figure 9B , in the seventh operation ⑦, the storage controller 110 may perform a first mapping update. For example, the storage controller 110 may map the first logical physical address LPN1 to the fifth physical address PPN5. For example, the fifth physical address PPN5 may be the address storing the first write data corresponding to the first write command wCMD1.

[0151] In the eighth operation ⑧, the storage controller 110 may update the hazard table HT. For example, after the storage controller 110 completes the first mapping update, the storage controller 110 may delete the information corresponding to the first logical physical address LPN1 from the hazard table HT.

[0152] In the ninth operation ⑨, the storage controller 110 may perform a second mapping update. The storage controller 110 may map the second logical physical address LPN2 to the sixth physical address PPN6. For example, the sixth physical address PPN6 may be the address storing the first write data corresponding to the second write command wCMD2.

[0153] After that, in the tenth operation ⑩, the storage controller 110 may update the hazard table HT. For example, after the storage controller 110 completes the first mapping update, the storage controller 110 may delete the information about the second logical physical address LPN2 from the hazard table HT.

[0154] In some example embodiments, related to Figure 9BUnlike the example shown, the storage controller 110 may receive a third write command during the execution of the second mapping update (i.e., during the running of the ninth operation). The third write command may correspond to the second logical address LPN2. In some example embodiments, the storage controller 110 may check whether information about the second logical address LPN2 exists in the hazard table HT. Thus, until the running of the second mapping update based on the second write command wCMD2 is completed (i.e., until the tenth operation ⑩ is completed), the storage controller 110 may wait without processing the third write command.

[0155] Figure 10 is a schematic diagram describing Figure 8 operation S1100 according to some example embodiments. Reference will be made to Figures 1 to 8 describe Figure 10 . Referring to Figure 10 , in operation S1110, the storage controller 110 may receive a first write command wCMD1.

[0156] In operation S1120, the storage controller 110 may check the logical address corresponding to the first write command wCMD1 (e.g., the first logical address LPN1).

[0157] In operation S1130, the storage controller 110 may store information about the logical address corresponding to the first write command wCMD1 (e.g., the first logical address LPN1) in the hazard table HT.

[0158] Based on Figure 8 operation S1100 is described Figure 10 , but the example embodiments are not limited thereto. For example, even when the storage controller 110 receives a second write command wCMD2 in Figure 8 operation S1300, the storage controller 110 may manage the hazard table HT in the same manner as Figure 10 shown. For example, after the storage controller 110 receives the second write command wCMD2, the storage controller 110 may store information about the logical address corresponding to the second write command wCMD2 (e.g., the second logical address LPN2) in the hazard table HT.

[0159] As described above, according to some example embodiments, based on the hazard table HT, the storage controller 110 may determine whether there is a probability of a hazard occurring. For example, when the storage controller 110 receives a write command, the storage controller 110 may determine whether there is a probability of a hazard occurring based on whether information about logical addresses belonging to the same logical address range as the logical address corresponding to the write command exists in the hazard table HT. For example, based on the hazard table HT, the storage controller 110 may check whether the mapping invalidation based on past write commands is completed.

[0160] Figure 11 is a block diagram depicting the operation of a mapping data manager according to some example embodiments. Reference will be made to Figure 1 for the description Figures 1 to 10 thereof. Referring to Figure 11 , Figure 11 the mapping data manager 114a may include a hazard detection unit 114a_1 and a mapping data processing unit 114a_2.

[0161] The hazard detection unit 114a_1 may receive a write command wCMD from the host 11. The hazard detection unit 114a_1 may generate a mapping data update request signal MUR based on the write command wCMD. The hazard detection unit 114a_1 may send, provide, or transmit the mapping data update request signal MUR to the mapping data processing unit 114a_2. The mapping data update request signal MUR may include hazard detection information. The hazard detection information may mean information regarding whether a hazard can be caused based on the write command wCMD. The hazard detection unit 114a_1 may generate the hazard detection information by referring to a hazard table HT. The hazard detection unit 114a_1 may manage the hazard table HT.

[0162] In some example embodiments, the hazard detection unit 114a_1 may receive a write command wCMD corresponding to a first logical address LPN1. The hazard detection unit 114a_1 may check the hazard table HT. The hazard table HT may not include information regarding the first logical address LPN1. In some example embodiments, the hazard detection unit 114a_1 may generate hazard detection information including information indicating that a hazard cannot be caused based on the write command wCMD. In some example embodiments, the hazard detection unit 114a_1 may send, provide, or transmit the mapping data update request signal MUR including the hazard detection information to the mapping data processing unit 114a_2. In some example embodiments, the hazard detection unit 114a_1 may store information regarding a first logical address range LAR1 including the first logical address LPN1 in the hazard table HT.

[0163] In some example embodiments, the hazard detection unit 114a_1 may receive a write command wCMD corresponding to a second logical page number LPN2. The hazard detection unit 114a_1 may check a hazard table HT. The hazard table HT may include information about at least one of logical page numbers LPN1 to LPN4 in a first logical address range LAR1 including a first logical page number LPN1. In some example embodiments, the hazard detection unit 114a_1 may check that the mapping invalidation of the first logical address range LAR1 is not completed, and may generate hazard detection information including information indicating that a hazard can be caused based on the write command wCMD. In some example embodiments, the hazard detection unit 114a_1 may send, provide, or transmit a mapping data update request signal MUR including the hazard detection information to the mapping data processing unit 114a_2.

[0164] The mapping data processing unit 114a_2 may receive the mapping data update request signal MUR. The mapping data processing unit 114a_2 may perform mapping invalidation and mapping update based on the mapping data update request signal MUR. For example, the mapping data processing unit 114a_2 may perform mapping invalidation and mapping update by referring to a mapping table MT, physical address information PBI, and a trim bitmap TBMP stored in the volatile memory device 130 (refer to Figure 2 ).

[0165] The mapping data processing unit 114a_2 may include a first processing unit PU1 to a sixth processing unit PU6. The first processing unit PU1 may check whether a trim bit is in an active state and whether the write command wCMD can cause a hazard. Each of the second processing unit PU2 to the fifth processing unit PU5 may perform mapping invalidation for a logical address range including a logical page number corresponding to the write command wCMD. The sixth processing unit PU6 may perform mapping update for a logical page number corresponding to the write command wCMD. In some example embodiments, at least a part of the hazard detection unit 114a_1, the mapping data processing unit 114a_2, and the first processing unit PU1 to the sixth processing unit PU6 may include or be implemented as corresponding processing circuits, such as hardware (e.g., logic circuits) or a combination of hardware and software (e.g., a computer-based electronic system), such as a processor running instruction codes or program routines (e.g., a software program).

[0166] In some example embodiments, the first processing unit PU1 may check the trim bitmap TBMP in response to the mapping data update request signal MUR. For example, the write command wCMD may correspond to the first logical address LPN1. The first processing unit PU1 may check that the trim bit corresponding to the first logical address LPN1 is in an active state. The first processing unit PU1 may check the hazard detection information of the mapping data update request signal MUR. The hazard detection information may include information indicating that a hazard caused by the write command wCMD cannot occur. In some example embodiments, the first processing unit PU1 may determine that a hazard cannot be caused by the write command wCMD. Additionally, the first processing unit PU1 may send, provide, or transmit the first invalid signal IS1 to the second processing unit PU2.

[0167] In some example embodiments, the second processing unit PU2 may perform mapping invalidation for the second logical address LPN2 and may send, provide, or transmit the second invalid signal IS2 to the third processing unit PU3. In response to the second invalid signal IS2, the third processing unit PU3 may perform mapping invalidation for the third logical address LPN3 and may send, provide, or transmit the third invalid signal IS3 to the fourth processing unit PU4. In response to the third invalid signal IS3, the fourth processing unit PU4 may perform mapping invalidation for the fourth logical address LPN4 and may send, provide, or transmit the fourth invalid signal IS4 to the fifth processing unit PU5. In response to the fourth invalid signal IS4, the fifth processing unit PU5 may perform mapping invalidation for the first logical address LPN1 and may send, provide, or transmit the completion signal CS to the sixth processing unit PU6. The sixth processing unit PU6 may perform mapping update for the first logical address LPN1 in response to the completion signal CS.

[0168] For example, when the first processing unit PU1 sends, provides, or transmits the first invalid signal IS1, each of the second processing unit PU2 to the fifth processing unit PU5 may perform mapping invalidation, and the sixth processing unit PU6 may perform mapping update.

[0169] In some example embodiments, the first processing unit PU1 may check the trimming bitmap TBMP in response to a mapping data update request signal MUR. For example, a write command wCMD may correspond to a second logical address LPN2. The first processing unit PU1 may check that the trimming bit corresponding to the second logical address LPN2 is in an active state. The first processing unit PU1 may check the hazard detection information of the mapping data update request signal MUR. The hazard detection information may include information indicating that a hazard can be caused by the write command wCMD. Thus, the first processing unit PU1 may determine that a hazard can be caused by the write command wCMD. In some example embodiments, the first processing unit PU1 may not send, provide, or transmit a first invalidation signal IS1 to the second processing unit PU2, and may send, provide, or transmit a hazard signal HS to the sixth processing unit PU6. In some example embodiments, the sixth processing unit PU6 may perform a mapping update for the second logical address LPN2 in response to the hazard signal HS.

[0170] In other words, when the write command wCMD can cause a hazard, the first processing unit PU1 may send, provide, or transmit a hazard signal HS to the sixth processing unit PU6 without sending, providing, or transmitting a first invalidation signal IS1 to the second processing unit PU2. Thus, the mapping invalidation based on the write command wCMD can be skipped. This may mean that the mapping invalidation of the logical address is not repeated and executed.

[0171] According to some example embodiments, when a write command can cause a hazard, the memory controller may skip the mapping invalidation operation based on the write command. Thus, a memory controller configured to control a non-volatile memory device, an operation method thereof, and a memory device including the memory controller with improved performance can be provided.

[0172] Although the inventive concept has been described with reference to some example embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A method for operating a storage controller, the storage controller being configured to control a non-volatile memory device, the method comprising: Receiving a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, the first trim bit being in an active state when the first write command is received; In response to the first write command, performing first mapping invalidation for the first logical address range; Before the first mapping invalidation is completed, receiving a second write command from the host corresponding to a second logical address included in the first logical address range; Skipping second mapping invalidation corresponding to the second write command; And After the first mapping invalidation is completed, performing mapping update for the second logical address.

2. The method according to claim 1, wherein When the second write command is received, the first trim bit is in the active state.

3. The method according to claim 1, wherein, The active state of the first trim bit indicates that the first logical address range is a target of mapping invalidation.

4. The method according to claim 1, wherein The receiving of the first write command is performed after the first trim bit is activated and before the storage controller enters an idle time.

5. The method according to claim 2, further comprising: After the first mapping invalidation is completed, performing mapping update for the first logical address, wherein, after the mapping update for the first logical address is completed, the mapping update for the second logical address is performed.

6. The method according to claim 5, wherein, The storage controller comprises: A hazard table including information about logical addresses corresponding to write commands.

7. The method according to claim 6, further comprising: After the receiving of the first write command, Storing information corresponding to the first logical address in the hazard table.

8. The method according to claim 7, further comprising: After the receiving of the second write command, Based on the first trim bit being in the active state and the information corresponding to the first logical address existing in the hazard table, determining that a hazard can be caused by the second write command.

9. The method according to claim 6, further comprising: After the first mapping invalidation is completed and the mapping update for the first logical address is performed, Deleting information corresponding to the first logical address from the hazard table.

10. The method according to claim 2, wherein The storage controller is configured to process multiple pieces of data corresponding to the first logical address range as invalid data, the first logical address range corresponding to the first trim bit in the active state.

11. The method according to claim 2, wherein, The first logical address range includes the first logical address and the second logical address, and wherein, the method further comprises: When the second write command is received, determining that a hazard can be caused by the second write command based on the first mapping invalidation not being completed.

12. A storage device, comprising: A non-volatile memory device; And A storage controller configured to control the non-volatile memory device, The storage controller is configured to: Receive a first write command of a first logical address included in a first logical address range corresponding to a first trim bit from an external host. In response to the first write command, perform a first mapping invalidation for the first logical address range. Before the completion of the first mapping invalidation, receive a second write command corresponding to a second logical address included in the first logical address range from the host. Skip a second mapping invalidation corresponding to the second write command, and After the completion of the first mapping invalidation, perform a mapping update for the second logical address.

13. The storage device according to claim 12, wherein, When the first write command is received, the first trim bit is in an active state, and wherein when the second write command is received, the first trim bit is in the active state.

14. The storage device according to claim 13, wherein, The storage controller includes: A hazard table including information about logical addresses corresponding to write commands.

15. The storage device according to claim 14, wherein, After the first write command is received, the storage controller is further configured to: Store information corresponding to the first logical address in the hazard table.

16. The storage device according to claim 15, wherein, After the second write command is received, the storage controller is further configured to: Determine that a hazard can be caused by the second write command based on the first trim bit being in the active state and the information corresponding to the first logical address existing in the hazard table.

17. The storage device according to claim 12, wherein, The storage controller is further configured to: When performing the first mapping invalidation, receive a third write command of a third logical address included in a second logical address range corresponding to a second trim bit from the host; And When the second trim bit is in an active state when the third write command is received, In response to the third write command, perform a third mapping invalidation for the second logical address range.

18. The storage device according to claim 12, wherein, The storage controller is further configured to: When performing the first mapping invalidation, receive a third write command of a third logical address included in a second logical address range corresponding to a second trim bit from the host; And When the second trim bit is in a deactivated state when the third write command is received, In response to the third write command, perform a third mapping invalidation for the third logical address among the logical addresses included in the second logical address range.

19. The storage device according to claim 12, wherein, The storage controller is further configured to: After the completion of the first mapping invalidation, perform a mapping update for the first logical address; and After the completion of the mapping update for the first logical address, perform a mapping update for the second logical address.

20. An operation method of a storage controller, the storage controller being configured to communicate with a host and a non-volatile memory device, the method including: In response to a trim command from the host, activate a first trim bit corresponding to a first logical address range; Receive a first write command of a first logical address included in the first logical address range from the host; In response to the first write command, initiate a first mapping invalidation of the first logical address range. Before the completion of the invalidation of the first mapping, receive a second write command from the host corresponding to a second logical address included in the first logical address range; When the second write command is received, skip the second mapping invalidation corresponding to the second write command based on the first trim bit being in an active state and the invalidation of the first mapping not being completed; Complete the invalidation of the first mapping and perform a first mapping update for the first logical address; And After the completion of the first mapping update, perform a mapping update for the second logical address.

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