Heterogeneous multi-core system, data transmission method, chip, equipment and medium

Abstract

The invention provides a heterogeneous multi-core system, a data transmission method, a chip, equipment and a medium. The heterogeneous multi-core system comprises a plurality of core processors, a memory, an arbiter and a direct memory access module, a memory space corresponding to each core processor is distributed in the memory; wherein the core processor is used for transmitting generated data to the memory; the memory is connected with the plurality of core processors and is used for storing the received data of any core processor to the memory space corresponding to the core processor; and the arbiter is connected with the memory and is used for determining data to be output from the data stored in the memory according to a currently configured output strategy and transmitting the data to be output to the peripheral interface through the direct memory access module so as to output the data to be output. According to the scheme, communication resources among heterogeneous multiple cores do not need to be occupied, so that the overall performance of the system can be improved.

Description

Technical Field

[0001] This application relates to the field of embedded design, and particularly to a heterogeneous multi-core system, a data transmission method, a chip, a device, and a medium. Background Art

[0002] With the diversified development of chip application scenarios, a single homogeneous multi-core chip architecture can no longer meet the requirements. Therefore, technicians have begun to adopt the design of a heterogeneous multi-core system architecture in chips, integrating different types of core processors, and these different types of core processors can meet the requirements of different business subsystem functions and performances.

[0003] A heterogeneous multi-core system includes a main core and slave cores, and adopts an asymmetric architecture design. The main core and slave cores run different systems respectively, and generate data to be transmitted to a peripheral interface, so as to be able to achieve synchronous cooperation and efficient communication between different systems, and give play to the performance of the multi-core processor.

[0004] However, the data transmission in the existing heterogeneous multi-core system will occupy a large amount of resources for inter-core communication, and at the same time will also cause the main core to frequently respond to interrupts, occupy the resources of the main core, disrupt the normal operation of the main core program, and further disrupt the concurrent response ability of the entire heterogeneous multi-core system, reducing the overall performance of the system. Summary of the Invention

[0005] This application provides a heterogeneous multi-core system, a data transmission method, a chip, a device, and a medium, which do not need to occupy the communication resources between heterogeneous multi-cores, thereby improving the overall performance of the system.

[0006] On the one hand, this application provides a heterogeneous multi-core system, which includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory; wherein: the core processor is used to transmit the generated data to the memory; the memory is connected to the multiple core processors and is used to store the data received from any core processor into the memory space corresponding to the core processor; the arbiter is connected to the memory and is used to determine the data to be output from the data stored in the memory according to the currently configured output policy, and transmit the data to be output to the peripheral interface through the direct memory access module to output the data to be output.

[0007] In a possible implementation manner, an independent transmission channel is established between each core processor and the memory, and the transmission channel corresponding to the core processor is mapped to the memory space corresponding to the core processor in the memory; specifically, the core processor is used to transmit the generated data to the memory through the transmission channel corresponding to the core processor; specifically, the memory is used to store the data into the memory space mapped by the transmission channel in the memory according to the transmission channel where the received data is located.

[0008] In a possible implementation, the heterogeneous multi-core system further includes a data formatting module; each core processor is connected to the data formatting module through a corresponding transmission channel, and a transmission channel corresponding to each core processor is established between the data formatting module and the memory; the core processor is specifically configured to transmit the generated data to the data formatting module through the transmission channel corresponding to the core processor; the data formatting module is configured to convert the data received from the core processor into data in a predetermined format, add a timestamp, and transmit the data of the core processor with the timestamp added to the memory through the transmission channel corresponding to the core processor.

[0009] In a possible implementation, multiple core processors are connected to the memory through a shared transmission channel; the core processor is specifically configured to transmit the generated data to the memory through the shared transmission channel, and the data carries the identifier of the core processor; the memory is specifically configured to store the data in the memory space corresponding to the core processor according to the identifier of the core processor carried by the received data.

[0010] In a possible implementation, the arbiter is specifically configured to: equally arbitrate the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data, and sequentially transmit the data to be output to the peripheral interface through the direct memory access module according to the response priorities of the transmission channels determined by the arbitration.

[0011] In a possible implementation, the arbiter is specifically configured to: according to the currently configured output policy, regularly select the first preset number of data from the data currently stored in the memory in the order of storage time, and use the first preset number of data selected as the data to be output.

[0012] In a possible implementation, the arbiter is specifically configured to: according to the currently configured output policy, if it is detected that the memory space corresponding to any core processor in the memory is full, use the data in the memory space corresponding to the core processor as the data to be output.

[0013] In a possible implementation, the arbiter is further configured to: receive the output policy issued by the main core processor among the multiple core processors, configure the arbiter according to the output policy, and record the event status and running status of the arbiter.

[0014] In a possible implementation, the heterogeneous multi-core system further includes an interrupt module and a response module; the interrupt module is connected to the arbiter; and is configured to trigger an interrupt signal indicating the arrival of data in the transmission channels corresponding to each core processor, and send the interrupt signal to the corresponding core processor; the response module is connected to the arbiter; and is configured to control each core processor to perform corresponding data processing according to the interrupt signal.

[0015] In a possible implementation, the peripheral interface includes at least one of the following: universal asynchronous receiver / transmitter interface, universal serial bus interface, PCIE interface, CAN bus interface, Ethernet interface, and PCI interface.

[0016] On the other hand, the present application provides a data output method for a heterogeneous multi-core system. The heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory; the method includes: the core processor transmits the generated data to the memory; the memory stores the data received from any core processor in the memory space corresponding to that core processor; the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy, and transmits the data to be output to the peripheral interface through the direct memory access module to output the data to be output.

[0017] In yet another aspect, the present application provides a chip including the system as described above.

[0018] In yet another aspect, the present application provides an electronic device including: a processor, a memory communicatively connected to the processor, and the system as described above.

[0019] In yet another aspect, the present application provides a computer-readable storage medium storing computer-executable instructions, including the system as described above.

[0020] In the heterogeneous multi-core system, data transmission method, chip, device, and medium provided by the present application, the heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory; wherein: the core processor is configured to transmit the generated data to the memory; the memory is connected to the multiple core processors and is configured to store the data received from any core processor in the memory space corresponding to that core processor; the arbiter is connected to the memory and is configured to determine the data to be output from the data stored in the memory according to the currently configured output policy, and transmit the data to be output to the peripheral interface through the direct memory access module to output the data to be output. The solution of the present application sets an arbiter in the heterogeneous multi-core system. The core processor first transmits the generated data to the memory, and then the memory stores the data received from any core processor in the corresponding memory space. The arbiter determines the data to be output in the memory according to the configured output policy, and then transmits the data to be output to the peripheral interface through the direct memory access module, which can implement data processing and data output of the heterogeneous multi-core system, thereby not relying on inter-core communication, not occupying the communication resources between heterogeneous multi-cores, reducing the participation of core processors, and improving the concurrency ability and system performance of the overall tasks of the heterogeneous multi-core system. Description of the Drawings

[0021] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0022] Figure 1 It is a schematic diagram of data transmission in an existing heterogeneous multi-core system;

[0023] Figure 2 Exemplarily shown is a schematic structural diagram of a heterogeneous multi-core system provided in Embodiment 1 of this application;

[0024] Figure 3 Exemplarily shown is a schematic structural diagram of an arbiter provided in this example;

[0025] Figure 4 Exemplarily shown is a schematic flowchart of a data output method for a heterogeneous multi-core system provided in Embodiment 2 of this application;

[0026] Figure 5 Exemplarily shown is a schematic flowchart of a data output method for a heterogeneous multi-core system provided in Embodiment 3 of this application;

[0027] Figure 6 It is a schematic structural diagram of an electronic device provided in Embodiment 4 of this application.

[0028] Through the above accompanying drawings, specific embodiments of this application have been shown, and there will be a more detailed description hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. Detailed Description of Specific Embodiments

[0029] Exemplary embodiments will be described in detail here, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0030] As used in this application, the terms "comprising" and "having" are used to mean an open inclusion, and refer to the existence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", etc. are only used as labels or for distinction, and do not limit the order or quantity of their objects. In addition, the different elements and regions in the drawings are only schematically shown, and thus are not limited to the sizes or distances shown in the drawings. The technical solutions will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the drawings.

[0031] With the development of computer technology, the improvement of chip design level, and the requirements and enhancements of applications, the single homogeneous multi-core chip architecture can no longer meet the needs of chip design, and heterogeneous multi-core systems are increasingly widely applied to products. As an example, in practical applications, Figure 1 FIG. is a schematic diagram of data transmission in an existing heterogeneous multi-core system. In the existing heterogeneous multi-core system, for data transmission, a specified size of shared memory is allocated to each core processor in the shared memory. Each core processor writes its own data in the specified allocated shared memory. When a certain core processor fills up the corresponding shared memory space, the core processor notifies the main core through inter-core communication. The main core responds to the interrupt of the slave core, collects the data shared memory of the corresponding core processor, reads out the data, and then sends it to the specified peripheral interface.

[0032] However, in a heterogeneous multi-core system, the data output of the slave cores uses inter-core communication to communicate with the main core, which will heavily occupy the resources of inter-core communication. The main core frequently responds to inter-core communication interrupts, disrupting the normal operation of the main core program. At the same time, it also heavily occupies the resources of the main core, reducing the real-time performance of the entire system and affecting the concurrent response ability of the entire heterogeneous multi-core system. In addition, the output channel is generally default specified as a universal asynchronous receiver / transmitter interface. When the heterogeneous multi-core system runs with high concurrency and has high requirements for overall real-time performance, due to the physical characteristics of the universal asynchronous receiver / transmitter interface, the data transmission bandwidth of the universal asynchronous receiver / transmitter interface may not be able to meet the high-concurrency data output, thus dragging down the overall performance of the system.

[0033] The technical content provided by this application aims to solve the above-mentioned technical problems in the related art. In the embodiments of this application, a heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory; wherein: the core processors are used to transfer the generated data to the memory; the memory is connected to the multiple core processors and is used to store the data received from any one of the core processors into the memory space corresponding to that core processor; the arbiter is connected to the memory and is used to determine the data to be output from the data stored in the memory according to the currently configured output policy, and transfer the data to be output to the peripheral interface through the direct memory access module to output the data to be output. The solution of this application sets an arbiter in the heterogeneous multi-core system. The core processors first transfer the generated data to the memory, and then the memory stores the data received from any one of the core processors into the corresponding memory space. The arbiter determines the data to be output in the memory according to the configured output policy, and then transfers the data to be output to the peripheral interface through the direct memory access module, which can realize the data processing and data output of the heterogeneous multi-core system, thus not relying on the communication between heterogeneous cores, not occupying the communication resources between heterogeneous multi-cores, reducing the participation of core processors, and improving the concurrency ability and system performance of the overall tasks of the heterogeneous multi-core system.

[0034] Some aspects of the examples of this application relate to the above considerations. The following introduces the solution with some examples.

[0035] Embodiment 1

[0036] Figure 2 FIG. schematically shows the structure of the heterogeneous multi-core system provided by Embodiment 1 of this application, as Figure 2 shown, the system includes: multiple core processors 21, a memory 22, an arbiter 23, and a direct memory access module 24; memory spaces corresponding to each core processor 21 are allocated in the memory 22; wherein:

[0037] The core processor 21 is used to transfer the generated data to the memory 22;

[0038] The memory 22 is connected to the multiple core processors 21 and is used to store the data received from any one of the core processors 21 into the memory space corresponding to that core processor 21;

[0039] The arbiter 23 is connected to the memory 22 and is used to determine the data to be output from the data stored in the memory 22 according to the currently configured output policy, and transfer the data to be output to the peripheral interface 25 through the direct memory access module 24 to output the data to be output.

[0040] In practical applications, there are various ways to implement such a heterogeneous multi-core system. For example, it can be implemented through a computer program, such as an application software; or, it can also be implemented as a medium storing relevant computer programs, such as a USB flash drive, a cloud drive, etc.; or, it can also be implemented through an entity device integrated or installed with relevant computer programs, such as a chip, etc.

[0041] Specifically, the heterogeneous multi-core system includes multiple core processors. Among them, the core includes a main core and a slave core. Usually, technicians adopt an asymmetric architecture design, and the number and type of core processors are determined according to design requirements. In the heterogeneous multi-core system, multiple cores run different tasks relatively independently, and each core processor is isolated from each other and can run different operating systems or application programs. Among them, the main core runs the Linux system, and the slave core runs a bare-metal program or a real-time operating system. At the same time, the programs of all core processors run concurrently, and meanwhile, data transmission will occur in the system.

[0042] In this example, the heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module. Memory spaces corresponding to each core processor are allocated in the memory. Specifically, the core processors transmit the generated data to the memory, and the generated data includes but is not limited to the data generated during communication output, the data generated in real-time during communication, etc. Among them, the data includes real-time data and non-real-time data. Real-time data refers to the data that needs to be transmitted and responded to in a timely and rapid manner, such as image data, video data, audio data, etc.; non-real-time data refers to the data that does not need to be transmitted and responded to immediately and rapidly, such as the log information data generated during the operation of the system, etc. After the core processors transmit the generated data to the memory, correspondingly, the memory stores the data received from any core processor in the memory space corresponding to that core processor. In the memory, memory spaces corresponding to each core processor are allocated, and each core processor has its own storage area in the memory. Then, the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy. Among them, the output policy is pre-configured inside the arbiter, and the output policy determines the content of the data to be output from the memory. After determining the data to be output from the memory, the direct memory access module independently transmits the data to be output to the peripheral interface, and then outputs the data to be output.

[0043] In the above example, first, the kernel processor transfers the generated data to the memory. Correspondingly, the memory stores any data received from the kernel processor in the memory space corresponding to that kernel processor. Then, based on the currently configured output policy, the arbiter determines the data to be output from the data stored in the memory, and transfers the data to be output to the peripheral interface through the direct memory access module to output the data to be output. The solution of this application can implement data processing and data output of a heterogeneous multi-core system, thereby not relying on communication between heterogeneous cores, not occupying the communication resources between heterogeneous multi-cores, reducing the participation of the kernel processor, and improving the concurrency ability and system performance of the overall tasks of the heterogeneous multi-core system.

[0044] Based on the above example, an independent transmission channel 26 is established between each kernel processor and the memory. The transmission channel 26 corresponding to the kernel processor is mapped to the memory space corresponding to that kernel processor in the memory. The kernel processor is specifically configured to transfer the generated data to the memory through the transmission channel 26 corresponding to that kernel processor. The memory is specifically configured to store the data in the memory space mapped by the transmission channel 26 in the memory according to the transmission channel 26 where the received data is located.

[0045] Specifically, in this example, still as Figure 2 shown, an independent transmission channel is established between each kernel processor and the memory. The transmission channel corresponding to the kernel processor is mapped to the memory space corresponding to that kernel processor in the memory. That is to say, when the kernel processor transfers the generated data to the memory, the data is transferred through the independent transmission channel corresponding to that kernel processor. There is a respective transmission channel corresponding to each kernel processor between each kernel processor and the memory. In the above example, establishing respective independent transmission channels between the kernel processor and the memory can make the data transmissions not interfere with each other, improve the data transmission efficiency, and transmit more accurately.

[0046] Based on the above example, the heterogeneous multi-core system further includes a data formatting module. Each kernel processor is connected to the data formatting module through the corresponding transmission channel. A transmission channel corresponding to each kernel processor is established between the data formatting module and the memory. The kernel processor is specifically configured to transfer the generated data to the data formatting module through the transmission channel corresponding to that kernel processor. The data formatting module is configured to convert the data received from the kernel processor into data in a predetermined format and add a timestamp, and transfer the data of the kernel processor with the timestamp added to the memory through the transmission channel corresponding to the kernel processor.

[0047] Specifically, the heterogeneous multi-core system further includes a data formatting module. Each core processor is connected to the data formatting module through a corresponding transmission channel, and a transmission channel corresponding to each core processor is established between the data formatting module and the memory. That is to say, a data formatting module is provided on multiple transmission channels. One side of the data formatting module is connected to the first part of multiple transmission channels, and each transmission channel is connected to its respective core processor. The other side of the data formatting module is connected to the second part of the multiple transmission channels mentioned above, and the multiple transmission channels are connected to the memory. After the core processor generates data, the generated data is transmitted to the data formatting module through the transmission channel corresponding to the core processor. The data formatting module converts the data generated by the received core processor into data in a predetermined format, where the predetermined format is the format preset before data transmission. After the data generated by the core processor is transmitted to the data formatting module, the data formatting module formats the data according to the preset format and uses a timestamp generator to add time information to the header of each data. After the data generated by the core processor is converted into data in a predetermined format and a timestamp is added, the data is transmitted to the memory through their respective corresponding transmission channels.

[0048] In the above example, the heterogeneous multi-core system further includes a data formatting module. When transmitting data to the memory, it is necessary to first transmit the data generated by each core processor to the data formatting module through the transmission channel corresponding to the core processor. The data formatting module converts the data into a predetermined format and adds a timestamp, and then transmits the processed data to the memory. Adding a timestamp to the data by the data formatting module facilitates the subsequent arbiter to equally arbitrate the response priority of the transmission channel corresponding to each core processor according to the timestamp and complete the output of the data.

[0049] In another example, the core processor transmits the generated data to the memory, and the memory stores the data received from any core processor in the memory space corresponding to the core processor. The following system can also be adopted: multiple core processors are connected to the memory through a shared transmission channel; the core processor is specifically used to transmit the generated data to the memory through the shared transmission channel, and the data carries the identifier of the core processor; the memory is specifically used to store the data in the memory space corresponding to the core processor according to the identifier of the core processor carried by the received data.

[0050] Specifically, in this example, a shared transmission channel is established between multiple core processors and memory. After a core processor generates data, the generated data is transmitted to the memory through this shared channel. The data generated by the core processor will carry the identifier of the corresponding core processor. When the core processor transmits the generated data to the memory, the memory will store the data in the memory space corresponding to the core processor according to the identifier of the core processor carried by the received data. In the above example, when a shared transmission channel is established between multiple core processors and memory, and the core processor transmits data to the memory, the data can also be transmitted through the shared transmission channel. The transmitted data carries the identifier of the corresponding core processor, and the memory can store it in the corresponding memory space according to the identifier of the core processor carried by the received data. This transmission method can save resources and release system space.

[0051] Based on the foregoing example, the arbiter is specifically configured to equally arbitrate the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data, and sequentially transmit the data to be output to the peripheral interface through the direct memory access module according to the response priorities of the respective transmission channels determined by the arbitration.

[0052] Figure 3 FIG. shows a schematic structural diagram of the arbiter provided in this example. The arbiter 23 includes a control register module 231, a channel status register module 232, a hardware event module 233, a first-in first-out queue channel module 234, and a round-robin arbiter module 235. Among them, the round-robin arbiter module equally arbitrates the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data in the memory, automatically reduces the priority of the responded channel to the lowest priority, and then the round-robin arbiter module sequentially transmits the data to be output to the peripheral interface one by one through the direct memory access module according to the response priorities. The arbiter is connected to the transmission channels of each core processor to control the data output enable of each transmission pipeline, achieving data aggregation and orderly transmission. In one example, the peripheral interface includes at least one of the following: universal asynchronous receiver / transmitter interface, universal serial bus interface, PCIE interface, CAN bus interface, Ethernet interface, and PCI interface. Specifically, the direct memory access module transmits the output data to the universal asynchronous receiver / transmitter interface, universal serial bus interface, PCIE interface, CAN bus interface, Ethernet interface, and PCI interface to complete the output of the data. It should be noted that the peripheral interface includes but is not limited to the above interfaces, and other interfaces can also be used, which is not limited here as long as the same function is satisfied.

[0053] In the above example, when the direct memory access module transfers data to the peripheral interface, the arbiter equally arbitrates the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data, and transfers the data to be output one by one through the direct memory access module to the peripheral interface in the order of response priorities, so as to output the data in sequence without relying on inter-core communication and the resources of the main core.

[0054] In one example, the arbiter is specifically configured to: according to the currently configured output policy, regularly select the first preset number of data from the data currently stored in the memory in the order of storage time, and use the first preset number of data obtained as the data to be output.

[0055] Specifically, in this example, as Figure 3 shown, when the arbiter determines the data to be output in the memory, the first-in-first-out queue channel module in the arbiter caches the data with timestamps after formatting transferred from the memory, avoids the arrival of concurrent messages, and according to the currently configured output policy, where the output policy is preset before data transmission. The first-in-first-out queue channel module regularly selects the first preset number of data from the data currently stored in the memory in the first-in-first-out rule, outputs the data stored first first and the data stored later later, and uses the first preset number of data selected as the data to be output, where the preset number can be set manually and is not limited here, thereby improving the efficiency of data transmission.

[0056] In another example, the arbiter is specifically configured to, according to the currently configured output policy, if it detects that the memory space corresponding to any core processor in the memory is full, use the data in the memory space corresponding to that core processor as the data to be output. Specifically, when the arbiter determines the data to be output in the memory, the arbiter can also, according to the currently configured output policy, if it detects that the memory space corresponding to the core processor is full, use the data in the memory space corresponding to that core processor as the data to be output, so as to release the memory space and avoid data loss.

[0057] In one example, the arbiter is further configured to receive the output policy issued by the main core processor among multiple core processors, and configure the arbiter according to the output policy, as well as record the event status and running status of the arbiter. Specifically, in this example, the arbiter only depends on the initialization configuration of the main core processor and the system clock. As Figure 3As shown, the data output strategy is sent from the main core processor in multiple core processors to the control register module in the arbiter. After receiving the data output strategy, the control register module configures the hardware event module in the arbiter. At the same time, the channel status register module in the arbiter records the time status and running status during the operation of the arbiter, facilitating timely error detection and correction in case of subsequent system problems.

[0058] Based on any of the foregoing examples, the heterogeneous multi-core system further includes an interrupt module and a response module; the interrupt module is connected to the arbiter; and is used to trigger an interrupt signal for the arrival of data in the transmission channel corresponding to each core processor and send the interrupt signal to the corresponding core processor; the response module is connected to the arbiter; and is used to control each core processor to perform corresponding data processing according to the interrupt signal.

[0059] Specifically, in this example, the heterogeneous multi-core system further includes an interrupt module and a response module. When data arrives in the transmission channel corresponding to each core processor, the interrupt module triggers an interrupt signal and sends the interrupt signal to the corresponding core processor. Then, the response module controls each core processor to perform corresponding data processing according to the interrupt signal triggered by the interrupt module, making the data transmission process of the entire system stable and orderly.

[0060] In the heterogeneous multi-core system provided in this embodiment, the heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory; wherein: the core processors transmit the generated data to the memory; the memory is connected to multiple core processors and stores the data received from any core processor in the memory space corresponding to that core processor; the arbiter is connected to the memory, determines the data to be output from the data stored in the memory according to the currently configured output strategy, and transmits the data to be output to the peripheral interface through the direct memory access module to output the data to be output. In the solution of this application, an arbiter is set in the heterogeneous multi-core system. The core processors first transmit the generated data to the memory, and then the memory stores the data received from any core processor in the corresponding memory space. The arbiter determines the data to be output in the memory according to the configured output strategy, and then transmits the data to be output to the peripheral interface through the direct memory access module, which can realize data processing and data output in the heterogeneous multi-core system, thus not relying on communication between heterogeneous cores, not occupying communication resources between heterogeneous multi-cores, reducing the participation of core processors, and improving the concurrency ability and system performance of the overall tasks in the heterogeneous multi-core system.

[0061] Embodiment 2

[0062] Figure 4The flowchart of the data output method for the heterogeneous multi-core system provided in the second embodiment of the present application is exemplarily shown. The execution subject of this example can be a heterogeneous multi-core system, which includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory, as Figure 4 shown, the method includes:

[0063] Step 101, the core processor transmits the generated data to the memory;

[0064] Step 102, the memory stores the data received from any core processor in the memory space corresponding to this core processor;

[0065] Step 103, the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy, and transmits the data to be output to the peripheral interface through the direct memory access module to output the data to be output.

[0066] In practical applications, the execution subject of this method can be a heterogeneous multi-core system, and there are various implementation methods. For example, it can be implemented through a computer program, such as an application software, etc.; or, it can also be implemented as a medium storing relevant computer programs, such as a USB flash drive, a cloud disk, etc.; or, it can also be implemented through an entity device integrated or installed with relevant computer programs, such as a chip, etc.

[0067] Specifically, the heterogeneous multi-core system includes multiple core processors, where the core includes a main core and slave cores. Usually, technicians adopt an asymmetric architecture design, and the number and type of core processors are determined according to design requirements. In the heterogeneous multi-core system, multiple cores run different tasks relatively independently, and each core processor is isolated from each other and can run different operating systems or application programs. For example, each core processor runs one of a firmware system, a bare-metal program, a real-time operating system, and Linux separately. Among them, the main core runs the Linux system, and the slave core runs the bare-metal program or the real-time operating system. At the same time, the programs of all core processors run concurrently, and at the same time, data transmission will occur in the system.

[0068] The data output method in this example is applied to as Figure 2The heterogeneous multi-core system shown includes multiple core processors, a memory, an arbiter, and a direct memory access module. Memory spaces corresponding to each core processor are allocated in the memory. Specifically, the core processors transmit the generated data to the memory. The generated data includes, but is not limited to, data generated during communication output, data generated in real time during communication, etc. Among them, the data includes real-time data and non-real-time data. Real-time data refers to data that needs to be transmitted and responded to promptly and quickly, such as image data, video data, audio data, etc.; non-real-time data refers to data that does not require immediate and rapid transmission and response, such as log information data generated during system operation. After the core processors transmit the generated data to the memory, correspondingly, the memory stores the data received from any core processor in the memory space corresponding to that core processor. In the memory, memory spaces corresponding to each core processor are allocated. For example, there are memory space 1, memory space 2, and memory space 3 in the memory, corresponding to core processor 1, core processor 2, and core processor 3 respectively. Core processor 1 stores the generated data in the corresponding memory space 1, core processor 2 stores the generated data in the corresponding memory space 2, and core processor 3 stores the generated data in the corresponding memory space 3. Then, the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy. Among them, the output policy is pre-configured inside the arbiter, and the output policy determines the content of the data to be output from the memory. After determining the data to be output from the memory, the direct memory access module independently transmits the data to be output to the peripheral interface, and then outputs the data to be output.

[0069] In the data output method of the heterogeneous multi-core system provided in this embodiment, first, the core processors transmit the generated data to the memory; correspondingly, the memory stores the data received from any core processor in the memory space corresponding to that core processor; then, the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy, and transmits the data to be output to the peripheral interface through the direct memory access module to output the data to be output. The solution of this application can implement data processing and data output of the heterogeneous multi-core system, thereby not relying on communication between heterogeneous cores, not occupying the communication resources between heterogeneous multi-cores, reducing the participation of core processors, and improving the concurrency ability and system performance of the overall tasks of the heterogeneous multi-core system.

[0070] Embodiment III

[0071] Based on Embodiment II, Figure 5 FIG. shows a schematic flow chart of the data output method of the heterogeneous multi-core system provided in Embodiment III of this application. The core processors transmit the generated data to the memory, and the memory stores the data received from any core processor in the memory space corresponding to that core processor, including:

[0072] Step 201: The kernel processor transmits the generated data to the memory through the transmission channel corresponding to the kernel processor.

[0073] Step 202: The memory stores the data in the memory space mapped by the transmission channel in the memory according to the transmission channel where the received data is located.

[0074] Specifically, in this example, an independent transmission channel is established between each kernel processor and the memory. The transmission channel corresponding to the kernel processor is mapped to the memory space corresponding to the kernel processor in the memory. That is to say, when the kernel processor transmits the generated data to the memory, the data is transmitted through the independent transmission channel corresponding to the kernel processor. There is a respective transmission channel corresponding to each kernel processor between each kernel processor and the memory. Combining the foregoing example, a transmission channel 1 is established between kernel processor 1 and the memory, a transmission channel 2 is established between kernel processor 2 and the memory, and a transmission channel 3 is established between kernel processor 3 and the memory; Transmission channel 1 is mapped to memory space 1 in the memory, transmission channel 2 is mapped to memory space 2 in the memory, and transmission channel 3 is mapped to memory space 3 in the memory. The data generated by kernel processor 1 is first transmitted to the memory through memory channel 1, and then the memory stores the data transmitted by kernel processor 1 in memory space 1 according to the data received through memory channel 1. Similarly, the data generated by kernel processor 2 is first transmitted to the memory through memory channel 2, and then the memory stores the data transmitted by kernel processor 2 in memory space 2 according to the data received through memory channel 2; The data generated by kernel processor 3 is first transmitted to the memory through memory channel 3, and then the memory stores the data transmitted by kernel processor 3 in memory space 3 according to the data received through memory channel 3. In the above example, establishing respective independent transmission channels between the kernel processor and the memory can make the data transmission not interfere with each other, improve the data transmission efficiency, and transmit more accurately.

[0075] On the basis of the foregoing example, the kernel processor transmits the generated data to the memory through the transmission channel corresponding to the kernel processor, including: The kernel processor transmits the generated data to the data formatting module through the transmission channel corresponding to the kernel processor; The data formatting module converts the data of the kernel processor received into data in a predetermined format and adds a time stamp, and transmits the data of the kernel processor after adding the time stamp to the memory through the transmission channel corresponding to the kernel processor.

[0076] Specifically, the heterogeneous multi-core system further includes a data formatting module. Each core processor is connected to the data formatting module through a corresponding transmission channel, and a transmission channel corresponding to each core processor is established between the data formatting module and the memory. That is to say, a data formatting module is provided on multiple transmission channels. One side of the data formatting module is connected to the front part of multiple transmission channels, each transmission channel is connected to its respective core processor, the other side of the data formatting module is connected to the back part of the aforementioned multiple transmission channels, and multiple transmission channels are connected to the memory. After the core processor generates data, the generated data is transmitted to the data formatting module through the transmission channel corresponding to this core processor. The data formatting module converts the data generated by the received core processor into data in a predetermined format. The predetermined format is the format preset before data transmission. After the data generated by the core processor is transmitted to the data formatting module, the data formatting module formats the data according to the preset format and uses a timestamp generator to add time information to the head of each data. After the data generated by the core processor is converted into data in a predetermined format and a timestamp is added, the data is transmitted to the memory through their respective corresponding transmission channels.

[0077] In the above example, the heterogeneous multi-core system further includes a data formatting module. When transmitting data to the memory, it is necessary to first transmit the data generated by each core processor to the data formatting module through the transmission channel corresponding to this core processor. The data formatting module converts the data into a predetermined format and adds a timestamp, and then transmits the processed data to the memory. Adding a timestamp to the data by the data formatting module facilitates the subsequent arbiter to equally arbitrate the response priority of the transmission channel corresponding to each core processor according to the timestamp and complete the output of the data.

[0078] In another example, the core processor transmits the generated data to the memory, and the memory stores the data received from any core processor in the memory space corresponding to this core processor. It further includes: the core processor transmits the generated data to the memory through a shared transmission channel, and the data carries the identifier of the core processor; the memory stores the data in the memory space corresponding to this core processor according to the identifier of the core processor carried by the received data.

[0079] Specifically, in this example, a shared transmission channel is established between multiple core processors and the memory. After a core processor generates data, the generated data is transmitted to the memory through this shared channel. The data generated by the core processor will carry the identifier of the corresponding core processor. For example, the data generated by core processor 1 will carry the identifier of core processor 1, marked as 1; the data generated by core processor 2 will carry the identifier of core processor 2, marked as 2; the data generated by core processor 3 will carry the identifier of core processor 3, marked as 3. When the core processor transmits the generated data to the memory, the memory will store the data in the memory space corresponding to the core processor according to the identifier of the core processor carried by the received data. For example, in the memory, there is memory space 1 corresponding to core processor 1, memory space 2 corresponding to core processor 2, and memory space 3 corresponding to core processor 3. When the memory receives the data generated by the core processor and recognizes that the data carries the mark 1, it indicates that the data is generated by core processor 1, so the memory stores the data in memory space 1 corresponding to core processor 1; when the memory receives the data generated by the core processor and recognizes that the data carries the mark 2, it indicates that the data is generated by core processor 2, so the memory stores the data in memory space 2 corresponding to core processor 2; when the memory receives the data generated by the core processor and recognizes that the data carries the mark 3, it indicates that the data is generated by core processor 3, so the memory stores the data in memory space 3 corresponding to core processor 3.

[0080] In the above example, when a shared transmission channel is established between multiple core processors and the memory, and the core processor transmits data to the memory, the data can also be transmitted through the shared transmission channel. The transmitted data carries the identifier of the corresponding core processor, and the memory can store it in the corresponding memory space according to the identifier of the core processor carried by the received data. This transmission method can save resources and release system space.

[0081] Based on the foregoing example, the data to be output is transmitted to the peripheral interface through the direct memory access module, including: the arbiter equally arbitrates the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data, and sequentially transmits the data to be output to the peripheral interface through the direct memory access module according to the response priorities of the respective transmission channels determined by the arbitration.

[0082] Such as Figure 3As shown in the figure, the arbiter includes a control register module, a channel status register module, a hardware event module, a first-in-first-out queue channel module, and a round-robin arbiter module. Among them, the round-robin arbiter module equally arbitrates the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data in the memory, and automatically reduces the priority of the channels that have been responded to to the lowest priority. For example, in the system, there are transmission channels 1, 2, 3, and 4. The round-robin arbiter module equally arbitrates the response priorities of each transmission channel according to the timestamps carried by the data. The response order is transmission channel 1, transmission channel 2, transmission channel 3, transmission channel 4. Transmission channel 1 responds first, and then transmission channels 2, 3, and 4 respond in turn. After transmission channel 1 responds, it automatically becomes the lowest priority and is ranked behind transmission channel 4. The response order becomes transmission channel 2, transmission channel 3, transmission channel 4, transmission channel 1. Then, the round-robin arbiter module sequentially transfers the data to be output one by one to the peripheral interface through the direct memory access module according to the response priority. The arbiter connects the transmission channels of each core processor and controls the data output enable of each transmission pipeline to achieve data aggregation and orderly transmission. In one example, the peripheral interface includes at least one of the following: universal asynchronous receiver / transmitter interface, universal serial bus interface, PCIe interface, CAN bus interface, Ethernet interface, and PCI interface. Specifically, the direct memory access module transfers the output data to the universal asynchronous receiver / transmitter interface, universal serial bus interface, PCIe interface, CAN bus interface, Ethernet interface, and PCI interface to complete the data output. It should be noted that the peripheral interface includes but is not limited to the above interfaces, and other interfaces can also be used, which are not limited here as long as the same function is satisfied.

[0083] In the above example, when the direct memory access module transfers the data to the peripheral interface, the arbiter equally arbitrates the response priorities of the transmission channels corresponding to each core processor according to the timestamps carried by the data, and sequentially transfers the data to be output one by one to the peripheral interface through the direct memory access module according to the response priority, so as to output the data sequentially without relying on inter-core communication and the resources of the main core.

[0084] In one example, the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy, including: the arbiter regularly selects the first preset number of data from the data currently stored in the memory according to the currently configured output policy in the order of storage time, and uses the selected first preset number of data as the data to be output.

[0085] Specifically, in this example, as Figure 3As shown, when the arbiter determines the data to be output in the memory, the first-in-first-out (FIFO) queue channel module in the arbiter caches the timestamped data that has been formatted and transferred from the memory, avoiding the arrival of concurrent messages, and according to the currently configured output policy, where the output policy is preset before data transfer. The FIFO queue channel module regularly outputs the data stored earlier first and the data stored later later from the data currently stored in the memory according to the first-in-first-out rule, selects the first preset number of data in the order of storage time, and uses the selected first preset number of data as the data to be output, where the preset number can be set manually and is not limited here, thereby improving the efficiency of data transfer.

[0086] In another example, when the arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy, it further includes: if the arbiter detects that the memory space corresponding to any kernel processor in the memory is full according to the currently configured output policy, the data in the memory space corresponding to the kernel processor is used as the data to be output.

[0087] Specifically, when the arbiter determines the data to be output in the memory, the arbiter can also use the data in the memory space corresponding to the kernel processor as the data to be output according to the currently configured output policy if it detects that the memory space corresponding to the kernel processor is full, thereby releasing the memory space and avoiding data loss.

[0088] In one example, the method further includes: the arbiter receives the output policy issued by the master core processor among multiple kernel processors, configures the arbiter according to the output policy, and records the event status and running status of the arbiter. Specifically, in this example, the arbiter only depends on the initialization configuration of the master core processor and the system clock. As Figure 3 shown, the data output policy is issued by the master core processor among multiple kernel processors to the control register module in the arbiter. After receiving the data output policy, the control register module configures the hardware event module in the arbiter. At the same time, the channel status register module in the arbiter records the time status and running status during the operation of the arbiter, facilitating timely error detection and correction in case of subsequent system problems.

[0089] Based on any of the foregoing examples, the method further includes: the heterogeneous multi-core system further includes an interrupt module and a response module; the interrupt module triggers the interrupt signal for the arrival of data in the transmission channels corresponding to each kernel processor and sends the interrupt signal to the corresponding kernel processor; the response module controls each kernel processor to perform corresponding data processing according to the interrupt signal.

[0090] Specifically, in this example, the heterogeneous multi-core system further includes an interrupt module and a response module. When data arrives in the transmission channels corresponding to each core processor, the interrupt module triggers an interrupt signal and sends the interrupt signal to the corresponding core processor. Then, the response module controls each core processor to perform corresponding data processing according to the interrupt signal triggered by the interrupt module, so that the data transmission process of the entire system is stable and orderly.

[0091] In the data output method of the heterogeneous multi-core system provided in this embodiment, an independent transmission channel is established between each core processor and the memory. The data generated by the core processor is first formatted by the data formatting module, then a timestamp is added, and then the data is transmitted to the memory through the independent transmission channel. The arbiter equally arbitrates the formatted data with a timestamp and then outputs the data. The solution of this application can implement data processing and data output of the heterogeneous multi-core system, thereby not relying on inter-heterogeneous core communication, not occupying the communication resources between heterogeneous multi-cores, reducing the participation of core processors, and improving the concurrency ability and system performance of the overall tasks of the heterogeneous multi-core system.

[0092] Embodiment 4

[0093] Figure 6 is a schematic structural diagram of an electronic device provided in Embodiment 4 of this application. As Figure 6 shown, the electronic device includes:

[0094] A processor 291, and the electronic device further includes a memory 292; it may also include a communication interface 293 and a bus 294. Among them, the processor 291, the memory 292, and the communication interface 293 can complete mutual communication through the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can call the logical instructions in the memory 292 to execute the method in the above example.

[0095] In addition, when the logical instructions in the above-mentioned memory 292 are implemented in the form of a software functional unit and sold or used as an independent product, they can be stored in a computer-readable storage medium.

[0096] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, that is, implements the methods in the above method examples.

[0097] The memory 292 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created according to the use of the terminal device and the like. In addition, the memory 292 may include a high-speed random access memory and may also include a non-volatile memory.

[0098] An embodiment of the present application also provides a computer-readable storage medium. Computer-executable instructions are stored in the computer-readable storage medium and are used to implement the method in any of the embodiments when executed by a processor.

[0099] An embodiment of the present application also provides a chip. When a computer program is executed by a processor, the method in any of the embodiments is implemented.

[0100] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the claims.

[0101] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A heterogeneous multi-core system, characterized in that, The heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module; a memory space corresponding to each core processor is allocated in the memory; wherein: The core processor is used to transmit the generated data to the memory; The memory is connected to the multiple core processors and is used to store the data received from any core processor into the memory space corresponding to the core processor; The arbiter is connected to the memory and is used to determine the data to be output from the data stored in the memory according to the currently configured output policy, and transmit the data to be output to the peripheral interface through the direct memory access module to output the data to be output.

2. The system according to claim 1, wherein An independent transmission channel is established between each core processor and the memory, and the transmission channel corresponding to the core processor is mapped to the memory space corresponding to the core processor in the memory; The core processor is specifically used to transmit the generated data to the memory through the transmission channel corresponding to the core processor; The memory is specifically used to store the data into the memory space mapped by the transmission channel in the memory according to the transmission channel where the received data is located.

3. The system according to claim 2, wherein The heterogeneous multi-core system further includes a data formatting module; each core processor is connected to the data formatting module through a corresponding transmission channel, and a transmission channel corresponding to each core processor is established between the data formatting module and the memory; The core processor is specifically used to transmit the generated data to the data formatting module through the transmission channel corresponding to the core processor; The data formatting module is used to convert the data received from the core processor into data in a predetermined format and add a timestamp, and transmit the data of the core processor with the timestamp added to the memory through the transmission channel corresponding to the core processor.

4. The system according to claim 1, wherein The multiple core processors are connected to the memory through a shared transmission channel; The core processor is specifically used to transmit the generated data to the memory through the shared transmission channel, and the data carries the identifier of the core processor; The memory is specifically used to store the data into the memory space corresponding to the core processor according to the identifier of the core processor carried by the received data.

5. The system according to claim 3, wherein The arbiter is specifically used for: According to the timestamp carried by the data, equally arbitrate the response priorities of the transmission channels corresponding to each core processor, and sequentially transmit the data to be output to the peripheral interface through the direct memory access module according to the response priorities of the transmission channels determined by the arbitration.

6. The system according to any one of claims 1-5, characterized in that The arbiter is specifically used for: According to the currently configured output policy, regularly select the first preset number of data from the data currently stored in the memory in the order of storage time, and use the selected first preset number of data as the data to be output.

7. The system according to any one of claims 1-5, characterized in that, The arbiter is specifically used for: According to the currently configured output policy, if it is detected that the memory space corresponding to any core processor in the memory is full, the data in the memory space corresponding to the core processor is used as the data to be output.

8. The system according to any one of claims 1-5, characterized in that, The arbiter is further configured to: receive the output policy issued by the master core processor among the multiple core processors, configure the arbiter according to the output policy, and record the event status and operation status of the arbiter.

9. The system according to any one of claims 1-5, characterized in that, The heterogeneous multi-core system further includes an interrupt module and a response module; The interrupt module is connected to the arbiter; and is configured to trigger an interrupt signal indicating the arrival of data in the transmission channel corresponding to each core processor, and send the interrupt signal to the corresponding core processor. The response module is connected to the arbiter; and is configured to control each core processor to perform corresponding data processing according to the interrupt signal.

10. The system according to any one of claims 1-5, characterized in that, The peripheral interface includes at least one of the following: a universal asynchronous receiver / transmitter interface, a universal serial bus interface, a PCIE interface, a CAN bus interface, an Ethernet interface, and a PCI interface.

11. A data output method for a heterogeneous multi-core system, characterized in that The heterogeneous multi-core system includes multiple core processors, a memory, an arbiter, and a direct memory access module; memory spaces corresponding to each core processor are allocated in the memory; the method includes: The core processor transfers the generated data to the memory; The memory stores the data received from any core processor in the memory space corresponding to that core processor; The arbiter determines the data to be output from the data stored in the memory according to the currently configured output policy, and transfers the data to be output to the peripheral interface through the direct memory access module to output the data to be output.

12. A chip, characterized in that, including the system according to any one of claims 1-10.

13. An electronic device, characterized in that, including: a processor, a memory communicatively connected to the processor, and the system according to any one of claims 1-10.

14. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium, including the system according to any one of claims 1-10.

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