Computing unit and array structure in counterpoint common floating gate type Flash memory

Abstract

The invention discloses an alignment common floating gate type Flash memory computing unit and an array structure, and belongs to the field of integrated circuits. The alignment common floating gate type Flash memory internal calculation unit comprises a metal oxide semiconductor (MOS) type gate tube, two Flash type weight programming tubes and two Flash type weight storage tubes; the two Flash type weight programming tubes and the two Flash type weight storage tubes share a floating gate polycrystal layer and a control gate polycrystal layer respectively, and the MOS type gate tube and the two Flash type weight programming tubes are sequentially connected in series. The in-memory calculation array formed by the alignment common floating gate type Flash in-memory calculation unit is used for completing weight storage and multiply-accumulate operation of in-memory calculation. The alignment common floating gate type Flash memory computing unit and array obtained by the invention are compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, wide in weight configuration range, high in reliability and suitable for a memory and computing integrated architecture circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a parallel-bit common floating gate type Flash in-memory computing unit and an array structure. Background Art

[0002] With the popularization of mobile terminal devices, human beings' ability to obtain information has been greatly improved, and the demand for processor computing power for timely storage and rapid processing of massive information is increasing. The neural network model can simulate the neural connection structure of the human brain, bringing breakthrough progress to large-scale data processing tasks such as images, videos and audio. The model is composed of a large number of nodes interconnected by a mesh structure. The connection strength between each two nodes is expressed as the weighted proportion of the connection signal between the two nodes, that is, the weight, which corresponds to the memory in the human neural network. There are often a large number of matrix-vector multiplication operations in the neural network model, and in the traditional von Neumann computing architecture, a large amount of data must be transmitted back and forth between the processing unit and the memory unit, resulting in computing delays and memory access power consumption, that is, the "storage wall" problem, which is particularly obvious when the system performs repeated calculations on a large amount of data.

[0003] The integrated storage and computing (also known as: storage and computing fusion, in-memory computing, in-memory processing, etc.) architecture is a new computing architecture that can perform computing tasks in situ in the memory unit, thereby realizing the integration of storage and computing functions. Processors using the integrated storage and computing architecture can meet the needs of artificial intelligence applications for high computing power, low power consumption, and low latency. They can be applied to face recognition, voice recognition, smart homes, security monitoring, unmanned driving and other fields. It is one of the cutting-edge technology directions in the field of integrated circuits in the post-Moore era.

[0004] As a semiconductor storage device, Flash has a high degree of technological maturity and the function of electrically erasable storage of information. The stored information will not be lost when the power is off. It is a non-volatile memory that can realize the characteristics and functions of bionic synaptic devices and build an integrated storage and computing infrastructure that integrates storage and computing. However, building an integrated storage and computing cross array through Flash devices also requires solving problems such as high-reliability multi-weight configuration. Summary of the invention

[0005] The object of the present invention is to provide a parallel-bit common floating gate Flash memory computing unit and array structure to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a bit-shared floating gate Flash in-memory computing unit and array structure, including: MOS type gating tube, a first Flash type weight programming tube, a second Flash type weight programming tube and a first Flash type weight storage tube, a second Flash type weight storage tube; The first Flash-type weight programming tube and the first Flash-type weight storage tube share a floating gate polycrystalline layer and a control gate polycrystalline layer, and the second Flash-type weight programming tube and the second Flash-type weight storage tube share a floating gate polycrystalline layer and a control gate polycrystalline layer; The drain end of the MOS-type gating tube is connected to the control terminal bit line, the source end is connected to the drain end of the first Flash-type weight programming tube, the source end of the first Flash-type weight programming tube is connected to the drain end of the second Flash-type weight programming tube, and the source end of the second Flash-type weight programming tube is connected to the control terminal source line; The source end of the first Flash-type weight storage tube is connected to the first readout terminal source line, the drain end is commonly connected to the readout terminal bit line with the drain end of the second Flash-type weight storage tube, and the source end of the second Flash-type weight storage tube is connected to the second readout terminal source line; The gate end of the MOS-type gating tube is connected to the selection gate word line, the first Flash-type weight programming tube and the first Flash-type weight storage tube share a control gate connected to the first control gate word line, the second Flash-type weight programming tube and the second Flash-type weight storage tube share a control gate connected to the second control gate word line, and the selection gate word line, the first control gate word line, and the second control gate word line are independently controlled and different potentials are applied respectively; When the first Flash-type weight programming tube performs a programming operation, a voltage is applied to the selection gate word line to turn on the MOS-type gating tube, a super-control voltage is applied to the second control gate word line to turn on the second Flash-type weight programming tube, a voltage is applied to the control terminal bit line, and the floating gate polycrystalline layer of the first Flash-type weight programming tube is charged with charges by the band-to-band tunneling method at the drain end. At this time, the first Flash-type weight storage tube and the first Flash-type weight programming tube share the floating gate polycrystalline layer that has been charged with charges; When the second Flash-type weight programming tube performs a programming operation, a voltage is applied to the selection gate word line to turn on the MOS-type gating tube, a super-control voltage is applied to the first control gate word line to turn on the first Flash-type weight programming tube, a voltage is applied to the control terminal bit line, and the floating gate polycrystalline layer of the second Flash-type weight programming tube is charged with charges by the band-to-band tunneling method at the drain end. At this time, the second Flash-type weight storage tube and the second Flash-type weight programming tube share the floating gate polycrystalline layer that has been charged with charges.

[0007] In one embodiment, the second control gate word line override voltage for turning on the second Flash type weight programming tube needs to be greater than the maximum threshold voltage of the second Flash type weight programming tube. Regardless of whether the floating gate polycrystalline layer of the second Flash type weight programming tube is charged or not, the second Flash type weight programming tube remains turned on.

[0008] In one embodiment, the first control gate word line override voltage for turning on the first Flash type weight programming tube needs to be greater than the maximum threshold voltage of the first Flash type weight programming tube. Regardless of whether the floating gate polycrystalline layer of the first Flash type weight programming tube is charged or not, the first Flash type weight programming tube remains turned on.

[0009] In one embodiment, when the first Flash type weight programming tube and the second Flash type weight programming tube perform an erase operation, the charge on the floating gate polycrystalline layer is removed simultaneously by the source-side FN tunneling method or the full-channel uniform FN tunneling method. At this time, the first Flash type weight storage tube and the second Flash type weight storage tube share the floating gate polycrystalline layer with the removed charge with the first Flash type weight programming tube and the second Flash type weight programming tube respectively.

[0010] In one embodiment, when the first Flash type weight storage tube performs a read operation, a voltage is applied to the first control gate word line to turn on the first Flash type weight storage tube. Voltages are applied to the read bit line and the first read source line respectively, and a current is read from the first read source line to obtain the conductance state of the first Flash type weight storage tube, and this conductance state is the weight.

[0011] In one embodiment, when the second Flash type weight storage tube performs a read operation, a voltage is applied to the second control gate word line to turn on the second Flash type weight storage tube. Voltages are applied to the read bit line and the second read source line respectively, and a current is read from the second read source line to obtain the conductance state of the second Flash type weight storage tube, and this conductance state is the weight.

[0012] In one embodiment, the MOS type strobe tube is a p-channel MOS tube or an n-channel MOS tube, and the two Flash type weight programming tubes and the two Flash type weight storage tubes are p-channel Flash tubes or n-channel Flash tubes; the MOS type strobe tube, the two Flash type weight programming tubes, and the two Flash type weight storage tubes are all p-channel MOS tubes or all n-channel MOS tubes.

[0013] The present invention also provides an array structure based on the above-mentioned counter-aligned floating-gate type Flash in-memory computing unit. The counter-aligned floating-gate type Flash in-memory computing array structure includes n rows of counter-aligned floating-gate type Flash in-memory computing units and m columns of counter-aligned floating-gate type Flash in-memory computing units, where m and n are positive integers and the minimum value is 1; The gate terminal of the MOS type strobe tube in the i-th row is serially connected to the selection gate word line of the i-th row. The control gate shared by the first Flash type weight programming tube and the first Flash type weight storage tube in the i-th row is serially connected to the first control gate word line of the i-th row. The control gate shared by the second Flash type weight programming tube and the second Flash type weight storage tube in the i-th row is serially connected to the second control gate word line of the i-th row. The source terminal of the second Flash type weight programming tube in the i-th row is serially connected to the control terminal source line of the i-th row. The source terminal of the first Flash type weight storage tube in the i-th row is serially connected to the first readout terminal source line of the i-th row. The source terminal of the second Flash type weight storage tube in the i-th row is serially connected to the second readout terminal source line of the i-th row. The first readout terminal source line and the second readout terminal source line in the i-th row are output after passing through a difference circuit; The drain terminal of the MOS type strobe tube in the j-th column is serially connected to the control terminal bit line of the j-th column. The drain terminals of the first Flash type weight storage tube and the second Flash type weight storage tube in the j-th column are serially connected to the readout terminal bit line of the j-th column; where i is a positive integer not greater than m, and j is a positive integer not greater than n.

[0014] In one embodiment, the counter-aligned floating-gate type Flash in-memory computing array structure performs a multiply-accumulate operation OUT =ΣV ij *W ij The implementation methods include: (1) When W ij ≥0, W ij The weight value stored in the first Flash type weight storage tube of the i-th row and j-th column of the parallel common floating gate Flash memory calculation unit in the parallel common floating gate Flash memory calculation array is converted into the weight value stored in the first Flash type weight storage tube of the i-th row and j-th column of the parallel common floating gate Flash memory calculation unit, that is, the conductivity value is W ij ; When W ij <0, W ij Transformed into the weight stored in the second Flash-type weight storage tube of the calculation unit in the common floating gate Flash memory of the i-th row and j-th column in the array, that is, the conductivity value is |W ij |; According to the programming operation of the parallel common floating gate type Flash memory computing unit, the weight configuration of any parallel common floating gate type Flash memory computing unit in the parallel common floating gate type Flash memory computing array is completed, so that the conductance of the first Flash type weight storage tube or the second Flash type weight storage tube reaches the target value; (2) Calculate the read-out bit line rBL of the jth column in the common-bit floating gate Flash memory array <j>Apply potential V ij ; (3) Sum up the readout currents of the first Flash-type weight storage transistors of all the corresponding-bit common floating-gate Flash in-memory computing units in the i-th row and output them to the first readout terminal source line of the i-th row; sum up the readout currents of the second Flash-type weight storage transistors of all the corresponding-bit common floating-gate Flash in-memory computing units in the i-th row and output them to the second readout terminal source line of the i-th row; (4) Subtract the readout current of the first readout terminal source line of the i-th row from the readout current of the second readout terminal source line of the i-th row through a difference circuit to finally obtain OUT 。

[0015] A counter-aligned co-floating gate type Flash in-memory computing unit and array structure provided by the present invention. The sharing of the floating gate polysilicon layer by the Flash type weight programming tube and the Flash type weight storage tube can realize the control of multiple conductance states of the Flash type weight storage tube by the Flash type weight programming tube, complete the in-memory operation of the Flash device, and have a wide weight adjustment range; the weight subtraction of the counter-aligned co-floating gate type Flash in-memory computing unit helps to further improve the weight configuration range of the in-memory computing unit; the BTBT (Band-to-band tunneling) programming method with high electron injection efficiency can effectively improve the programming rate; at the same time, compared with the CHHE (Channel hot-hole induced hot-electron injection) and FN (Fowler-nordheim) programming methods, the BTBT programming method can reduce the damage to the tunnel oxide layer of the Flash device during the programming operation, thereby improving the reliability and working life of the in-memory computing device structure; the MOS type gating tube can solve the problem of weight configuration interference of Flash cells in the in-memory computing array and enhance the configuration reliability of the Flash array. The counter-aligned co-floating gate type Flash in-memory computing unit and array obtained by the present invention are compatible with the CMOS process, have a wide weight configuration range and high reliability, and are suitable for in-memory computing architecture circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic structural diagram of the counter-aligned co-floating gate type Flash in-memory computing unit provided by the present invention; Figure 2 It is a schematic programming operation diagram of the counter-aligned co-floating gate type Flash in-memory computing unit provided by the present invention; Figure 3 It is a schematic erasing operation diagram of the counter-aligned co-floating gate type Flash in-memory computing unit provided by the present invention; Figure 4 It is a schematic diagram of the transfer characteristic curve of the Flash type weight storage tube during charging and discharging on the shared floating gate polysilicon layer of the counter-aligned co-floating gate type Flash in-memory computing unit provided by the present invention; Figure 5 It is a schematic reading operation diagram of the counter-aligned co-floating gate type Flash in-memory computing unit provided by the present invention; Figure 6 It is a schematic structural diagram of the counter-aligned co-floating gate type Flash in-memory computing array provided by the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The following is a further detailed description of a bit-by-bit common floating gate Flash in-memory computing unit and array structure proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] The present invention provides a parallel-bit common floating gate Flash in-memory computing unit, comprising a MOS-type gating tube T1, two Flash-type weight programming tubes (i.e., a first Flash-type weight programming tube T2, a second Flash-type weight programming tube T3) and two Flash-type weight storage tubes (i.e., a first Flash-type weight storage tube T4, a second Flash-type weight storage tube T5); In the embodiment of the present invention, the MOS type gating tube is described with a p-channel MOS tube as a typical example, and the MOS type gating tube of the present invention may also be selected but not limited to an n-channel MOS tube to achieve the same effect and purpose. In the embodiment of the present invention, two Flash type weight programming tubes and two Flash type weight storage tubes are described with a p-channel Flash tube as a typical example, and the two Flash type weight programming tubes and two Flash type weight storage tubes of the present invention may also be selected but not limited to an n-channel Flash tube to achieve the same effect and purpose.

[0019] like Figure 1 As shown, the first Flash type weight programming tube T2 shares the floating gate polycrystalline layer and the control gate polycrystalline layer with the first Flash type weight storage tube T4, and the second Flash type weight programming tube T3 shares the floating gate polycrystalline layer and the control gate polycrystalline layer with the second Flash type weight storage tube T5.

[0020] The drain end of the MOS type selection tube T1 is connected to the control end bit line cBL, and the source end is connected to the drain end of the first Flash type weight programming tube T2. The source end of the first Flash type weight programming tube T2 is connected to the drain end of the second Flash type weight programming tube T3. The source end of the second Flash type weight programming tube T3 is connected to the control end source line cSL, that is, the MOS type selection tube T1, the first Flash type weight programming tube T2 and the second Flash type weight programming tube T3 are in a series relationship.

[0021] The source end of the first Flash type weight storage tube T4 is connected to the first readout source line rSLP, and the drain end is connected to the readout bit line rBL together with the drain end of the second Flash type weight storage tube T5. The source end of the second Flash type weight storage tube T5 is connected to the second readout source line rSLN.

[0022] The gate terminal of the MOS type strobe tube T1 is connected to the selection gate word line sgWL, and the shared control gates of the first Flash type weight programming tube T2 and the first Flash type weight storage tube T4 are connected to the first control gate word line cgWLP; the shared control gates of the second Flash type weight programming tube T3 and the second Flash type weight storage tube T5 are connected to the second control gate word line cgWLN, that is, the selection gate word line sgWL, the first control gate word line cgWLP, and the second control gate word line cgWLN can be independently controlled respectively and different potentials can be applied respectively.

[0023] As Figure 2 shown, when programming the first Flash type weight programming tube T2, an override voltage is applied on the selection gate word line sgWL to turn on the MOS type strobe tube T1; a voltage is applied on the second control gate word line cgWLN to turn on the second Flash type weight programming tube T3; a voltage is applied on the control end bit line cBL, and the floating gate polycrystalline layer of the first Flash type weight programming tube T2 is charged by the BTBT method at the drain end. At this time, the first Flash type weight storage tube T4 can share the floating gate polycrystalline layer charged with charge with the first Flash type weight programming tube T2. Among them, the override voltage of the second control gate word line cgWLN that turns on the second Flash type weight programming tube T3 needs to be greater than the maximum threshold voltage of the second Flash type weight programming tube T3. Whether or not the floating gate polycrystalline layer of the second Flash type weight programming tube T3 is charged, the second Flash type weight programming tube T3 remains on. At the same time, this override voltage cannot be too large and should be less than half of the erase voltage applied on the second control gate word line cgWLN when erasing the second Flash type weight programming tube T3 to prevent the second Flash type weight programming tube T3 and the second Flash type weight storage tube T5 from being erased due to FN tunneling.

[0024] When programming the second Flash-type weight programming transistor T3, a voltage is applied to the select gate word line sgWL to turn on the MOS-type select transistor T1; an override voltage is applied to the first control gate word line cgWLP to turn on the first Flash-type weight programming transistor T2; a voltage is applied to the control end bit line cBL, and the floating gate polycrystalline layer of the second Flash-type weight programming transistor T3 is charged with charges in the BTBT mode at the drain end. At this time, the second Flash-type weight storage transistor T5 can share the floating gate polycrystalline layer with the charged charges with the second Flash-type weight programming transistor T3. The override voltage of the first control gate word line cgWLP that turns on the first Flash-type weight programming transistor T2 needs to be greater than the maximum threshold voltage of the first Flash-type weight programming transistor T2. Whether or not the floating gate polycrystalline layer of the first Flash-type weight programming transistor T2 is charged, the first Flash-type weight programming transistor T2 remains turned on. At the same time, this override voltage cannot be too large and should be less than half of the erase voltage applied to the first control gate word line cgWLP when erasing the first Flash-type weight programming transistor T2, to prevent the second Flash-type weight programming transistor T3 and the second Flash-type weight storage transistor T5 from being erased due to FN tunneling.

[0025] As Figure 3 shown, when erasing the first Flash-type weight programming transistor T2 and the second Flash-type weight programming transistor T3, the charges on the floating gate polycrystalline layer are removed simultaneously by the source-end FN tunneling method or the full-channel uniform FN tunneling method. At this time, the first Flash-type weight storage transistor T4 shares the floating gate polycrystalline layer with the removed charges with the first Flash-type weight programming transistor T2; the second Flash-type weight storage transistor T5 shares the floating gate polycrystalline layer with the removed charges with the second Flash-type weight programming transistor T3.

[0026] Through the above programming and erasing operations on the first Flash-type weight programming transistor T2, the conductance state (i.e., weight) of the first Flash-type weight storage transistor T4 can be controlled; the programming and erasing operations of the second Flash-type weight programming transistor T3 can control the conductance state (i.e., weight) of the second Flash-type weight storage transistor T5. That is, when electrons are charged on the floating gate polycrystalline layers shared by the first Flash-type weight programming transistor T2 and the second Flash-type weight programming transistor T3 with the first Flash-type weight storage transistor T4 and the second Flash-type weight storage transistor T5 respectively, the transfer characteristic curves of the first Flash-type weight storage transistor T4 or the second Flash-type weight storage transistor T5 are as Figure 4 As shown, when the potential of the first control gate word line cgWLP or the second control gate word line cgWLN is 0V, the change in the amount of charge injected into the floating gate polysilicon layer shared by the first Flash-type weight programming transistor T2 and the second Flash-type weight programming transistor T3 with the first Flash-type weight storage transistor T4 and the second Flash-type weight storage transistor T5 respectively causes a change in the conductance state of the second Flash-type weight programming transistor T3; when the electrons in the floating gate polysilicon layer shared by the first Flash-type weight programming transistor T2 and the second Flash-type weight programming transistor T3 with the first Flash-type weight storage transistor T4 and the second Flash-type weight storage transistor T5 respectively are completely removed, the transfer characteristic curve of the first Flash-type weight storage transistor T4 or the second Flash-type weight storage transistor T5 is as Figure 4 As shown, when the potential of the first control gate word line cgWLP or the second control gate word line cgWLN is 0V, the first Flash-type weight storage transistor T4 or the second Flash-type weight storage transistor T5 is in the off state.

[0027] As Figure 5 As shown, when performing a read operation on the first Flash-type weight storage transistor T4, a voltage is applied to the first control gate word line cgWLP to turn on the first Flash-type weight storage transistor T4, voltages are applied to the read bit line rBL and the first read source line rSLP respectively, and a current is read from the first read source line rSLP, thereby obtaining the conductance state (i.e., the weight) of the first Flash-type weight storage transistor T4; When performing a read operation on the second Flash-type weight storage transistor T5, a voltage is applied to the second control gate word line cgWLN to turn on the second Flash-type weight storage transistor T5, voltages are applied to the read bit line rBL and the second read source line rSLN respectively, and a current is read from the second read source line rSLN, thereby obtaining the conductance state (i.e., the weight) of the second Flash-type weight storage transistor T5.

[0028] The present invention also provides a pair-aligned floating-gate Flash in-memory computing array structure, and this array structure is as Figure 6 shown, including n rows of pair-aligned floating-gate Flash in-memory computing units and m columns of pair-aligned floating-gate Flash in-memory computing units, where m and n are positive integers and the minimum value is 1.

[0029] The gate terminal of the MOS-type strobe transistor T1 in the i-th row is serially connected to the select gate word line sgWL of the i-th row , the control gates shared by the first Flash-type weight programming transistor T2 and the first Flash-type weight storage transistor T4 in the i-th row are connected in series to the first control gate word line cgWLP of the i-th row , the control gates shared by the second Flash-type weight programming transistor T3 and the second Flash-type weight storage transistor T5 in the i-th row are connected in series to the second control gate word line cgWLN of the i-th row , the source terminal of the second Flash-type weight programming tube T3 in the i-th row is connected in series to the control terminal source line cSL of the i-th row , the source terminal of the first Flash-type weight storage tube T4 in the i-th row is connected in series to the first readout terminal source line rSLP of the i-th row , the source terminal of the second Flash-type weight storage tube T5 in the i-th row is connected in series to the second readout source line rSLN of the i-th row , the first readout terminal source line rSLP of the i-th row and a second readout terminal source line rSLN After the difference circuit DC post-output; The drain terminal of the MOS type strobe tube T1 in the j-th column is connected in series to the control terminal bit line cBL of the j-th column <j>, the drain terminals of the first Flash-type weight storage transistor T4 and the second Flash-type weight storage transistor T5 in the j-th column are connected in series to the readout terminal bit line rBL of the j-th column <j>.

[0030] The present invention performs multiplication and accumulation operations OUT on the bit-shared floating gate type Flash memory calculation array structure =ΣV ij *W ij The implementation method is as follows: (1) When W ij ≥0 (i.e. positive weight), W ij Transformed into the weight value stored in the first Flash type weight storage tube T4 of the i-th row and j-th column of the parallel common floating gate Flash memory calculation unit in the parallel common floating gate Flash memory calculation array, that is, the conductance value W ij When W ij <0 (i.e. negative weight), W ij Transformed into the weight stored in the second Flash weight storage tube T5 of the common floating gate Flash memory computing unit in the i-th row and j-th column of the array, that is, the conductance value |W ij |.

[0031] According to the above programming operation, the weight configuration of any one of the parallel common floating gate type Flash memory computing units in the parallel common floating gate type Flash memory computing array can be completed, taking the parallel common floating gate type Flash memory computing unit 110 in the first row and the first column as an example: The select gate word line sgWL in row 1 <1> A voltage is applied to the MOS gate transistor 111 to turn on the second control gate word line cgWLN in the first row. <1> Applying an over-control voltage to turn on the second Flash type weight programming tube 113, the control terminal bit line cBL of the first column <1> A voltage is applied to the floating gate polycrystalline layer of the first Flash type weight programming tube 112, and a charge is charged into the floating gate polycrystalline layer of the first Flash type weight programming tube 112 by a BTBT method at the drain end until the conductance of the first Flash type weight storage tube 114 reaches the target value W ij , wherein the second control gate word line cgWLN of the first row that enables the second Flash type weight programming tube 113 to be turned on <1> The over-control voltage is the same as the range required during the above programming operation; The select gate word line sgWL in row 1 <1> A voltage is applied to open the MOS gate transistor 111, and the first control gate word line cgWLP in the first row <1> Applying an over-control voltage to turn on the first Flash type weight programming tube 112, the control terminal bit line cBL of the first column <1> A voltage is applied to the floating gate polycrystalline layer of the second Flash type weight programming tube 113, and a charge is charged into the floating gate polycrystalline layer of the second Flash type weight programming tube 113 by a BTBT method at the drain end until the conductance of the second Flash type weight storage tube 115 reaches the target value |W ij |, wherein the first control gate word line cgWLP of the first row of the first Flash type weight programming tube 112 is turned on <1> The over-control voltage is the same as the range required during the above programming operation.

[0032] (2) Calculate the read-out bit line rBL of the jth column in the common-bit floating gate Flash memory array <j>Applied potential V ij .

[0033] (3) The read current I of the first Flash weight storage tube T4 of all the common floating gate Flash memory computing units in the i-th row Pij =V ij *W ij Add and output to the first read-out source line rSLP of row i ; The second Flash type weight storage tube T5 read current I of all the bit-aligned common floating gate type Flash in-memory computing units in the i-th row Nij =V ij *|W ij | is summed and output to the second read terminal source line rSLN of the i-th row Through the difference circuit DC , the first readout terminal source line rSLP of the i-th row Readout current I Pij and the second readout terminal source line rSLN of the i-th row The readout current I Nij Subtract, and finally obtain OUT 。

[0034] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims. < / j> < / j> < / j> < / j>

Claims

1. A parallel-bit common floating gate Flash in-memory computing unit, characterized in that: Including: A MOS type gated tube, a first Flash type weight programming tube, a second Flash type weight programming tube, a first Flash type weight storage tube, and a second Flash type weight storage tube; The first Flash type weight programming tube and the first Flash type weight storage tube share a floating gate polysilicon layer and a control gate polysilicon layer, and the second Flash type weight programming tube and the second Flash type weight storage tube share a floating gate polysilicon layer and a control gate polysilicon layer; The drain end of the MOS type gated tube is connected to the control end bit line, the source end is connected to the drain end of the first Flash type weight programming tube, the source end of the first Flash type weight programming tube is connected to the drain end of the second Flash type weight programming tube, and the source end of the second Flash type weight programming tube is connected to the control end source line; The source end of the first Flash type weight storage tube is connected to the first readout end source line, the drain end is commonly connected to the readout end bit line with the drain end of the second Flash type weight storage tube, and the source end of the second Flash type weight storage tube is connected to the second readout end source line; The gate end of the MOS type gated tube is connected to the selection gate word line, the first Flash type weight programming tube and the first Flash type weight storage tube share a control gate connected to the first control gate word line, the second Flash type weight programming tube and the second Flash type weight storage tube share a control gate connected to the second control gate word line, and the selection gate word line, the first control gate word line, and the second control gate word line are respectively independently controlled and different potentials are respectively applied; When the first Flash type weight programming tube performs a programming operation, a voltage is applied to the selection gate word line to turn on the MOS type gated tube, a super-control voltage is applied to the second control gate word line to turn on the second Flash type weight programming tube, a voltage is applied to the control end bit line, and the floating gate polysilicon layer of the first Flash type weight programming tube is charged with charges by the band-to-band tunneling method at the drain end. At this time, the first Flash type weight storage tube and the first Flash type weight programming tube share the floating gate polysilicon layer that has been charged with charges; When the second Flash type weight programming tube performs a programming operation, a voltage is applied to the selection gate word line to turn on the MOS type gated tube, a super-control voltage is applied to the first control gate word line to turn on the first Flash type weight programming tube, a voltage is applied to the control end bit line, and the floating gate polysilicon layer of the second Flash type weight programming tube is charged with charges by the band-to-band tunneling method at the drain end. At this time, the second Flash type weight storage tube and the second Flash type weight programming tube share the floating gate polysilicon layer that has been charged with charges.

2. The bit-aligned co-floating-gate type Flash in-memory computing unit according to claim 1, wherein The super-control voltage of the second control gate word line for turning on the second Flash type weight programming tube needs to be greater than the maximum threshold voltage of the second Flash type weight programming tube. Whether or not the floating gate polysilicon layer of the second Flash type weight programming tube is charged with charges, the second Flash type weight programming tube remains turned on.

3. The bit-aligned co-floating-gate type Flash in-memory computing unit according to claim 1, wherein, The first control gate word line override voltage for turning on the first Flash-type weight programming tube needs to be greater than the maximum threshold voltage of the first Flash-type weight programming tube. Whether or not charge is injected into the floating gate polycrystalline layer of the first Flash-type weight programming tube, the first Flash-type weight programming tube remains turned on.

4. The bit-aligned co-floating-gate type Flash in-memory computing unit according to claim 1, characterized in that, When the first Flash-type weight programming tube and the second Flash-type weight programming tube perform an erase operation, the charge on the floating gate polycrystalline layer is removed simultaneously by the source-side FN tunneling method or the full-channel uniform FN tunneling method. At this time, the first Flash-type weight storage tube and the second Flash-type weight storage tube share the floating gate polycrystalline layer from which the charge has been removed with the first Flash-type weight programming tube and the second Flash-type weight programming tube respectively.

5. The parallel-bit common floating gate Flash in-memory computing unit according to claim 1, characterized in that: When the first Flash-type weight storage tube performs a read operation, a voltage is applied to the first control gate word line to turn on the first Flash-type weight storage tube. Voltages are applied to the readout bit line and the first readout source line respectively, and current is read from the first readout source line to obtain the conductance state of the first Flash-type weight storage tube, and this conductance state is the weight.

6. The parallel-bit common floating gate Flash in-memory computing unit according to claim 1, characterized in that: When the second Flash-type weight storage tube performs a read operation, a voltage is applied to the second control gate word line to turn on the second Flash-type weight storage tube. Voltages are applied to the readout bit line and the second readout source line respectively, and current is read from the second readout source line to obtain the conductance state of the second Flash-type weight storage tube, and this conductance state is the weight.

7. The parallel-bit common floating gate Flash in-memory computing unit according to claim 1, characterized in that: The MOS-type gating tube is a p-channel MOS tube or an n-channel MOS tube, and the two Flash-type weight programming tubes and the two Flash-type weight storage tubes are p-channel Flash tubes or n-channel Flash tubes; the MOS-type gating tube, the two Flash-type weight programming tubes and the two Flash-type weight storage tubes are all p-channel MOS tubes or all n-channel MOS tubes.

8. An array structure based on a parallel-positioned common floating gate type Flash memory computing unit, using the parallel-positioned common floating gate type Flash memory computing unit according to any one of claims 1 to 7, characterized in that: The bit-aligned co-floating gate type Flash in-memory computing array structure includes n rows of bit-aligned co-floating gate type Flash in-memory computing units and m columns of bit-aligned co-floating gate type Flash in-memory computing units, where m and n are positive integers and the minimum value is 1; The gate terminal of the MOS-type gating tube in the i-th row is connected in series to the i-th row of select gate word lines, the control gate shared by the first Flash-type weight programming tube and the first Flash-type weight storage tube in the i-th row is connected in series to the i-th row of first control gate word lines, the control gate shared by the second Flash-type weight programming tube and the second Flash-type weight storage tube in the i-th row is connected in series to the i-th row of second control gate word lines, the source terminal of the second Flash-type weight programming tube in the i-th row is connected in series to the i-th row of control source lines, the source terminal of the first Flash-type weight storage tube in the i-th row is connected in series to the i-th row of first readout source lines, the source terminal of the second Flash-type weight storage tube in the i-th row is connected in series to the i-th row of second readout source lines, and the first readout source line and the second readout source line in the i-th row are output after passing through a difference circuit; The drain terminal of the MOS-type strobe tube in the j-th column is connected in series to the control terminal bit line of the j-th column, and the drain terminals of the first Flash-type weight storage tube and the second Flash-type weight storage tube in the j-th column are connected in series to the readout terminal bit line of the j-th column; where i is a positive integer not greater than m, and j is a positive integer not greater than n.

9. The array structure based on the parallel-bit common floating gate Flash in-memory computing unit as claimed in claim 8, characterized in that: Perform multiplication and accumulation operation OUT on the described alignment co-floating gate type Flash in-memory computing array structure = ΣV ij * W ij The implementation method includes: (1) When W ij ≥0, W ij The weight value stored in the first Flash type weight storage tube of the i-th row and j-th column of the parallel common floating gate Flash memory calculation unit in the parallel common floating gate Flash memory calculation array is converted into the weight value stored in the first Flash type weight storage tube of the i-th row and j-th column of the parallel common floating gate Flash memory calculation unit, that is, the conductivity value is W ij When W ij <0, W ij Transformed into the weight stored in the second Flash-type weight storage tube of the calculation unit in the common floating gate Flash memory of the i-th row and j-th column in the array, that is, the conductivity value is |W ij |; According to the programming operation of the bit-aligned common floating-gate type Flash in-memory computing unit, the weight configuration of any bit-aligned common floating-gate type Flash in-memory computing unit in the bit-aligned common floating-gate type Flash in-memory computing array is completed, so that the conductance of the first Flash-type weight storage tube or the second Flash-type weight storage tube reaches the target value; (2)For the readout terminal bit line rBL of the j-th column in the counter-aligned common floating gate type Flash in-memory computing array <j>Apply potential V ij ;< / j> (3) The readout currents of the first Flash-type weight storage tubes of all the bit-aligned common floating-gate type Flash in-memory computing units in the i-th row are summed and output to the first readout terminal source line of the i-th row; the readout currents of the second Flash-type weight storage tubes of all the bit-aligned common floating-gate type Flash in-memory computing units in the i-th row are summed and output to the second readout terminal source line of the i-th row; (4) Through a difference circuit, subtract the read current of the first readout source line of the i-th row from the read current of the second readout source line of the i-th row, and finally obtain OUT 。

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