Memory fault determination method and MRAM (Magnetic Random Access Memory)

Abstract

The invention provides a fault determination method of a memory and an MRAM (Magnetic Random Access Memory), and the method comprises the steps: respectively writing reference bits in a first column group and a second column group into a low-resistance state and a high-resistance state, starting all bits in the same row, writing 0 to the storage bits, reading the output voltage of an amplifier, and obtaining a first reading; respectively writing the reference bits in the first column group and the second column group into a high-resistance state and a low-resistance state, starting all bits in the same row, and writing 0 to the storage bits and reading the output voltage of the amplifier to obtain a second reading; when abnormal reading exists, determining that abnormal reference bits exist in the row; and when all the reference bits are opened, at least controlling the redundant switching tubes corresponding to part of the reference columns to be closed, connecting the redundant MTJs to the reference columns, reading the output voltage of the amplifier to obtain a third reading, and determining the reference column where the abnormal reference bit is located according to the third reading and the preset range. According to the method and the device, the problem that the abnormal reference bit is relatively complex to position when the memory fails to read 0 is solved.

Description

Technical Field

[0001] The present application relates to the field of memories, and in particular, to a method for determining a fault of a memory and an MRAM. Background Art

[0002] A magnetic random access memory includes a reference bit and a storage bit. When a short circuit anomaly occurs in the MTJ of the reference bit, the current at the reference terminal will be too large, resulting in a failure to read 0 in the magnetic random access memory. In this case, generally, an additional read circuit needs to be added to locate the position of the abnormal reference bit, and the operation is complex. Summary of the Invention

[0003] The main purpose of the present application is to provide a method for determining a fault of a memory and an MRAM, so as to at least solve the problem that the positioning process of an abnormal reference bit is relatively complex when a memory fails to read 0 in the prior art.

[0004] To achieve the above object, according to one aspect of the present application, a method for determining a fault of a memory is provided. The memory includes a plurality of reference columns, a plurality of storage columns, and a plurality of amplifiers. The reference columns include a plurality of reference bits arranged along the column direction. The storage columns include a plurality of storage bits arranged along the column direction. The first ends of the reference bits in the same column are connected to the same first bit line. The first ends of the storage bits in the same column are connected to the same second bit line. The first bit lines are connected to the first input ends of the amplifiers in a one-to-one correspondence. The second bit lines are connected to the second input ends of the amplifiers in a one-to-one correspondence. The first input ends of the plurality of amplifiers are connected. The second ends of the reference bits and the storage bits in the same row are connected to the same word line. Each reference column further includes at least one redundant MTJ and at least one redundant switch transistor. The redundant MTJ and the redundant switch transistor are connected in series in a one-to-one correspondence and then connected in parallel to the corresponding first bit line. The plurality of reference columns are evenly divided into two column groups, namely a first column group and a second column group. The method includes: writing the reference bits in the first column group to a low resistance state and writing the reference bits in the second column group to a high resistance state. By the word line, the reference bits and the storage bits in the same row are turned on, a write 0 operation is performed on the turned-on storage bits, and the output terminal voltages of the amplifiers are read to obtain a plurality of first readings corresponding to each word line; in the case of writing the reference bits in the first column group to the high resistance state and writing the reference bits in the second column group to the low resistance state, by the word line, the reference bits and the storage bits in the same row are turned on, a write 0 operation is performed on the turned-on storage bits, and the output terminal voltages of the amplifiers are read to obtain a plurality of second readings corresponding to each word line; in the case of the existence of abnormal readings, it is determined that there are abnormal reference bits in the row where the word line corresponding to the abnormal reading is located. The abnormal reading is the first reading and / or the second reading that is not within a predetermined range; in the case where all the reference bits are turned on, at least the redundant switch transistors corresponding to some of the reference columns are controlled to be closed to connect the redundant MTJ to the reference column, and the output terminal voltages of the amplifiers after the redundant MTJ is connected to the reference column are read to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, the reference column where the abnormal reference bit is located is determined.

[0005] Optionally, the initial state of each of the redundant switching transistors is an open state, and at least the redundant switching transistors corresponding to the reference columns in the control part are closed to connect the redundant MTJs to the reference columns, and the output terminal voltages of the amplifiers after the redundant MTJs are connected to the reference columns are read to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, the reference column where the abnormal reference bit is located is determined, including: a closing step of closing the redundant switching transistors corresponding to the reference columns in each of the first column group or the second column group to connect the redundant MTJs to the reference columns in each of the first column group or the second column group; a first reading step of reading the output terminal voltages of the amplifiers to obtain a plurality of the third readings when the redundant MTJs are connected to the reference columns in each of the first column group or the second column group, and controlling the closed redundant switching transistors to be opened; a first determining step of determining an abnormal column group according to the magnitude relationship between the plurality of third readings and the predetermined range, where the abnormal column group is the column group where the abnormal reference bit is located, and when the abnormal column group includes more than one reference column, dividing the abnormal column group into a new first column group and a second column group; a loop step of looping through the closing step, the first reading step, and the first determining step a first predetermined number of times until the new abnormal column group only includes one reference column, and when the target reference column is obtained, determining the reference column where the abnormal reference bit is located as the target reference column.

[0006] Optionally, the determining step includes: determining whether a plurality of the third readings are all within the predetermined range according to the magnitude relationship between the plurality of third readings and the predetermined range; when the plurality of third readings are all within the predetermined range, determining the abnormal column group as the column group where the closed redundant switch is located; when there is a third reading that is not within the predetermined range, determining the abnormal column group as the column group where the open redundant switch is located.

[0007] Optionally, the initial state of each of the redundant switching transistors is an off state. At least the redundant switching transistors corresponding to the reference columns of the control part are closed to connect the redundant MTJs to the reference columns, and the output terminal voltages of the amplifiers after the redundant MTJs are connected to the reference columns are read to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, determining the reference column where the abnormal reference bit is located includes: a control step of controlling the redundant switching transistors corresponding to the to-be-tested reference column to be closed to connect the redundant MTJs to the to-be-tested reference column, where the to-be-tested reference column is one of the plurality of reference columns; a second reading step of reading the output terminal voltages of the amplifiers after the redundant MTJs are connected to the reference column to obtain the plurality of third readings; a second determination step of determining whether all the plurality of third readings are within the predetermined range; a replacement step of, when it is determined that there are third readings not within the predetermined range, replacing the to-be-tested reference column, controlling the closed redundant switching transistors to be turned off, and repeatedly executing the control step, the second reading step, and the second determination step for a second predetermined number of times until it is determined that all the plurality of third readings are within the predetermined range; a third determination step of, when it is determined that all the plurality of third readings are within the predetermined range, determining that the to-be-tested reference column corresponding to the plurality of third readings within the predetermined range is the reference column where the abnormal reference bit is located.

[0008] Optionally, each reference column further includes a plurality of the redundant MTJs and a plurality of the redundant switching transistors. The word line corresponding to the abnormal reading is the target word line. When there are multiple target word lines, at least the redundant switching transistors corresponding to the reference columns of the control part are closed to connect the redundant MTJs to the reference columns, including: closing at least the same number of the redundant switching transistors as the number of the target word lines in the reference columns of at least the control part to connect the same number of the redundant MTJs as the number of the target word lines to the reference columns.

[0009] Optionally, before writing each of the reference bits in the first column group to the low resistance state and writing each of the reference bits in the second column group to the high resistance state, the method further includes: magnetizing each of the redundant MTJs to the high resistance state.

[0010] Optionally, after determining the reference column where the abnormal reference bit is located, the method further includes: storing the position information of the abnormal reference bit in a memory, where the position information includes the reference column and the word line where it is located; when receiving an access to a target storage bit, reading the position information from the memory, and determining whether to access a target redundant MTJ according to the position information of the abnormal reference bit and the position information of the target storage bit, where the target storage bit is one of the multiple storage bits, and the target redundant MTJ is the redundant MTJ included in the reference column where the abnormal reference bit is located, and when the word line where the target storage bit is located is the same as the word line where the abnormal reference bit is located, and the reference column where the target storage bit is located and the reference column where the abnormal reference bit is located are connected to the same amplifier, it is determined that the target redundant MTJ needs to be accessed; when it is determined that the target redundant MTJ needs to be accessed, controlling the redundant switch tube connected to the target redundant MTJ to close.

[0011] Optionally, the method further includes: when there is 1 abnormal reading, determining that the resistance state of the reference bit corresponding to the abnormal reading is the target resistance state; when there are multiple abnormal readings, determining that the resistance state of the reference bit corresponding to the maximum or minimum value among the multiple abnormal readings is the target resistance state, when all the multiple abnormal readings are less than the minimum value of the predetermined range, the maximum or minimum value is the minimum value among the multiple abnormal readings, and when all the multiple abnormal readings are greater than the maximum value of the predetermined range, the maximum or minimum value is the maximum value among the multiple abnormal readings, reading the output terminal voltages of the amplifiers after the redundant MTJ is accessed to the reference column, obtaining multiple third readings, including: reading the output terminal voltage of the amplifier when the reference column is in the target resistance state after the redundant MTJ is accessed to the reference column, obtaining multiple third readings.

[0012] Optionally, one of the first column group and the second column group includes each reference column with an odd position serial number in the column direction, and the other of the first column group and the second column group includes each reference column with an even position serial number.

[0013] According to another aspect of the present application, there is provided a MRAM, including: one or more processors, a memory, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include those for executing any one of the methods.

[0014] Applying the technical solution of the present application, when the reference bits in two column groups are in different resistance states, first sequentially turn on the memory bits through the word lines and perform write 0 and read 0 operations to obtain a plurality of first readings and a plurality of second readings. By comparing the size relationship between the first readings and the second readings and a predetermined range, the row where the abnormal reference bit is located is locked. Then, at least part of the reference columns are connected to redundant MTJs to replace the abnormal reference bits, and then a read 0 operation is performed. By comparing the size relationship between the third reading and the predetermined range, the column where the abnormal bit is located is locked. In this way, the positioning of the abnormal reference bit can be achieved without adding additional circuits, ensuring that the position of the abnormal reference bit can be relatively simply and easily determined from the bit array of the memory, and solving the problem that the positioning process of the abnormal reference bit is relatively complex when a read 0 failure occurs in the prior art memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings forming a part of this application are used to provide a further understanding of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0016] Figure 1 A flowchart showing a method for determining a fault of a memory provided in an embodiment of the present application is shown;

[0017] Figure 2 A partial structural diagram of a memory provided in an embodiment of the present application is shown;

[0018] Figure 3 Another partial structural diagram of a memory provided in an embodiment of the present application is shown;

[0019] Figure 4 A diagram showing a method for determining a fault of a memory provided in an embodiment of the present application is shown;

[0020] Figure 5 A diagram showing another method for determining a fault of a memory provided in an embodiment of the present application is shown;

[0021] Figure 6 Another partial structural diagram of a memory provided in an embodiment of the present application is shown;

[0022] Figure 7 Another partial structural diagram of a memory provided in an embodiment of the present application is shown;

[0023] Figure 8 A flowchart showing a method for determining a fault of a specific memory provided in an embodiment of the present application is shown.

[0024] Among them, the above-mentioned drawings include the following reference numerals:

[0025] 10. Reference column; 11. Reference bit; 12. Redundant MTJ; 13. Redundant switching transistor; 14. First switching transistor; 15. MTJ; 16. AND gate; 17. Inverter; 18. Second switching transistor; 20. Storage column; 21. Storage bit; 30. Amplifier; 40. First bit line; 50. Second bit line; 60. Word line; 70. First source line; 80. Second source line. Detailed implementation manners

[0026] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so as to implement the embodiments of the present application described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] As introduced in the background art, when a read 0 failure occurs in a memory in the prior art, the positioning process of abnormal reference bits is relatively complex. To solve the above problems, embodiments of the present application provide a method for determining a memory failure and an MRAM.

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

[0031] In this embodiment, a method for determining a fault of a memory is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0032] Figure 1 It is a flowchart of a method for determining a fault of a memory according to an embodiment of the present application. Figure 2 It is a partial structural schematic diagram of a memory provided according to an embodiment of the present application. As Figure 2 shown, the memory includes a plurality of reference columns 10, a plurality of storage columns 20, and a plurality of amplifiers 30. The reference columns 10 include a plurality of reference bits 11 arranged in a column direction. The storage columns 20 include a plurality of storage bits 21 arranged in the column direction. The first ends of the reference bits 11 in the same column are connected to the same first bit line 40. The first ends of the storage bits in the same column are connected to the same second bit line 50. The first bit line 40 is connected to the first input end of the amplifier 30 in a one-to-one correspondence. The second bit line 50 is connected to the second input end of the amplifier 30 in a one-to-one correspondence. The first input ends of the plurality of amplifiers 30 are connected. The second ends of the reference bits 11 and the storage bits 21 in the same row are connected to the same word line 60. The plurality of reference columns 10 are evenly divided into two column groups, namely a first column group and a second column group. Figure 3 It is another partial structural schematic diagram of a memory provided according to an embodiment of the present application. As Figure 3 shown, each reference column 10 further includes at least one redundant MTJ 12 and at least one redundant switching transistor 13. The redundant MTJ 12 and the redundant switching transistor 13 are connected in series one by one and then connected in parallel to the corresponding first bit line 40. As Figure 1 shown, the method includes the following steps:

[0033] Step S101, write each reference bit in the first column group to a low-resistance state and write each reference bit in the second column group to a high-resistance state. Turn on the reference bits and the storage bits in the same row through the word line, perform a write 0 operation on the turned-on storage bits, and read the output terminal voltages of the amplifiers to obtain a plurality of first readings corresponding to each word line.

[0034] Specifically, the low resistance state is the P state, and the high resistance state is the AP state. The resistance state of the reference bit can be changed by changing the current direction. For example, when the current direction is from BL to SL, it is in the low resistance state, and vice versa. The amplifier is used to compare the current at the first input terminal (i.e., the current value flowing through the reference bits in the same column) with the current at the second input terminal (i.e., the current value flowing through the memory bits in the same column), and output a reading according to the comparison result. The amplifier can be a sense amplifier or other types of amplifiers.

[0035] Step S102, when writing each of the reference bits in the first column group to the high resistance state and writing each of the reference bits in the second column group to the low resistance state, turn on the reference bit and the memory bit in the same row through the word line, perform a write 0 operation on the turned-on memory bit, and read the output terminal voltage of each amplifier to obtain a plurality of second readings corresponding to each word line;

[0036] Specifically, the first reading and the second reading may be the same or different. The number of the first readings and the number of the second readings corresponding to the word line are both equal to the number of amplifiers in the memory.

[0037] Step S103, in the case of an abnormal reading, determine that there is an abnormal reference bit in the row where the word line corresponding to the abnormal reading is located, and the abnormal reading is the first reading and / or the second reading that is not within a predetermined range;

[0038] Specifically, when turning on the reference bit and the memory bit in a row through the word line, if there is a short-circuited reference bit in that row, it will cause the first reading or the second reading corresponding to the word line to be abnormal, and the short-circuited reference bit is the abnormal reference bit. There may be one or more word lines corresponding to the abnormal reading. Similarly, there may be one or more abnormal reference bits on one word line.

[0039] In the actual application process, those skilled in the art can set the predetermined range according to empirical values or obtain it through multiple experiments. This application does not make specific limitations on this.

[0040] Step S104, when all the reference bits are turned on, at least control some of the redundant switch transistors corresponding to the reference columns to be closed to connect the redundant MTJ to the reference column, and read the output terminal voltage of each amplifier after the redundant MTJ is connected to the reference column to obtain a plurality of third readings, and determine the reference column where the abnormal reference bit is located according to the plurality of third readings and the predetermined range;

[0041] Specifically, the third reading may be the same as or different from the first reading and / or the second reading, and there may be one or more reference columns where the abnormal reference bit is located.

[0042] Through the above embodiments, when the reference bits in the two column groups are in different resistance states respectively, first, the storage bits are sequentially enabled through the word lines and the write 0 read 0 operation is performed to obtain a plurality of first readings and a plurality of second readings. By comparing the first readings and the second readings with the size relationship of a predetermined range, the row where the abnormal reference bit is located is locked. Then, at least part of the reference columns are connected to the redundant MTJ to replace the abnormal reference bit, and then the read 0 operation is performed. By comparing the size relationship between the third reading and the predetermined range, the column where the abnormal bit is located is locked. In this way, the positioning of the abnormal reference bit can be realized without additionally increasing the circuit, which ensures that the position of the abnormal reference bit can be determined relatively simply and easily from the bit array of the memory, and solves the problem that the positioning process of the abnormal reference bit is relatively complicated when the memory fails to read 0 in the prior art.

[0043] Figure 2 It shows the arrangement mode in which the reference column 10 and the storage column 20 are alternately distributed in the row direction. Except for Figure 2 the structure shown, those skilled in the art can flexibly set the specific arrangement mode of the reference column and the storage column according to the actual situation.

[0044] In the specific application process, when the reference bit in the memory is open-circuited, the current at the first input end will be relatively small. Since the reference columns are connected in parallel, when evenly divided by each reference column, the influence of the open circuit on the memory can be basically ignored; while when the reference bit is short-circuited, it will cause the current at the first input end to be relatively large, resulting in the memory failing to read 0. And when the MTJ where the reference bit itself should be in a high-resistance state is short-circuited, the current at the first input end is even worse, and the influence on the memory reading is greater. Therefore, it is necessary to locate and replace the short-circuited reference bit in the memory.

[0045] Specifically, the row direction described in the present application and the column direction may be perpendicular or not perpendicular. It should be noted that, as Figure 3 shown, the first end of the redundant MTJ 12 is electrically connected to the first end of the redundant switch tube 13, the second end of the redundant MTJ 12 is electrically connected to the first bit line, the second end of the redundant switch tube 13 is electrically connected to the first bit line, and a section of the first bit line connected to the second end of the redundant MTJ 12 and the second end of the redundant switch tube 13 is not electrically connected to other reference bits. That is to say, there are no other reference bits on the first bit line between the second end of the redundant MTJ 12 and the second end of the redundant switch tube 13.

[0046] The redundant switching transistor described above can be any suitable switching transistor in the prior art, such as transistors like MOS transistors and bipolar transistors. In a specific embodiment, the redundant switching transistor is a MOS transistor. One of the source or drain of the MOS transistor is the first end of the redundant switching transistor, and the other of the source or drain of the MOS transistor is the second end of the redundant switching transistor.

[0047] In the embodiments of the present application, as Figure 3 shown, each of the reference columns 10 further includes at least one AND gate 16, at least one inverter 17, and at least one second switching transistor 18. The first input terminal of the AND gate 16 is electrically connected to the word line 60, the second input terminal of the AND gate 16 is used to be connected to a reference terminal power supply, the output terminal of the AND gate 16 is electrically connected to the control terminal of one of the redundant switching transistors 13, the input terminal of the inverter 17 is electrically connected to the output terminal of the AND gate 16, the output terminal of the inverter 17 is electrically connected to the control terminal of the second switching transistor 18, and the AND gate 16 and the inverter 17 are used to control the on / off of the second switching transistor 18.

[0048] In the actual application process, the bit of a spin-transfer torque magnetic random access memory (STT-MRAM) includes 1 magnetic tunnel junction (MTJ) and 1 or more metal-oxide-semiconductor field-effect transistors (MOSFETs). The reading of information in a single MTJ depends on the difference between the parallel-state resistance Rp and the anti-parallel-state resistance Rap, and the "1" state or "0" state stored in the array is read out through a sense amplifier (abbreviated as SA). The sense amplifier usually compares the current at the storage bit end with the current at the reference bit end. Therefore, the reference current is usually set to I ref =(I L +I H ) / 2, where I L is the current value corresponding to the MTJ in the anti-parallel state at the reference terminal, and I H is the current value corresponding to the MTJ in the parallel state at the reference bit. In order to obtain a suitable I ref , the reference terminal of the read circuit uses a parallel connection of Rap and Rp, and each word line (abbreviated as WL) uses a group of reference resistors, where the ratio of the number of Rap and Rp states is the same, that is, Rap:Rp = 1:1.

[0049] This method can not only achieve the required Iref, but also have a better temperature compensation coefficient to meet the read window requirements at high and low temperatures.

[0050] Since in the memory, multiple reference columns are connected in parallel, it is impossible to directly determine the target reference column from the multiple reference columns. To solve this problem, in an alternative solution, as Figure 2 and Figure 4As shown, the initial state of each of the redundant switching transistors is an open state. At least the redundant switching transistors corresponding to the reference column 10 of the control part are closed to connect the redundant MTJ12 to the reference column 10, and the output terminal voltages of the amplifiers 30 after the redundant MTJ12 is connected to the reference column 10 are read to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, determining the reference column 10 where the abnormal reference bit is located includes:

[0051] Closing step: Closing the redundant switching transistors corresponding to each of the reference columns 10 in the first column group or the second column group to connect the redundant MTJ12 to each of the reference columns 10 in the first column group or the second column group;

[0052] Specifically, when there is only one word line corresponding to the abnormal reading, there is one corresponding closed redundant switching transistor. When there are n word lines corresponding to the abnormal reading, there are n corresponding closed redundant switching transistors.

[0053] First reading step: When the redundant MTJ12 is connected to each of the reference columns 10 in the first column group or the second column group, reading the output terminal voltages of the amplifiers 30 to obtain a plurality of the third readings, and controlling the closed redundant switching transistors to open;

[0054] First determination step: According to the magnitude relationship between the plurality of third readings and the predetermined range, determining the abnormal column group, where the abnormal column group is the column group where the abnormal reference bit 11 is located. When the abnormal column group includes more than one reference column 10, dividing the abnormal column group into a new first column group and a second column group;

[0055] Circulation step: Circulatingly executing the closing step, the first reading step, and the first determination step for a first predetermined number of times until the new abnormal column group only includes one reference column 10. When obtaining the target reference column, determining the reference column 10 where the abnormal reference bit is located as the target reference column.

[0056] The embodiment adopts the dichotomy method to find the target reference column from multiple reference columns. Specifically, by controlling the closing of the redundant switch tube, the redundant MTJ is connected to the reference column where it is located. When there is an abnormal reference bit with a short circuit in the reference column, the connected redundant MTJ replaces the role of the abnormal reference bit in the reference column, that is, the redundant MTJ provides the resistance value that the abnormal reference bit should have provided. Then, the voltage at the output terminal of the amplifier is read again. Through the third reading, the column group where the abnormal reference bit is located can be confirmed, and through the division step and the loop step, the target reference column where the abnormal reference bit is located can be accurately and quickly found. This is more suitable for memories with more reference columns, and further realizes the quick and accurate positioning of the abnormal reference bit. Moreover, since the temperature characteristics of the redundant MTJ and the MTJ in the reference bit are basically the same, the stability of the entire circuit can be further ensured.

[0057] In order to further solve the problem that the positioning process of abnormal reference bits is relatively complex when a memory fails to read 0 in the prior art, further, the first determination step includes: determining whether multiple third readings are all within the predetermined range according to the size relationship between the multiple third readings and the predetermined range; when the multiple third readings are all within the predetermined range, determining the abnormal column group as the column group where the closed redundant switch is located; when there is a third reading that is not within the predetermined range, determining the abnormal column group as the column group where the open redundant switch is located. In this embodiment, when the multiple third readings are all within the predetermined range, it indicates that the reference column where the abnormal reference bit originally existed has been repaired by connecting the redundant MTJ. Therefore, the reference column where the abnormal reference bit is located is in the column group where the closed redundant switch is located; when there is a third reading that is not within the predetermined range, it indicates that the reference column where the abnormal reference bit originally existed has not been repaired by connecting the redundant MTJ. Therefore, the reference column where the abnormal reference bit is located is in the column group where the open redundant switch is located. According to whether the multiple third readings are all within the predetermined range, this application can judge the abnormal column group, and can more quickly find the abnormal column group from the two column groups, further ensuring the simple and accurate positioning of the reference column where the abnormal reference bit is located.

[0058] In addition to the dichotomy method, those skilled in the art can also adopt any other suitable method to determine the reference column where the abnormal reference bit is located. In some alternative solutions of the present application, such as Figure 2 and Figure 5As shown, the initial state of each of the redundant switching transistors is an off state. At least the redundant switching transistors corresponding to the reference column 10 of the control part are closed to connect the redundant MTJ12 to the reference column 10, and the output terminal voltages of the amplifiers 30 after the redundant MTJ12 is connected to the reference column 10 are read to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, determining the reference column 10 where the abnormal reference bit is located includes:

[0059] A control step of controlling the redundant switching transistors corresponding to the reference column to be measured to be closed to connect the redundant MTJ12 to the reference column to be measured, where the reference column to be measured is one of the plurality of reference columns 10;

[0060] Specifically, when there is only 1 word line corresponding to the abnormal reading, there is 1 corresponding closed redundant switching transistor. When there are n word lines corresponding to the abnormal reading, there are n corresponding closed redundant switching transistors.

[0061] A second reading step of reading the output terminal voltages of the amplifiers 30 after the redundant MTJ12 is connected to the reference column 10 to obtain a plurality of the third readings;

[0062] A second determination step of determining whether all of the plurality of third readings are within the predetermined range;

[0063] A replacement step. In the case where it is determined that there are third readings not within the predetermined range, replace the reference column to be measured, control the closed redundant switching transistors to be turned off, and repeatedly execute the control step, the second reading step, and the second determination step for a second predetermined number of times until it is determined that all of the plurality of third readings are within the predetermined range;

[0064] Specifically, the reference column to be measured after replacement is different from the reference column to be measured before replacement. In the case where there are third readings not within the predetermined range, it indicates that by connecting the redundant MTJ, the reference column where the abnormal reference bit originally existed has not been repaired. Therefore, the reference column where the abnormal reference bit is located is not the reference column of the currently closed redundant switching transistors.

[0065] A third determination step of, in the case where it is determined that all of the plurality of third readings are within the predetermined range, determining that the reference column to be measured corresponding to the plurality of third readings within the predetermined range is the reference column 10 where the abnormal reference bit is located.

[0066] In the embodiment, the redundant switch tubes of a reference column are sequentially controlled to be turned on to find the reference column where the abnormal reference bit is located. The control logic is relatively simple and is more suitable for memories with fewer reference columns. Further, the quick and accurate positioning of the abnormal reference bit is realized. Moreover, the redundant MTJ corresponding to each reference column can replace the MTJ in any damaged reference bit in the column, and the utilization rate of the redundant MTJ is relatively high, making full use of the resources in the memory.

[0067] In other embodiments, as Figure 6 shown, each of the reference columns 10 further includes a plurality of the redundant MTJs 12 and a plurality of the redundant switch tubes 13. The word line 60 corresponding to the abnormal reading is the target word line. When there are multiple target word lines, at least some of the redundant switch tubes 13 corresponding to the reference columns 10 are controlled to be turned on to connect the redundant MTJs 12 to the reference columns 10, including: at least controlling some of the redundant switch tubes 13 in the reference columns 10 that are the same in number as the target word lines to be turned on to connect the redundant MTJs 12 that are the same in number as the target word lines to the reference columns 10. In this embodiment, a plurality of the redundant MTJs and the redundant switch tubes are provided. When there are multiple target word lines corresponding to the abnormal reading, it indicates that there are multiple abnormal reference bits in the reference column, and the number of the abnormal reference bits is the same as the number of the target word lines. Specifically, by controlling the redundant switch tubes in the reference column that are the same in number as the target word lines to be turned on, the redundant MTJs that are the same in number as the target word lines can be connected to the reference column. These connected redundant MTJs respectively replace the functions of the abnormal reference bits in the reference column, that is, the redundant MTJs provide the resistance values that the abnormal reference bits should have provided. Further, the redundant replacement of all the abnormal reference bits is realized, and further, it is convenient to lock the position of the reference bit according to the abnormal reading after replacement. The solution of this embodiment is more suitable for memories with more word lines, and further realizes the quick and accurate positioning of the abnormal reference bit.

[0068] According to some other exemplary embodiments of the present application, as Figure 7As shown, the third ends of the reference bits 11 in the same column are connected to the same first source line 70, and the third ends of the storage bits 21 in the same column are connected to the same second source line 80. The storage bit 21 and the reference bit 11 respectively include a three-terminal first switching transistor 14 and an MTJ 15. The control end of the first switching transistor 14 is the second end of the corresponding storage bit 21 or reference bit 11, that is, the control end of the first switching transistor 14 is electrically connected to the word line 60. The input end of the first switching transistor 14 is the third end of the corresponding storage bit 21 or reference bit 11, that is, the input end of the first switching transistor 14 is electrically connected to the first source line 70 or the second source line 80. The output end of the first switching transistor 14 is connected to the first end of the MTJ 15. The second end of the MTJ 15 is the first end of the corresponding storage bit 21 or reference bit 11, that is, the second end of the MTJ 15 is electrically connected to the first bit line 40 or the second bit line 50. By turning on the reference bit 11 and the storage bit 21 in the same row through the word line 60, a write-0 operation is performed on the turned-on storage bit 21, including: controlling the level of the word line 60 to a predetermined level so that the first switching transistors 14 of the storage bit 21 and the reference bit 11 connected to the word line 60 are turned on; controlling the level of the second source line 80 to a low level to perform the write-0 operation on each turned-on storage bit 21. In this embodiment, specifically, a predetermined level is provided to the control end of the switching transistor through the word line to turn on the switching transistor, so that a predetermined number of storage bits and reference bits corresponding to the word line can be controlled to be turned on each time. A low level is input to the switching transistor through the second source line to perform the write-0 operation on the storage bit.

[0069] In the actual application process, those skilled in the art can set the voltage values of the predetermined level and the low level according to empirical values, or obtain them through multiple experiments. This application does not make specific limitations on this. The switching transistor can be any suitable switching transistor in the prior art, such as transistors like diodes, MOS transistors, bipolar transistors, etc. In a specific embodiment, the switching transistor is a MOS transistor.

[0070] It should be noted that the first source line and the second source line can be different source lines or the same source line. In the case where the first source line and the second source line are different source lines, different or the same write operations can be performed on the reference bit and the storage bit corresponding to the same amplifier respectively; in the case where the first source line and the second source line are the same source line, the same write operation can be performed on the reference bit and the storage bit corresponding to the same amplifier.

[0071] In an embodiment of the present application, after determining the reference column where the abnormal reference bit is located, the method further includes: storing the position information of the abnormal reference bit in a memory, where the position information includes the reference column and the word line where the abnormal reference bit is located; when receiving an access to a target storage bit, reading the position information from the memory, and determining whether it is necessary to access a target redundant MTJ according to the position information of the abnormal reference bit and the position information of the target storage bit, where the target storage bit is one of a plurality of the storage bits, and the target redundant MTJ is the redundant MTJ included in the reference column where the abnormal reference bit is located. When the word line where the target storage bit is located is the same as the word line where the abnormal reference bit is located, and the reference column where the target storage bit is located and the reference column where the abnormal reference bit is located are connected to the same amplifier, it is determined that it is necessary to access the target redundant MTJ; when it is determined that it is necessary to access the target redundant MTJ, controlling the redundant switch tube connected to the target redundant MTJ to close. In this embodiment, the position information of the abnormal reference bit is stored in the memory. When receiving an access to the target storage bit, it is judged whether the position information of the target storage bit corresponds to the position information of the abnormal reference bit. In the case of correspondence, it is determined that it is necessary to access the target redundant MTJ, and the redundant switch tube connected to the target redundant MTJ is controlled to close. In this way, the accessed target redundant MTJ can replace the role of the abnormal reference bit in the reference column, that is, the target redundant MTJ provides the resistance value that the abnormal reference bit should have provided, so that the abnormal reference bit can be repaired, ensuring the normal operation of the memory.

[0072] Optionally, the method further includes: when there is one abnormal reading, determining the resistance state in which the reference bit corresponding to the abnormal reading is located as the target resistance state; when there are multiple abnormal readings, determining the resistance state in which the reference bit corresponding to the maximum or minimum value among the multiple abnormal readings is located as the target resistance state. When all the multiple abnormal readings are less than the minimum value of the predetermined range, the maximum or minimum value is the minimum value among the multiple abnormal readings. When all the multiple abnormal readings are greater than the maximum value of the predetermined range, the maximum or minimum value is the maximum value among the multiple abnormal readings. Reading the output terminal voltages of the amplifiers after the redundant MTJs are connected to the reference column, obtaining multiple third readings, including: reading the output terminal voltages of the amplifiers when the reference column is in the target resistance state after the redundant MTJs are connected to the reference column, obtaining the multiple third readings. In this embodiment, after obtaining the abnormal readings and determining the word line where the abnormal reference bit is located, the resistance states of the reference bits in each column are different, and the reading changes of the abnormal reference bit in different resistance states are also different. By determining the resistance state corresponding to the worst abnormal reading and reading the third readings in this resistance state, the magnitude relationship between the third readings and the predetermined range can be more clearly seen, further avoiding the problems of false detection or missed detection, and further ensuring that the reference column where the abnormal reference bit is located is determined more accurately.

[0073] Except for the two cases where all of the multiple abnormal readings are less than the minimum value of the predetermined range or all are greater than the maximum value of the predetermined range, there is also a case where some of the multiple abnormal readings are less than the minimum value of the predetermined range and the remaining part of the multiple abnormal readings is greater than the maximum value of the predetermined range. In this case, calculate the difference between the abnormal reading less than the minimum value of the predetermined range and the minimum value, and calculate the difference between the abnormal reading greater than the maximum value of the predetermined range and the maximum value, and determine the resistance state corresponding to the abnormal reading with the largest difference as the target resistance state.

[0074] Specifically, the target resistance state may be a low resistance state or a high resistance state. For example, when the target resistance state is a high resistance state, it means that when the reference bit is in a low resistance state and there is an abnormal reference bit with a short circuit, the change in the current at the first input terminal of the amplifier is not very obvious, resulting in the magnitude relationship between the output terminal voltage of the amplifier and the predetermined range not being very obvious. However, when the reference bit is in a high resistance state and there is an abnormal reference bit with a short circuit, the current at the first input terminal is worse and changes greatly, and the magnitude relationship between the output terminal voltage of the amplifier and the predetermined range is very obvious. The principle when the target configuration is a low resistance state is similar and will not be elaborated here.

[0075] Those skilled in the art can flexibly divide the first column group and the second column group according to the actual situation. For example, if there are 2n reference columns in total, the first n reference columns can be divided into the first column group, and the last n reference columns can be divided into the second column group, etc. The present application does not make specific restrictions on this. In some specific embodiments, one of the first column group and the second column group includes each of the reference columns with odd position serial numbers in the column direction, and the other of the first column group and the second column group includes each of the reference columns with even position serial numbers. In this embodiment, the reference columns are divided into column groups according to the odd or even position serial numbers of the reference columns in the column direction, and the operation is simple and easy to implement.

[0076] Specifically, the reference columns with odd position serial numbers in the column direction can be assigned to the first column group, and at the same time, the reference columns with even position serial numbers in the column direction can be assigned to the second column group; alternatively, the reference columns with even position serial numbers in the column direction can be assigned to the first column group, and at the same time, the reference columns with odd position serial numbers in the column direction can be assigned to the second column group.

[0077] It should be noted that in the actual application process, the reference bits in the memory have a write circuit, and the reference bits can be written to the P state or the AP state through the write circuit. However, the redundant MTJs in the memory do not have a write circuit. Therefore, before determining the fault, it is necessary to magnetically initialize each redundant MTJ to the AP state through a magnetic field. That is to say, before writing each reference bit in the first column group to the low-resistance state and writing each reference bit in the second column group to the high-resistance state, the method further includes: magnetizing each redundant MTJ to the high-resistance state.

[0078] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the fault determination method of the memory of the present application will be described in detail below with specific embodiments.

[0079] This embodiment relates to a specific method for determining faults in a memory, such as Figure 8 shown, and includes the following steps:

[0080] Step S1: Write each reference bit in the first column group to the low-resistance state and write each reference bit in the second column group to the high-resistance state. Turn on the reference bits and the storage bits in the same row through the word line, perform a write 0 operation on the turned-on storage bits, and read the output voltages of each amplifier to obtain a plurality of first readings corresponding to each word line;

[0081] Step S2: When writing each of the reference bits in the first column group to the high impedance state and writing each of the reference bits in the second column group to the low impedance state, turn on the reference bits and the memory bits in the same row through the word line, read the output terminal voltages of the amplifiers, and obtain a plurality of second readings corresponding to each word line;

[0082] Step S3: When there are abnormal readings, determine that there are abnormal reference bits in the row where the word line corresponding to the abnormal reading is located, and the abnormal readings are the first readings and / or the second readings that are not within a predetermined range;

[0083] Step S4: Write each of the reference bits in the first column group to the target impedance state, write each of the reference bits in the second column group to another impedance state other than the target impedance state, when all the reference bits are turned on, control the redundant switch transistors corresponding to the reference columns in the first column group to close, so as to connect the redundant MTJ to the reference columns in the first column group, and read the output terminal voltages of the amplifiers after the redundant MTJ is connected to the reference columns in the first column group, and obtain a plurality of third readings;

[0084] Step S5: When a plurality of the third readings are all within the predetermined range, determine that there are abnormal reference bits in the first column group, and when the first column group includes more than one reference column, divide the first column group into a new first column group and a second column group, and then loop to execute Step S4 until only one reference column is included in the new first column group or the second column group, obtain the reference column where the abnormal reference bit is located, when there are third readings that are not within the predetermined range, determine that there are abnormal reference bits in the second column group, and the processing method is the same as the method when there are abnormal reference bits in the first column group, which will not be elaborated here;

[0085] Step S6: Store the position information of the abnormal reference bit in a memory, and the position information includes the reference column and the word line where it is located;

[0086] Step S7: When receiving an access to a target storage bit, read the position information from the memory, and determine whether to access a target redundant MTJ according to the position information of the abnormal reference bit and the position information of the target storage bit, where the target storage bit is one of the multiple storage bits, and the target redundant MTJ is the redundant MTJ included in the reference column where the abnormal reference bit is located. When the word line where the target storage bit is located is the same as the word line where the abnormal reference bit is located, and the reference column where the target storage bit is located and the reference column where the abnormal reference bit is located are connected to the same amplifier, it is determined that the target redundant MTJ needs to be accessed;

[0087] Step S8: When it is determined that the target redundant MTJ needs to be accessed, control the redundant switch tube connected to the target redundant MTJ to close.

[0088] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0089] According to another aspect of the present application, there is provided a MRAM, including: one or more processors, a memory, and one or more programs, where the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include those for executing any one of the methods.

[0090] The MRAM is used to execute any one of the methods. When the reference bits in two column groups are in different resistance states respectively, first sequentially turn on the storage bits through the word line and perform write 0 and read 0 operations to obtain a plurality of first readings and a plurality of second readings. By comparing the first readings and the second readings with a predetermined range, the row where the abnormal reference bit is located is locked. Then at least part of the reference columns are connected to the redundant MTJ to replace the abnormal reference bit, and then a read 0 operation is performed. By comparing the third reading with the predetermined range, the column where the abnormal bit is located is locked. In this way, the positioning of the abnormal reference bit can be realized without additionally increasing the circuit, which ensures that the position of the abnormal reference bit can be relatively simply and easily determined from the bit array of the memory, and solves the problem that the positioning process of the abnormal reference bit is relatively complicated when a read 0 failure occurs in the prior art memory.

[0091] Obviously, those skilled in the art should understand that each module or step of the present invention can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order than here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.

[0092] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0093] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or multiple flows and / or blocks

[0094] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one or more of the flows Figure 1 or multiple flows and / or blocks

[0095] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the functions in the flowFigure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0096] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0097] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0098] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0099] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0100] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0101] 1) In the method for determining the fault of the memory of the present application, when the reference bits in two column groups are respectively in different resistance states, first, the memory bits are enabled by word lines in sequence and write 0 read 0 operations are performed to obtain a plurality of first readings and a plurality of second readings. By comparing the size relationship between the first readings and the second readings and a predetermined range, the row where the abnormal reference bit is located is locked. Then, at least some redundant MTJs are connected to the reference columns to replace the abnormal reference bits, and then a read 0 operation is performed. By comparing the size relationship between the third reading and the predetermined range, the column where the abnormal bit is located is locked. In this way, the positioning of the abnormal reference bit can be achieved without adding extra circuits, which ensures that the position of the abnormal reference bit can be determined relatively simply and easily from the bit array of the memory, and solves the problem that the positioning process of the abnormal reference bit is relatively complex when a read 0 failure occurs in the memory in the prior art.

[0102] 2) The MRAM of the present application is used to execute any one of the above-mentioned methods. When the reference bits in two column groups are respectively in different resistance states, first, the memory bits are enabled by word lines in sequence and write 0 read 0 operations are performed to obtain a plurality of first readings and a plurality of second readings. By comparing the size relationship between the first readings and the second readings and a predetermined range, the row where the abnormal reference bit is located is locked. Then, at least some redundant MTJs are connected to the reference columns to replace the abnormal reference bits, and then a read 0 operation is performed. By comparing the size relationship between the third reading and the predetermined range, the column where the abnormal bit is located is locked. In this way, the positioning of the abnormal reference bit can be achieved without adding extra circuits, which ensures that the position of the abnormal reference bit can be determined relatively simply and easily from the bit array of the memory, and solves the problem that the positioning process of the abnormal reference bit is relatively complex when a read 0 failure occurs in the memory in the prior art.

[0103] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for determining a fault of a memory, the memory including a plurality of reference columns, a plurality of storage columns, and a plurality of amplifiers, the reference columns including a plurality of reference bits arranged in a column direction, the storage columns including a plurality of storage bits arranged in the column direction, a first end of the reference bits in the same column being connected to the same first bit line, a first end of the storage bits in the same column being connected to the same second bit line, the first bit line being correspondingly connected to a first input end of the amplifier one by one, the second bit line being correspondingly connected to a second input end of the amplifier one by one, the first input ends of the plurality of amplifiers being connected, a second end of the reference bits and the storage bits in the same row being connected to the same word line, characterized in that, Each of the reference columns further includes at least one redundant MTJ and at least one redundant switching transistor. The redundant MTJs and the redundant switching transistors are connected in series one by one and then connected in parallel to the corresponding first bit line. The multiple reference columns are evenly divided into two column groups, namely a first column group and a second column group. The method includes: Writing each of the reference bits in the first column group to a low resistance state and writing each of the reference bits in the second column group to a high resistance state. Turning on the reference bit and the memory bit in the same row through the word line, performing a write 0 operation on the turned-on memory bit, and reading the output terminal voltages of the amplifiers to obtain a plurality of first readings corresponding to each word line. When writing each of the reference bits in the first column group to the high resistance state and writing each of the reference bits in the second column group to the low resistance state, turning on the reference bit and the memory bit in the same row through the word line, performing a write 0 operation on the turned-on memory bit, and reading the output terminal voltages of the amplifiers to obtain a plurality of second readings corresponding to each word line. In the case of an abnormal reading, determining that there is an abnormal reference bit in the row where the word line corresponding to the abnormal reading is located. The abnormal reading is the first reading and / or the second reading not within a predetermined range. When all the reference bits are turned on, at least controlling the redundant switching transistors corresponding to some of the reference columns to close, so as to connect the redundant MTJs to the reference columns, and reading the output terminal voltages of the amplifiers after the redundant MTJs are connected to the reference columns to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, determining the reference column where the abnormal reference bit is located.

2. The method according to claim 1, wherein The initial state of each of the redundant switching transistors is an off state. At least controlling the redundant switching transistors corresponding to some of the reference columns to close, so as to connect the redundant MTJs to the reference columns, and reading the output terminal voltages of the amplifiers after the redundant MTJs are connected to the reference columns to obtain a plurality of third readings. According to the plurality of third readings and the predetermined range, determining the reference column where the abnormal reference bit is located, including: A closing step of closing the redundant switching transistors corresponding to each of the reference columns in the first column group or the second column group, so as to connect the redundant MTJs to each of the reference columns in the first column group or the second column group. A first reading step of reading the output terminal voltages of the amplifiers to obtain a plurality of the third readings when the redundant MTJs are connected to each of the reference columns in the first column group or the second column group, and controlling the closed redundant switching transistors to turn off. A first determining step of determining an abnormal column group according to the magnitude relationship between the plurality of third readings and the predetermined range. The abnormal column group is the column group where the abnormal reference bit is located. When the abnormal column group includes more than one reference column, dividing the abnormal column group into a new first column group and a second column group. Loop step, loop and execute the closing step, the first reading step, and the first determination step a first predetermined number of times until the new abnormal column group only includes 1 reference column. When the target reference column is obtained, determine the reference column where the abnormal reference bit is located as the target reference column.

3. The method according to claim 2, characterized in that, The first determination step includes: According to the size relationship between multiple third readings and the predetermined range, determine whether multiple third readings are all within the predetermined range; When multiple third readings are all within the predetermined range, determine the abnormal column group as the column group where the closed redundant switch is located; When there is a third reading that is not within the predetermined range, determine the abnormal column group as the column group where the open redundant switch is located.

4. The method according to claim 1, wherein The initial state of each redundant switch tube is an open state. At least control the redundant switch tubes corresponding to some of the reference columns to close, so as to connect the redundant MTJ to the reference column, and read the output terminal voltages of each amplifier after the redundant MTJ is connected to the reference column to obtain multiple third readings. According to multiple third readings and the predetermined range, determine the reference column where the abnormal reference bit is located, including: Control step, control the redundant switch tube corresponding to the reference column to be measured to close, so as to connect the redundant MTJ to the reference column to be measured, and the reference column to be measured is one of multiple reference columns; Second reading step, read the output terminal voltages of each amplifier after the redundant MTJ is connected to the reference column to obtain multiple third readings; Second determination step, determine whether multiple third readings are all within the predetermined range; Replacement step, when it is determined that there is a third reading that is not within the predetermined range, replace the reference column to be measured, control the closed redundant switch tubes to open, and loop and execute the control step, the second reading step, and the second determination step a second predetermined number of times until it is determined that multiple third readings are all within the predetermined range; Third determination step, when it is determined that multiple third readings are all within the predetermined range, determine the reference column to be measured corresponding to the multiple third readings within the predetermined range as the reference column where the abnormal reference bit is located.

5. The method according to any one of claims 1 to 4, characterized in that, Each reference column further includes multiple redundant MTJs and multiple redundant switch tubes. The word line corresponding to the abnormal reading is the target word line. When there are multiple target word lines, at least control the redundant switch tubes corresponding to some of the reference columns to close, so as to connect the redundant MTJ to the reference column, including: At least control the redundant switch tubes with the same number as the target word lines in some of the reference columns to close, so as to connect the redundant MTJs with the same number as the target word lines to the reference column.

6. The method according to any one of claims 1 to 4, characterized in that, Before writing each reference bit in the first column group to the low resistance state and writing each reference bit in the second column group to the high resistance state, the method further includes: Magnetize each redundant MTJ to the high resistance state.

7. The method according to any one of claims 1 to 4, characterized in that After determining the reference column where the abnormal reference bit is located, the method further includes: Storing the position information of the abnormal reference bit in a memory, where the position information includes the reference column and the word line where it is located; When receiving an access to a target storage bit, reading the position information from the memory, and determining whether it is necessary to access a target redundant MTJ according to the position information of the abnormal reference bit and the position information of the target storage bit, where the target storage bit is one of the multiple storage bits, and the target redundant MTJ is the redundant MTJ included in the reference column where the abnormal reference bit is located. When the word line where the target storage bit is located is the same as the word line where the abnormal reference bit is located, and the reference column where the target storage bit is located and the reference column where the abnormal reference bit is located are connected to the same amplifier, it is determined that it is necessary to access the target redundant MTJ; When it is determined that it is necessary to access the target redundant MTJ, controlling the redundant switch tube connected to the target redundant MTJ to close.

8. The method according to any one of claims 1 to 4, wherein: The method further includes: when there is 1 abnormal reading, determining that the resistance state of the reference bit corresponding to the abnormal reading is the target resistance state; when there are multiple abnormal readings, determining that the resistance state of the reference bit corresponding to the maximum or minimum value among the multiple abnormal readings is the target resistance state. When all the multiple abnormal readings are less than the minimum value of the predetermined range, the maximum or minimum value is the minimum value among the multiple abnormal readings. When all the multiple abnormal readings are greater than the maximum value of the predetermined range, the maximum or minimum value is the maximum value among the multiple abnormal readings. Reading the output terminal voltages of the amplifiers after the redundant MTJ is accessed to the reference column, obtaining multiple third readings, including: reading the output terminal voltages of the amplifiers when the reference column is in the target resistance state after the redundant MTJ is accessed to the reference column, obtaining the multiple third readings.

9. The method according to any one of claims 1 to 4, characterized in that One of the first column group and the second column group includes each reference column with an odd position serial number in the column direction, and the other of the first column group and the second column group includes each reference column with an even position serial number.

10. A MRAM, characterized in that, Including: One or more processors, a memory, and one or more programs, where the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include methods for executing any one of claims 1 to 9.

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