Etching method of buffer layer
By adding the top oxide layer to the top nitride layer of the buffer layer multilayer film and performing etching, the problem of etching by-product adhesion is solved, and the reliability of the product is improved.
Patent Information
- Application Number
- CN202510293729.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-07-08
AI Technical Summary
When etching open the buffer layer above the top metal layer, the etching by-products tend to adhere to the side walls and bottom of the trench, affecting the packaging reliability of the product.
A top oxide layer is added to the top nitride layer of the buffer layer multilayer film, and etching is performed after removing the photoresist in the target area by exposure and development, forming a trench to expose the top metal layer.
Reduces the generation of etching by-products and improves product reliability.
Smart Images
Figure CN120280341A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular, to an etching method for a buffer layer. Background Art
[0002] The buffer layer (passivation layer) is the last process in the manufacture of semiconductor integrated circuits, and is used to protect the entire chip. The buffer layer thin film structure generally includes a silicon nitride (Si3N4) layer / an oxide layer / a titanium nitride (TiN) layer / an aluminum (Al) metal layer. Since copper (Cu) has good electrical conductivity and has good performance in automotive-grade electronic applications, the top aluminum metal layer is discarded during manufacture, so that the passivation layer is directly covered on the surface of the top copper metal layer of the metal interconnect structure, and then the dielectric layer above the top copper metal layer is etched open through a photolithography process so as to connect the lead to the top copper metal layer subsequently. While realizing chip functions such as electrode lead-out, the manufacturing cost is reduced.
[0003] Reference Figure 1 , which shows a schematic cross-sectional view of etching the dielectric layer above the top copper metal layer provided in the related art. Exemplarily, as Figure 1 shown, a first inter-layer dielectric (ILD) layer 120 is formed on a substrate 110, a second inter-layer dielectric layer 131 and a third inter-layer dielectric layer 132 are formed on the first inter-layer dielectric layer 120. Among them, a top copper metal layer 140 is formed in the third inter-layer dielectric layer 132. A first buffer layer 151, a second buffer layer 152 and a third buffer layer 153 are sequentially formed on the third inter-layer dielectric layer 132. The third buffer layer 153 includes a silicon nitride layer. After etching through a photolithography process, a trench 301 is formed in the buffer layer, and the top copper metal layer 140 at the bottom of the trench 301 is exposed.
[0004] However, before etching and opening the first buffer layer 151 and the second buffer layer 152 below the third buffer layer 153, it is usually necessary to use oxygen (O2) to consume the photoresist completely. Therefore, in the over-etching step of etching the first buffer layer 151 and the second buffer layer 152, in order to ensure sufficient etching amount, the plasma will bombard both copper and silicon nitride simultaneously, resulting in relatively serious by-products containing nitrogen element (N), fluorine element (F) and oxygen element (O) formed by the etched silicon nitride adhering to the side walls and the bottom of the trench, thereby affecting the packaging reliability of the product. Summary of the Invention
[0005] The present application provides an etching method for a buffer layer, which can solve the problem that etching by-products are easily formed when opening the buffer layer above the top metal layer provided in the related art. The method includes:
[0006] A top oxide layer is formed on the buffer layer multi-layer film, which includes a top nitride layer and at least one dielectric layer located below the top nitride layer from bottom to top. The buffer layer multi-layer film is formed on a metal interconnect structure, and a top metal layer is formed in the top interlayer dielectric layer of the metal interconnect structure. The metal interconnect structure is formed on a substrate;
[0007] A photoresist is covered on the top oxide layer;
[0008] The photoresist in the target area is removed by exposure and development in sequence;
[0009] Etching is performed to remove the top oxide layer and the buffer layer multi-layer film in the target area, and a trench is formed in the top oxide layer and the buffer layer multi-layer film to expose the top metal layer at the bottom of the trench.
[0010] In some embodiments, the top metal layer includes a copper layer.
[0011] In some embodiments, the at least one dielectric layer includes at least one silicon dioxide layer.
[0012] In some embodiments, the metal interconnect structure includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer from bottom to top in sequence, and the top metal layer is formed in the third interlayer dielectric layer.
[0013] In some embodiments, the first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer include silicon dioxide layers.
[0014] The technical solution of the present application has at least the following advantages:
[0015] By adding a top oxide layer on the top nitride layer of the buffer layer multi-layer film, when etching to open the buffer layer and the top oxide layer above the top metal layer through the photolithography process, it can avoid the plasma of etching from bombarding the nitride and the metal layer simultaneously, thereby reducing the generation of etching by-products and improving the reliability of the product. Description of the Drawings
[0016] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.
[0017] Figure 1It is a schematic cross-sectional view of etching a dielectric layer above a top copper metal layer provided in the related art;
[0018] Figure 2 It is a flowchart of an etching method for a buffer layer provided by an exemplary embodiment of the present application;
[0019] Figure 3 It is a schematic etching view of a buffer layer provided by an exemplary embodiment of the present application. Detailed implementation manners
[0020] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.
[0021] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0022] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
[0023] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0024] Refer to Figure 2 , which shows a flowchart of an etching method for a buffer layer provided by an exemplary embodiment of the present application. As Figure 2 shown, the method includes:
[0025] Step S1, form a top oxide layer on the buffer layer multi-layer film, which includes a top nitride layer and at least one dielectric layer below the top nitride layer from bottom to top. The buffer layer multi-layer film is formed on a metal interconnect structure, and a top metal layer is formed in the top interlayer dielectric layer of the metal interconnect structure. The metal interconnect structure is formed on a substrate.
[0026] Step S2, cover a photoresist on the top oxide layer.
[0027] Step S3, remove the photoresist in the target area by exposure and development in sequence.
[0028] Step S4, perform etching to remove the top oxide layer and the buffer layer multi-layer film in the target area, and form a trench in the top oxide layer and the buffer layer multi-layer film to expose the top metal layer at the bottom of the trench.
[0029] Reference Figure 3 , which shows a schematic diagram of etching the buffer layer. Exemplarily, as Figure 3 shown, a metal interconnect structure is formed on a substrate 210, which includes a first interlayer dielectric layer 220, a second interlayer dielectric layer 231, and a third interlayer dielectric layer 232 from bottom to top (it should be noted that Figure 3 uses three interlayer dielectric layers as an exemplary illustration, and the number of interlayer dielectric layers can be set according to requirements in actual applications). A top metal layer 240 is formed in the top third interlayer dielectric layer 232. The top metal layer 240 may include a copper layer. A buffer layer multi-layer film is formed on the third interlayer dielectric layer 232, which includes a first dielectric layer 251, a second dielectric layer 252, and a top nitride layer 253. A top oxide layer 260 is formed on the top nitride layer 253. Among them, the first dielectric layer 251 is nitride-doped and the second dielectric layer 252 includes a silicon dioxide layer. The first interlayer dielectric layer 220, the second interlayer dielectric layer 231, and the third interlayer dielectric layer 232 include silicon dioxide layers.
[0030] A photoresist can be covered on the top oxide layer 260 ( Figure 3 not shown in the figure). Remove the photoresist in the target area (the target area is the area corresponding to the trench 302) by exposure and development in sequence, perform etching to remove the top oxide layer 260 and the buffer layer multi-layer film in the target area, and form a trench 302 in the top oxide layer 260 and the buffer layer multi-layer film to expose the top metal layer 240 at the bottom of the trench 302. As Figure 3 shown, since a top oxide layer 260 is formed on the buffer layer multi-layer film, it is possible to avoid the plasma from bombarding the top nitride layer 253 and the top metal layer 260 simultaneously (the sidewall of the trench 302 is relatively steep, and the bombardment of the plasma on the top nitride layer 253 below the top oxide layer 260 can be ignored).
[0031] In summary, in the embodiments of the present application, by adding a top oxide layer on the top nitride layer of the buffer layer multi-layer film, when etching to open the buffer layer and the top oxide layer above the top metal layer through a lithography process, it is possible to avoid the plasma of etching from bombarding the nitride and the metal layer simultaneously, thereby reducing the generation of etching by-products and improving the reliability of the product.
[0032] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.
Claims
1. An etching method for a buffer layer, characterized in that, Comprising: Forming a top oxide layer on a buffer layer multi-layer film, the buffer layer multi-layer film including a top nitride layer and at least one dielectric layer located below the top nitride layer from bottom to top, the buffer layer multi-layer film being formed on a metal interconnect structure, a top metal layer being formed in the top interlayer dielectric layer of the metal interconnect structure, and the metal interconnect structure being formed on a substrate; Covering a photoresist on the top oxide layer; Removing the photoresist in a target area by exposure and development in sequence; Performing etching to remove the top oxide layer and the buffer layer multi-layer film in the target area, forming a trench in the top oxide layer and the buffer layer multi-layer film, and exposing the top metal layer at the bottom of the trench.
2. The method according to claim 1, characterized in that, The top metal layer includes a copper layer.
3. The method according to claim 1 or 2, characterized in that, The at least one dielectric layer includes at least one silicon dioxide layer.
4. The method according to claim 3, characterized in that The metal interconnect structure sequentially includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer from bottom to top, and the top metal layer is formed in the third interlayer dielectric layer.
5. The method according to claim 4, characterized in that, The first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer include silicon dioxide layers.