Substrate structure and manufacturing method thereof

Abstract

The invention discloses a substrate structure and a manufacturing method of the substrate structure, relates to the technical field of semiconductor packaging, and aims at solving the problem that in an existing substrate structure, thermal stress is generated at the interface of a conductive column and a substrate when the temperature changes, so that cracks appear on the interface. The substrate structure comprises a substrate, a conductive column, a dielectric layer and a circuit layer. The substrate is provided with a first surface and a second surface which are opposite, and a through hole penetrating through the first surface and the second surface; the through hole is filled with the conductive column, the conductive column is sequentially divided into a first conductive section, a second conductive section and a third conductive section in the axial direction of the through hole, the first conductive section and the third conductive section are adjacent to the first face and the second face of the substrate respectively, and gaps exist between the first conductive section and the inner wall of the through hole and between the third conductive section and the inner wall of the through hole; the dielectric layer covers the first surface and the second surface of the substrate, and part of the dielectric layer fills the gap; and the circuit layer is arranged in the dielectric layer and is conductively connected with the end part of the first conductive section and the end part of the third conductive section.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly relates to a substrate structure and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor packaging, with the continuous improvement of chip integration and performance requirements, higher requirements are put forward for the performance and reliability of the substrate. As an important carrier for connecting the chip and the external circuit, the structural design and manufacturing process of the substrate directly affect the electrical performance and stability of the package.

[0003] During the use of traditional substrate structures, due to the influence of factors such as thermal stress and mechanical stress, problems such as connection failure between the conductive posts and the substrate and degradation of insulation performance are likely to occur, thus affecting the reliability and service life of the package. When the temperature changes, due to the different thermal expansion coefficients of the conductive material and the substrate material, thermal stress will be generated at the interface between the conductive post and the substrate, resulting in cracks at the interface, and further affecting the stability of the electrical connection.

[0004] To solve the above problems, various measures have been taken in the prior art, such as optimizing the substrate material and improving the manufacturing process of the conductive posts. However, these methods still have certain limitations in practical applications and cannot fully meet the requirements of high-performance packaging. Summary of the Invention

[0005] The purpose of the present invention is to provide a substrate structure and a manufacturing method thereof to reduce the interfacial thermal stress generated during temperature changes, inhibit the generation of cracks on the substrate, and improve the stability of the substrate structure and the packaging reliability.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] In the first aspect, the present invention provides a substrate structure, including:

[0008] A substrate having opposite first and second surfaces and through holes penetrating the first and second surfaces;

[0009] Conductive posts filled in the through holes, the conductive posts are sequentially divided into a first conductive section, a second conductive section, and a third conductive section along the axial direction of the through holes. Among them, the first conductive section and the third conductive section are respectively adjacent to the first surface and the second surface of the substrate, and both have gaps with the inner wall of the through holes; the diameter of the second conductive section is larger than the diameters of the first conductive section and the third conductive section;

[0010] A dielectric layer covering the first surface and the second surface of the substrate, and part of the dielectric layer fills the gaps;

[0011] The circuit layer is disposed in the dielectric layer and is electrically connected to the ends of the first conductive segment and the third conductive segment.

[0012] Compared with the prior art, for the substrate structure provided by the present invention, by providing conductive posts in the through holes, the conductive posts are divided into a first conductive segment, a second conductive segment, and a third conductive segment. The diameter of the second conductive segment is larger than that of the first conductive segment and the third conductive segment at both ends, and a gap is formed between the first conductive segment and the third conductive segment and the inner wall of the through hole. The gap is filled with a dielectric layer and the surface of the substrate is covered, thereby solving the problems of thermal stress concentration and crack propagation caused by the difference in the thermal expansion coefficients of the conductive material and the substrate during the lamination process. Specifically, the second conductive segment serves as the main conductive channel, while the diameters of the first and third conductive segments at both ends are reduced and separated from the inner wall of the through hole, enabling the dielectric layer to fill the gap and form a flexible buffer zone. The dielectric layer can absorb the thermal expansion difference between the conductive material and the substrate during electroplating and curing processes, dispersing the interfacial stress; at the same time, only the middle second conductive segment is in direct contact with the substrate, reducing the contact area between the conductive material and the substrate and lowering the stress peak. The above structural design significantly reduces the maximum principal stress in the through hole area by reducing the direct contact area between the conductive material and the substrate and utilizing the elastic deformation of the dielectric layer to absorb stress, thereby improving the structural stability and packaging reliability of the substrate.

[0013] Optionally, in the above substrate structure, the first conductive segment and the third conductive segment have the same diameter, and are both greater than or equal to 0.6 times the diameter of the second conductive segment and less than or equal to 0.9 times the diameter of the second conductive segment.

[0014] Optionally, in the above substrate structure, the ends of the first conductive segment and the third conductive segment respectively extend out of the first surface and the second surface of the substrate.

[0015] Optionally, in the above substrate structure, the material of the dielectric layer is ABF, RCC, or polyimide.

[0016] Optionally, in the above substrate structure, the substrate is a glass substrate.

[0017] Optionally, in the above substrate structure, the axial length of the second conductive segment is 60%-90% of the total length of the conductive post.

[0018] Optionally, in the above substrate structure, the material of the conductive post is copper.

[0019] In a second aspect, the present invention also provides a method for manufacturing a substrate structure, including:

[0020] Providing a substrate; the substrate has opposite first and second surfaces, and a through hole penetrating the first and second surfaces;

[0021] Filling a conductive material in the through hole to form a conductive post penetrating the substrate;

[0022] Wet-etch both ends of the conductive column so that both ends of the conductive column are retracted into the through-hole relative to the first surface and the second surface of the substrate respectively to form a second conductive segment;

[0023] Laminating dielectric layers on the first surface and the second surface of the substrate, so that the dielectric layers cover the surface of the substrate and partially fill the spaces between both ends of the second conductive segment and both end faces of the through-hole;

[0024] Open holes in the dielectric layer to form openings exposing the ends of the second conductive segment; wherein, the aperture of the opening is smaller than the diameter of the second conductive segment;

[0025] Electroplating a metal material in the opening to form a first conductive segment and a third conductive segment connected to the second conductive segment;

[0026] Form a circuit layer on the dielectric layer, such that the circuit layer is electrically connected to the ends of the first conductive segment and the third conductive segment.

[0027] Compared with the prior art, in the manufacturing method of the substrate structure provided by the present invention, first, a conductive material is filled in the through-hole of the substrate to form a conductive column penetrating the substrate, and then both ends of the conductive column in the through-hole are wet-etched so that both ends of the conductive column are retracted to form the middle second conductive segment, thereby directly reducing the thermal stress generated due to the difference in the coefficient of thermal expansion by reducing the contact area between the conductive material and the substrate; subsequently, dielectric layers are laminated and the gaps between both ends of the second conductive segment and the through-hole are filled, and the elastic deformation of the dielectric layers is utilized to absorb the thermal expansion difference, converting the rigid stress into recoverable deformation of the flexible buffer zone; then, openings smaller than the diameter of the second conductive segment are formed by laser drilling, and a first conductive segment and a third conductive segment at both ends are electroplated in the openings, the diameters of which are reduced and separated from the inner wall of the through-hole to form gaps for the dielectric layers to fill, and then a circuit layer is formed on the dielectric layer, such that the circuit layer is electrically connected to the ends of the first conductive segment and the third conductive segment, so that while realizing double-sided electrical interconnection of the substrate, the thermal stress is absorbed through the elastic deformation of the insulating layer. Thus, the maximum principal stress at the interface is significantly reduced, thereby improving the structural stability and packaging reliability of the substrate.

[0028] Optionally, in the manufacturing method of the above-mentioned substrate structure, opening holes in the dielectric layer to form openings exposing the ends of the second conductive segment specifically includes: laser-drilling the dielectric layer to form openings exposing the ends of the second conductive segment. Description of the Drawings

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0030] Figure 1Schematic cross-sectional structure diagram of a substrate structure provided by an embodiment of the present invention;

[0031] Figure 2 is Figure 1 An enlarged schematic diagram of area a in;

[0032] Figure 3 Schematic cross-sectional structure diagram of a substrate structure in the prior art;

[0033] Figure 4 is Figure 3 An enlarged schematic diagram of area b in;

[0034] Figure 5 Top view schematic diagram of a substrate structure provided by an embodiment of the present invention;

[0035] Figure 6 Cross-sectional schematic diagram of a substrate structure provided by an embodiment of the present invention after opening through holes;

[0036] Figure 7 Cross-sectional schematic diagram of a substrate structure provided by an embodiment of the present invention after filling with conductive material;

[0037] Figure 8 Cross-sectional schematic diagram of a substrate structure provided by an embodiment of the present invention after wet etching;

[0038] Figure 9 Cross-sectional schematic diagram of a substrate structure provided by an embodiment of the present invention after laminating a dielectric layer;

[0039] Figure 10 Cross-sectional schematic diagram of a substrate structure provided by an embodiment of the present invention after opening holes in the dielectric layer;

[0040] Figure 11 Cross-sectional schematic diagram of a substrate structure provided by an embodiment of the present invention after electroplating a metal material;

[0041] Figure 12 Stress diagram of a through hole filled with conductive material in a simulated substrate structure after temperature cycling;

[0042] Figure 13 Stress diagram of a through hole with a shortened filling height of conductive material in a simulated substrate structure after temperature cycling;

[0043] Figure 14 Flowchart of a manufacturing method of a substrate structure provided by an embodiment of the present invention.

[0044] Reference numerals: 1 is the substrate, 10 is the through hole, 2 is the conductive column, 20 is the first conductive segment, 21 is the second conductive segment, 22 is the third conductive segment, 3 is the dielectric layer, 4 is the circuit layer, 5 is the crack. Detailed implementation manners

[0045] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0047] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined. "Several" means one or more unless otherwise specifically defined.

[0048] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0049] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0050] In the first aspect, please refer to Figure 1, the substrate 1 structure provided by the present invention includes a substrate 1, conductive posts 2, a dielectric layer 3, and a circuit layer 4; wherein, the substrate 1 has opposite first and second surfaces, and a through hole 10 penetrating the first and second surfaces; the conductive posts 2 are filled in the through hole 10, and the conductive posts 2 are sequentially divided into a first conductive section 20, a second conductive section 21, and a third conductive section 22 along the axial direction of the through hole 10, wherein the first conductive section 20 and the third conductive section 22 are respectively adjacent to the first and second surfaces of the substrate 1, and both have a gap with the inner wall of the through hole 10; the second conductive section 21 is located between the first conductive section 20 and the third conductive section 22, and the diameter of the second conductive section 21 is greater than the diameters of the first conductive section 20 and the third conductive section 22; the dielectric layer 3 covers the first and second surfaces of the substrate 1, and part of the dielectric layer 3 fills the gap; the circuit layer 4 is disposed in the dielectric layer 3 and is electrically connected to the ends of the first conductive section 20 and the third conductive section 22.

[0051] In specific implementation: a conductive post 2 is disposed in the through hole 10, and the conductive post 2 is divided into a first conductive section 20, a second conductive section 21, and a third conductive section 22, wherein the diameter of the second conductive section 21 is greater than those of the first conductive section 20 and the third conductive section 22 at both ends, and a gap is formed between the first conductive section 20 and the third conductive section 22 and the inner wall of the through hole 10. The gap is filled by the dielectric layer 3 and the surface of the substrate 1 is covered, solving the problems of thermal stress concentration and crack 5 propagation caused by the difference in thermal expansion coefficients between the conductive material and the substrate 1 in the lamination process. Specifically, the second conductive section 21 serves as the main conductive channel, while the diameters of the first and third conductive sections 22 at both ends are reduced and separated from the inner wall of the through hole 10, enabling the dielectric layer 3 to fill the gap and form a flexible buffer zone. The dielectric layer 3 can absorb the thermal expansion difference between the conductive material and the substrate 1 during the electroplating and curing processes and disperse the interfacial stress; at the same time, only the middle second conductive section 21 is in direct contact with the substrate 1, reducing the contact area between the conductive material and the substrate 1 and lowering the stress peak. The above structural design significantly reduces the maximum principal stress in the through hole 10 region by reducing the direct contact area between the conductive material and the substrate 1 and using the elastic deformation of the dielectric layer 3 to absorb stress, thereby improving the structural stability and packaging reliability of the substrate 1.

[0052] As a possible implementation, such as Figure 1 and Figure 2As shown, the diameters of the first conductive segment 20 and the third conductive segment 22 are the same, and are both greater than or equal to 0.6 times and less than or equal to 0.9 times the diameter of the second conductive segment 21. That is, the diameters of the first conductive segment 20 and the third conductive segment 22 can be 0.6 times, 0.7 times, 0.8 times, or 0.9 times the diameter of the second conductive segment 21, etc., or any value between 0.6 times and 0.9 times. With such a setting, by reducing the diameters of the first conductive segment 20 and the third conductive segment 22 at both ends of the conductive column 2, a uniform gap is formed between them and the inner wall of the through hole 10. This gap is completely filled by the dielectric layer 3. The elastic deformation of the flexible material is used to absorb the thermal stress between the conductive material and the substrate 1, converting the rigid interface stress into recoverable deformation, thereby reducing the peak value of the thermal stress. At the same time, the symmetric design of the first conductive segment 20 and the third conductive segment 22 at both ends ensures the balanced distribution of stress on both sides of the substrate 1, avoiding local stress concentration caused by diameter differences and further suppressing the generation of cracks 5. In addition, the first conductive segment 20 and the third conductive segment 22 and the middle second conductive segment 21 form a continuous conductive channel. While realizing the double-sided conductive interconnection of the substrate 1, a physical isolation zone is formed by filling the gap with the dielectric layer 3, blocking the path for the crack 5 to extend into the interior of the substrate 1.

[0053] Meanwhile, the setting of this diameter ratio range achieves the coordination of multiple effects. First, in terms of conductive function and stress buffering, if the ratio is too small (i.e., the diameters of the first conductive segment 20 and the third conductive segment 22 are less than 0.6 times the diameter of the second conductive segment 21), it is easy to cause too high current density and exacerbate the temperature rise. If the ratio is too large (i.e., the diameters of the first conductive segment 20 and the third conductive segment 22 are greater than 0.9 times the diameter of the second conductive segment 21), the gap buffering ability will be weakened. While the range of 0.6 - 0.9 times can take into account both the conductive performance and stress absorption at the same time.

[0054] As a possible implementation method, please refer to Figure 1 and Figure 2 , the end parts of the first conductive segment 20 and the third conductive segment 22 respectively extend out of the first surface and the second surface of the substrate 1.

[0055] This structural configuration means that on both sides of the substrate 1, the first conductive segment 20 and the third conductive segment 22 extend beyond the boundary range of the substrate 1 itself. With such a setting, since the ends of the first conductive segment 20 and the third conductive segment 22 play the role of electrically connecting with the external circuit layer 4, after extending out of the first surface and the second surface of the substrate 1, they can provide a larger contact area for the electrical connection with the external circuit. Compared with the non-extended situation, the connection stability is greatly enhanced. And the larger contact area can effectively reduce the contact resistance and reduce the risk of signal interruption caused by poor contact, ensuring that the current can conduct smoothly and stably between the conductive posts 2 and the external circuit layer 4, thereby improving the reliability of the entire substrate 1 structure in terms of electrical connection and laying a solid foundation for realizing high-performance circuit functions.

[0056] As a possible implementation, the material of the dielectric layer 3 is ABF, RCC or polyimide.

[0057] Specifically, materials such as ABF (Ajinomoto Build-up Film), RCC (Resin Coated Copper), and polyimide, due to their excellent elasticity and flexibility, can absorb the stress generated by the thermal expansion difference between the conductive material and the substrate 1 through deformation, converting the rigid interface stress into recoverable deformation in the flexible buffer zone, thereby significantly reducing the peak value of the thermal stress in the via 10 region; at the same time, the high toughness of the above materials can effectively prevent the crack 5 from extending from the edge of the via 10 into the interior of the substrate 1, avoiding structural failure caused by stress concentration. The thermal expansion coefficients of the above materials are between the conductive material and the substrate 1, further alleviating the problem of interfacial thermal mismatch. In addition, the above materials have excellent fluidity during the curing process, can fully fill the micron-level gap between the conductive posts 2 and the via 10, and form a uniform covering layer to ensure the flatness of the surface of the substrate 1 to support the requirements of high-density wiring. Thus, the above materials cooperate with the segmented conductive post 2 design, through multi-faceted cooperation of elastic buffering, stress dispersion, and crack 5 suppression, while realizing the conductive function, significantly improving the mechanical stability and long-term reliability of the substrate 1 in high-temperature and high-density packaging scenarios.

[0058] As a possible implementation, the substrate 1 is a glass substrate. Specifically, the glass substrate has excellent flatness, which can ensure that various processes such as the filling of the conductive posts 2, the laying of the dielectric layer 3, and the fabrication of the circuit layer 4 on it can be carried out precisely and uniformly, thereby guaranteeing the high precision and consistency of the entire substrate 1. Its relatively low coefficient of thermal expansion has a relatively small difference from the coefficient of thermal expansion of the material of the conductive posts 2, which can effectively reduce the thermal stress generated at the interface due to temperature changes and reduce the risk of cracks 5 caused by thermal stress concentration. At the same time, the high stiffness of the glass substrate provides stable mechanical support in the entire structure of the substrate 1, can effectively resist external forces, prevent the substrate 1 from deforming, and further guarantee the integrity and stability of the internal structures such as the conductive posts 2, the dielectric layer 3, and the circuit layer 4, improving the reliability of the package. In addition, the glass substrate has good electrical properties such as high insulation resistance and low dielectric constant, which helps to improve the stability of signal transmission.

[0059] As a possible implementation, please refer to Figure 1 and Figure 2 , the axial length of the second conductive segment 21 is 60%-90% of the total length of the conductive post 2. This length ratio of the second conductive segment 21 ensures that the second conductive segment 21 can serve as the main conductive channel, undertaking the role of stably transmitting current and guaranteeing the conductivity of the entire conductive post 2. When the axial length of the second conductive segment 21 is within the range of 60%-90% of the total length of the conductive post 2, specifically, it can be a ratio of 60%, 70%, 80%, or 90%, etc., or any ratio within the range. The second conductive segment 21 can fully contact the inner wall of the through hole 10, effectively reducing the resistance and reducing the power loss. At the same time, this length ratio enables the first conductive segment 20 and the third conductive segment 22 at both ends of the conductive post 2 to have sufficient space at both ends to form a gap with the inner wall of the through hole 10 for the filling of the dielectric layer 3, so as to better disperse and absorb thermal stress. At the same time, the appropriate length of the second conductive segment 21 ensures the stability of the entire structure of the conductive post 2 in terms of mechanical properties. When subjected to external forces, it will not cause structural deformation or damage due to unreasonable length ratios of each segment, thereby ensuring the integrity of the internal dielectric layer 3 and the circuit layer 4 and other structures, and enhancing the reliability of the substrate 1 structure.

[0060] As a possible implementation method, the material of the conductive column 2 is copper. Copper has a high electrical conductivity, which can ensure that the current is efficiently transmitted in the conductive column 2, greatly reducing the power loss caused by resistance, thereby ensuring the stability and rapid transmission of the signal, and meeting the requirements of semiconductor packaging for electrical conductivity. Its good thermal conductivity also helps to quickly and evenly conduct heat when the temperature changes, reduce the concentration of thermal stress caused by excessive local temperature, and cooperate with the low thermal expansion coefficient characteristics of the glass substrate to further alleviate the impact of thermal stress on the structure of the substrate 1. In addition, copper has good processing performance and is easy to be accurately filled into the through hole 10 through processes such as electroplating to form the required structure. In subsequent process links such as wet etching, the processing effect can be accurately controlled to ensure the dimensional accuracy of each section of the conductive column 2, providing strong support for building a stable and reliable substrate 1 structure, and improving the reliability and stability of the entire semiconductor package.

[0061] Second, see Figures 6 - 11 The embodiment of the present invention further provides a method for manufacturing a substrate 1 structure, comprising the following steps:

[0062] Step S100: Please refer to Figure 5 and Figure 6 , a substrate 1 is provided, wherein the substrate 1 has a first surface and a second surface opposite to each other, and a through hole 10 penetrating the first surface and the second surface.

[0063] Step S200: Please refer to Figure 7 , filling the through hole 10 with a conductive material to form a conductive column 2 penetrating the substrate 1;

[0064] Step S300: Please refer to Figure 8 , wet-etching the two ends of the conductive pillar 2 so that the two ends of the conductive pillar 2 are respectively retracted into the through hole 10 relative to the first surface and the second surface of the substrate 1 to form a second conductive segment 21;

[0065] Step S400: Please refer to Figure 9 , laminating a dielectric layer 3 on the first surface and the second surface of the substrate 1, so that the dielectric layer 3 covers the surface of the substrate 1 and partially fills between the two ends of the second conductive segment 21 and the two end surfaces of the through hole 10;

[0066] Step S500: Please refer to Figure 10 , opening the dielectric layer 3 to form an opening exposing the end of the second conductive segment 21; wherein the aperture of the opening is smaller than the diameter of the second conductive segment 21;

[0067] Step S600: Please refer to Figure 11 , electroplating metal material in the opening to form a first conductive segment 20 and a third conductive segment 22 connected to the second conductive segment 21;

[0068] Step S700: Please refer toFigure 1 and Figure 2 , a circuit layer 4 is formed on the dielectric layer 3, such that the circuit layer 4 is electrically connected to the ends of the first conductive segment 20 and the third conductive segment 22.

[0069] In the substrate 1 structure formed by using the manufacturing method of the above substrate 1 structure, through the segmented design of the conductive posts 2 and the processing technology of the dielectric layer 3, the stability of the substrate 1 structure is improved. Specifically, wet etching is performed on both ends of the conductive posts 2 formed in the through holes 10 to form a gap by inward shrinking. This structure reduces the contact area between the conductive posts 2 and the substrate 1, making the generated heat stress concentration area smaller; at the same time, the dielectric layer covers the surface of the substrate 1 and fills the gap, and uses its elastic buffering characteristics to absorb stress and avoid the generation of interface cracks. In the manufacturing method of the above substrate 1 structure, the middle conductive segment is first formed by wet etching, and then openings are formed in the dielectric layer 3 and electroplated to form the two-end conductive segments. This step-by-step forming method not only ensures the strength of the main structure of the conductive posts 2, but also realizes physical isolation from the substrate 1 by reducing the diameters of both ends. This method, through structural optimization and process coordination, takes into account both the conductive performance and the stress resistance ability while optimizing the steps, reduces the generation of interface cracks, and improves the structural stability and packaging reliability of the substrate 1.

[0070] As a possible implementation, please refer to Figure 10 , openings are formed in the dielectric layer 3 to expose the ends of the second conductive segment 21, specifically including: using ultraviolet laser to perform laser opening on the dielectric layer 3 to form openings that expose the ends of the second conductive segment 21.

[0071] Specifically, this method utilizes the high energy density and high focusing characteristics of the ultraviolet laser, and can precisely process the dielectric layer 3. The wavelength of the ultraviolet laser is relatively short, and when interacting with the material of the dielectric layer 3, it can achieve fine thermal processing, thereby precisely removing the material at the position where the opening needs to be formed, and at the same time reducing the thermal influence on the surrounding dielectric layer 3 and the second conductive segment 21. On the one hand, the high precision of the ultraviolet laser enables the opening size and position to be formed strictly according to the design requirements, ensuring that the opening aperture is smaller than the diameter of the second conductive segment 21, providing a prerequisite for the formation of the first conductive segment 20 and the third conductive segment 22 in the subsequent process; on the other hand, this non-contact processing method avoids the material damage and stress concentration that may be brought by mechanical opening, ensures the integrity and performance of the dielectric layer 3, lays a good foundation for electroplating metal materials in the opening and constructing a stable and reliable electrical connection later, and improves the precision and stability of the entire manufacturing process of the substrate 1 structure.

[0072] As Figure 12 shown, Figure 12 is a stress diagram of a through hole after temperature cycling in a state where the through hole of a simulated substrate structure is fully filled with conductive material; as Figure 13As shown Figure 13 Under the state where the filling height of the conductive material in the through-hole of a simulation substrate structure with the same substrate structure as that in the present application provided by the embodiment of the present invention is shortened, it is a stress diagram of the through-hole after temperature cycling. It can be understood that through appropriate temperature cycling, the effect of temperature increase in the electroplating and curing processes can be simulated. The temperature in one temperature cycle can be 25°C - 190°C to achieve a better simulation effect. It can be seen that by shortening the height of the conductive column, the stress distribution is optimized. During the electroplating and curing processes, the maximum value of the first principal stress in the through-hole will be correspondingly reduced, thereby achieving the purpose of reducing the stress in the through-hole and avoiding crack generation.

[0073] In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0074] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claimed rights.

Claims

1. A substrate structure, characterized in that, Comprising: A substrate having opposite first and second surfaces and a through hole penetrating the first and second surfaces; A conductive post filled in the through hole, the conductive post being successively divided into a first conductive section, a second conductive section, and a third conductive section along the axial direction of the through hole. Wherein, the first conductive section and the third conductive section are respectively adjacent to the first and second surfaces of the substrate and both have a gap with the inner wall of the through hole; the diameter of the second conductive section is larger than the diameters of the first conductive section and the third conductive section; A dielectric layer covering the first and second surfaces of the substrate, and a part of the dielectric layer filling the gap; A circuit layer disposed in the dielectric layer and electrically connected to the ends of the first conductive section and the third conductive section.

2. The substrate structure according to claim 1, wherein The diameters of the first conductive section and the third conductive section are the same, and are both greater than or equal to 0.6 times the diameter of the second conductive section and less than or equal to 0.9 times the diameter of the second conductive section.

3. The substrate structure according to claim 1, wherein The ends of the first conductive section and the third conductive section respectively extend out of the first and second surfaces of the substrate.

4. The substrate structure according to claim 1, wherein The material of the dielectric layer is ABF, RCC or polyimide.

5. The substrate structure according to claim 1, wherein The substrate is a glass substrate.

6. The substrate structure according to claim 1, characterized in that, The axial length of the second conductive section is 60%-90% of the total length of the conductive post.

7. The substrate structure according to claim 1, wherein, The material of the conductive post is copper.

8. A manufacturing method of a substrate structure, characterized in that, Comprising: Providing a substrate having opposite first and second surfaces and a through hole penetrating the first and second surfaces; Filling a conductive material in the through hole to form a conductive post penetrating the substrate; Wet etching the two ends of the conductive post so that the two ends of the conductive post are respectively retracted into the through hole relative to the first and second surfaces of the substrate to form a second conductive section; Laminating a dielectric layer on the first and second surfaces of the substrate so that the dielectric layer covers the surface of the substrate and partially fills the spaces between the two ends of the second conductive section and the two end faces of the through hole; Performing hole opening on the dielectric layer to form an opening exposing the end of the second conductive section; wherein, the aperture of the opening is smaller than the diameter of the second conductive section; Electroplating a metal material in the opening to form a first conductive section and a third conductive section connected to the second conductive section; Forming a circuit layer on the dielectric layer such that the circuit layer is electrically connected to the ends of the first conductive section and the third conductive section.

9. The manufacturing method of the substrate structure according to claim 8, characterized in that, The performing hole opening on the dielectric layer to form an opening exposing the end of the second conductive section specifically includes: performing laser hole opening on the dielectric layer to form an opening exposing the end of the second conductive section.

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