Control method and device of two-stage bidirectional DC-DC converter and medium

Abstract

The invention discloses a control method and device for a two-stage bidirectional DC-DC converter and a medium, and relates to the technical field of power conversion, and the method comprises the steps: achieving the adjustment of the gain of each CLLLC branch through fixing the duty ratio of a primary side switch tube of each CLLLC branch, and controlling the switching frequency of the primary side switch tube of each CLLLC branch; meanwhile, after the switching frequency of the switching tube of each BUCK branch or each BOOST branch is fixed, the duty ratio of the switching tube of each BUCK branch or each BOOST branch is controlled through a PI loop, the gain of each BUCK branch or each BOOST branch is adjusted, the overall gain of the converter depends on the combination of the gain of the CLLLC branch and the gain of the BUCK branch or the gain of the BOOST branch, and the overall gain of the converter is adjusted. Therefore, the overall gain of the forward and reverse two-stage converter of the two-stage bidirectional DC-DC converter can be flexibly controlled, so that the output of voltage in a wider range is realized.

Description

Technical Field

[0001] The present application relates to the technical field of power conversion, and particularly to a control method, device and medium for a two-stage bidirectional DC-DC converter. Background Art

[0002] With the continuous progress of power electronics technology, bidirectional DC_DC converters with a wide voltage range are increasingly widely used, mainly in the charging and discharging of electric vehicle batteries, realizing bidirectional energy flow. The CLLLC branch can achieve soft switching within the full load range near the resonant switching frequency. It has excellent soft-switching characteristics, as well as advantages such as high efficiency and high power density, and has become the focus of research in the power supply industry. With the increasing demand for bidirectional CLLLC high-power switching power supplies, the popularization of high-power application scenarios, and the expansion of the required output voltage range, the traditional single-stage bidirectional CLLLC branch can no longer meet the requirements of wider voltage and power output. To pursue a wider voltage range, higher power density, higher efficiency, lower cost and smaller volume, researchers have proposed multi-path parallel bidirectional CLLLC and BUCK-BOOST branches to share power, reduce the output current ripple through interleaved parallel technology, and use a two-stage bidirectional DC_DC converter to achieve a wide voltage range output.

[0003] However, if current imbalance occurs in the multi-path parallel two-stage bidirectional DC_DC branches, it may cause overheating or even damage to the devices in the branch with excessive current, which will bring serious safety hazards. With the increase in the number of parallel branches, it is difficult to keep the magnetic device parameters of each branch consistent, and the parameter inconsistency will lead to current imbalance in each branch, which will seriously affect the reliability of the circuit. Given the continuous expansion of the battery voltage range of electric vehicles and the increasing requirements for charging and discharging power and rate, how to effectively control the branches of the two-stage bidirectional DC-DC converter to achieve a wider voltage range output is crucial for improving the performance and reliability of the converter. Summary of the Invention

[0004] The purpose of the present application is to provide a control method, device and medium for a two-stage bidirectional DC-DC converter, which can achieve a wider voltage range output and improve the performance and reliability of the converter.

[0005] To achieve the above object, the present application provides the following solutions: In a first aspect, the present application provides a control method for a two-stage bidirectional DC-DC converter. The two-stage bidirectional DC-DC converter includes a bidirectional CLLLC circuit and a bidirectional BUCK-BOOST circuit. The bidirectional CLLLC circuit includes a plurality of bidirectionally interleaved CLLLC branches. The primary sides of the forward and reverse CLLLC branches adopt interleaved phase control, and the secondary sides of each CLLLC branch adopt synchronous rectification control. The bidirectional BUCK-BOOST circuit includes a plurality of bidirectionally interleaved BUCK-BOOST branches. The BUCK-BOOST branch includes a BUCK branch and a BOOST branch. The primary sides of the forward and reverse BUCK-BOOST branches adopt interleaved phase control. The control method for the two-stage bidirectional DC-DC converter includes the following steps: Fix the duty cycle of the primary switch tubes of each CLLLC branch, and adjust the gain of each CLLLC branch by controlling the switching frequency of the primary switch tubes of each CLLLC branch.

[0006] Fix the switching frequency of the switch tubes of each BUCK branch or each BOOST branch, and adjust the gain of each BUCK branch or each BOOST branch by controlling the duty cycle of the switch tubes of each BUCK branch or each BOOST branch through a PI loop.

[0007] In a second aspect, the present application provides a computer device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. The processor executes the computer program to implement the steps of the control method for a two-stage bidirectional DC-DC converter described above.

[0008] In a third aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the control method for a two-stage bidirectional DC-DC converter described above.

[0009] According to the specific embodiments provided by the present application, the following technical effects are disclosed in the present application: The present application provides a control method, device and medium for a two-stage bidirectional DC-DC converter. In this control method, by fixing the duty cycle of the primary switching tubes of each CLLLC branch and controlling the switching frequency of the primary switching tubes of each CLLLC branch, the gain of each CLLLC branch is adjusted. At the same time, after fixing the switching frequency of the switching tubes of each BUCK branch or each BOOST branch, the duty cycle of the switching tubes of each BUCK branch or each BOOST branch is controlled through a PI loop to adjust the gain of each BUCK branch or each BOOST branch. In this way, the overall gain of the forward and reverse two-stage converters of the two-stage bidirectional DC-DC converter can be flexibly controlled, so as to achieve the output of a wider range of voltages, thereby greatly improving the performance and reliability of the two-stage bidirectional DC-DC converter. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 It is a flowchart of a control method for a two-stage bidirectional DC-DC converter provided by an embodiment of the present application.

[0012] Figure 2 It is a schematic diagram of the voltage gain of the bidirectional CLLLC circuit in the frequency modulation mode in the method provided by an embodiment of the present application.

[0013] Figure 3 It is a schematic diagram comparing the output current ripples of two CLLLC branches with a phase difference of π / 2 in the method provided by an embodiment of the present application.

[0014] Figure 4 It is a schematic diagram comparing the output current ripples of two BUCK-BOOST branches with a phase difference of π in the method provided by an embodiment of the present application.

[0015] Figure 5 It is a schematic diagram of the forward gain curve of the two-stage bidirectional DC-DC converter in the method provided by an embodiment of the present application.

[0016] Figure 6 It is a schematic diagram of the reverse gain curve of the two-stage bidirectional DC-DC converter in the method provided by an embodiment of the present application.

[0017] Figure 7 It is a schematic diagram of the circuit of an input-parallel output-parallel two-stage bidirectional DC-DC converter provided by an embodiment of the present application.

[0018] Figure 8 This is a schematic circuit diagram of a two - stage bidirectional DC - DC converter with input series and output parallel provided by an embodiment of the present application.

[0019] Figure 9 This is a schematic circuit diagram of a two - stage bidirectional DC - DC converter with input parallel and output series provided by an embodiment of the present application.

[0020] Figure 10 This is a schematic structural diagram of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0022] To make the above - mentioned objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0023] A control method for a two - stage bidirectional DC - DC converter provided by an embodiment of the present application. The two - stage bidirectional DC - DC converter includes a bidirectional CLLLC circuit and a bidirectional BUCK - BOOST circuit. The bidirectional CLLLC circuit includes a plurality of bidirectionally interleaved CLLLC branches. The primary sides of the forward and reverse CLLLC branches adopt interleaved phase control, and the secondary sides of each CLLLC branch adopt synchronous rectification control. The bidirectional BUCK - BOOST circuit includes a plurality of bidirectionally interleaved BUCK - BOOST branches. The BUCK - BOOST branch includes a BUCK branch and a BOOST branch. The primary sides of the forward and reverse BUCK - BOOST branches adopt interleaved phase control. As Figure 1 shown, the method includes the following steps: S1. Fix the duty cycle of the primary - side switching tubes of each CLLLC branch, and adjust the gain of each CLLLC branch by controlling the switching frequency of the primary - side switching tubes of each CLLLC branch.

[0024] In this embodiment, the gain of the CLLLC branch can be adjusted according to the following formula: .

[0025] Wherein, G ( Q , m , Fx) is the gain of the GLLLC branch, Q is the quality factor, , Lr is the inductance of the resonant inductor, Cr is the capacitance of the resonant capacitor, Rac is the equivalent resistance of the output load resistance reflected to the primary side, , N is the turns ratio of the primary and secondary sides of the transformer, R 0 is the equivalent resistance of the output load, Fx is the normalized switching frequency, , fs is the switching frequency of the primary switch of the CLLLC branch, fr is the resonant frequency of the primary switch of the CLLLC branch, m is the ratio of the total inductance of the primary side to the inductance of the resonant inductor, , Lm is the inductance of the exciting inductor, and the total inductance of the primary side is the sum of the inductance of the resonant inductor and the inductance of the exciting inductor.

[0026] According to the above formula, for different Q values and various different m values, the gain G of the CLLLC branch and the switching frequency fs are plotted as a curve as Figure 2 shown. According to the principle of the bidirectional CLLLC branch, the switching frequency range is selected in the design as: fmin < fs < fmax ; fmax It is determined according to the losses of different bidirectional CLLLC circuits. Through the combined control of the two-stage topology, the operating frequency fs of the CLLLC branch can work near the resonant point fr , thereby reducing the circuit losses of the CLLLC branch and increasing the transmission efficiency of the branch.

[0027] Specifically, the adjustment range of the switching frequency fs of the primary switch of the CLLLC branch is from the minimum switching frequency fmin to the maximum switching frequency fmax ; the relationship between the resonant frequency and the maximum / minimum switching frequency is: fmin < fr < fmax , where fmin = 60KHZ, fmax = 300KHZ, fr = 100KHZ.

[0028] S2. Fix the switching frequencies of the switching tubes in each BUCK branch or each BOOST branch, and control the duty cycles of the switching tubes in each BUCK branch or each BOOST branch through the PI loop to adjust the gains of each BUCK branch or each BOOST branch.

[0029] During forward and reverse operation, the switching frequency of the BUCK - BOOST branch is fixed at 40KHZ without adjustment.

[0030] During forward operation, the formula for calculating the duty cycle D2 of the BUCK branch is: D2 = Vout_buck / Vin_buck; where Vout_buck is the output voltage of the BUCK branch and Vin_buck is the input voltage of the BUCK branch. The value range of D2 is: 0 - 1; when D2 = 0, that is, Vout = 0, the BUCK branch has no output voltage; when D2 = 1, that is, Vout = Vin, the output voltage of the BUCK branch is equal to the input voltage.

[0031] During reverse operation, the formula for calculating the duty cycle D3 of the BOOST branch is: D3 = 1 - (Vin_boost / Vout_boost); where Vin_boost is the input voltage of the BOOST branch and Vout_boost is the output voltage of the BOOST branch. The value range of D3 is: 0 - 0.7; when D3 = 0, that is, Vin_boost = Vout_boost, the output voltage of the BOOST branch is equal to the input voltage, and the gain M4 of the BOOST branch is 1; when D3 = 0.7, that is, Vout_boost ≈ 3 * Vin_boost, the output voltage of the BOOST branch is approximately equal to 3 times the input voltage, and the gain M4 of the BOOST branch is 3; considering the inductor temperature rise and loss of the BOOST branch, the maximum gain M4 of the BOOST branch is 3, that is, the maximum value of the duty cycle D3 is 0.7.

[0032] Specifically in this embodiment, during the forward operation of the two - stage bidirectional DC - DC converter, the topological combination method is the CLLLC branch + BUCK branch, the input side is the CLLLC branch, and the output side is the BUCK branch; during the reverse operation of the two - stage bidirectional DC - DC converter, the topological combination method is the BOOST branch + CLLLC branch, the input side is the BOOST branch, and the output side is the CLLLC branch.

[0033] During the forward operation of the two - stage bidirectional DC - DC converter, step S2 in the above method specifically includes the following steps: A21. Fix the switching frequencies of the switching tubes in each BUCK branch, and obtain the current error factor by real - time detecting the current in the primary side of each BUCK branch.

[0034] A22. According to the voltage error factor between the given voltage and the actual output voltage of the parallel total output of each BUCK branch.

[0035] A23. According to the current error factor and the voltage error factor, through the negative feedback of the PI loop, adjust the duty cycle of the switching tubes of each BUCK branch to achieve the adjustment of the gain of each BUCK branch. In this embodiment, step A23 specifically includes the following steps: A231. Substitute the current error factor of the primary side of each BUCK branch into the calculation formula of the current sharing adjustment factor respectively to calculate the current sharing adjustment factor of each BUCK branch.

[0036] A232. According to the current sharing adjustment factor and the voltage error factor of each BUCK branch, through the negative feedback of the PI loop, adjust the duty cycle of the switching tubes of each BUCK branch.

[0037] When the two-stage bidirectional DC-DC converter operates in the reverse direction, step S2 in the above solution specifically includes the following steps: B21. Fix the switching frequency of the switching tubes of each BOOST branch, and obtain the current error factor by real-time detecting the current of the primary side of each BOOST branch.

[0038] B22. According to the voltage error factor between the given voltage and the actual output voltage of the parallel total output of each BOOST branch.

[0039] B23. According to the current error factor and the voltage error factor, through the negative feedback of the PI loop, adjust the duty cycle of the switching tubes of each BOOST branch to achieve the adjustment of the gain of each BOOST branch. In this embodiment, step B23 specifically includes the following steps: B231. Substitute the current error factor of the primary side of each BOOST branch into the calculation formula of the current sharing adjustment factor respectively to obtain the current sharing adjustment factor of each BOOST branch.

[0040] B232. According to the current sharing adjustment factor and the voltage error factor of each BOOST branch, through the negative feedback of the PI loop, adjust the duty cycle of the switching tubes of each BOOST branch.

[0041] Embodiment 2 In this embodiment, the PWM wave generation of each CLLLC branch in the bidirectional interleaving is out of phase by 90°, and the switching frequency of the synchronous rectification of the secondary side switching tubes of each CLLLC branch is the same as that of the primary side switching tubes; the PWM switching frequencies of each BUCK-BOOST branch in the bidirectional interleaving are the same, and the PWM wave generation between each BUCK-BOOST branch is out of phase by 180°, which can effectively reduce the output current ripple.

[0042] For a two-way interleaved parallel CLLLC circuit, to achieve two-way interleaved parallel connection, the switching frequencies of the two paths need to be the same to achieve phase misalignment between the two paths. When the phase misalignment between the two paths is π / 2, the output current ripple of the two paths can be greatly reduced.

[0043] As Figure 3 shown, the output current waveform of the first two-way CLLLC circuit is approximately a sine wave, that is: .

[0044] The second two-way CLLLC circuit is phase misaligned by π / 2 relative to the first path, and its output current waveform is: .

[0045] The current waveform of the two-way parallel output is: , through the addition operation of the output currents of the two paths with a phase misalignment of π / 2, as Figure 3 shown, it can be seen that the output current ripple can be greatly reduced.

[0046] Since the upper and lower switches of the primary side switch are in a complementary wave generation mode, the adjustment range of the duty cycle D is: Dmin < D < 0.5, and the adjustment of the duty cycle and the gain size are in a proportional relationship.

[0047] For a two-way interleaved parallel BUCK-BOOST circuit, to achieve two-way interleaved parallel connection, the switching frequencies of the two paths need to be the same to achieve phase misalignment between the two paths. When the phase misalignment between the two paths is π, the output current ripple of the two paths can be greatly reduced.

[0048] As Figure 4 shown, the output current waveform of the first two-way BUCK-BOOST circuit is approximately a triangular wave y4(x).

[0049] The second two-way BUCK-BOOST circuit is phase misaligned by π relative to the first path, and its output current waveform is y5(x), and y5(x) is phase misaligned by 180° relative to y4(x).

[0050] The current waveform of the two-way parallel output is: , through the addition operation of the output currents of the two paths with a phase misalignment of π, as Figure 4 shown, it can be seen that the output current ripple can be greatly reduced.

[0051] Specifically, when the converter is operating in the forward direction, the PWM waves of the primary side switches of each CLLLC branch are phase misaligned by 90°, the duty cycle D1 of the primary side switches of the fixed CLLLC branch is 50%, and by controlling the switching frequency of the primary side switches of the CLLLC branch fs, the range of the gain M1 of the CLLLC branch is 0 to 1.2; the PWM waves of each BUCK branch are phase-shifted by 180°, and the switching frequency of the BUCK branch is fixed. f 1. By controlling the duty cycle D2 of the BUCK branch through the PI loop, the range of the gain M2 is 0 to 1, so that the range of the total gain M of the two-stage converter during forward operation is 0 to 1.2. According to the current-sharing adjustment factor d i of each BUCK branch V i and the error factor between the given voltage and the actual output voltage of the parallel total output of each BUCK branch,

[0052] As Figure 5 shown, during the forward operation of the converter, the gain calculation formula of the two-stage converter is: M = M1 * M2; where M is the overall gain of the two-stage converter, M1 is the gain of the CLLLC branch, and M2 is the gain of the BUCK branch. The gain ratios in intervals I, II, and III are as follows: Interval I represents that the switching frequency fs of the CLLLC branch ranges from the minimum switching frequency fmin to the resonance frequency fr, the switching duty cycle D1 is 0.5, the gain M1 of the CLLLC branch is 1 to 1.2; the duty cycle D2 of the BUCK branch is 1, the gain M2 of the BUCK branch is 1, and the total gain of the two-stage converter is M = M1 * M2, and the range of M is 1 to 1.2.

[0053] Interval II represents that the switching frequency fs of the CLLLC branch ranges from the resonance frequency fr to the maximum switching frequency fmax, the switching duty cycle D1 is 0.5, the gain M1 of the CLLLC branch is 0 to 1; the duty cycle D2 of the BUCK branch is 1, the gain M2 of the BUCK branch is 1, and the total gain of the two-stage converter is M = M1 * M2, and the range of M is 0 to 1.

[0054] Interval III represents that the switching frequency fs of the CLLLC branch = the maximum switching frequency fmax, the switching duty cycle D1 decreases from 0.5 to 0, the gain M1 of the CLLLC branch is 0; the duty cycle D2 of the BUCK branch decreases from 1 to 0, the gain M2 of the BUCK branch is 0 to 1, and the total gain of the two-stage converter is M = M1 * M2, and the range of M is 0.

[0055] During the reverse operation of the converter, the PWM waves of each BOOST branch are phase-shifted by 180°, and the PWM switching frequency of the input-side BOOST branch is fixed. f2. The duty cycle D3 is controlled through a PI loop to achieve a gain M4 range of 1 to 3; the PWM waves of the primary side switching tubes of each CLLLC branch are out of phase by 90°, the duty cycle D1 of the primary side switching tubes of the CLLLC branch is fixed at 50%, and by controlling the switching frequency of the primary side switching tubes of the CLLLC branch, the gain M5 range of the CLLLC branch is achieved to be 0 to 1.2, and the total gain M3 range of the two-stage converter during reverse operation is achieved to be 0 to 3.6. According to the current sharing adjustment factor d i of each BOOST branch V i and the error factor between the given voltage and the actual output voltage of the parallel total output of each BOOST branch

[0056] As Figure 6 shown, when the converter operates in reverse, the gain calculation formula of the two-stage converter is: M3 = M4 * M5; where, M3 is the total gain of the two-stage converter, M4 is the gain of the BOOST branch, and M5 is the gain of the CLLLC branch. The gain ratios in intervals I, II, and III are as follows: Interval I represents the switching frequency of the CLLLC branch fs ranging from the minimum switching frequency fmin to the resonant frequency fr , the switching duty cycle D1 is 0.5, the gain M5 of the CLLLC branch is 1 to 1.2; the duty cycle D3 of the BOOST branch is 0 to 0.7, the gain M4 of the BUCK branch is 1 to 3, and the total gain of the two-stage converter is M3 = M4 * M5, and the range of M3 is 1 to 3.6.

[0057] Interval II represents the switching frequency of the CLLLC branch fs ranging from the resonant frequency fr to the maximum switching frequency fmax , the switching duty cycle D1 is 0.5, the gain M5 of the CLLLC branch is 0 to 1; the duty cycle D3 of the BOOST branch is 0, the gain M4 of the BOOST branch is 1, and the total gain of the two-stage converter is M3 = M4 * M5, and the range of M3 is 0 to 1.

[0058] Interval III represents the switching frequency of the CLLLC branch fs = the maximum switching frequency fmax , the switching duty cycle D1 is 0 to 0.5, the gain M5 of the CLLLC branch is 0; the duty cycle D3 of the BOOST branch is 0, the gain M4 of the BOOST branch is 1, and the total gain of the two-stage converter is M3 = M4 * M5, and the value of M3 is 0.

[0059] Embodiment 3 Specifically in this embodiment, in the above steps A21 and B21, the current error factor can be calculated according to the following formula: ε i = I i -( I 1 + I 2 + I 3 + I 4 +... + I n ) / n .

[0060] Wherein, ε i is the current error factor of the i th BUCK branch or the current error factor of the i th BOOST branch, I i is the current on the primary side of the i th BUCK branch or the current on the primary side of the i th BOOST branch, i = 1, 2, 3,..., n , n is the number of BUCK - BOOST branches in the bidirectional BUCK - BOOST circuit.

[0061] In the above steps A231 and B231, the current sharing adjustment factor is calculated according to the following formula: d i = d i-1 + Kp' * ε i + Ki' * ε i .

[0062] Wherein, d i is the current sharing adjustment factor of the i th BUCK branch or the current sharing adjustment factor of the i th BOOST branch, Kp' and Ki' are respectively the proportionality coefficient and the integral coefficient of the current sharing adjustment factor calculation formula.

[0063] In the above steps A232 and B232, the duty cycle of the switching tube of the BUCK branch or the duty cycle of the switching tube of the BOOST branch is adjusted according to the following formula: P i =d i + Kp'' * V i + Ki'' * V i 。

[0064] Among them, P i is the duty ratio of the switching tube of the i th BUCK branch or the duty ratio of the switching tube of the i th BOOST branch, V i is the voltage error factor of the i th BUCK branch or the voltage error factor of the i th BOOST branch, Kp'' and Ki'' are the proportional coefficient and integral coefficient of the PI loop controller respectively.

[0065] Before calculating the current sharing adjustment factor, in order to ensure the stability of subsequent calculations, it is necessary to compare the current error factor with the corresponding maximum and minimum values and perform clipping control. Specifically, in this embodiment, the control method of the two-stage bidirectional DC-DC converter further includes the following steps: For the current error factor of any BUCK branch or BOOST branch, determine whether the current error factor ε i is greater than the maximum current error factor ε max , and obtain the first judgment result.

[0066] If the first judgment result is yes, then assign the maximum current error factor ε max to the current error factor ε i .

[0067] If the first judgment result is no, then determine whether the current error factor ε i is less than the minimum current error factor ε min , and obtain the second judgment result.

[0068] If the second judgment result is yes, then assign the minimum current error factor ε min to the current error factor ε i .

[0069] If the second judgment result is no, then do not perform any processing on the current error factor ε i .

[0070] Before adjusting the duty ratio of the switching tube, in order to ensure the stability of subsequent calculations, it is necessary to use the current sharing adjustment factor d i and the voltage error factorV i Compare with the corresponding maximum and minimum values respectively for amplitude limiting control. Specifically, in this embodiment, the control method of the two-stage bidirectional DC-DC converter further includes the following steps: For the current sharing adjustment factor of any BUCK branch or BOOST branch, judge the current sharing adjustment factor d i Whether it is greater than the maximum value of the current sharing adjustment factor d max to obtain a third judgment result.

[0071] If the third judgment result is yes, then assign the maximum value of the current sharing adjustment factor d max to the current sharing adjustment factor d i .

[0072] If the third judgment result is no, then judge the current sharing adjustment factor d i Whether it is less than the minimum value of the current sharing adjustment factor d min to obtain a fourth judgment result.

[0073] If the fourth judgment result is yes, then assign the minimum value of the current sharing adjustment factor d min to the current sharing adjustment factor d i .

[0074] If the fourth judgment result is no, then do not perform any processing on the current sharing adjustment factor d i .

[0075] For the voltage error factor of any BUCK branch or BOOST branch, judge the voltage error factor V i Whether it is greater than the maximum value of the voltage error factor V max to obtain a fifth judgment result.

[0076] If the fifth judgment result is yes, then assign the maximum value of the voltage error factor V max to the voltage error factor V i .

[0077] If the fifth judgment result is no, then judge the voltage error factor V i Whether it is less than the minimum value of the voltage error factor V min to obtain a sixth judgment result.

[0078] If the result of the sixth determination is yes, then assign the minimum value of the voltage error factor V min to the voltage error factor V i .

[0079] If the result of the sixth determination is no, then do not perform any processing on the voltage error factor V i .

[0080] Embodiment 4 In an exemplary embodiment of the present application, as Figure 7 shown, a two-stage bidirectional DC-DC converter with input parallel and output parallel (two-way interleaved parallel CLLLC circuits + bidirectional BUCK-BOOST circuits) is presented. As Figure 7 shown, where L1 and L2 are two-way CLLLC branches of two paths respectively, and L3 and L4 are two-way BUCK-BOOST branches of two paths respectively. In the first branch L1 and L3, the input voltage is: Vin1 = (Vin+ - Vin-), where Q1, Q2, Q3, Q4 are the switching transistors of the primary CLLLC of the full bridge, Lr1, Lr2 are the primary resonant inductors, C1 is the primary resonant capacitor, T1, T2 are transformers, T1-1, T1-2 are the primary and secondary sides of transformer T1 respectively, T2-1, T2-2 are the primary and secondary sides of transformer T2 respectively, Lr3, Lr4 are the secondary resonant inductors, C2 is the secondary resonant capacitor, C3 is the output filter capacitor, Q5, Q6, Q7, Q8 are the synchronous rectification switching transistors of the secondary CLLLC of the full bridge, Q17, Q18 are the upper and lower switching transistors of the BUCK-BOOST, L9 is the inductor of the BUCK-BOOST, and C7 is the output filter capacitor of the BUCK-BOOST.

[0081] In the second branch L2 and L4, the input voltage is: Vin2 = (Vin+ - Vin-), where Q9, Q10, Q11, Q12 are the primary side CLLLC switching transistors of the full bridge, Lr5, Lr6 are the primary side resonant inductors, C4 is the primary side resonant capacitor, T3, T4 are transformers, T3-1, T3-2 are the primary side and secondary side of transformer T3, T4-1, T4-2 are the primary side and secondary side of transformer T4, Lr7, Lr8 are the secondary side resonant inductors, C5 is the secondary side resonant capacitor, C6 is the output filter capacitor, Q13, Q14, Q15, Q16 are the secondary side CLLLC synchronous rectifier switching transistors of the full bridge, Q19, Q20 are the upper and lower switching transistors of the BUCK - BOOST, L10 is the inductor of the BUCK - BOOST, and R1 is the output load. IL1 and IL2 are the primary side resonant cavity currents of the first CLLLC branch and the second CLLLC branch respectively, and Iout1 and Iout2 are the output currents of the first BUCK - BOOST branch and the second BUCK - BOOST branch respectively.

[0082] The two - way CLLLC circuits control the switching transistor wave - generation on the primary side through the method of in - phase interleaved parallel connection. The phase difference between the two paths is π / 2, and the switching frequencies of the primary side full - bridge switching transistors are kept consistent. This can greatly reduce the output current ripple. The specific effect is as Figure 3 shown. The secondary side adopts the synchronous rectification control method. The secondary side switching transistors (switching transistors) follow the wave - generation of the primary side switching transistors (switching transistors). Through synchronous rectification, the loss of the secondary side switching transistors can be greatly reduced, thereby preventing the overheating and damage of the body diodes of the switching transistors, and also reducing the module volume and cost. The two - way BUCK - BOOST circuits control the switching transistor wave - generation through the method of in - phase interleaved parallel connection. The phase difference between the two paths is π, and the switching frequencies of the two paths are kept consistent. This can greatly reduce the output current ripple. The specific effect is as Figure 4 shown.

[0083] The current - sharing error of the two - way BUCK - BOOST circuits ε i = Iout1 - Iout2. The current - sharing control process for the two - way BUCK - BOOST circuits includes: First, limit the current error factor ε i . When ε i > ε max , then ε i = ε max ; when ε i < ε min , thenε i = ε min ; When ε min < ε i < ε min , then ε i = ε i . The current sharing regulation factor is calculated according to the current sharing regulation factor calculation formula, and then the current sharing regulation factor of this BUCK - BOOST branch d i is limited. When d i > d max , then d i = d max ; When d i < d min , then d i = d min ; When d min < d i < d max , then d i = d i . Since the upper and lower transistors use a complementary wave - emitting method, among which d max the maximum duty cycle is 0.5, d min the minimum duty cycle is 0. The switching frequency range of the primary - side switching transistor is 60KHZ - 300KHZ. The drive of Q5 switching transistor follows the drive of Q1 switching transistor, and the drive of Q5 switching transistor is within the envelope of the drive of Q1 switching transistor, that is, the rising edge of the drive of Q5 switching transistor lags behind that of Q1 switching transistor, and the falling edge of the drive of Q5 switching transistor is ahead of that of Q1 switching transistor.

[0084] Such as Figure 8As shown, it presents the structure of a two-stage bidirectional CD-CD converter with series input and parallel output. Among them, L1 and L2 are two bidirectional CLLLC branches respectively, and L3 and L4 are two bidirectional BUCK-BOOST branches respectively. In the first branch L1, the input capacitor is C7 and the input voltage is Vin1; in the second branch L2, the input capacitor is C8 and the input voltage is Vin2. The input capacitors C7 and C8 are in series, and the total input voltage Vin = Vin1 + Vin2. The current sharing control method for the two bidirectional BUCK-BOOST circuits includes: by detecting the current values of each BUCK-BOOST branch in real time, obtaining the current error factor ε i ; at the same time, according to the error factor V i between the given voltage and the actual output voltage of the parallel total output of the BUCK-BOOST branches, the duty cycle of the switching tubes of each BUCK-BOOST branch is controlled and adjusted through the negative feedback of the PI loop.

[0085] As Figure 9 shown, it presents a bidirectional CLLLC + BUCK-BOOST circuit with parallel input and series output. Among them, L1 and L2 are two bidirectional CLLLC branches respectively, and L3 and L4 are two bidirectional BUCK-BOOST branches respectively. In the first branch L1, the output capacitor is C3 and the output voltage is Vout1; in the first branch L3, the output capacitor is C7 and the output voltage is Vout3, in the second branch L2, the output capacitor is C6 and the output voltage is Vout2; in the second branch L4, the output capacitor is C8 and the output voltage is Vout4. The output capacitors C3 and C6 are in series, the output capacitors C7 and C8 are in series, the total output voltage of CLLLC Vout_clllc = Vout1 + Vout2, and the total output voltage of BUCK-BOOST Vout_buck-boost = Vout3 + Vout4. The current sharing control method for the two bidirectional BUCK-BOOST circuits includes: by detecting the current values of the primary sides of each BUCK-BOOST branch in real time, obtaining the current error factor ε i ; at the same time, according to the error factor V i between the given voltage and the actual output voltage of the parallel total output of the BUCK-BOOST branches, the duty cycle of the switching tubes of each BUCK-BOOST branch is controlled and adjusted through the negative feedback of the PI loop.

[0086] In the above of this application Figures 7 to 9The three examples are all applied to a two-way bidirectional CLLLC + BUCK - BOOST circuit. In these three examples, the two paths of the CLLLC are interleaved with a phase shift of π / 2, and the two paths of the BUCK - BOOST are interleaved with a phase shift of π. However, other phase shift values can also be used, such as Figures 3 to 4 As shown, interleaving the two paths of the CLLLC with a phase shift of π / 2 and interleaving the two paths of the BUCK - BOOST with a phase shift of π are the optimal solutions, which can minimize the output current ripple to the greatest extent.

[0087] Embodiment 5 The control methods provided in the above embodiments can also be applied to the gain control of a multi - path parallel bidirectional BUCK - BOOST circuit. In an N - path parallel bidirectional BUCK - BOOST circuit, the mutual phase shift value is π / N.

[0088] For a BUCK - BOOST circuit with a circuit stringing method of input series output parallel, or input parallel output parallel, or input parallel output series bidirectional BUCK - BOOST circuit, the current error factor ε i = I i -( I 1 + I 2 + I 3 + I 4 +..... I n ) / n , ( i = 1~ n , i and n are integers), where I i is the current of the i th path of the BUCK - BOOST branch, I 1, I 2, I 3, I 4..... I n correspond to the circuits of the 1st, 2nd, 3rd, 4th... n th paths of the BUCK - BOOST branches respectively. By detecting the unbalanced current difference ε i of the multi - path BUCK - BOOST circuit in real time, and calculating the current sharing adjustment factor d i according to the current sharing adjustment factor calculation formula; at the same time, according to the error factor V i, the duty ratio of the switching tubes in each BUCK - BOOST branch is controlled and adjusted through the negative feedback of the PI loop.

[0089] In another exemplary embodiment, a computer device is provided. The computer device can be a server or a terminal, and its internal structure diagram can be as Figure 10 shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non - volatile storage medium and an internal memory. The non - volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non - volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with an external terminal through a network connection. When the computer program is executed by the processor, it can implement the control method of a two - stage bidirectional DC - DC converter provided in the foregoing embodiments.

[0090] Those skilled in the art can understand that Figure 10 the structure shown in

[0091] is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0092] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0093] The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logics, data processing logics based on quantum computing, etc., without limitation.

[0094] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0095] Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A control method for a two-stage bidirectional DC-DC converter, the two-stage bidirectional DC-DC converter comprising a bidirectional CLLLC circuit and a bidirectional BUCK-BOOST circuit, the bidirectional CLLLC circuit comprising a plurality of bidirectionally interleaved CLLLC branches, the primary sides of the forward and reverse CLLLC branches being controlled with interleaved phases, and the secondary sides of the CLLLC branches being controlled with synchronous rectification; the bidirectional BUCK-BOOST circuit comprising a plurality of bidirectionally interleaved BUCK-BOOST branches, the BUCK-BOOST branches comprising a BUCK branch and a BOOST branch; the primary sides of the forward and reverse BUCK-BOOST branches being controlled with interleaved phases; characterized in that, The control method of the two-stage bidirectional DC-DC converter includes: Fixing the duty cycle of the primary switch tubes of each CLLLC branch, and adjusting the gain of each CLLLC branch by controlling the switching frequency of the primary switch tubes of each CLLLC branch; Fixing the switching frequency of the switch tubes of each BUCK branch or each BOOST branch, and adjusting the gain of each BUCK branch or each BOOST branch by controlling the duty cycle of the switch tubes of each BUCK branch or each BOOST branch through a PI loop.

2. The control method of the two-stage bidirectional DC-DC converter according to claim 1, when the two-stage bidirectional DC-DC converter operates in the forward direction, the topology combination mode is the CLLLC branch + the BUCK branch, the input side is the CLLLC branch, and the output side is the BUCK branch; when the two-stage bidirectional DC-DC converter operates in the reverse direction, the topology combination mode is the BOOST branch + the CLLLC branch, the input side is the BOOST branch, and the output side is the CLLLC branch; characterized in that, When the two-stage bidirectional DC-DC converter operates in the forward direction, fixing the switching frequency of the switch tubes of each BUCK branch or each BOOST branch, and controlling the duty cycle of the switch tubes of each BUCK branch or each BOOST branch through a PI loop, specifically including: Fixing the switching frequency of the switch tubes of each BUCK branch, and obtaining a current error factor by real-time detecting the current of the primary side of each BUCK branch; According to the voltage error factor between the given voltage and the actual output voltage of the parallel total output of each BUCK branch; According to the current error factor and the voltage error factor, adjusting the duty cycle of the switch tubes of each BUCK branch through the negative feedback of the PI loop to realize the adjustment of the gain of each BUCK branch; When the two-stage bidirectional DC-DC converter operates in the reverse direction, fixing the switching frequency of the switch tubes of each BUCK branch or each BOOST branch, and controlling the duty cycle of the switch tubes of each BUCK branch or each BOOST branch through a PI loop, specifically including: Fixing the switching frequency of the switch tubes of each BOOST branch, and obtaining a current error factor by real-time detecting the current of the primary side of each BOOST branch; According to the voltage error factor between the given voltage and the actual output voltage of the parallel total output of each BOOST branch; According to the current error factor and the voltage error factor, adjusting the duty cycle of the switch tubes of each BOOST branch through the negative feedback of the PI loop to realize the adjustment of the gain of each BOOST branch.

3. The control method of the two-stage bidirectional DC-DC converter according to claim 2, characterized in that According to the current error factor and the voltage error factor, adjusting the duty cycle of the switch tubes of each BOOST branch through the negative feedback of the PI loop specifically includes: Substituting the current error factor of the primary side of each BOOST branch into the calculation formula of the current sharing adjustment factor respectively to obtain the current sharing adjustment factor of each BOOST branch; According to the current sharing adjustment factors of each BOOST branch and the voltage error factor, adjusting the duty cycle of the switch tubes of each BOOST branch through the negative feedback of the PI loop; According to the current error factor and the voltage error factor, adjusting the duty cycle of the switch tubes of each BUCK branch through the negative feedback of the PI loop specifically includes: Substituting the current error factor of the primary side of each BUCK branch into the calculation formula of the current sharing adjustment factor respectively to calculate the current sharing adjustment factor of each BUCK branch; According to the current sharing adjustment factor and the voltage error factor of each BUCK branch, the duty ratio of the switching tube of each BUCK branch is adjusted through the negative feedback of the PI loop.

4. The control method of the two-stage bidirectional DC-DC converter according to claim 3, characterized in that, The current error factor is calculated according to the following formula: ε i = I i -( I 1+ I 2+ I 3+ I 4+...+ I n ) / n ； Among them, ε i is the current error factor of the i th BUCK branch or the current error factor of the i th BOOST branch, I i is the current on the primary side of the i th BUCK branch or the current on the primary side of the i th BOOST branch, i = 1, 2, 3, …, n , n is the number of the BUCK - BOOST branches in the bidirectional BUCK - BOOST circuit; The current sharing adjustment factor is calculated according to the following formula: d i = d i-1 + Kp' * ε i + Ki' * ε i ； Among them, d i is the current sharing regulation factor of the i th BUCK branch or the current sharing regulation factor of the i th BOOST branch, Kp' and Ki' are the proportional coefficient and the integral coefficient of the current sharing regulation factor calculation formula respectively; The duty ratio of the switching tube of the BUCK branch or the duty ratio of the switching tube of the BOOST branch is adjusted according to the following formula: P i = d i + Kp'' * V i + Ki'' * V i ； Among them, P i is the duty cycle of the switching transistor of the i th BUCK branch or the duty cycle of the switching transistor of the i th BOOST branch, V i is the voltage error factor of the i th BUCK branch or the voltage error factor of the i th BOOST branch, Kp'' and Ki'' are the proportional coefficient and integral coefficient of the PI loop controller respectively.

5. The control method of the two-stage bidirectional DC-DC converter according to claim 4, characterized in that, Before calculating the current sharing adjustment factor, the control method of the two-stage bidirectional DC-DC converter further includes: For the current error factor of any BUCK branch or BOOST branch, judge whether the current error factor is greater than the maximum value of the current error factor to obtain a first judgment result; If the first judgment result is yes, assign the maximum value of the current error factor to the current error factor; If the first judgment result is no, judge whether the current error factor is less than the minimum value of the current error factor to obtain a second judgment result; If the second judgment result is yes, assign the minimum value of the current error factor to the current error factor; If the second judgment result is no, do not perform any processing on the current error factor.

6. The control method of the two-stage bidirectional DC-DC converter according to claim 4, characterized in that Before adjusting the duty ratio of the switching tube, the control method of the two-stage bidirectional DC-DC converter further includes: For the current sharing adjustment factor of any BUCK branch or BOOST branch, judge whether the current sharing adjustment factor is greater than the maximum value of the current sharing adjustment factor to obtain a third judgment result; If the third judgment result is yes, assign the maximum value of the current sharing adjustment factor to the current sharing adjustment factor; If the third judgment result is no, judge whether the current sharing adjustment factor is less than the minimum value of the current sharing adjustment factor to obtain a fourth judgment result; If the fourth judgment result is yes, assign the minimum value of the current sharing adjustment factor to the current sharing adjustment factor; If the fourth judgment result is no, do not perform any processing on the current sharing adjustment factor; For the voltage error factor of any BUCK branch or BOOST branch, judge whether the voltage error factor is greater than the maximum value of the voltage error factor to obtain a fifth judgment result; If the fifth judgment result is yes, assign the maximum value of the voltage error factor to the voltage error factor; If the fifth judgment result is no, judge whether the voltage error factor is less than the minimum value of the voltage error factor to obtain a sixth judgment result; If the sixth judgment result is yes, assign the minimum value of the voltage error factor to the voltage error factor; If the sixth judgment result is no, do not perform any processing on the voltage error factor.

7. The control method of the two-stage bidirectional DC-DC converter according to claim 1, characterized in that, The PWM wave generation of each CLLLC branch in the bidirectional interleaving is phase-shifted by 90°, and the switching frequency of the synchronous rectification of the secondary side switching tube and the switching frequency of the primary side switching tube of each CLLLC branch are kept consistent; the PWM switching frequencies of each BUCK-BOOST branch in the bidirectional interleaving are kept consistent, and the PWM wave generation between each BUCK-BOOST branch is phase-shifted by 180°.

8. The control method of the two-stage bidirectional DC-DC converter according to claim 1, wherein The gain of the CLLLC branch is adjusted according to the following formula: ； Among them, G ( Q , m , Fx ) is the gain of the GLLLC branch, Q is the quality factor, , Lr is the inductance of the resonant inductor, Cr is the capacitance of the resonant capacitor, Rac is the equivalent resistance of the output load resistance reflected to the primary side, , N is the turns ratio of the primary and secondary sides of the transformer, R 0 is the equivalent resistance of the output load, Fx is the normalized switching frequency, , fs is the switching frequency of the primary side switching tube of the CLLLC branch, fr is the resonant frequency of the primary side switching tube of the CLLLC branch, m is the ratio of the total inductance of the primary side to the inductance of the resonant inductor, , Lm is the inductance of the exciting inductor, and the total inductance of the primary side is the sum of the inductance of the resonant inductor and the inductance of the exciting inductor.

9. A computer device, comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that the processor executes the computer program to implement the control method of the two-stage bidirectional DC-DC converter according to any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the control method of the two-stage bidirectional DC-DC converter according to any one of claims 1-8.

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