A control circuit

Abstract

This disclosure provides a control circuit, including: a comparator circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparator circuit having a bias power supply for providing current to the comparator circuit; a monitoring circuit having an input terminal coupled to a first node within the comparator circuit and an output terminal coupled to an acceleration circuit, configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, such that the acceleration circuit is turned on when the control circuit is in a startup phase and turned off when the control circuit is in a stable phase; and an acceleration circuit having an input terminal coupled to the monitoring circuit and an output terminal coupled to the bias power supply, configured to adjust the bias current output by the bias power supply.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit technology, and more particularly to a control circuit. Background Technology

[0002] In the field of integrated circuits, low-power design is an important principle. Most circuit modules are kept off when not needed, and are only activated by an enable signal from the system when necessary. At the same time, to reduce current consumption, the steady-state operating current of many circuit modules is very small, and the related bias current is reduced to the μA level or even lower.

[0003] Low bias current makes rapid enable setup of circuit modules a challenge, especially for circuits with feedback loops, such as LDOs (Low Dropout Linear Regulators). Circuits with loops typically require large capacitors for loop compensation to prevent significant overshoot or oscillations, ensuring proper circuit operation. To reduce mismatch, the components within the loop are usually larger, resulting in larger parasitic capacitances. In low-power designs, excessively low bias current leads to significantly prolonged capacitor charging time; in other words, circuit setup speed is limited by low bias current. Summary of the Invention

[0004] In view of this, the present disclosure provides a control circuit.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] This disclosure provides a control circuit, including: a comparator circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparator circuit having a bias power supply for providing current to the comparator circuit; a monitoring circuit having an input terminal coupled to a first node within the comparator circuit and an output terminal coupled to an acceleration circuit, configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, such that the acceleration circuit is turned on when the control circuit is in a startup phase and turned off when the control circuit is in a stable phase; and an acceleration circuit having an input terminal coupled to the monitoring circuit and an output terminal coupled to the bias power supply, configured to adjust the bias current output by the bias power supply.

[0007] In some embodiments, the monitoring circuit is specifically configured to output a second control signal based on the voltage and / or current of the first node; the acceleration circuit is specifically configured to adjust the bias current output by the bias power supply in response to the second control signal, so that the bias current of the control circuit in the startup phase is greater than the bias current of the control circuit in the steady phase.

[0008] In some embodiments, the monitoring circuit is configured to shut down the acceleration circuit when it detects that the voltage and / or current of the first node reaches a first preset value during the startup phase.

[0009] In some embodiments, the comparator circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein the control terminals of the first transistor and the second transistor are coupled; the input terminals of the first transistor and the second transistor are coupled to a power supply; the output terminal of the first transistor is coupled to the input terminal of the third transistor and the control terminal of the first transistor; a first node is located at the output terminal of the first transistor; the output terminal of the second transistor is coupled to the input terminal of the fourth transistor and the output terminal of the comparator circuit; the output terminals of the third transistor and the fourth transistor are coupled to a ground terminal; the control terminal of the third transistor is the first input terminal of the comparator circuit for receiving a feedback voltage; and the control terminal of the fourth transistor is the second input terminal of the comparator circuit for receiving a reference voltage.

[0010] In some embodiments, the monitoring circuit includes a detection unit, an initialization unit, and a current limiting unit; the detection unit and the current limiting unit are connected in series, and the initialization unit and the current limiting unit are connected in parallel; the output terminal of the detection unit is coupled to the input terminal of the acceleration circuit, and the detection unit is coupled to a first node; the detection unit is used to provide a regulating current based on the voltage of the first node; the current limiting unit is used to regulate the rate of change of the voltage at the output terminal of the detection unit; the initialization unit is used to provide an initial voltage to the output terminal of the detection unit during the startup phase to enable the acceleration circuit.

[0011] In some embodiments, the detection unit includes a fifth transistor; and / or the initialization unit includes a sixth transistor; the output terminal of the fifth transistor is coupled to a current limiting unit, the output terminal of the fifth transistor is the output terminal of the monitoring circuit, and the output terminals of the current limiting unit and the sixth transistor are coupled to a ground terminal.

[0012] In some embodiments, the current limiting unit includes a resistor and / or a capacitor.

[0013] In some embodiments, the monitoring circuit further includes a first resistor for adjusting the rate of change of the voltage at the output terminal of the detection unit.

[0014] In some embodiments, the acceleration circuit includes a seventh transistor; the control terminal of the seventh transistor is coupled to the output terminal of the monitoring circuit, and the output terminal of the seventh transistor is the output terminal of the acceleration circuit.

[0015] In some embodiments, the acceleration circuit further includes a second resistor connected in series with the seventh transistor for adjusting the acceleration current output by the acceleration circuit; the input terminal of the seventh transistor is coupled to the power supply through the second resistor.

[0016] In some embodiments, the bias power supply includes a current source and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled together, the output terminal of the current source is coupled to the input terminal of the current mirror, the input terminal of the current mirror is coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply; the output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

[0017] In some embodiments, the acceleration circuit is specifically configured to turn on in response to a second control signal when the control circuit is in the startup phase to generate an acceleration current and output the acceleration current to a bias power supply.

[0018] In some embodiments, the acceleration circuit includes an eighth transistor and a third resistor connected in parallel; the control terminal of the eighth transistor is coupled to the output terminal of the fifth transistor, the input terminal of the eighth transistor is coupled to a power supply, and the output terminal of the eighth transistor is the output terminal of the acceleration circuit.

[0019] In some embodiments, the bias power supply includes a fourth resistor and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled together, the fourth resistor is connected in series with the third resistor and coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply; the output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

[0020] In some embodiments, the circuit further includes: a switching circuit coupled to the comparator circuit and configured to control the operating state of the comparator circuit based on an enable signal; the switching circuit includes a ninth transistor and a tenth transistor; the control terminals of the ninth transistor and the tenth transistor receive an enable signal, the input terminals of the ninth transistor and the tenth transistor are coupled to a power supply, the output terminal of the ninth transistor is coupled to the control terminals of the first transistor and the second transistor, and the output terminal of the tenth transistor is coupled to the output terminal of the second transistor.

[0021] This disclosure provides a control circuit including: a comparator circuit configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparator circuit having a bias power supply for providing current to the comparator circuit; a monitoring circuit, its input terminal coupled to a first node within the comparator circuit, its output terminal coupled to an acceleration circuit, configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, so that the acceleration circuit is turned on when the control circuit is in a startup phase and turned off when the control circuit is in a stable phase; and an acceleration circuit, its input terminal coupled to the monitoring circuit, its output terminal coupled to the bias power supply, configured to adjust the bias current output by the bias power supply. In this disclosure, the monitoring circuit is coupled to an internal node (first node) of the comparator circuit, and the internal node of the comparator circuit can more accurately reflect the loop establishment state, thereby enabling timely start-up and shutdown of the acceleration circuit. Attached Figure Description

[0022] Figure 1 A schematic diagram of an amplifier circuit provided in an embodiment of this disclosure;

[0023] Figure 2 A schematic diagram of a control circuit provided in an embodiment of this disclosure;

[0024] Figure 3 A schematic diagram of a monitoring circuit provided in an embodiment of this disclosure;

[0025] Figure 4 A schematic diagram of an acceleration circuit provided in an embodiment of this disclosure. Figure 1 ;

[0026] Figure 5 A schematic diagram of a bias power supply provided in an embodiment of this disclosure. Figure 1 ;

[0027] Figure 6 A schematic diagram of an acceleration circuit and bias power supply provided in an embodiment of this disclosure. Figure 2 . Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0035] Figure 1 This is a schematic diagram of an amplifier circuit provided in an embodiment of the present disclosure. The circuit is a typical LDO (Low Voltage Regulator), including a comparator 11, a voltage regulation loop 12, and a feedback output module 13. The input terminal of the comparator 11 receives a reference voltage Vref, and the output terminal of the comparator 11 is coupled to the feedback output module 13. The feedback output module 13 includes an output transistor MP connected in series, a first feedback resistor RF1, and a second feedback resistor RF2; the node between the first feedback resistor RF1 and the second feedback resistor RF2 is connected to the feedback input terminal of the comparator 11. The feedback output module 13 outputs a feedback voltage VFB to the feedback input terminal of the comparator 11. The input terminal of the output transistor MP is connected to the power supply VDD, and its output terminal serves as the output terminal of the amplifier circuit, providing current to the output voltage of the amplifier circuit.

[0036] Comparator 11 can be connected to an adjustable bias power supply. A larger bias current results in a faster operational amplifier response and a shorter settling time for the corresponding amplifier circuit. Conversely, a smaller bias current results in a slower operational amplifier response and a shorter settling time for the corresponding amplifier circuit. Because this amplifier circuit incorporates a large internal capacitor node to ensure loop stability, and to reduce mismatch, the components within the amplifier circuit are typically large, resulting in significant parasitic capacitance. These capacitances all affect the circuit's settling time, especially when the bias current is low.

[0037] Figure 2 This is a schematic diagram of a control circuit provided for an embodiment of this disclosure. Figure 2As shown, the control circuit includes: a comparator circuit 210 configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparator circuit 210 having a bias power supply 211 for providing current to the comparator circuit 210; a monitoring circuit 220, the input of which is coupled to a first node within the comparator circuit 210, and the output of which is coupled to an acceleration circuit 230, configured to control the operating state of the acceleration circuit 230 based on the voltage and / or current of the first node, so that the acceleration circuit 230 is turned on when the control circuit is in the startup phase and turned off when the control circuit is in the stable phase; and the acceleration circuit 230, the input of which is coupled to the monitoring circuit 220, and the output of which is coupled to the bias power supply 211, configured to adjust the bias current output by the bias power supply 211.

[0038] In this embodiment, the operation of the monitoring circuit 220 based on the voltage of the first node to control the acceleration circuit 230 is described as an example. In the following embodiments, the voltage of the first node is represented by VB.

[0039] In some embodiments, capacitor Cp1 in the control circuit is the equivalent parasitic capacitance of the output terminal of the control circuit, capacitor Cc is the Miller capacitance connected across the two ends of the subsequent circuit, and capacitor Cload is the load capacitance output by the subsequent circuit.

[0040] In some embodiments, Figure 2 The illustrated control circuit may specifically include the following subsequent circuits: Figure 1 The feedback output module 13 is shown. Here, the output of the comparator circuit 210 is connected to the subsequent circuit. In a specific example, the output of the comparator circuit 210 is connected to the control terminal of the output transistor MP.

[0041] In some embodiments, the front-end circuit in the control circuit is the input terminal of the control circuit, used to receive external input signals.

[0042] In this embodiment, the monitoring circuit is coupled to the internal node (first node) of the comparator circuit. Compared to the output of the monitoring and control circuit, the output establishment process is smoother. Because the output establishment is affected by the load and the feedback link has a delay, directly sampling the output can easily cause overshoot. Therefore, the monitoring circuit controls the operating state of the acceleration circuit according to the internal node of the comparator circuit, which can avoid the influence of load and delay. The internal node of the comparator circuit can more accurately reflect the establishment state of the loop, and promptly turn the acceleration circuit on and off, so that the output voltage is established smoothly.

[0043] In some embodiments, the monitoring circuit 220 is specifically configured to output a second control signal VC based on the voltage and / or current of the first node; the acceleration circuit 230 is specifically configured to adjust the bias current output by the bias power supply 211 in response to the second control signal VC, so that the bias current of the control circuit in the startup phase is greater than the bias current of the control circuit in the stable phase.

[0044] In this embodiment of the present disclosure, the acceleration circuit 230 can make the bias current of the control circuit in the startup phase greater than the bias current of the control circuit in the stable phase, thereby accelerating the establishment speed of the control circuit in the startup phase.

[0045] In some embodiments, the comparator circuit 210 includes: a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; wherein the control terminal of the first transistor M1 and the control terminal of the second transistor M2 are coupled; the input terminals of the first transistor M1 and the second transistor M2 are coupled to a power supply; the output terminal of the first transistor M1 is coupled to the input terminal of the third transistor M3 and the control terminal of the first transistor M1; a first node is located at the output terminal of the first transistor M1; the output terminal of the second transistor M2 is coupled to the input terminal of the fourth transistor M4 and the output terminal of the comparator circuit; the output terminals of the third transistor M3 and the fourth transistor M4 are coupled to a ground terminal; the control terminal of the third transistor M3 is the first input terminal of the comparator circuit for receiving a feedback voltage Vb; and the control terminal of the fourth transistor M4 is the second input terminal of the comparator circuit for receiving a reference voltage Va.

[0046] In some embodiments, the feedback voltage Vb is the feedback voltage of the subsequent circuit. Specifically, the feedback voltage Vb can be the output voltage of the subsequent circuit, or it can be the voltage at the node between the first feedback resistor R1 and the second feedback resistor R2 in the subsequent circuit.

[0047] In some embodiments, the output terminals of the third transistor M3 and the fourth transistor M4 are both coupled to the output terminal of the bias power supply.

[0048] In some embodiments, the first transistor M1 and the second transistor M2 are PMOS transistors, and the third transistor M3 and the fourth transistor M4 are NMOS transistors.

[0049] In some embodiments, the control circuit further includes: a switching circuit coupled to the comparator circuit 210, configured to control the operating state of the comparator circuit 210 based on an enable signal; the switching circuit includes a ninth transistor M9 and a tenth transistor M10; the control terminals of the ninth transistor M9 and the tenth transistor M10 receive an enable signal EN, the input terminals of the ninth transistor M9 and the tenth transistor M10 are coupled to a power supply VDD, the output terminal of the ninth transistor M9 is coupled to the control terminals of the first transistor M1 and the second transistor M2, and the output terminal of the tenth transistor M10 is coupled to the output terminal of the second transistor M2.

[0050] It should be noted that, Figure 2 The dashed box containing the comparison circuit 210 in the figure includes the switching circuit, but is not intended to limit the switching circuit to be subordinate to the comparison circuit 210.

[0051] When the control circuit is not enabled, the ninth transistor M9 and the tenth transistor M10 are turned on by the enable signal EN. At this time, the first node is pulled up to VDD, thereby turning off the output transistor MP in the subsequent circuit, and the control circuit is in a non-working state.

[0052] When the control circuit is enabled, the enable signal EN controls the ninth transistor M9 and the tenth transistor M10 to turn off, the bias power supply operates, and provides current to the comparator circuit; the paths of the third transistor M3 and the fourth transistor M4 are turned on, and the voltage at the output of the comparator circuit 210 is fed back to the front-end circuit through the subsequent circuit. The front-end circuit outputs a reference voltage Va and a feedback voltage Vb based on the voltage fed back from the subsequent circuit to the third transistor M3 and the fourth transistor M4. In the initial stage of loop establishment, the reference voltage Va output by the front-end circuit is greater than the feedback voltage Vb, the conduction degree of the fourth transistor M4 is greater than that of the third transistor M3, and the bias current Ib output by the bias power supply is almost entirely used for the path of the fourth transistor M4, pulling down the output of the comparator circuit through the path of the fourth transistor M4. At this time, there is almost no pull-down current at the first node. Until the output voltage of the comparator circuit rises to the turn-on voltage of the output transistor MP, the subsequent circuit activates feedback. The preceding circuit adjusts the feedback voltage Vb based on the feedback from the subsequent circuit to reduce the difference between the reference voltage Va and the feedback voltage Vb. When the reference voltage Va and the feedback voltage Vb are close, the bias current lb flows into the path of the third transistor M3, and the voltage of the first node begins to decrease. This corresponds to the loop being established almost completely, because at this time the reference voltage Va and the feedback voltage Vb are close, that is, the difference between the reference voltage Va and the feedback voltage Vb is very small or 0, making the output voltage value of the comparator circuit stable, and the loop enters a steady state. Based on this, the first node detected in this embodiment is an internal node of the comparator circuit that can accurately reflect the loop establishment state, thereby enabling the acceleration circuit to be turned on and off in a timely manner.

[0053] Figure 3 This is a schematic diagram of a monitoring circuit provided for an embodiment of this disclosure. (In conjunction with...) Figure 2 and Figure 3 As shown, the monitoring circuit 220 includes a detection unit 221, an initialization unit 222, and a current limiting unit 223. The detection unit 221 and the current limiting unit are connected in series, and the initialization unit 222 is connected in parallel with the current limiting unit. The output terminal of the detection unit 221 is coupled to the input terminal of the acceleration circuit, and the detection unit 221 is coupled to the first node. The detection unit is used to provide an adjustment current based on the voltage of the first node. The current limiting unit 223 is used to adjust the rate of change of the voltage at the output terminal of the detection unit. The initialization unit 222 is used to provide an initial voltage to the output terminal of the detection unit during the startup phase to enable the acceleration circuit.

[0054] In some embodiments, the detection unit 221 includes a fifth transistor M5; and / or the initialization unit 222 includes a sixth transistor M6; the output terminal of the fifth transistor M5 is coupled to the current limiting unit 223, and the output terminal of the fifth transistor M5 is the output terminal of the monitoring circuit 220; the output terminals of the current limiting unit 223 and the sixth transistor M6 are coupled to the ground terminal. Here, the signal output by the output terminal of the monitoring circuit 220 is the second control signal VC.

[0055] In some embodiments, the fifth transistor M5 is a PMOS transistor.

[0056] In some embodiments, the control terminal of the sixth transistor M6 is connected to the inverting enable signal EN_INV. The transistor type of the sixth transistor M6 is different from that of the ninth transistor M9 and the tenth transistor M10. Specifically, the ninth transistor M9 and the tenth transistor M10 are PMOS transistors, while the sixth transistor M6 is an NMOS transistor.

[0057] In some embodiments, the current limiting unit 223 includes a resistor and / or a capacitor. In a specific example, the current limiting voltage 223 is capacitor C1, wherein the output terminal of the fifth transistor M5 is coupled to the first plate of capacitor C1, and the second plate of capacitor C1 and the output terminal of the sixth transistor M6 are coupled to ground.

[0058] In some embodiments, the monitoring circuit 220 further includes a first resistor R1, used to adjust the rate of change of the voltage at the output terminal of the detection unit 221. It should be noted that the capacitor C1 is also used to adjust the rate of change of the voltage at the output terminal of the detection unit 221. In other words, the first resistor R1 and the capacitor C1 can adjust the delay between the on and off states of the acceleration circuit, and the resistance value of the first resistor R1 and the capacitance value of the capacitor C1 can be set according to actual needs.

[0059] When the control circuit is disabled, the first node is pulled up to VDD, the fifth transistor M5 is turned off, the monitoring circuit is turned off, and the sixth transistor M6 is turned on by the reverse enable signal EN_INV, pulling the output of the fifth transistor to the ground. At this time, the voltage at the output of the monitoring circuit (the second control signal VC) is the initial voltage (but the control circuit is not enabled at this time, and the acceleration circuit cannot be turned on).

[0060] When the control circuit is enabled and the loop is just beginning to form, the sixth transistor M6 is turned off via the reverse enable signal EN_INV. The voltage at the first node approaches VDD, the fifth transistor M5 remains off, and the voltage at the output of the monitoring circuit (the second control signal VC) remains at its initial value, thus turning on the acceleration circuit. As the loop is nearing completion, the voltage at the first node begins to decrease. At this point, the fifth transistor M5 turns on, and the voltage at the output of the monitoring circuit (the second control signal VC) rises, providing a turn-off signal for the acceleration circuit, which then turns off. Once the loop is fully formed, the voltage at the output of the monitoring circuit (the second control signal VC) is fixed, and it no longer responds to inputs, thus avoiding multiple triggers and saving circuit power.

[0061] Figure 4 A schematic diagram of an acceleration circuit provided in an embodiment of this disclosure. Figure 1 Combining Figure 2 , Figure 3 and Figure 4 As shown, the acceleration circuit 230 includes a seventh transistor M7; the control terminal of the seventh transistor M7 is coupled to the output terminal of the monitoring circuit 220, and the output terminal of the seventh transistor M7 is the output terminal of the acceleration circuit 230.

[0062] In some embodiments, the seventh transistor M7 is a PMOS transistor.

[0063] In some embodiments, the acceleration circuit 230 further includes a second resistor R2 for adjusting the acceleration current output by the acceleration circuit; the input terminal of the seventh transistor M7 is coupled to the power supply VDD through the second resistor R2.

[0064] The seventh transistor M7 is off when the monitoring circuit is off. In some embodiments, a switch can be added between the seventh transistor M7 and the second resistor R2 as needed to further accurately control the turn-on timing of the seventh transistor M7. When the voltage at the output of the monitoring circuit (the second control signal VC) is the initial voltage, the seventh transistor M7 is turned on, and the acceleration circuit provides an acceleration current Iacc determined by the power supply VDD and the second resistor R2.

[0065] In some embodiments, the acceleration circuit is specifically configured to turn on in response to a second control signal VC when the control circuit is in the startup phase to generate an acceleration current Iacc and output the acceleration current to a bias power supply.

[0066] Figure 5 A schematic diagram of a bias power supply provided in an embodiment of this disclosure. Figure 1 Combining Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, the bias power supply 211 includes a current source and a current mirror; the current mirror includes at least two mirror transistors M11 and Mb1-Mbn; the control terminals of the mirror transistors M11 and Mb1-Mbn are coupled to each other, the output terminal of the current source is coupled to the input terminal of the current mirror, the input terminal of the current mirror is also coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply 211; the output terminals of the third transistor M3 and the fourth transistor M4 are both coupled to the output terminal of the bias power supply 211. Wherein, n is greater than or equal to 0.

[0067] When the acceleration circuit is turned on, the acceleration circuit 230 outputs an acceleration current Iacc to the bias power supply 211, and the output current of the current source is Ib0. Therefore, the bias current output by the bias power supply 211 is Ib = Ib0 + Iacc. When the acceleration circuit is turned off, the acceleration current Iacc = 0, and the bias current output by the bias power supply 211 is Ib = Ib0. At this time, it is a fixed bias state.

[0068] Figure 6 A schematic diagram of an acceleration circuit and bias power supply provided in an embodiment of this disclosure. Figure 2 Combining Figure 2 , Figure 3 and Figure 6 As shown, the acceleration circuit includes an eighth transistor M8 and a third resistor R3 connected in parallel. The control terminal of the eighth transistor M8 is coupled to the output terminal of the fifth transistor M5, the input terminal of the eighth transistor M8 is coupled to the power supply VDD, and the output terminal of the eighth transistor M8 is the output terminal of the acceleration circuit. The bias power supply includes a fourth resistor R4 and a current mirror. The current mirror includes at least two mirror transistors M11' and Mb1'-Mbn'. The control terminals of the mirror transistors M11' and Mb1'-Mbn' are coupled to each other. The fourth resistor R4 and the third resistor R3 are connected in series and coupled to the output terminal of the acceleration circuit 230. The output terminal of the current mirror is the output terminal of the bias power supply 211. The output terminals of the third transistor M3 and the fourth transistor M4 are both coupled to the output terminal of the bias power supply. Where n is greater than or equal to 0.

[0069] When the control circuit is enabled and the second control signal VC is the initial voltage (or lower than the first preset value), the eighth transistor M8 is turned on. At this time, the bias current output by the bias power supply 211 is generated by the power supply VDD and the fourth resistor R4. The bias current output by the bias power supply 211 is Ib = (Vb - V gsM11’When the second control signal VC is greater than the first preset value, the eighth transistor M8 is turned off. At this time, the bias current output by the bias power supply 211 is generated by the power supply VDD, the fourth resistor R4, and the third resistor R3. The bias current output by the bias power supply 211 is Ib = (Vb - V) / R4; gsM11’ (R3+R4). When the acceleration circuit 230 is started, the bias current output by the bias power supply 211 is greater than the bias current output by the bias power supply 211 when the acceleration circuit 230 is turned off. The magnitude of the bias current Ib can be adjusted by regulating the values ​​of the fourth resistor R4 and the third resistor R3, thereby achieving the acceleration effect. V gsM11’ This is the gate-source voltage of the mirror transistor M11'.

[0070] In this embodiment of the present disclosure, the monitoring point of the monitoring circuit is set inside the comparison circuit. The first node inside the comparison circuit can accurately reflect the establishment state of the loop. Therefore, the opening and closing of the acceleration circuit can be controlled based on the voltage and / or current of the first node, thereby avoiding premature shutdown of the acceleration circuit.

[0071] In this embodiment, the monitoring point of the monitoring circuit is not directly related to the output of the control circuit, is not easily affected by the output, and will not be triggered multiple times. The monitoring circuit does not increase power consumption after it completes its operation.

[0072] In this embodiment, the acceleration circuit acts on the bias power supply to adjust the bias current output by the bias power supply, so that the acceleration effect can be applied evenly to each node of the loop without affecting the loop's own establishment process, thus avoiding jitter or overshoot.

[0073] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0074] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A control circuit, characterized in that, include: A comparator circuit is configured to compare a reference voltage and a feedback voltage to generate a first control signal, the comparator circuit having a bias power supply for providing current to the comparator circuit; The comparator circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein the control terminals of the first transistor and the second transistor are coupled; the input terminals of the first transistor and the second transistor are coupled to a power supply; the output terminal of the first transistor is coupled to the input terminal of the third transistor and the control terminal of the first transistor; a first node is located at the output terminal of the first transistor; the output terminal of the second transistor is coupled to the input terminal of the fourth transistor and the output terminal of the comparator circuit; the output terminals of the third transistor and the fourth transistor are coupled to a ground terminal; the control terminal of the third transistor is the first input terminal of the comparator circuit for receiving the feedback voltage; and the control terminal of the fourth transistor is the second input terminal of the comparator circuit for receiving the reference voltage. A monitoring circuit, whose input is coupled to the first node and whose output is coupled to the acceleration circuit, is configured to control the operating state of the acceleration circuit based on the voltage and / or current of the first node, so that the acceleration circuit is turned on when the control circuit is in the startup phase and turned off when the control circuit is in the stable phase. The acceleration circuit, whose input terminal is coupled to the monitoring circuit and whose output terminal is coupled to the bias power supply, is configured to adjust the bias current output by the bias power supply; the output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

2. The control circuit according to claim 1, characterized in that, The monitoring circuit is specifically configured to output a second control signal based on the voltage and / or current of the first node; The acceleration circuit is specifically configured to adjust the bias current output by the bias power supply in response to the second control signal, so that the bias current of the control circuit in the startup phase is greater than the bias current of the control circuit in the stable phase.

3. The control circuit according to claim 1, characterized in that, The monitoring circuit is configured to shut down the acceleration circuit when it detects that the voltage and / or current of the first node reaches a first preset value during the startup phase.

4. The control circuit according to claim 1, characterized in that, The monitoring circuit includes a detection unit, an initialization unit, and a current limiting unit. The detection unit and the current limiting unit are connected in series, and the initialization unit is connected in parallel with the current limiting unit. The output terminal of the detection unit is coupled to the input terminal of the acceleration circuit, and the detection unit is coupled to the first node. The detection unit is used to provide an adjustable current based on the voltage of the first node; The current limiting unit is used to adjust the rate of change of the voltage at the output terminal of the detection unit; The initialization unit is used to provide an initial voltage to the output of the detection unit during the startup phase, so as to turn on the acceleration circuit.

5. The control circuit according to claim 4, characterized in that, The detection unit includes a fifth transistor; and / or the initialization unit includes a sixth transistor; The output terminal of the fifth transistor is coupled to the current limiting unit, and the output terminal of the fifth transistor is the output terminal of the monitoring circuit. The output terminals of the current limiting unit and the sixth transistor are coupled to the ground terminal.

6. The control circuit according to claim 4, characterized in that, The current limiting unit includes a resistor and / or a capacitor.

7. The control circuit according to claim 4, characterized in that, The monitoring circuit further includes a first resistor for adjusting the rate of change of the voltage at the output terminal of the detection unit.

8. The control circuit according to claim 4, characterized in that, The acceleration circuit includes a seventh transistor; the control terminal of the seventh transistor is coupled to the output terminal of the monitoring circuit, and the output terminal of the seventh transistor is the output terminal of the acceleration circuit.

9. The control circuit according to claim 8, characterized in that, The acceleration circuit also includes a second resistor connected in series with the seventh transistor for adjusting the acceleration current output by the acceleration circuit; the input terminal of the seventh transistor is coupled to the power supply through the second resistor.

10. The control circuit according to claim 9, characterized in that, The bias power supply includes a current source and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled together, the output terminal of the current source is coupled to the input terminal of the current mirror, the input terminal of the current mirror is coupled to the output terminal of the acceleration circuit, and the output terminal of the current mirror is the output terminal of the bias power supply. The output terminals of the third transistor and the fourth transistor are both coupled to the output terminal of the bias power supply.

11. The control circuit according to claim 6, characterized in that, The acceleration circuit is specifically configured to activate in response to a second control signal when the control circuit is in the startup phase to generate an acceleration current and output the acceleration current to the bias power supply.

12. The control circuit according to claim 5, characterized in that, The acceleration circuit includes an eighth transistor and a third resistor connected in parallel; the control terminal of the eighth transistor is coupled to the output terminal of the fifth transistor, the input terminal of the eighth transistor is coupled to the power supply, and the output terminal of the eighth transistor is the output terminal of the acceleration circuit.

13. The control circuit according to claim 12, characterized in that, The bias power supply includes a fourth resistor and a current mirror; the current mirror includes at least two mirror transistors; the control terminals of the at least two mirror transistors are coupled together; the fourth resistor is connected in series with the third resistor and coupled to the output terminal of the acceleration circuit; the output terminal of the current mirror is the output terminal of the bias power supply.

14. The control circuit according to claim 1, characterized in that, Also includes: A switching circuit, coupled to the comparator circuit, is configured to control the operating state of the comparator circuit based on an enable signal; The switching circuit includes a ninth transistor and a tenth transistor; The control terminals of the ninth transistor and the tenth transistor receive the enable signal. The input terminals of the ninth transistor and the tenth transistor are coupled to a power supply. The output terminal of the ninth transistor is coupled to the control terminals of the first transistor and the second transistor. The output terminal of the tenth transistor is coupled to the output terminal of the second transistor.

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