Power management circuits and methods for integrated circuits having multiple power domains

Abstract

The invention discloses a power management circuit and a method for managing an integrated circuit. The power management circuit includes a level shifter and an output buffer. The level shifter is powered by at least a first supply voltage usable in a first supply domain of the integrated circuit. The level shifter converts a first control signal to a second control signal usable in the first power domain. The first control signal indicates a power state of a second supply voltage usable in a second power domain of the integrated circuit. The first supply voltage is ready earlier than the second supply voltage. The second power domain is different from the first power domain. The first control signal is provided by a third power domain different from the first and second power domains. The output buffer is used for buffering the second control signal to generate a third control signal, and performing power supply control of the integrated circuit according to the third control signal. The power management circuit can reduce the chip area and power consumption.

Description

Technical Field

[0001] This application relates to power management, and more particularly to a power management circuit for an integrated circuit having multiple power domains, and a method for managing an integrated circuit having multiple power domains. Background Art

[0002] System-on-chip (SoC) designs can integrate different circuit blocks (which include analog and digital circuits) onto a single chip to implement multiple functions. To reduce power consumption, the system-on-chip can be divided into different power domains, where different power domains can withstand different voltage levels. A power domain refers to a collection of hierarchical instances that share the same power supply. For example, each circuit block can operate at a suitable voltage level to reduce dynamic and static power consumption. In addition, unused power domains can be turned off so that the circuit blocks located therein can be disabled to reduce leakage power consumption. Summary of the Invention

[0003] Embodiments of this application disclose a power management circuit for an integrated circuit having multiple power domains, and a power management solution, which includes power-on control and power isolation in a circuit design having multiple power domains.

[0004] Some embodiments of this application disclose a power management circuit for an integrated circuit. The power management circuit includes a level shifter and an output buffer. The level shifter is powered at least by a first power voltage available in a first power domain of the integrated circuit. The level shifter is configured to convert a first control signal into a second control signal available in the first power domain. The first control signal indicates the power state of a second power voltage available in a second power domain of the integrated circuit. The first power voltage is ready earlier than the second power voltage. The second power domain is different from the first power domain. The first control signal is provided by a third power domain different from the first power domain and the second power domain. The output buffer is coupled to the level shifter and configured to buffer the second control signal to generate a third control signal and perform power control of the integrated circuit based thereon.

[0005] Some embodiments of the present application disclose a power management circuit for an integrated circuit. The power management circuit includes a level shifter and an output buffer. The level shifter is powered by at least a first power voltage available in a first power domain of the integrated circuit. The level shifter is configured to convert a first control signal into a second control signal available in the first power domain. The first control signal indicates whether both the first power voltage available in the first power domain of the integrated circuit and a second power voltage available in a second power domain of the integrated circuit are ready. The first power voltage is ready earlier than the second power voltage. The second power domain is different from the first power domain. The output buffer is coupled to the level shifter and configured to buffer the second control signal to generate a third control signal for power control of the integrated circuit accordingly.

[0006] Some embodiments of the present application disclose a method for managing an integrated circuit. The method includes: operating a level shifter at a first power voltage that powers a first power domain of the integrated circuit, where the first power domain is configured to receive an input signal from a second power domain of the integrated circuit, and the second power domain is powered by a second power voltage; when the first power voltage is ready and the second power voltage is not ready, using the level shifter to convert a first control signal provided by a third power domain different from the first power domain and the second power domain into a second control signal having a first logic level to isolate the second power domain from the first power domain, where the first control signal indicates at least a power state of the second power voltage; and when both the first power voltage and the second power voltage are ready, using the level shifter to convert the first control signal provided by the third power domain into the second control signal having a second logic level different from the first logic level to allow the first power domain to receive the input signal from the second power domain.

[0007] The power management solution disclosed in the present application can perform power control operations on an integrated circuit, such as power-on control operations or power isolation, in a situation where zero quiescent current is achieved. In addition, the power management solution disclosed in the present application can use a single control signal to isolate different power domains, thereby reducing the circuit chip area and power consumption. The physical layer of the integrated circuit can tolerate different power-on / off sequences. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an embodiment of an integrated circuit of the present application including multiple power domains.

[0009] Figure 2 It is a schematic diagram of a functional block of at least a part of the power management circuit of the present application.

[0010] Figure 3 It is Figure 2 a schematic diagram of a specific embodiment of the power management circuit shown.

[0011] Figure 4 It is Figure 3 a schematic diagram of an embodiment of the signal waveform involved in the operation of the power management circuit shown.

[0012] Figure 5 It is Figure 2 a schematic diagram of another specific embodiment of the power management circuit shown.

[0013] Figure 6 It is Figure 5 a schematic diagram of an embodiment of the signal waveform involved in the operation of the power management circuit shown.

[0014] Figure 7 It is Figure 2 a schematic diagram of another specific embodiment of the power management circuit shown.

[0015] Figure 8 It is Figure 7 a schematic diagram of an embodiment of the signal waveform involved in the operation of the power management circuit shown.

[0016] Figure 9 It is Figure 1 a schematic diagram of a specific embodiment of the integrated circuit shown.

[0017] Figure 10 It is Figure 2 a schematic diagram of another specific embodiment of the power management circuit shown.

[0018] Figure 11 It is Figure 10 a schematic diagram of an embodiment of the signal waveform involved in the operation of the power management circuit shown.

[0019] Figure 12 It is Figure 10 a schematic diagram of another embodiment of the signal waveform involved in the operation of the power management circuit shown.

[0020] Figure 13 It is Figure 2 a schematic diagram of another specific embodiment of the power management circuit shown.

[0021] Figure 14 It is Figure 13Schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit shown.

[0022] Figure 15 is Figure 13 Schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit shown.

[0023] Figure 16 is Figure 2 Schematic diagram of another specific implementation manner of the power management circuit shown.

[0024] Figure 17 Flowchart of an embodiment of the method for the present application to manage an integrated circuit. Specific implementation manner

[0025] The following disclosure discloses various embodiments or exemplifications that can be used to implement different features of the present application. Specific examples of parameter values, components, and configurations described below are used to simplify the content of the present application. As can be imagined, these descriptions are only for illustration and are not intended to limit the content of the present application. For example, the present application may reuse component symbols and / or reference numerals in multiple embodiments. Such reuse is for the purpose of simplicity and clarity, and in itself does not represent the relationship between different embodiments and / or configurations discussed.

[0026] In addition, it can be understood that if a component is described as "connected to" or "coupled to" another component, the two can be directly connected or coupled, or other intermediate components may appear between the two.

[0027] In a circuit system with multiple power domains, power-supply sequencing is used to reduce transient inrush current to a tolerable level. Incorrect power-supply sequencing can damage the circuit system. For example, in a situation where there is unwanted propagation of signals between a power-down domain and a power-on domain, a functioning block running in the power-on domain may receive input signals with an unknown state from the power-down domain, which can cause a large inrush current in the functioning block. To reduce leakage power consumption, power isolation is performed using a dedicated control signal for the power-on domain to disconnect the circuit blocks running in the power-down and power-on domains. However, since each power domain requires its own dedicated control signal, a circuit design with multiple different power domains will require a large number of control signals, resulting in an increase in chip area and power consumption.

[0028] Another concern is the power consumption of power-on control (POC), which includes power-on reset (POR) and brownout detection (BOD). For example, after a circuit system powered by a supply voltage is started, the POC circuit can keep the circuit system in a reset state until the supply voltage stabilizes. When the supply voltage stabilizes, the POC circuit can release the circuit system from the reset state and initialize the circuit system. However, the POC circuit consumes non-zero quiescent current. In low-power applications, the power consumption caused by this non-zero quiescent current accounts for a large part of the overall power consumption.

[0029] The present application discloses multiple power management circuits for an integrated circuit, which may have multiple power domains, including a first power domain powered by a first power voltage and a second power domain powered by a second power voltage. The multiple power management circuits may perform power control of the integrated circuit according to the second power voltage and a control signal, wherein the control signal may carry power state information of the first power voltage. The second power voltage may be ready earlier than the first power voltage, or be an available power voltage earlier than the first power voltage. In some embodiments, the power control includes (but is not limited to) power-on reset, power-down detection, and power isolation between different power domains. In some embodiments, the control signal may be a delayed version of the first power voltage, a power state signal indicating whether the first power voltage is ready, or other control signals capable of carrying the power state information of the first power voltage.

[0030] In some embodiments, at least one power management circuit may include a latch circuit controlled by the control signal. In some embodiments, at least one power management circuit may include a level shifter controlled by the control signal. In some embodiments, the level shifter may be implemented using a latch-type level shifter, a single-ended level shifter, or other types of level shifters. In some embodiments, at least one power management circuit may use the same control signal to achieve power isolation between any two of the multiple power domains of the integrated circuit. Additionally, or alternatively, at least one power management circuit may consume zero transient current during a power control operation. Further description is as follows.

[0031] Please refer to Figure 1, which shows an integrated circuit 10 including multiple power domains 11 and 12 in certain embodiments of the present application. The multiple power domains 11 and 12 are respectively powered by different power supply voltages VCC1 and VCC2. When the power domain 11 is powered up, it takes some time for the power supply voltage VCC1 to become available or ready for use. Similarly, when the power domain 12 is powered up, it takes some time for the power supply voltage VCC2 to become available or ready for use. The multiple power supply voltages VCC1 and VCC2 can both be provided by a power control module (PCM) 16 located in an always-on power domain. The power control module 16 can be an on-chip PCM in the integrated circuit 10 or an off-chip PCM outside the integrated circuit 10. In certain embodiments, one of the multiple power supply voltages VCC1 and VCC2 can be the core voltage at which a processor core operates, and the other of the multiple power supply voltages VCC1 and VCC2 can be the input / output voltage (I / O voltage) at which an input / output circuit (I / O circuit) operates. The processor core can be used to control the input / output circuit.

[0032] A power management circuit 100 is coupled to the multiple power domains 11 and 12 and can be used to perform power control of the integrated circuit 10 according to the power supply voltage VCC2 and a control signal CS, where the control signal CS carries power status information of the power supply voltage VCC1. The power control performed by the power management circuit 100 can include (but is not limited to) power-on reset, power-down detection, and power isolation between the multiple power domains 11 and 12, where the power isolation can be referred to as power gating or power shut-off (PSO). For example, in certain embodiments where the power supply voltage VCC2 is ready earlier than the power supply voltage VCC1, the power management circuit 100 can detect whether the power supply voltage VCC1 is ready according to the power supply voltage VCC2 and the control signal CS and perform a power-on control operation on the integrated circuit 10 accordingly. Additionally, or alternatively, in certain embodiments where the power supply voltage VCC2 that can be operative in the power domain 12 is ready earlier than the power supply voltage VCC1 that can be operative in the power domain 11, the power management circuit 100 can selectively isolate the power domain 11 and the power domain 12 according to the power supply voltage VCC2 and the control signal CS.

[0033] The control signal CS can be implemented using (but not limited to) the power supply voltage VCC1, a delayed version of the power supply voltage VCC1, or other power state signal that can indicate whether the power supply voltage VCC1 is ready. For example, the power state signal can indicate whether the power supply voltage VCC1 has reached a threshold level. When the voltage level of the power supply voltage VCC1 is lower than the threshold level, the power supply voltage VCC1 is not ready. When the voltage level of the power supply voltage VCC1 reaches or exceeds the threshold level, the power supply voltage VCC1 is ready. In some embodiments, the control signal CS can be implemented using a power state signal that can indicate whether both the power supply voltage VCC1 and the power supply voltage VCC2 are ready. For example, the control signal CS can be implemented using the power state signal provided by the normally-on power domain.

[0034] In this embodiment, the power management circuit 100 can be implemented as an on-chip circuit in the integrated circuit 10. However, this is not used to limit the protection scope of the present application. In some embodiments, the power management circuit 100 can be implemented as an off-chip circuit outside the integrated circuit 10. In some embodiments, the power management circuit 100 can be integrated into the power control module 16 without departing from the protection scope of the present application.

[0035] Figure 2 is a functional block diagram of an embodiment of the power management circuit of the present application. The power management circuit 200 can be used to implement Figure 1 at least a part of the power management circuit 100 shown. The power management circuit 200 includes (but not limited to) an inverter circuit 210 and a latch circuit 220. The inverter circuit 210 has an inverter input terminal T I and an inverter output terminal T O . The inverter circuit 210 can be used to receive the control signal CS from the inverter input terminal T I and generate a control signal CSB at the inverter output terminal TO.

[0036] The latch circuit 220 has a latch supply terminal T SL , a latch input terminal T I1 and a latch input terminal T I2 . The latch supply terminal T SL is coupled to the power supply voltage VCC2. The latch input terminal T I1 and the latch input terminal T I2 are respectively coupled to the inverter output terminal TO and the inverter input terminal T I . The latch circuit 220 can be used to generate a control signal S I1 and the latch input terminal T I2 respectively according to the signal levels of each, and perform OUTB the power control of the integrated circuit 10 shown. That is, the latch circuit 220 can be used to generate the control signal S Figure 1 according to the control signal CSB input to the latch input terminal T I1 and the control signal CS input to the latch input terminal T I2 . In some embodiments, the control signal S OUTB and the power supply voltage VCC2 can be used in the same power supply domain. OUTB

[0037] Since the control signal CS carrying the power supply state information of the power supply voltage VCC1 is input to the latch circuit 220, the control signal S OUTB output from the latch circuit 220 can exhibit the power supply state information. For example, the power supply state information can indicate the voltage level of the power supply voltage VCC1 or the power supply state of the power supply voltage VCC1, such as whether the power supply voltage VCC1 is ready. In addition, when the power supply voltage VCC2 reaches a threshold level and thus becomes a ready power supply voltage, the latch circuit 220 can start to operate properly. Therefore, the control signal S OUTB can also indicate whether both the power supply voltage VCC1 and the power supply voltage VCC2 are ready.

[0038] In some embodiments, when the power supply state information indicates that the power supply voltage VCC1 is not ready, one of the signal levels of the signal levels of the latch input terminal T I1 and the latch input terminal T I2 respectively will be higher than the other signal level of the signal levels of the latch input terminal T I1 and the latch input terminal T I2 respectively. The control signal S OUTB can have a first level, such as one of a logic high level and a logic low level. When the power supply state information indicates that the power supply voltage VCC1 is ready, one of the signal levels of the signal levels of the latch input terminal T I1 and the latch input terminal T I2 respectively will be lower than the other signal level of the signal levels of the latch input terminal T I1 and the latch input terminal T I2 respectively. The control signal S OUTBmay have a second level different from the first level, such as the other one of the logic high level and the logic low level. Thus, when the power supply voltage VCC2 is ready earlier than the power supply voltage VCC1, the control signal S OUTB may have different levels before and after the power supply voltage VCC1 becomes the ready power supply voltage.

[0039] For example, when the power supply status information indicates that the power supply voltage VCC1 is not ready, the signal level of the control signal CSB generated from the inverter circuit 210 may be higher than the signal level of the control signal CS. When the power supply status information indicates that the power supply voltage VCC1 is ready, the signal level of the control signal CSB may be lower than the signal level of the control signal CS. Also for example, when the power supply status information indicates that the power supply voltage VCC1 is not ready, the signal level of the control signal CSB generated from the inverter circuit 210 may be lower than the signal level of the control signal CS. When the power supply status information indicates that the power supply voltage VCC1 is ready, the signal level of the control signal CSB may be higher than the signal level of the control signal CS.

[0040] In this embodiment, the power management circuit 200 may further include an output buffer 230, which can be used to buffer the control signal S OUTB to generate a control signal S OUT . The power management circuit 200 may perform OUT the power control of the integrated circuit 10 as shown in Figure 1 . In some embodiments, the output buffer 230 can be used to reduce the loading effect and / or change the signal level of the control signal S OUTB . The output buffer 230 can be implemented using (but not limited to) a buffer amplifier, a voltage follower, or an inverter circuit. In some embodiments, the output buffer 230 can also be omitted. The power management circuit 200 can directly output the control signal S OUTB to perform Figure 1 the power control of the integrated circuit 10 as shown, without departing from the scope of protection of the present application. In some embodiments, the power domain applicable to the control signal S OUTB output from the latch circuit 220 may be different from the power domain applicable to the control signal CS input to the inverter circuit 210. For example (but the present application is not limited thereto), the control signal CS can be implemented using the power supply voltage VCC1 or a delayed version of the power supply voltage VCC1, where the power supply voltage VCC1 can be applicable to the power domain 11 (i.e., the power supply voltage VCC1 can be used in the power domain 11), which is different from the control signal S OUTBThe applicable power domain 12 (i.e., the control signal S OUTB can be used in the power domain 12). For another example, the control signal CS can be implemented by using a power status signal provided by a normally-on power domain different from the power domain 12. Therefore, the inverter circuit 210 and the latch circuit 220 can be used to implement at least a part of a level shifter 202, where the level shifter 202 can be used to convert the control signal CS into a control signal S OUTB that can be used in the power domain 12. The control signal CS can be used in a power domain different from the power domain 12. In this embodiment, the level shifter 202 can be regarded as a latched level shifter. In some embodiments, the power management scheme disclosed in the present application can use a single-ended level shifter or other types of level shifters to generate the control signal S OUTB , without departing from the protection scope of the present application. The relevant description will be described later.

[0041] Please refer to Figure 1 and Figure 2 together. In some embodiments, the power management circuit 200 can perform a power-on control operation on the integrated circuit 10 according to the control signal S OUTB / S OUT . The latch circuit 220 operates at the power supply voltage VCC2, which can be ready earlier than the power supply voltage VCC1. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 is not ready, the latch circuit 220 can be used to generate the control signal S OUTB to keep the integrated circuit 10 in the reset state. For example, the latch circuit 220 can generate a control signal S OUTB with a first level to keep at least one circuit block operating in the power domain 12 in the reset state, and / or keep at least one circuit block operating in the power domain 11 in the reset state. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 is ready, the latch circuit 220 can be used to generate the control signal S OUTB to release the integrated circuit 10 from the reset state. For example, the latch circuit 220 can generate a control signal S OUTB with a second level to release the at least one circuit block operating in the power domain 12 from the reset state, and / or release the at least one circuit block operating in the power domain 11 from the reset state.

[0042] In some embodiments, the power management circuit 200 can perform a power-on control operation on the integrated circuit 10 according to the control signal S OUTB / S OUT, power isolation is provided between different power domains in the integrated circuit 10. For example, the latch circuit 220 can operate at a power supply voltage VCC2, which may be ready earlier than the power supply voltage VCC1. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 used by the power domain 11 is not yet ready, the latch circuit 220 can be used to generate a control signal S OUTB , to isolate the power domain 11 and a part of the integrated circuit 10. The said part of the integrated circuit 10 operates in the power domain 12. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 used by the power domain 11 is ready, the latch circuit 220 can be used to generate a control signal S OUTB , to allow the power domain 11 to be coupled to the said part of the integrated circuit 10.

[0043] It should be noted that the power management scheme disclosed in the present application can perform power-on control operations or power isolation in the case of achieving zero static current. For example, when multiple power supply voltages VCC1 and the power supply voltage VCC2 are both ready or stable, the inverter circuit 210 and the latch circuit 220 can both consume zero transient current.

[0044] For the convenience of understanding the content of the present application, the power management scheme disclosed in the present application is further described below based on certain embodiments. First, the power management scheme disclosed in the present application is described by taking the application of power-on control as an example. Figure 3 shows Figure 2 a specific implementation manner of the power management circuit 200 shown. In this embodiment, the power management circuit 300 can be used to perform a power-on control operation on Figure 1 the integrated circuit 10 shown. The power-on control operation may include (but is not limited to) power-on reset and power-down detection. The power management circuit 300 may include an inverter circuit 310, a latch circuit 320, an output buffer 330, a resistive element 340, and a delay element 350. The inverter circuit 310, the latch circuit 320, and the output buffer 330 can be respectively used as Figure 2 embodiments of the inverter circuit 210, the latch circuit 220, and the output buffer 230 shown.

[0045] In this embodiment, the inverter circuit 310 can be implemented by using multiple transistors M PI and M NI . The gates of multiple transistors M PI and M NI are each coupled to the inverter input terminal T I of the inverter circuit 310. The gates of multiple transistors M PI and M NITheir respective drains are all coupled to the inverter output terminal T of the inverter circuit 310 O The source of transistor M PI is coupled to the inverter power supply terminal T of the inverter circuit 310 SI The source of transistor M NI is coupled to a reference voltage, such as a ground voltage.

[0046] The latch circuit 320 can act as a comparator having a non-inverting input terminal and an inverting input terminal. In this embodiment, the latch input terminal T I1 and the latch input terminal T I2 can respectively serve as the non-inverting input terminal and the inverting input terminal. Therefore, when the signal level of the latch input terminal T I1 is higher than the signal level of the latch input terminal T I2 , the control signal S OL output from the latch output terminal T OUTB can have a high level or a logic high level. When the signal level of the latch input terminal T I1 is lower than the signal level of the latch input terminal T I2 , the control signal S OL output from the latch output terminal T OUTB can have a low level or a logic low level.

[0047] The output buffer 330 is coupled to the latch circuit 320 to buffer the control signal S OUTB to generate the control signal S OUT . In this embodiment, the output buffer 330 can be implemented using an inverter circuit operating at the power supply voltage VCC2. Therefore, the power management circuit 300 can use the inverted signal of the control signal S OUTB , that is, the control signal S OUT , to perform the power-on control operation.

[0048] The resistor unit 340 is coupled between the power supply voltage VCC2 and the inverter power supply terminal T SI to generate a voltage drop V R according to a current signal I D flowing through the resistor unit 340. In some embodiments, the resistor unit 340 can be implemented using at least one resistor, at least one diode, at least one diode-connected transistor, at least one circuit unit capable of providing electrical resistance, and combinations thereof.

[0049] The delay unit 350 is coupled to the inverter input terminal T I, for receiving the power supply voltage VCC1 and outputting a delayed version of the power supply voltage VCC1 to the inverter input terminal T I The delayed version of the power supply voltage VCC1, hereinafter referred to as the power supply voltage VCCR1, may carry power supply status information indicating the voltage level of the power supply voltage VCC1. The power supply voltage VCCR1 may be used as Figure 2 The control signal CS is shown in the embodiment. From the inverter output terminal T O Output voltage signal V COM Available as Figure 2 An embodiment of the control signal CSB is shown.

[0050] Figure 4 Shows Figure 3 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of the power management circuit 300. Figure 1 , Figure 3 See also Figure 4 At time point t0, the power control module 16 may start (power up) the power domain 12, and the power voltage VCC2 begins to rise. Since the power voltage VCC2 is not ready (unready), the power management circuit 300 may keep the integrated circuit 10 in a reset state. For example, the output buffer 330 may control the signal S OUTB Inverting to generate a control signal S with a logic low level OUT , so that one or more circuit blocks operating in the power domain 12 are in a reset state.

[0051] Between time point t0 and time point t1, since the power supply voltage VCCR1 / VCC1 is at a low level, the transistor M PI can be turned on, and transistor M NI can be turned off. Applying a latch input T I1 The voltage signal V COM When the power supply voltage VCC2 reaches a threshold level, so that the latch circuit 320 can operate correctly, since the power supply voltage VCC1 and the power supply voltage VCC2 are not ready yet, the control signal S OUT Still at the logic low level.

[0052] At time point t1, the power supply voltage VCC2 reaches a nominal / rated level, such as 3.3V. COM may have a voltage equal to or approximately equal to the rated level minus the voltage drop V DThe voltage level. In addition, the power supply control module 16 can activate the power supply domain 11, and the power supply voltages VCC1 / VCCR1 start to rise. Between time point t1 and time point t2, due to the signal level at the latch input T I1 of the signal level (voltage signal V COM of the voltage level) is high enough for the signal level at the latch input T I2 of the signal level (voltage level of the power supply voltage VCCR1), therefore, the control signal S OUTB can have a logic high level, such as 3.3V. The control signal S OUT can be at the logic low level.

[0053] At time point t2, the power supply voltage VCC1 reaches or exceeds a threshold level V CT1 , enabling the transistor M NI to be turned on. The voltage signal V COM can be reduced to zero or approximately zero. For example (but not limited to this application), when the power supply voltage VCCR1 ramps up / gradually increases to the threshold voltage of the transistor M NI , the power supply voltage VCC1 reaches the threshold level V CT1 . In addition, the difference between the respective signal levels of the latch input T I1 and the latch input T I2 , such as |V COM - VCCR1|, reaches or exceeds a transition threshold. The control signal S OUTB can transition from the logic high level to the logic low level, thereby indicating that the power supply voltage VCC1 is ready. The power management circuit 300 can release the integrated circuit 10 from the reset state. For example, the output buffer 330 can invert the control signal S OUTB to generate a control signal S OUT with the logic high level (such as 3.3V), thereby releasing the one or more circuit blocks operating in the power supply domain 12 of the integrated circuit 10 from the reset state. Between time point t2 and time point t3, the control signal S OUTB can be at the logic low level, and the control signal S OUT can be at the logic high level. The transistor M PI can be turned off. During the period when both the power supply voltage VCC1 and the power supply voltage VCC2 are ready, the power management circuit 300 can consume zero transient current.

[0054] At time point t3, for example, due to a power-down situation, the power supply voltage VCC1 drops below or reaches a threshold level V CT2 . The transistor MNI can be turned off, while transistor M PI can be turned on. The voltage signal V COM can be increased to a voltage level equal to or approximately equal to the rated level of the power supply voltage VCC2 minus the voltage drop V D . For example (but not limited to this application), when the power supply voltage VCCR1 ramps down / step-downs to the threshold voltage of transistor M NI , the power supply voltage VCC1 will reach the threshold level V CT2 . The control signal S OUTB can transition from the logic low level to the logic high level, thereby indicating that the power supply voltage VCC1 is not ready. The power management circuit 300 can put the integrated circuit 10 in a reset state. For example, the output buffer 330 can invert the control signal S OUTB to generate a control signal S OUT with the logic low level, thereby keeping the one or more circuit blocks of the integrated circuit 10 operating in the power domain 12 in the reset state.

[0055] The above based on Figure 3 and Figure 4 the described circuit structure and operations are for illustrative purposes only and are not intended to limit the scope of protection of this application. In some embodiments, the inverter power supply terminal T SI of the inverter circuit 310 can be directly coupled to a power supply voltage, where the power supply voltage can be ready earlier than the power supply voltage VCC1 and has a nominal / rated voltage level lower than the nominal / rated voltage level of the power supply voltage VCC2. In some embodiments, the latch input terminal T I1 and the latch input terminal T I2 can serve as the inverting input terminal and non-inverting input terminal of a comparator, respectively. In some embodiments, the output buffer 330 can be implemented by other types of buffers (such as a voltage follower). In some embodiments, the output buffer 330 can be omitted. The power management circuit 300 can directly output the control signal S OUTB for power-on control operations. In some embodiments, the delay unit 350 can be omitted. The power supply voltage VCC1 can be directly input to the inverter input terminal T I and the latch input terminal T I2 . These changes and variations are all included in the scope of protection of this application.

[0056] In some embodiments, the delay unit 350 can be used to ensure that the power supply voltage VCC1 is at a certain state before the control signal S OUThas reached a stable state when transitioning to the high logic level. For example, when the supply voltage VCCR1 ramps up to a voltage level, since the supply voltage VCCR1 is a delayed version of the supply voltage VCC1, the supply voltage VCC1 may already have risen above the voltage level. Therefore, when the control signal S OUT transitions from the low logic level to the high logic level to indicate that the supply voltage VCC1 is ready, the supply voltage VCC1 will be closer to the rated level of the supply voltage VCC1, such as 1.2V, than the supply voltage VCCR1.

[0057] Please refer to Figure 5 , in some embodiments, Figure 3 the delay unit 350 shown can be implemented using a delay unit 550, where the delay unit 550 includes a resistor R D1 and a transistor M D1 . In this embodiment, the resistor R D1 is coupled to the supply voltage VCC1 to provide the supply voltage VCCR1. The gate of the transistor M D1 is coupled to the supply voltage VCCR1. The drain and source of the transistor M D1 are shorted to each other. Therefore, the transistor M D1 can act as a capacitor, which is coupled between the supply voltage VCCR1 and a reference voltage VSS. The delay unit 550 can act as a resistor-capacitor delay unit (RC delay element). In addition, the resistor unit 540 of the power management circuit 500 can be used as Figure 3 an embodiment of the resistor unit 340 shown. The resistor unit 540 includes a plurality of diode-connected transistors M R1 -M R3 connected in series with each other. When each of the diode-connected transistors M R1 -M R3 in the plurality of diode-connected transistors conducts, the voltage drop V D of the resistor unit 540 can be approximately equal to the sum of the threshold voltages of each of the diode-connected transistors M R1 -M R3 .

[0058] In this embodiment, the power management circuit 500 may further include a transistor M L , which can act as a capacitor coupled between the latch power supply terminal T SL of the latch circuit 320 and the latch output terminal T OL . During the ramp-up period of the supply voltage VCC2, the signal level of the latch output terminal T OL can be adjusted using the transistor M Land is pulled up to the power supply voltage VCC2.

[0059] Figure 6 illustrates Figure 5 a schematic diagram showing an example of the signal waveforms involved in the operation of the power management circuit 500 shown. Please refer also to Figure 5 and Figure 6 , at time point tA1, the power supply voltage VCC1 starts to rise. For example, Figure 1 the power supply domain 11 shown can be activated at time point tA1. In addition, since the power supply voltage VCC1 can be applied to the transistor M D1 through the resistor R D1 (acting as a capacitor), the power supply voltage VCCR1 can start to rise. After a period of time tP, the power supply voltage VCC1 can rise to the threshold level V CT1 . The power supply voltage VCCR1 can rise to the threshold voltage of the transistor M NI . Therefore, the transistor M NI can be turned on at time point tA2. Additionally, the voltage signal V COM can be reduced to zero or approximately zero

[0060] At time point tA3, the power supply voltage VCCR1 can be higher than the voltage signal V COM by a transition threshold, causing the difference between the signal levels of the latch input terminal T I1 and the latch input terminal T I2 , such as |VCCR1 - V COM |, to reach the transition threshold. The control signal S OUTB can transition from the logic high level to the logic low level. In addition, the control signal S OUT can transition from the logic low level to the logic high level, thereby indicating that the power supply voltage VCC1 is ready. It should be noted that when the control signal S OUT transitions from the logic low level to the logic high level, due to the presence of the delay unit 550, the voltage level of the power supply voltage VCC1 can be higher than the voltage level of the power supply voltage VCCR1. The power supply voltage VCC1 can become a sufficiently stable power supply voltage for the device to operate correctly.

[0061] At time point tA4, the power supply voltage VCC1 drops below or reaches the threshold level V CT2 (e.g., a power - down situation occurs). The power supply voltage VCCR1 can drop to the threshold voltage of the transistor M NI . The control signal S OUTB can transition from the logic low level to the logic high level. In addition, the control signal S OUTcan transition from the logic high level to the logic low level, thereby indicating that the power supply voltage VCC1 has become an unready power supply voltage. In this embodiment, the threshold level V CT2 can be equal to the threshold level V CT1 .

[0062] Since those skilled in the art should be able to understand the operation details of the power management circuit 500 after reading Figures 1 to 4 the relevant paragraphs, further description will not be elaborated herein.

[0063] Please refer to Figure 3 and Figure 4 again. In some embodiments, the delay unit 350 can provide hysteresis to increase noise immunity and system stability. For example, the delay unit 350 can utilize a delay unit with a hysteresis function, which can be used to generate a delayed version of the power supply voltage VCC1. During the ramp-up period of the power supply voltage VCC1, the delayed version of the power supply voltage VCC1 rises to a reference level when the power supply voltage VCC1 rises to a first threshold level. During the ramp-down period of the power supply voltage VCC1, the delayed version of the power supply voltage VCC1 drops to the reference level when the power supply voltage VCC1 drops to a second threshold level lower than the first threshold level. When the reference level is the voltage level of the threshold voltage of the transistor M NI , the first threshold level and the second threshold level can be the threshold level V CT1 and the threshold level V CT2 respectively. When the power supply voltage VCC1 ramps down to a voltage level between the threshold level V CT1 and the threshold level V CT2 due to noise interference, since the voltage level of the power supply voltage VCCR1 can still be higher than the voltage level of the threshold voltage of the transistor M NI , the control signal S OUT can still be at the logic high level. The delay unit with a hysteresis function can reduce the possibility of false transitions of the signal level in the control signal S OUTB / S OUT .

[0064] Please refer to Figure 7 . In some embodiments Figure 3 the delay unit 350 shown can be implemented by using a delay unit 750. The circuit structure of the power management circuit 700 is the same as that of Figure 5The circuit structures of the power management circuits 500 shown are similar / identical. The main difference between the two is that the delay unit 750 further includes a resistor R D2 and a transistor M D2 . In this embodiment, one end of the resistor R D2 is coupled to the input terminal T of the inverter I1 and the transistor M D2 . The transistor M D2 is used to selectively couple the other end of the resistor R COM to the reference voltage VSS according to the voltage signal V D2 .

[0065] Figure 8 Shows Figure 7 a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 700 shown. Please refer to Figure 7 and Figure 8 together. At time point tB1, the power supply voltage VCC1 starts to rise from a low voltage level. The transistor M PI can be turned on, while the transistor M NI can be turned off. The voltage signal V COM can have a high enough level to turn on the transistor M D2 . Therefore, the resistor R D1 and the resistor R D2 can act as a voltage divider to divide the power supply voltage VCC1. Since the power supply voltage VCC1 can be applied to the transistor M D1 (as a capacitor) through the voltage divider, the power supply voltage VCCR1 can start to rise. The power supply voltage VCCR1 can be regarded as the divided voltage related to the power supply voltage VCC1.

[0066] After a period of time tQ, the power supply voltage VCC1 can rise to the threshold level V CT1 . In addition, the power supply voltage VCCR1 can rise to the threshold voltage of the transistor M NI . Therefore, the transistor M NI can be turned on at time point tB2. In some embodiments, since Figure 8 the threshold level V CT1 shown can be higher than Figure 6 the threshold level V CT1 shown, the length of the period of time tQ can be longer than Figure 6 the length of the period of time tP shown. Between time point tB2 and time point tB3, the transistor M PI can be turned off. The voltage signal V COM can have a low level, turning off the transistor M D2is turned off. The voltage level of the power supply voltage VCCR1 can be approximately equal to the voltage level of the power supply voltage VCC1.

[0067] At time point tB3, the latch input terminal T I1 and the latch input terminal T I2 The difference between the respective signal levels, such as |VCCR1 - V COM |, can reach a transition threshold. The control signal S OUTB can transition from the logic high level to the logic low level. In addition, the control signal S OUT can transition from the logic low level to the logic high level, thereby indicating that the power supply voltage VCC1 is ready.

[0068] At time point tB4, the power supply voltage VCC1 drops below or reaches the threshold level V CT2 (e.g., a power - down situation occurs). The power supply voltage VCCR1 can drop below or reach the threshold voltage of the transistor M NI . The transistor M NI can be turned off, while the transistor M PI can be turned on. The voltage signal V COM can have a high enough level to turn on the transistor M D2 . The power supply voltage VCCR1 can again become a voltage division related to the power supply voltage VCC1. The control signal S OUTB can transition from the logic low level to the logic high level. In addition, the control signal S OUT can transition from the logic high level to the logic low level, thereby indicating that the power supply voltage VCC1 becomes an unready power supply voltage. In this embodiment, Figure 8 the threshold level V shown CT2 can be equal to Figure 6 the threshold level V shown CT1 .

[0069] Since those skilled in the art should be able to understand the operation details of the power management circuit 700 after reading the relevant paragraphs of Figures 1 to 6 , further description will not be elaborated here.

[0070] In some embodiments, the power management scheme disclosed in this application can be applied to power isolation. Figure 9 is Figure 1 a specific implementation of the integrated circuit 10 shown. In this embodiment, the integrated circuit 90 has multiple power domains, which include a power domain 13, a normally - on power domain 14, and Figure 1The power domains 11 and 12 shown. A plurality of power domains 11-13 can be respectively powered by a plurality of power supply voltages VCC1-VCC3 transmitted by the normally-on power domain 14. In some embodiments, the plurality of power supply voltages VCC1-VCC3 can be a switchable power domain.

[0071] The integrated circuit 90 can utilize one or more power gating mechanisms to perform power isolation between different power domains. For example, the integrated circuit 90 can include a power management circuit 900, which can be used for power isolation between the plurality of power domains 11 and 12. The power management circuit 900 can be implemented as Figure 1 An embodiment of the power management circuit 100 shown. For another example, the integrated circuit 90 can include an isolation cell 901, which can be used for power isolation between the plurality of power domains 11 and 13. The isolation cell 901 can be implemented using (but not limited to) an OR gate. It should be noted that in some embodiments, the power management circuit 900 can be used for power isolation between any two of the plurality of power domains 11-13 without departing from the scope of protection of this application. In addition, the isolation cell 901 can be used for power isolation between any two of the plurality of power domains 11-13 without departing from the scope of protection of this application. Furthermore, in some embodiments, the power management circuit 900 can be disposed in the physical medium attachment layer (PMA) 961, the physical coding sublayer (PCS) 962, or the power control module 16 without departing from the scope of protection of this application.

[0072] For ease of explanation, the integrated circuit 90 will be described below as at least a part of an application processor (AP), and the application processor can support the specifications of the Mobile Industry Processor Interface (MIPI). Those skilled in the art can understand that the integrated circuit 90 can be implemented as an integrated circuit capable of supporting other types of communication interface specifications without departing from the scope of protection of this application.

[0073] In this embodiment, the integrated circuit 90 can further include Figure 1A power control module 16, an image signal processor (ISP) 92, a graphic processing unit (GPU) 94, and a receiver 96 are shown. The power control module 16 operates in the always-on power domain 14 and is used to provide multiple power voltages VCC1-VCC3 to multiple power domains 11-13, and to control the power-on / off timing of the multiple power domains 11-13. In addition, the power control module 16 can be used to generate a power status signal, such as a power good signal PWR_OK, to indicate that the multiple power voltages VCC1-VCC3 are all ready or available.

[0074] The image signal processor 92 operates in the power domain 11 and can be started by a start-up signal PWR_ON provided by the power control module 16. The graphic processing unit 94 operates in the power domain 13 and can be controlled by the isolation unit 901 to selectively isolate from the image signal processor 92. For example (but not limited to this application), when the power domain 11 is not ready or unavailable, the power control module 16 can transmit a control signal ISO_EN1 with a predetermined level (such as a high logic level). The isolation unit 901 can isolate the signal from the power domain 11 and the graphic processing unit 94 in the power domain 13 according to the control signal ISO_EN1.

[0075] A receiver 96, such as a Mobile Industry Processor Interface (MIPI) differential physical receiver (MIPI D-PHY receiver), may have a physical layer that may include a Physical Medium Attachment (PMA) layer 961 and a Physical Coding Sublayer (PCS) 962. Using a power management circuit 900 coupled between the PMA layer 961 and the PCS layer 962, the physical layer of the receiver 96 may allow different power-up / power-down timings. For example (but not limited to this application), when power domain 11 is not yet ready or unavailable, the power management circuit 900 may disconnect the PMA layer 961 in power domain 11 from the PCS layer 962 in power domain 12 according to a control signal ISO_EN2 provided by the power control module 16. In some embodiments, the control signal ISO_EN2 may carry power status information of the power supply voltage VCC1, thereby indicating whether the power supply voltage VCC1 is ready. In some embodiments, the control signal ISO_EN2 may carry power status information of multiple power supply voltages VCC1 and VCC2, respectively, thereby indicating whether multiple power supply voltages VCC1 and VCC2 are both ready. In some embodiments, the control signal ISO_EN2 may be a power status signal, such as a power ready signal PWR_OK or an inverted signal of the power ready signal PWR_OK.

[0076] Figure 10 Yes Figure 2 A specific implementation of the power management circuit 200 shown. In this embodiment, Figure 10 The power management circuit 1000 shown can be used to Figure 9 perform power isolation on different power domains of the integrated circuit 90 shown. The circuit structure of the power management circuit 1000 is similar / identical to Figure 3 the circuit structure of the power management circuit 300 shown. The main difference between the two is that the inverter power supply terminal T SI can be selectively coupled to one of the multiple power supply voltages VCC1 and VCC2. In this embodiment, the power management circuit 1000 may include an inverter circuit 1010, a latch circuit 1020, a switch circuit 1060, an output buffer 1070, and Figure 3 the output buffer 330 shown. The inverter circuit 1010 and the latch circuit 1020 may be embodiments of Figure 2 the inverter circuit 210 and the latch circuit 220 shown, respectively.

[0077] The latch circuit 1020 can utilize (but is not limited to) a cross-coupled inverter pair, which can include multiple transistors M LU1 , M LD1 , M LU2 and M LD2 . The latch input terminal T I1 is coupled to the gate of the transistor M LD1 to receive a voltage signal PWRB generated by the inverter circuit 1010. The latch input terminal T I2 is coupled to the gate of the transistor M LD2 to receive the control signal ISO_EN2 input to the inverter circuit 1010. The control signal ISO_EN2 can be an embodiment of the control signal CS as shown in Figure 2 . The voltage signal PWRB can be an embodiment of the control signal CSB as shown in Figure 2 . The latch power supply terminal T SL is coupled to the respective sources of the multiple transistors M LU1 and M LU2 to receive the power supply voltage VCC2. The latch output terminal T OL is coupled between the respective drains of the multiple transistors M LU2 and M LD2 to output the control signal S OUTB . Another latch output terminal T OLC is coupled between the respective drains of the multiple transistors M LU1 and M LD1 to output the inverted or complementary signal of the control signal S OUTB .

[0078] The switching circuit 1060 can include a resistor unit 1062, a switch 1064, and a switch 1066. The resistor unit 1062 is coupled between a circuit node N C and the inverter power supply terminal T SI . In this embodiment, the resistor unit 1062 can be implemented by a resistor R G . In some embodiments, the resistor unit 1062 can be implemented by at least one resistor, at least one diode, at least one transistor in a diode-connected form, at least one circuit unit capable of providing resistance, and combinations thereof, without departing from the scope of protection of this application. The switch 1064 can be selectively coupled between the power supply voltage VCC1 and the inverter power supply terminal T OLC according to a control signal PWRS (i.e., the signal level of the latch output terminal T SI . The switch 1066 can be selectively coupled between the power supply voltage VCC2 and the circuit node N CWhen one of switch 1064 and switch 1066 is turned on, the other one of switch 1064 and switch 1066 can be turned off. In this embodiment, switch 1064 and switch 1066 can be implemented by transistor M S1 and transistor M S2 respectively. In some embodiments, both switch 1064 and switch 1066 can be implemented by other types of switch units without departing from the protection scope of this application.

[0079] Output buffer 1070 is coupled to the latch output terminal T of latch circuit 1020 OLC , and can be used to buffer the complementary signal of control signal S OUTB to generate control signal PWRS. In this embodiment, output buffer 1070 can be implemented by a voltage follower operating at power supply voltage VCC2.

[0080] Figure 11 shows Figure 10 a schematic diagram of an embodiment of the signal waveforms involved in the operation of the power management circuit 1000 shown. Please refer to Figure 9 , Figure 10 together with Figure 11 . Before time point tC1, the control signal ISO_EN2 from the normally-open power domain 14 has a logic low level (such as 0V). In this embodiment, the control signal ISO_EN2 can be implemented by the power ready signal PWR_OK. The power ready signal PWR_OK with the logic low level can indicate that multiple power supply voltages VCC1 and VCC2 are not yet ready. In addition, the voltage signal PWRB can rise in response to the power supply voltage VCC2 having a rated level V1 (such as 3.3V). For example, inverter circuit 1010 can be implemented by Figure 3 the inverter circuit 310 shown. Since the power ready signal PWR_OK input to the gate of a p-channel transistor (such as Figure 3 the transistor M shown PI ) has the logic low level, the power supply voltage VCC2 can be applied to the inverter output terminal T through the resistance unit 1062 and the p-channel transistor O .

[0081] At time point tC1, since the voltage signal PWRB reaches or is higher than a threshold level, the latch input terminal T I1 and the latch input terminal T I2The difference between their respective signal levels (such as |PWRB-VCCR1|) reaches or exceeds a transition threshold (such as 0.9V). The control signal PWRS can have a logic low level that is valid in power domain 12, such as 0V. The control signal S OUTB can have a logic high level that is valid in power domain 12, such as 3.3V. Thus, the control signal S applicable to power domain 12 OUT can have the logic low level to indicate that neither of the multiple power supply voltages VCC1 and VCC2 is ready yet. Further, since the control signal PWRS can be at the logic low level in response to the power ready signal PWR_OK, before the power supply voltage VCC1 is ready, switch 1064 is turned off and switch 1066 is turned on.

[0082] At time point tC2, the power supply voltage VCC1 reaches its rated level V2, such as 1.2V. After a delay time, the power ready signal PWR_OK transitions to a logic high level V3, such as 1.2V, at time point tC3. At time point tC4, the voltage signal PWRB can drop to a voltage level V4, which can be equal to or approximately equal to the power supply voltage VCC2 minus the voltage drop V DG . The voltage drop V DG is generated according to a current signal flowing through resistor RG. By way of example (but not limited to this application), the voltage level V4 can be close to 0V, such as 0.2V.

[0083] At time point tC5, since the difference between the signal levels of latch input T I1 and latch input T I2 reaches or exceeds a transition threshold (such as |PWR_OK-PWRB|) (such as 0.9V), the control signal PWRS and the control signal S OUT can both transition to the logic high level (such as 3.3V) in power domain 12. Since the control signal PWRS can be at the logic high level in response to the power ready signal PWR_OK, when both of the multiple power supply voltages VCC1 and VCC2 are ready, switch 1064 is turned on and switch 1066 is turned off. At time point tC6, since switch 1064 is turned on to couple the power supply voltage VCC1 to inverter input T I , the voltage signal PWRB can be reduced to the logic low level (such as 0V) in power domain 11.

[0084] At time point tC7, the power control module 16 can deactivate the power ready signal PWR_OK (i.e., the control signal ISO_EN2) to turn off the power domain 11. The power ready signal PWR_OK can transition from the logic high level in the normally-on power domain 14 to the logic low level. At time point tC8, since the difference (such as |PWRB - PWR_OK|) between the respective signal levels of latch input T I1 and latch input T I2 reaches or exceeds a transition threshold (such as 0.9V), thus, the control signal PWRS and the control signal S OUT can both transition to the logic low level in the power domain 12. The voltage signal PWRB can rise to a rated level approximately equal to the power supply voltage VCC1 (such as 1.2V). At time point tC9, since the switch 1066 conducts according to the control signal PWRS, the power supply voltage VCC2 is coupled to the inverter power supply terminal T I through the resistor unit 1062. The voltage signal PWRB can rise to the rated level V1 of the power supply voltage VCC2.

[0085] Using the power ready signal PWR_OK that can indicate the power status of the power supply voltage VCC1, when the power supply voltage VCC1 is not yet ready or not yet available, the power management circuit 1000 can isolate one or more circuit blocks (such as the physical media connection layer 961) in the power domain 11 and the power domain 12. In addition, when both the power supply voltage VCC1 and the power supply voltage VCC2 are ready, the power management circuit 1000 can generate the control signal S OUTB / S OUT applicable to the power domain 12 to allow the power domain 11 to be coupled to the one or more circuit blocks in the power domain 12.

[0086] In some embodiments, the control signal ISO_EN2 can also carry the power status information of the power supply voltage VCC2. When one of the multiple power supply voltages VCC1 and VCC2 is ready and the other is not yet ready (for example, during the power startup timing), the control signal ISO_EN2 can be at a first level (such as one of a logic high level and a logic low level). When both the multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 can be at a second level different from the first level. Figure 12 Shows Figure 10 a schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit 1000 shown. Figure 12 The signal waveforms shown are related to Figure 11The signal waveforms shown are similar / identical. The difference between the two is that the control signal ISO_EN2 can be at a logic high level before the power supply voltage VCC2 is ready. In addition, when the power supply voltage VCC2 is ready and the power supply voltage VCC1 is not ready, the control signal ISO_EN2 can be at a logic low level. When multiple power supply voltages VCC1 and VCC2 are both ready, the control signal ISO_EN2 can return to a logic high level. Since those skilled in the art should understand the operation details of the power management circuit 1000 shown by reading the relevant paragraphs of Figures 1 to 11 afterwards, Figure 10 the power management circuit 1000 shown adopts Figure 12 the operation details of the signal waveform shown, therefore, further description will not be elaborated here.

[0087] In some embodiments, the power management solution disclosed in the present application can utilize the inverted signal of the power ready signal (provided by the always-on power domain) for power isolation. Figure 13 is Figure 2 another specific implementation of the power management circuit 200 shown. In this embodiment, Figure 13 the power management circuit 1300 shown can be used to perform power isolation on different power domains of the integrated circuit 90 shown. The circuit structure of the power management circuit 1300 is similar / identical to the circuit structure of the power management circuit 1000 shown, and the main difference between the two is that the power supply voltage VCC1 can be coupled to the inverter power supply terminal T before it is ready Figure 9 Figure 10 SI . In addition, the output buffer 1330 can be implemented using a voltage follower. In this embodiment, the power management circuit 1300 can utilize a power status signal PWR_OKN (which is the inverted signal of the power ready signal PWR_OK shown) for power isolation. The power status signal PWR_OKN can be used as an embodiment of the control signal ISO_EN2 shown Figure 9 Figure 9

[0088] Figure 14 shows Figure 13 a schematic diagram of an embodiment of the signal waveform involved in the operation of the power management circuit 1300 shown. Please refer to Figure 9 and Figure 13 together with Figure 14 . Before the time point tD1, the power status signal PWR_OKN can be at a logic high level to indicate that not all of the multiple power supply voltages VCC1 and VCC2 are ready. The voltage signal PWRB input to the latch input terminal T I1 can have a logic low level. Therefore, the signal level at the latch input terminal T I1 will be lower than the signal level at the latch input terminal T I2 ​​​​The signal level. Control signal S OUTB may have a logic low level to indicate that the power supply voltage VCC1 is not yet ready. The power management circuit 1300 may thereby generate a control signal S having a logic low level OUT , thereby isolating the power domain 11 from the physical media attachment layer 961 operating in the power domain 12.

[0089] At time point tD1, the power status signal PWR_OKN may transition to a logic low level to indicate that both power supply voltages VCC1 and VCC2 are ready. The signal level at the latch input T I1 will be higher than the signal level at the latch input T I2 The signal level. Control signal S OUTB may have a logic high level. The power management circuit 1300 may thereby generate a control signal S having a logic high level OUT , thereby allowing signals to be transmitted from the power domain 11 to the physical media attachment layer 961 operating in the power domain 12. At time point tD2, the power control module 16 may deactivate the power ready signal PWR_OK to turn off the power domain 11. The power status signal PWR_OKN may transition to the logic high level. The power domain 11 may be isolated from the physical media attachment layer 961 operating in the power domain 12 again.

[0090] In some embodiments, the control signal ISO_EN2 may also carry the power status information of the power supply voltage VCC2. When one of the power supply voltages VCC1 and VCC2 is ready while the other is not yet ready (e.g., during the power-up timing sequence), the control signal ISO_EN2 may be at a first level (such as one of a logic high level and a logic low level). When both power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 may be at a second level different from the first level. Figure 15 illustrates Figure 13 a schematic diagram of another embodiment of the signal waveforms involved in the operation of the power management circuit 1300 shown in Figure 15 The signal waveforms shown in Figure 14 are similar / same as the signal waveforms shown in Figures 1 to 14 , with the difference that the control signal ISO_EN2 may be at a logic low level before the power supply voltage VCC2 is ready. In addition, when the power supply voltage VCC2 is ready while the power supply voltage VCC1 is not yet ready, the control signal ISO_EN2 may transition to a logic high level. When both power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 may return to a logic low level. Since those skilled in the art should understand after reading Figure 13 the power management circuit 1300 shown inFigure 15 The operation details of the signal waveform shown are thus not further elaborated herein.

[0091] As described above, the power management solution disclosed in the present application can convert a control signal applicable to one power domain into a control signal applicable to another power domain, thereby performing power control operations. For example (but not limited to this application), the aforementioned power management circuits 200 / 300 / 1000 / 1300 can be implemented to include a level shifter and an output buffer. In Figure 2 the illustrated embodiment, the inverter circuit 210 and the latch circuit 220 can be used to implement at least a part of the level shifter 202. In Figure 3 the illustrated embodiment, the inverter circuit 310, the latch circuit 320, and the resistor unit 340 can be used to implement at least a part of the level shifter 302. In Figure 10 the illustrated embodiment, the inverter circuit 1010, the latch circuit 1020, and the switching circuit 1060 can be used to implement at least a part of the level shifter 1002. In Figure 13 the illustrated embodiment, the inverter circuit 1010 and the latch circuit 1020 can be used to implement at least a part of the level shifter 1302.

[0092] In some embodiments, the power management solution disclosed in the present application can use a single-ended level shifter and an output buffer for power isolation. Figure 16 is Figure 2 another specific implementation of the power management circuit 200 shown. In this embodiment, the power management circuit 1600 can be used to Figure 9 perform power isolation on different power domains of the integrated circuit 90 shown. In addition, the power management circuit 1600 can be implemented to include a single-ended level shifter.

[0093] Please also refer to Figure 9 and Figure 16 , the power management circuit 1600 can include a level shifter 1602 and Figure 3 the output buffer 330 shown. The level shifter 1602 is powered by the power supply voltage VCC2 used in the power domain 12. The level shifter 1602 can be used to convert the control signal ISO_EN2 into a control signal S applicable to the power domain 12 OUTB . In this embodiment, the level shifter 1602 includes a transistor M LS and a resistor unit R S (such as a resistor). In addition, the control signal ISO_EN2 for controlling the switching state of the transistor M LS can be implemented using a power supply status signal (such as the power ready signal PWR_OK).

[0094] During operation, before the power supply voltage VCC1 is ready, the power supply ready signal PWR_OK is at a logic low level. The transistor M LS is turned off. The control signal S OUTB can have a logic high level, such as the rated level of the power supply voltage VCC2. The control signal S OUT can have a logic low level to indicate that the power supply voltage VCC1 is not yet ready. The power management circuit 1600 can isolate the physical media connection layer 961 in the power domains 11 and 12 according to the control signal S OUT . When multiple power supply voltages VCC1 and VCC2 are both ready, the power supply ready signal PWR_OK changes from the logic low level to a logic high level to turn on the transistor M LS . The control signal S OUTB can change to the logic low level. The control signal S OUT can change to the logic high level, which can indicate that multiple power supply voltages VCC1 and VCC2 are both ready. The power management circuit 1600 can allow the power domain 11 to be coupled to the physical media connection layer 961 in the power domain 12 according to the control signal S OUT .

[0095] It should be noted that the power management scheme disclosed in the present application can use a single control signal (such as a power status signal directly provided from a normally-on power domain) to perform power isolation between different power domains. Please refer to Figure 9 and Figure 13 again. In some embodiments, since the control signal ISO_EN2 can be level-converted to a control signal applicable to the power domain 13, the power management circuit 900 can isolate one or more circuit blocks in the power domains 11 and 13 according to the control signal ISO_EN2. For example, when the power management circuit 900 is used to isolate the graphics processing unit 94 in the power domains 11 and 13, the inverter circuit 110 and the latch circuit 1020 can be powered by the power supply voltages VCC1 and VCC3 respectively. The level converter 1302 can still receive the power status signal PWR_OKN to convert the power status signal PWR_OKN into a control signal S OUTB , which can be used in the power domain VCC3. Using the power management scheme disclosed in the present application, a single control signal can be used to perform power isolation between multiple power domains, so the circuit chip area and power consumption can be reduced.

[0096] Figure 17 is a flowchart of an embodiment of the method for managing an integrated circuit in the present application. For the convenience of description, the following is based on Figure 9 the integrated circuit shown in Figure 2The method 1700 will be described with reference to the level shifter shown. Those skilled in the art will appreciate that the method 1700 can be applied to Figure 1 the integrated circuit 10 shown or other integrated circuits having multiple power domains without departing from the scope of the present application. In addition, those skilled in the art will appreciate that the method 1700 can utilize other level shifters, such as Figure 3 the level shifter 302 shown, Figure 10 the level shifter 1002 shown, Figure 13 the level shifter 1302 shown, Figure 16 the level shifter 1602 shown, or other types of level shifters, without departing from the scope of the present application. In addition, in some embodiments, other operations may be performed in the method 1700. In some embodiments, the operations in the method 1700 may be performed in a different order or implemented by other operations. In some embodiments, one or more operations in the method 1700 may be omitted.

[0097] In operation 1702, a level shifter is used and the level shifter is operated at a first power voltage of a first power domain that supplies power to the integrated circuit. The first power domain is used to receive an input signal from a second power domain of the integrated circuit, and the second power domain is powered by a second power voltage. For example, the level shifter 202 may be powered by the power voltage VCC2 in the power domain 12. The physical media attachment layer 961 in the power domain 12 may receive an input signal, such as a data input or a control input, from the physical coding sublayer 962 in the power domain 11 that is powered by the power voltage VCC1.

[0098] In operation 1704, when the first power voltage is ready and the second power voltage is not ready, the level shifter is used to convert a first control signal into a second control signal having a first logic level to isolate the second power domain from the first power domain, where the first control signal at least indicates the power state of the second power voltage. For example, the level shifter 202 may be implemented in the power management circuit 900. When the power voltage VCC2 is ready and the power voltage VCC1 is not ready, the level shifter 202 may be used to convert the control signal CS into a control signal S OUTB having a first logic level (such as one of a logic high level and a logic low level) to isolate the power domain 11 from the power domain 12. Thus, the input signal (which may have an unknown state transmitted from the power domain 11) can be isolated from the power domain 12. The physical coding sublayer 962 in the power domain 11 may not be coupled to the physical media attachment layer 961 in the power domain 12.

[0099] In some embodiments, Figure 2The control signal CS shown can be implemented using the power status signal provided by the always-on power domain 14. In some embodiments, Figure 2 The control signal CS shown can be implemented using a power status signal that can indicate whether the power supply voltage VCC1 is ready. In some embodiments, Figure 2 The control signal CS shown can be implemented using a power status signal that can indicate whether both the power supply voltage VCC1 and the power supply voltage VCC2 are ready. For example, the control signal CS can be implemented by the power ready signal PWR_OK transmitted by the power control module 16. Another example is that the control signal CS can be implemented by a control signal ISO_EN2 having a signal waveform Figure 11 、 Figure 12 、 Figure 14 or Figure 15 similar / same as.

[0100] In operation 1706, when both the first power supply voltage and the second power supply voltage are ready, the level shifter is used to convert the first control signal into the second control signal having a second logic level to allow the first power domain to receive the input signal from the second power domain. For example, when the power supply voltage VCC1 and the power supply voltage VCC2 are both ready, the level shifter 202 can be used to convert the control signal CS into a control signal S OUTB having a second logic level (such as the other one of the logic high level and the logic low level) to allow the power domain 12 to receive the input signal from the power domain 11. Therefore, the input signal provided by the power domain 11 can be transmitted to the power domain 12. The physical coding sublayer 962 in the power domain 11 can be allowed to be coupled to the physical medium attachment layer 961 in the power domain 12.

[0101] Since those skilled in the art should be able to understand the operation details of the power management circuit 1700 after reading the relevant paragraphs Figures 1 to 16 description, further description will not be elaborated here.

[0102] The above description briefly presents the features of some embodiments of the present application, enabling those skilled in the art to more comprehensively understand various aspects of the present application. Those skilled in the art of the present application should understand that they can easily use the content of the present application as a basis to design or modify other processes and structures to achieve the same purpose and / or reach the same advantages as the embodiments described herein. Those skilled in the art of the present application should understand that these equivalent embodiments still fall within the spirit and scope of the content of the present application, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of the content of the present application.

Claims

1. A power management circuit for an integrated circuit, characterized in that, Comprising: A level shifter, powered at least by a first power supply voltage usable in a first power domain of the integrated circuit, the level shifter being configured to convert a first control signal into a second control signal usable in the first power domain, the first control signal indicating a power supply state of a second power supply voltage usable in a second power domain of the integrated circuit, the first power supply voltage being ready earlier than the second power supply voltage, the second power domain being different from the first power domain, wherein the first control signal is provided by a third power domain different from the first power domain and the second power domain; And An output buffer, coupled to the level shifter, configured to buffer the second control signal to generate a third control signal and perform power supply control of the integrated circuit based thereon.

2. The power management circuit according to claim 1, characterized in that, The third power domain is a always-on power domain.

3. The power management circuit according to claim 1, wherein The first control signal is a power supply state signal for indicating whether both the first power supply voltage and the second power supply voltage are ready.

4. The power management circuit according to claim 1, wherein When the first control signal indicates that the second power supply voltage is not ready, the output buffer is configured to generate the third control signal to isolate the second power domain and a part of the integrated circuit operating in the first power domain; When the first control signal indicates that the second power supply voltage is ready, the output buffer is configured to generate the third control signal to allow the second power domain to be coupled to the part of the integrated circuit.

5. The power management circuit according to claim 1, wherein The level shifter includes: An inverter circuit, having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive the first control signal from the inverter input terminal and generate a fourth control signal at the inverter output terminal; and A latch circuit, having a latch power supply terminal, a first latch input terminal and a second latch input terminal, the latch power supply terminal being coupled to the first power supply voltage, the first latch input terminal being coupled to the inverter output terminal to receive the fourth control signal, the second latch input terminal being coupled to the inverter input terminal to receive the first control signal, the latch circuit being configured to generate the second control signal according to signal levels of the first control signal and the fourth control signal respectively.

6. The power management circuit according to claim 5, wherein The inverter power supply terminal of the inverter circuit is configured to receive the second power supply voltage; wherein when the second power supply voltage is not ready, the first control signal has a first logic level; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level.

7. The power management circuit according to claim 5, wherein The latch circuit further includes a first latch output terminal and a second latch output terminal, the first latch output terminal being configured to output the second control signal; The level shifter further includes: a resistor unit, coupled between a circuit node and the inverter power supply terminal of the inverter circuit; A first switch, selectively coupled between the first power supply voltage and the circuit node according to a signal level of the second latch output terminal; and A second switch selectively coupled between the second power supply voltage and the inverter power supply terminal according to the signal level at the output terminal of the second latch; Wherein when the second power supply voltage is not yet ready, the first control signal has a first logic level, the first switch is turned on, and the second switch is turned off; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level, the first switch is turned off, and the second switch is turned on.

8. The power management circuit according to claim 1, wherein The level converter includes: A resistor unit coupled between the first power supply voltage and the input terminal of the output buffer; and A transistor having a control terminal, a first connection terminal, and a second connection terminal, wherein the control terminal is coupled to the first control signal, the first connection terminal is coupled to the input terminal of the output buffer, and the second connection terminal is coupled to a reference voltage.

9. The power management circuit according to claim 1, characterized in that The first control signal also indicates the power supply state of the first power supply voltage; when neither the first power supply voltage nor the second power supply voltage is ready, the first control signal has a first logic level; when the first power supply voltage is ready and the second power supply voltage is not yet ready, the first control signal has a second logic level different from the first logic level; When both the first power supply voltage and the second power supply voltage are ready, the first control signal has the first logic level.

10. A power management circuit for an integrated circuit, characterized in that, Comprising: A level converter powered at least by a first power supply voltage available in a first power domain of the integrated circuit, the level converter being configured to convert a first control signal into a second control signal available in the first power domain, the first control signal indicating whether both a first power supply voltage available in the first power domain of the integrated circuit and a second power supply voltage available in a second power domain of the integrated circuit are ready, the first power supply voltage being ready earlier than the second power supply voltage, the second power domain being different from the first power domain; And An output buffer coupled to the level converter for buffering the second control signal to generate a third control signal and for performing power supply control of the integrated circuit based thereon.

11. The power management circuit according to claim 10, wherein, The first control signal is provided by a third power domain different from the first power domain and the second power domain.

12. The power management circuit according to claim 10, wherein, When the first control signal indicates that the second power supply voltage is not yet ready, the output buffer is configured to generate the third control signal to isolate the second power domain and a portion of the integrated circuit operating in the first power domain; When the first control signal indicates that the second power supply voltage is ready, the output buffer is configured to generate the third control signal to allow the second power domain to be coupled to the portion of the integrated circuit.

13. The power management circuit according to claim 10, wherein The level converter includes: An inverter circuit having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive the first control signal from the inverter input terminal and to generate a fourth control signal at the inverter output terminal; and A latch circuit, having a latch power supply terminal, a first latch input terminal and a second latch input terminal, wherein the latch power supply terminal is coupled to the first power supply voltage, the first latch input terminal is coupled to the output terminal of the inverter to receive the fourth control signal, the second latch input terminal is coupled to the input terminal of the inverter to receive the first control signal, and the latch circuit is configured to generate the second control signal according to the signal levels of the first control signal and the fourth control signal respectively.

14. The power management circuit according to claim 13, wherein The inverter power supply terminal of the inverter circuit is configured to receive the second power supply voltage; wherein when the second power supply voltage is not ready, the first control signal has a first logic level; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level.

15. The power management circuit according to claim 13, wherein The latch circuit further includes a first latch output terminal and a second latch output terminal, and the first latch output terminal is configured to output the second control signal; The level shifter further includes: A resistor unit, coupled between a circuit node and the inverter power supply terminal of the inverter circuit; A first switch, selectively coupled between the first power supply voltage and the circuit node according to the signal level of the second latch output terminal; and A second switch, selectively coupled between the second power supply voltage and the inverter power supply terminal according to the signal level of the second latch output terminal; Wherein when the second power supply voltage is not ready, the first control signal has a first logic level, the first switch is turned on, and the second switch is turned off; when both the first power supply voltage and the second power supply voltage are ready, the first control signal has a second logic level different from the first logic level, the first switch is turned off, and the second switch is turned on.

16. The power management circuit according to claim 10, wherein, The level shifter includes: A resistor unit, coupled between the first power supply voltage and the input terminal of the output buffer; and A transistor, having a control terminal, a first connection terminal and a second connection terminal, wherein the control terminal is coupled to the first control signal, the first connection terminal is coupled to the input terminal of the output buffer, and the second connection terminal is coupled to a reference voltage.

17. The power management circuit according to claim 10, wherein When both the first power supply voltage and the second power supply voltage are not ready, the first control signal has a first logic level; when the first power supply voltage is ready and the second power supply voltage is not ready, the first control signal has a second logic level different from the first logic level; When both the first power supply voltage and the second power supply voltage are ready, the first control signal has the first logic level.

18. A method for managing an integrated circuit, characterized in that, Including: Operating a level shifter with a first power supply voltage in a first power supply domain that supplies power to the integrated circuit, wherein the first power supply domain is configured to receive an input signal from a second power supply domain of the integrated circuit, and the second power supply domain is powered by a second power supply voltage; When the first power supply voltage is ready and the second power supply voltage is not ready, the level shifter is used to convert a first control signal provided by a third power supply domain different from the first power supply domain and the second power supply domain into a second control signal having a first logic level, so as to isolate the second power supply domain from the first power supply domain, wherein the first control signal at least indicates the power supply state of the second power supply voltage; And When both the first power supply voltage and the second power supply voltage are ready, the level shifter is used to convert the first control signal provided by the third power supply domain into the second control signal having a second logic level different from the first logic level, so as to allow the first power supply domain to receive the input signal from the second power supply domain.

19. The method according to claim 18, characterized in that, The third power supply domain is a normally-on power supply domain.

20. The method according to claim 19, wherein The first control signal is a power supply state signal used to indicate whether both the first power supply voltage and the second power supply voltage are ready.

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