Bidirectional level shifter and electronic equipment

Abstract

The invention provides a bidirectional level converter and electronic equipment, and relates to the technical field of analog integrated circuits, the bidirectional level converter comprises a first port, a second port and a conversion circuit arranged between the first port and the second port; the first port comprises a first input / output port and a first reference level port; the second port comprises a second input / output port and a second reference level port; the conversion circuit comprises a first Schmidt comparator, a clamping circuit, a pull-up module, a pull-down module and a second Schmidt compartment.The bidirectional level converter and the electronic equipment have the advantages that under the condition that an input signal is converted from a high signal to a low signal, driving of an input stage does not need extremely high driving capacity, input and output are in an isolated state, and the conversion efficiency is improved; and the load size of the output stage has no influence on the driving capability of the input stage, so that the integrity of signals can be maintained, the system design is more flexible, and meanwhile, the circuit can adapt to more application scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and more particularly to a bidirectional level shifter and an electronic device. Background Art

[0002] In today's electronic systems, it is very common that the operating voltages of processor interfaces and peripheral devices are incompatible, or the operating voltages between devices are incompatible. In such cases, a level shifter is required to enable communication between the processor and peripheral devices, or between devices, at different operating voltages, thereby solving the problems of abnormal communication caused by different operating voltages between devices or device damage due to overvoltage problems.

[0003] Since the level shifter can achieve a wide range of operating voltages and adapt to designs with different operating frequencies, data widths, and drive types (Open-Drain or Push-pull), the level shifter can be used for the transmission of protocol signals such as I2C (Inter-Integrated Circuit), I3C (Improved Inter-Integrated Circuit), SPI (Serial Peripheral Interface, synchronous serial bus), SD Card, etc. A level shifter with automatic bidirectional signal transmission has more advantages in system design. On the one hand, it can simplify software design and does not require real-time discrimination of the transmission direction on the system. On the other hand, no additional direction control pin is required in hardware design, which simplifies PCB design and saves controller hardware resources.

[0004] However, traditional level shifters with automatic bidirectional signal transmission have high requirements for the driving ability of the driving stage when transmitting high-to-low level signals, or there is an overshoot problem during the transmission of wide-range voltage level signals, resulting in device damage and a decline in the overall performance of the level shifter, making it difficult to adapt to more application scenarios. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a bidirectional level shifter and an electronic device to alleviate the above technical problems.

[0006] In a first aspect, an embodiment of the present invention provides a bidirectional level converter. The bidirectional level converter includes: a first port, a second port, and a conversion circuit disposed between the first port and the second port; the first port, the conversion circuit, and the second port are sequentially arranged along the signal transmission direction; the first port includes a first input / output port and a first reference level port; the second port includes a second input / output port and a second reference level port; wherein, the first reference level port and the second reference level port are used to connect to a reference level; the conversion circuit includes: a first Schmitt comparator, an input end of the first Schmitt comparator is connected to the first input / output port, and an output end is connected to a clamping circuit, a pull-up module, and a pull-down module; a second Schmitt comparator, an input end of the second Schmitt comparator is connected to the second input / output port, and an output end is connected to the clamping circuit, the pull-up module, and the pull-down module; the clamping circuit is disposed between the first input / output port and the second input / output port, and is used to prevent overvoltage from occurring at the first input / output port and the second input / output port; the pull-up module is used to perform a pull-up process on a first level signal when the first level signal is input to the first input / output port or the second input / output port; the pull-down module is used to perform a pull-down process on a second level signal when the second level signal is input to the first input / output port or the second input / output port; wherein, the first level signal is higher than the second level signal.

[0007] Combined with the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect. Among them, the above-mentioned pull-up module includes: a first pulse circuit, an input end of the first pulse circuit is connected to output ends of the first Schmitt comparator and the second Schmitt comparator, and an output end is respectively connected to a first control circuit and a second control circuit; the first control circuit, an input end of the first control circuit is connected to the output end of the first pulse circuit, and an output end is connected to a control end of a first pull-up MOS transistor; one end of the first pull-up MOS transistor is connected to the first input / output port, and the other end is connected to the first reference level port; the second control circuit, an input end of the second control circuit is connected to the output end of the first pulse circuit, and an output end is connected to a control end of a second pull-up MOS transistor; one end of the second pull-up MOS transistor is connected to the second input / output port, and the other end is connected to the second reference level port.

[0008] Combined with the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect. Wherein, the above-mentioned pull-down module includes: a second pulse circuit, the input end of the second pulse circuit is connected to the output ends of the first Schmitt comparator and the second Schmitt comparator, and the output end is respectively connected to a third control circuit and a fourth control circuit; the third control circuit, the input end of the third control circuit is connected to the output end of the second pulse circuit, and the output end is connected to the control end of a first pull-down MOS transistor; one end of the first pull-down MOS transistor is connected to the first input / output port, and the other end is grounded; the fourth control circuit, the input end of the fourth control circuit is connected to the output end of the second pulse circuit, and the output end is connected to the control end of a second pull-down MOS transistor; one end of the second pull-down MOS transistor is connected to the second input / output port, and the other end is grounded.

[0009] Combined with the first possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect. Wherein, the above-mentioned first pull-up MOS transistor and the second pull-up MOS transistor are PMOS transistors; the gate of the first pull-up MOS transistor is connected to the output end of the first control circuit, the source is connected to the first reference level port, and the drain is connected to the first input / output port; the gate of the second pull-up MOS transistor is connected to the output end of the second control circuit, the source is connected to the second reference level port, and the drain is connected to the second input / output port.

[0010] Combined with the second possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect. Wherein, the above-mentioned first pull-down MOS transistor and the second pull-down MOS transistor are NMOS transistors; the gate of the first pull-down MOS transistor is connected to the output end of the third control circuit, the source is grounded, and the drain is connected to the first input / output port; the gate of the second pull-down MOS transistor is connected to the output end of the fourth control circuit, the source is grounded, and the drain is connected to the second input / output port.

[0011] Combined with the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect. Wherein, the above-mentioned bidirectional level converter further includes: a first pull-up resistor circuit, including a first pull-up resistor and a first switch connected in series; one end of the first pull-up resistor circuit is connected to the first input / output port, and the other end is connected to the first reference level port; a second pull-up resistor circuit, including a second pull-up resistor and a second switch connected in series; one end of the second pull-up resistor circuit is connected to the second input / output port, and the other end is connected to the second reference level port.

[0012] In combination with the first aspect, an embodiment of the present invention provides a sixth possible implementation manner of the first aspect. The clamping circuit includes a first switching tube and a second switching tube connected in parallel, and a switching circuit of the first switching tube and the second switching tube. The switching circuit of the first switching tube is connected to the first input / output port, and the signal input from the first input / output port controls the turning on and off of the first switching tube. The switching circuit of the second switching tube is connected to the second input / output port, and the signal input from the second input / output port controls the turning on and off of the second switching tube.

[0013] In combination with the first aspect, an embodiment of the present invention provides a seventh possible implementation manner of the first aspect. The clamping circuit includes a first switching tube and a second switching tube connected in series. A switching circuit is connected to the control end of the first switching tube. The switching circuit is connected to the first input / output port and the second input / output port. The control end of the second switching tube is connected to a current source, and the voltage at the control end of the second switching tube is biased at a preset voltage value.

[0014] In combination with the first aspect, an embodiment of the present invention provides an eighth possible implementation manner of the first aspect. The clamping circuit includes a first switching tube and a switching circuit connected to the control end of the first switching tube. The switching circuit includes a logic port connected to the first input / output port and the second input / output port, and the signal of the first input / output port or the second input / output port is used to turn on the first switching tube.

[0015] In the second aspect, an embodiment of the present invention further provides an electronic device, and the electronic device is configured with the bidirectional level converter described in the first aspect.

[0016] The embodiments of the present invention bring the following beneficial effects: A bidirectional level converter and an electronic device provided by an embodiment of the present invention. In the bidirectional level converter, it includes: a first port, a second port, and a conversion circuit disposed between the first port and the second port; in the conversion circuit, it includes a first Schmitt comparator, a second Schmitt comparator, and a clamping circuit. Among them, the clamping circuit is disposed between the first input / output port and the second input / output port for realizing load isolation between the first input / output port and the second input / output port; in the conversion circuit, a pull-up module is further included, which is used for pulling up the first level signal when the first input / output port or the second input / output port inputs a first level signal; and a pull-down module, which is used for pulling down the second level signal when the first input / output port or the second input / output port inputs a second level signal, so that the clamping circuit is in a closed state, thereby realizing that when the input signal changes from high to low, the driving of the input stage does not require particularly strong driving ability, the input and output are in an isolated state, the load size of the output stage has no influence on the driving ability of the input stage, and even with a relatively weak driving pull-down ability, a better signal waveform can be obtained, which is beneficial to maintaining signal integrity, is more flexible for system design, and can adapt to more application scenarios.

[0017] Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification, claims, and drawings.

[0018] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is a structural block diagram of a bidirectional level converter provided by an embodiment of the present invention; Figure 2 It is a circuit schematic diagram of a bidirectional level converter provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of a clamping circuit provided by an embodiment of the present invention; Figure 4 It is a signal transmission schematic diagram provided by an embodiment of the present invention; Figure 5 Schematic diagram of another clamping circuit provided by an embodiment of the present invention; Figure 6 Schematic diagram of a signal transmission provided by an embodiment of the present invention; Figure 7 Schematic diagram of a third clamping circuit provided by an embodiment of the present invention; Figure 8 Schematic diagram of a signal transmission provided by an embodiment of the present invention; Figure 9 Schematic circuit diagram of a control circuit provided by an embodiment of the present invention. Detailed implementation manners

[0021] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0022] Currently, for traditional level converters for automatic bidirectional signal transmission, when transmitting a high-to-low level signal, a relatively high driving ability of the driving stage is required, and the power consumption is relatively large during signal transmission or when the signal is at a low level, which is not friendly to battery-powered systems. In addition, when transmitting a wide range of voltage level signals, there is an overshoot problem with the high level during the process of the input signal transitioning from low to high, and this overshoot voltage can damage the processor interface circuit and damage the device, resulting in the level converter being difficult to adapt to more application scenarios.

[0023] Based on this, an embodiment of the present invention provides a bidirectional level converter and an electronic device to alleviate the above technical problems.

[0024] To facilitate the understanding of this embodiment, a bidirectional level converter disclosed in an embodiment of the present invention will be introduced in detail first.

[0025] In a possible implementation manner, an embodiment of the present invention provides a bidirectional level converter. Specifically, as Figure 1 shown in the block diagram of a bidirectional level converter, it includes: a first port 10, a second port 20, and a conversion circuit 30 disposed between the first port 10 and the second port 20.

[0026] Among them, the first port 10, the conversion circuit 30, and the second port 20 are arranged in sequence along the signal transmission direction; moreover, the first port 10 includes a first input / output port 101 and a first reference level port 102; the second port 20 includes a second input / output port 201 and a second reference level port 202; wherein, the first reference level port 102 and the second reference level port 202 are used to connect to the reference level.

[0027] In specific implementation, since the level converter provided by the embodiment of the present invention is a bidirectional level converter, therefore, the above-mentioned first input / output port 101 and second input / output port 201 can be used as both input ports and output ports.

[0028] Furthermore, the above-mentioned conversion circuit 30 includes: A first Schmitt comparator 301, the input end of the first Schmitt comparator is connected to the first input / output port, and the output end is connected to the clamping circuit 303, the pull-up module 304, and the pull-down module 305; A second Schmitt comparator 302, the input end of the second Schmitt comparator is connected to the second input / output port, and the output end is connected to the clamping circuit 303, the pull-up module 304, and the pull-down module 305; The clamping circuit 303 is arranged between the first input / output port 101 and the second input / output port 201, and is used to realize the load isolation between the first input / output port 101 and the second input / output port 201, and avoid overvoltage phenomena at the first input / output port and the second input / output port; The pull-up module 304 is used to perform a pull-up process on the first level signal when the first input / output port 101 or the second input / output port 201 inputs the first level signal; The pull-down module 305 is used to perform a pull-down process on the second level signal when the first input / output port 101 or the second input / output port 201 inputs the second level signal; wherein, the first level signal is higher than the second level signal.

[0029] In actual use, the above-mentioned bidirectional level converter in the embodiment of the present invention can be used between a processor interface and a peripheral device, or between different devices, to realize the mutual communication between the processor and the peripheral device, or between devices under different operating voltages.

[0030] Furthermore, the first reference level port and the second reference level port are connected to a reference power supply, and the reference power supply is also used to power the bidirectional level converter. For example, the first reference level port is connected to VCCA, and the second reference level port is connected to VCCB. At this time, the high level of the input signal An of the first input / output port refers to the voltage of VCCA, and the high level of the input signal Bn of the second input / output port refers to the voltage of VCCB. Moreover, when the bidirectional level converter is used, the signal can be transmitted from the first input / output port to the second input / output port, and can also be transmitted from the second input / output port to the first input / output port.

[0031] Specifically, for ease of understanding, Figure 1 On the basis of Figure 2 A circuit diagram of a bidirectional level converter is also shown, wherein an input signal An of a first input / output port, an input signal Bn of a second input / output port, a reference voltage VCCA of a first reference level port, and a reference voltage VCCB of a second reference level port are shown.

[0032] Further, if Figure 2 As shown, the pull-up module in the embodiment of the present invention includes: The first pulse circuit 306 has an input terminal connected to the first Schmidt comparator 301 ( Figure 2 301 and the second Schmitt comparator 302 ( Figure 2 302) shown in the figure, the output end of the first pulse circuit 306 is connected to the first control circuit 307 and the second control circuit 308 respectively; A first control circuit 307, wherein the input end of the first control circuit 307 is connected to the output end of the first pulse circuit 306, and the output end of the first control circuit 307 is connected to the control end of the first pull-up MOS transistor T1; One end of the first pull-up MOS transistor T1 is connected to the first input / output port 101 , and the other end is connected to the first reference level port 102 ; A second control circuit 308, wherein the input end of the second control circuit 308 is connected to the output end of the first pulse circuit 306, and the output end of the second control circuit 308 is connected to the control end of the second pull-up MOS transistor T2; One end of the second pull-up MOS transistor T2 is connected to the second input / output port 201 , and the other end is connected to the second reference level port 202 .

[0033] Further, if Figure 2 As shown, the above-mentioned pull-down module in the embodiment of the present invention includes: The second pulse circuit 309, the input end of the second pulse circuit 309 is connected to the output ends of the first Schmitt comparator 301 and the second Schmitt comparator 302, and the output end of the second pulse circuit 309 is respectively connected to the third control circuit 310 and the fourth control circuit 311; The third control circuit 310, the input end of the third control circuit 310 is connected to the output end of the second pulse circuit 309, and the output end of the third control circuit 310 is connected to the control end of the first pull-down MOS transistor T3; one end of the first pull-down MOS transistor T3 is connected to the first input / output port, and the other end is grounded; The fourth control circuit 311, the input end of the fourth control circuit 311 is connected to the output end of the second pulse circuit 309, and the output end of the fourth control circuit 311 is connected to the control end of the second pull-down MOS transistor T4; one end of the second pull-down MOS transistor T4 is connected to the second input / output port, and the other end is grounded.

[0034] Further, as Figure 2 shown, the above-mentioned first pull-up MOS transistor and second pull-up MOS transistor in the embodiment of the present invention are PMOS transistors; specifically, the gate of the first pull-up MOS transistor T1 is connected to the output end of the first control circuit, the source is connected to the first reference level port, and the drain is connected to the first input / output port; the gate of the second pull-up MOS transistor T2 is connected to the output end of the second control circuit, the source is connected to the second reference level port, and the drain is connected to the second input / output port.

[0035] Further, Figure 2 in, the above-mentioned first pull-down MOS transistor and second pull-down MOS transistor are NMOS transistors; specifically, the gate of the first pull-down MOS transistor T3 is connected to the output end of the third control circuit, the source is grounded, and the drain is connected to the first input / output port; the gate of the second pull-down MOS transistor T4 is connected to the output end of the fourth control circuit, the source is grounded, and the drain is connected to the second input / output port.

[0036] Further, in the embodiment of the present invention, the above-mentioned bidirectional level converter further includes: pull-up resistors provided at the first port and the second port.

[0037] Specifically, as Figure 2 shown, the bidirectional level converter includes a first pull-up resistor circuit, and in the first pull-up resistor circuit, a first pull-up resistor R PUa and a first switch Sa are connected in series; one end of the first pull-up resistor circuit is connected to the first input / output port, and the other end is connected to the first reference level port; and, a second pull-up resistor circuit, including a second pull-up resistor R PUb and a second switch Sb connected in series; one end of the second pull-up resistor circuit is connected to the second input / output port, and the other end is connected to the second reference level port.

[0038] Further, based on the following Figure 2 , the working process of the bidirectional level converter in the embodiments of the present invention will be further described as follows: Among them, Figure 2 in, it is assumed that the bidirectional level converter in the embodiments of the present invention is powered by VCCA and VCCB, and An and Bn belong to the signals of the input / output ports, that is, An and Bn can be both input and output. The high level of An refers to the VCCA voltage, and the high level of Bn refers to the VCCB voltage. Moreover, in the embodiments of the present invention, taking the signal transmission from the first input / output port to the second input / output port as an example, that is, Figure 2 the An in

[0039] transmits a signal to Bn. During the process of An changing from low to high, that is, during the process of the voltage changing from a low voltage to a high voltage, at this time, the input end of the bidirectional level converter, that is, the first Schmidt comparator 301 of the first port, is used to detect the input voltage of the first input / output port. When the detected input voltage exceeds the VIH of the first Schmidt comparator, the first Schmidt comparator outputs a first level signal from low to high, that is, the first level signal is used to characterize the process that the first Schmidt comparator detects that the input voltage of the first input / output port changes from low to high and exceeds VIH.

[0040] This first level signal is transmitted to the clamping circuit 303, the pull-up module 304, and the pull-down module 305.

[0041] Further, the first pulse circuit 306 of the pull-up module usually refers to a rising-edge monostable circuit (also known as Rising edge One-Shot). This rising-edge monostable circuit can output a high-level pulse with a fixed width after receiving a trigger signal, and then automatically return to the low-level state.

[0042] After the above first level signal is input to the first pulse circuit 306, the first pulse circuit 306 receives this low-to-high first level signal through the pin A_in, and then A_out and B_out output a pulse signal of about several ns. The time or duty cycle of this pulse signal is determined by the load size of the bidirectional level converter, and this pulse signal turns on two pull-up PMOS transistors T1 and T2 through the first control circuit 307 and the second control circuit 308.

[0043] In specific implementation, the above-mentioned first control circuit 307 and second control circuit 308 are driving circuits with SR control (Slew Rate Control). This driving circuit with SR control can control the output port voltage to change relatively smoothly, which is beneficial to signal transmission. The specific SR parameters can be set according to actual usage situations, and the embodiments of the present invention do not limit this.

[0044] Meanwhile, for the pull-down module, its trigger signal can be configured so that it is not triggered when receiving the first level signal, that is, only the pull-up module works at this time.

[0045] Further, after the two pull-up PMOS transistors T1 and T2 are turned on, An, Bn are connected to VCCA and VCCB through the two pull-up PMOS transistors T1 and T2 with relatively small on-resistance, and An and Bn are quickly pulled high to VCCA and VCCB. At the same time, the switches Sa and Sb connected to the first pull-up resistor R PUa and the second pull-up resistor R PUb are closed, and the clamping circuit 303 is ready to turn off at this time.

[0046] In actual use, the clamping circuit in the embodiments of the present invention can be a Clamped Pass Gate clamping transmission gate circuit. Usually, a clamping circuit is introduced to control the conduction and cut-off of the transmission gate. When the transmission gate needs to conduct, the clamping circuit will fix the signal at a specific potential so that the transmission gate can work normally; when the transmission gate needs to cut off, the clamping circuit will clamp the signal at another potential to prevent the signal from passing through.

[0047] In the embodiments of the present invention, the clamping circuit 303 can cut off when receiving the above-mentioned first level signal.

[0048] After the signal of the first pulse circuit 306 ends, the high levels of An and Bn are maintained by the pull-up resistors R PUa and R PUb The clamping circuit 303 maintains the OFF (cut-off) state, realizing the conversion of the high-level signal in the VCCA voltage domain to the high-level signal in the VCCB voltage domain.

[0049] In actual use, for the sake of easy understanding, Figure 3 a schematic diagram of a clamping circuit is shown. Specifically, as Figure 3As shown in the figure, the clamping circuit 303 in the embodiment of the present invention includes: a first switching transistor N2 and a second switching transistor N1 connected in parallel, and a switching circuit for the first switching transistor N2 and the second switching transistor N1; wherein, the switching circuit of the first switching transistor N2 is connected to the first input / output port, and the signal input from the first input / output port controls the turning on and off of the first switching transistor; the switching circuit of the second switching transistor N2 is connected to the second input / output port, and the signal input from the second input / output port controls the turning on and off of the second switching transistor.

[0050] Specifically, Figure 3 In, P1 is a long-channel PMOS transistor, and this long-channel PMOS transistor P1 realizes a simple current source. Among them, the long-channel MOS transistor is also called the Long channel MOS transistor. In the embodiment of the present invention, the long-channel MOS transistor is a P-type MOS transistor, that is, the long-channel PMOS transistor P1 in the embodiment of the present invention; further, the first switching transistor N2 and the second switching transistor N1 are NMOS transistors and are connected in parallel, and the sources of the first switching transistor N2 and the second switching transistor N1 are both connected to the APG_in port, and the drains are both connected to the BPG_in port, and, from Figure 2 It can be seen that the APG_in port is connected to the input signal An of the first input / output port, and the BPG_in port is connected to the input signal Bn of the second input / output port (in this example, Bn of the second input / output port is the output signal).

[0051] Further, in combination with Figure 2 , where the signal AL_in corresponds to the output terminal of the first Schmidt comparator 301, that is, the signal input from the first input / output port. This signal AL_in is connected to the gate of the first switching transistor N2 through a logic gate ( Figure 3 the NOT gate A1 in) to control the turning on and off of the first switching transistor N2. At this time, the NOT gate A1 is equivalent to the switching circuit of the first switching transistor N2.

[0052] Further, the signal BL_in corresponds to the output terminal of the second Schmidt comparator 302, that is, the signal input from the second input / output port. This signal BL_in is input to Figure 3 the third pulse circuit 312 in Figure 3 through a logic gate (

[0053] the NOT gate B1 in). The third pulse circuit 312 is a monostable circuit with a specific bias voltage and can output a corresponding pulse signal to the gate of the PMOS transistor T5.

[0054] Therefore, the switching circuit of the second switching transistor N1 actually includes an inverter B1, a third pulse circuit 312, a PMOS transistor T5, a grounded MOS transistor PG3, and a current source implemented by a long-channel PMOS transistor P1.

[0055] Further, when An changes from low to high, during the process of pulling up An and Bn, the gate voltage of the first switching transistor N2 (the first switch N2 and the second switching transistor N1 are also referred to as Pass Gate) in the clamping circuit will be pulled down to a low level after a certain delay time, and this delay time is caused by the logic gate circuit included in the switching circuit. Therefore, at this time, the first switching transistor N2 will be in a ready-to-OFF state. Therefore, when Bn is pulled up to VCCB, Pass Gate (N2) is still at the VCCB high level. Then, the input signal at the An terminal will be pulled up simultaneously by VCCA through T1 and VCCB through T2 and the second switching transistor N1.

[0056] If the difference between the gate voltage VG_N2 of the first switching transistor N2 and the threshold voltage VTH_N2 of the first switching transistor N2 is greater than VCCA, that is, VG_N2 - VTH_N2 > VCCA, then the An signal will have a large overshoot. The higher VCCB is, the larger the overshoot is. In the embodiment of the present invention, the above-mentioned clamping circuit 303 is added, which can Figure 3 the PMOS transistor T5 in it is restricted to be near VCCA + VTH. When the An signal is near VCCA, the first switching transistor N2 is in the OFF state. It is not necessary to wait until the gate voltage of Pass Gate N2 is pulled to low by the logic signal, but Pass Gate N2 is turned off through an extremely fast logic signal, which is very difficult to achieve in related designs. However, in the embodiment of the present invention, this scheme can be realized, thereby alleviating the problem of large overshoot of the An signal.

[0057] And, Figure 3 in, when the signal of BL_in falls, the gate voltage of the second switching transistor N1 will be quickly pulled up to VCCA + VTH by the gate bias of a single pulse signal of PMOS T5 and the third pulse circuit. After the pulse signal of the third pulse circuit ends, the high level is maintained by the current flowing through the long-channel PMOS transistor P1. This circuit realizes the clamping of the gate voltage of Pass Gate N2. At the same time, the Figure 3 circuit design shown has a simple structure and can realize the logic combination of AL_in and BL_in without complex additional circuits.

[0058] Further, the above Figure 2 and Figure 3 describe the process of An changing from low to high. The following further describes the process of An changing from high to low, specifically as follows: For the sake of convenience, taking the transmission of a signal from the first input / output port to the second input / output port as an example, that is, Figure 2 An in Figure 2 transmits a signal to Bn.

[0059] At this time, at the input end of the bidirectional level converter, that is, when the first Schmidt comparator 301 of the first port detects that the input voltage exceeds the VIL of the first Schmidt comparator, it outputs a second level signal from high to low. That is, the second level signal is used to indicate that the first Schmidt comparator detects that the input voltage of the first input / output port changes from high to low and exceeds the voltage value corresponding to VIL. Among them, the VIL and VIH of the above-mentioned first Schmidt comparator can be set based on the reference voltage or threshold voltage of the first Schmidt comparator, and the embodiments of the present invention do not limit this.

[0060] This second level signal will also be transmitted to the clamping circuit 303, the pull-up module 304, and the pull-down module 305.

[0061] Among them, for the pull-up module, its trigger signal can be configured so that it does not trigger when receiving the second level signal. That is, at this time, only the pull-down module works.

[0062] Furthermore, the second pulse circuit 309 of the pull-down module generally refers to a falling-edge monostable circuit (also called Falling edge One-Shot). This falling-edge monostable circuit can output a high-level pulse with a fixed width after receiving a trigger signal, and then automatically return to the low-level state.

[0063] After the above-mentioned second level signal is input to the second pulse circuit 309, the A_in port of the second pulse circuit 309 receives this second level signal, and the A_out and B_out of the second pulse circuit 309 output a pulse signal of about several nanoseconds. The time or duty cycle of this pulse signal is determined by the load size of the bidirectional level converter. And this pulse signal turns on two pull-down NMOS transistors T3 and T4 through the third control circuit 310 and the fourth control circuit 311. Then, An, Bn and the ground are connected by T3 and T4 with a smaller on-resistance, so that An and Bn are quickly pulled down to the low level.

[0064] Furthermore, based on Figure 3 , during the process of pulling down An and Bn, the gate voltage of the second switching transistor N1 in the clamping circuit, also called Pass Gate N1, will be pulled up to the high level, so that the entire clamping circuit is in the ON conduction state. At the same time, the first pull-up resistor R PUa and the second pull-up resistor R PUbThe connected switches Sa and Sb are turned off. After the pulse signal of the second pulse circuit 309 ends, since Pass Gate N1 is in the ON state, the low levels of An and Bn are simultaneously pulled low by an external drive. The low-level signal in the VCCA voltage domain is transmitted to the low-level signal in the VCCB voltage domain.

[0065] Moreover, during the process of An changing from high to low, the clamping circuit is in the OFF state at the beginning stage. Therefore, the load capacitors at the An and Bn terminals are in an isolated state from each other. The drive input at the An terminal only needs to discharge the charge on the load at the An terminal, and the charge on the load at the Bn terminal is discharged by T4. Therefore, in the embodiment of the present invention, the design of the bidirectional level converter has a lower requirement for the driving ability of the An terminal, and at the same time can ensure the speed of the falling edge of the input and output signals.

[0066] In the state where the signal is low, the first pull-up resistor R PUa and the second pull-up resistor R PUb The connected switches Sa and Sb are in the off state. Therefore, no current will flow from VCCA and VCCB to the input drive terminal in the bidirectional level converter itself. Compared with the circuit architecture of the traditional bidirectional level converter, the bidirectional level converter in the embodiment of the present invention saves the power consumption of VCCA and VCCB. That is, in a system where an external pull-up resistor is not required for signal transmission, such as the transmission of SPI signals, when the transmitted signal is low, due to R PUa and R PUb being in the off state, no additional current flows through the pull-up resistor. Therefore, the system power consumption is saved.

[0067] Moreover, for the sake of easy understanding, based on the above Figure 2 and Figure 3 , Figure 4 A signal transmission schematic diagram from An to Bn is also shown, specifically including the signal change schematic diagrams of An, AL_in, the gate voltage of the first switching tube N2, the gate voltage of the second switching tube N1, and Bn, BL_in during the transmission process.

[0068] Furthermore, in addition to the clamping circuit shown above Figure 3 , in the embodiment of the present invention, the above clamping circuit may further include: a first switching tube and a second switching tube connected in series; that is, the first switching tube N2 and the second switching tube N1 in the above Figure 3 may also be in a series form. Specifically, Figure 5The schematic diagram of another clamping circuit is shown, that is, it includes a first switching transistor N2 and a second switching transistor N1 connected in series. Among them, the control terminal of the first switching transistor N2 is connected with a switching circuit, and this switching circuit is connected with a first input / output port and a second input / output port; the control terminal of the second switching transistor N1 is connected with a current source, and moreover, the voltage of the control terminal of the second switching transistor N1 is biased at a preset voltage value.

[0069] Specifically, Figure 5 In, the current source is also implemented by a long-channel PMOS transistor P1, which can simplify the circuit design. The first switching transistor N2 and the second switching transistor N1 are connected in series, and the gate voltage of N1 is always biased near VCCA + VTH. The turning on and off of N2 are realized by the AL_in and BL_in signals and the logic circuit. Among them, Figure 5 It includes a high-speed level conversion unit, also called High Speed Level-shift, which is used to quickly convert the AL_in signal from the VCCA voltage domain to the VCCB voltage domain. It can be realized by a unidirectional level conversion circuit in related technologies. Its high speed is to minimize the logical gate delay. Figure 5 For the series connection method shown, if a smaller on-resistance of the Pass Gate is to be achieved, a larger physical area is required.

[0070] Moreover, for the sake of easy understanding, Figure 6 The schematic diagram of the signal transmission from An to Bn is also shown, specifically including the schematic diagram of the changes of An, AL_in, the gate voltage of the first switching transistor N2, the gate voltage of the second switching transistor N1, and the signals corresponding to Bn and BL_in during the transmission process.

[0071] Furthermore, Figure 7 The schematic diagram of the third clamping circuit is also shown, that is, the third implementation manner of the clamping circuit. In this implementation manner, the above-mentioned clamping circuit only includes one switching transistor, that is Figure 7 the first switching transistor N1 in, and the switching circuit connected to the control terminal of the first switching transistor N1; specifically, the switching circuit at this time includes a logic port connected to the first input / output port and the second input / output port, and the signal of the first input / output port or the second input / output port is used to turn on the first switching transistor N1.

[0072] Specifically, Figure 7 In, the logic port included in the switching circuit can be directly connected to AL_in and BL_in. A logic gate circuit is also provided inside the switching circuit, and the specific logic gates it includes can be set according to the actual usage situation. The embodiments of the present invention do not limit this.

[0073] And, in Figure 7In it, the current source is also implemented by the long-channel PMOS transistor P1, and also includes a high-speed level conversion unit. The falling edge of AL_in or BL_in will turn on the first switch transistor N1 (also called Pass Gate N1) in the above Figure 7 . And at this time, the gate voltage of the first switch transistor N1 will be quickly pulled up to VCCA + VTH by the PMOS T5 and a pulse signal of the third pulse circuit. After the pulse signal ends, the high level is maintained by the current flowing through the long-channel PMOS transistor P1. This circuit realizes the gate voltage clamping of Pass Gate N1.

[0074] At the same time, the high-speed level conversion unit is a unidirectional level conversion circuit, which is used to quickly convert the AL_in signal from the VCCA voltage domain to the VCCB voltage domain. The fast speed is to minimize the logical gate delay. This implementation method only uses one NMOS as the Pass Gate in the clamping potential circuit, and the gate voltage is biased under the condition of VCCA + VTH. Compared with the parallel connection method of the previous two Pass Gates ( Figure 3 N1 and N2 in it) and are respectively biased under the conditions of VCCA and VCCB, the on-resistance obtained with the same layout area is relatively small. And compared with the series connection method of the above N1 and N2, the area is relatively smaller and more advantageous. Further, when transmitting a low-level signal, if the port of the bidirectional level converter is connected to a pull-up resistor, such as when transmitting an I2C signal, an external pull-up resistor is required. To ensure the smallest difference between the input and output voltages, the smaller the on-resistance of the clamping circuit, the better. And the bidirectional level converter provided by the embodiment of the present invention can well meet the above design requirements.

[0075] Further, corresponding to Figure 7 , Figure 8 also shows a signal transmission schematic diagram from An to Bn, specifically including the change schematic diagrams of An, AL_in, the gate voltage of the first switch transistor N1, the gate voltage of the second switch transistor N1, and Bn, BL_in during the transmission process.

[0076] In addition, Figure 9 also shows a circuit schematic diagram of a control circuit, where Figure 9 in (a) corresponds to the above first control circuit and second control circuit, which are used to drive the above first pull-up MOS transistor and second pull-up MOS transistor, Figure 9 in (b) corresponds to the above third control circuit and fourth control circuit, which are used to drive the above first pull-down MOS transistor and second pull-down MOS transistor.

[0077] Specifically, based on Figure 9In the illustrated embodiment, the output signal out (out_n, out_p) is controlled by PM4, NM4, as well as PM7, NM7, in combination with the input signal in (in_n, in_p) and the voltage An of the input / output port as a feedback signal. Here, in_n or in_p refers to the output signal of the first pulse circuit or the second pulse circuit, which serves as the input to the control circuit. out_n or out_p is then connected to the gate of one of the corresponding pull-up MOS transistors or pull-down MOS transistors ( Figure 2 one of the four MOS transistors T1, T2, T3, and T4 in Figure 2 ). Therefore, this circuit can effectively control

[0078] In summary, the bidirectional level shifter provided by the embodiments of the present invention has the following beneficial effects: (1) It has automatic bidirectional signal transmission and does not require a direction control port; (2) When the signal transitions from high to low, the input stage does not require particularly strong driving ability. The input and output are in an isolated state, and the load size of the output stage has no impact on the driving ability of the input stage. Even with a relatively weak pull-down driving ability, a good signal waveform can be obtained, which is beneficial to maintaining signal integrity and provides greater flexibility for system design; (3) When the signal is being transmitted or the input signal is low, the overall power consumption is low, which is more advantageous in terms of power consumption for battery-powered systems; (4) The voltage of VCCB can be a very wide operating voltage. For example, as long as VCCA <= VCCB is ensured, it can operate within the range from 1.2V to 5.5V, enabling it to adapt to more application scenarios.

[0079] (5) On the basis of solving the problems of the prior art, the embodiments of the present invention also add an on-rate control circuit for the pull-up PMOS and pull-down NMOS, namely the first control circuit, the second control circuit, the third control circuit, or the fourth control circuit, to optimize the transient current at the moment when the pulse circuit is turned on, which can better match the transmission line impedance, ensure signal integrity, and reduce electromagnetic interference.

[0080] Furthermore, the embodiments of the present invention also provide an electronic device configured with the bidirectional level shifter provided in the above embodiments.

[0081] The electronic device provided by the embodiments of the present invention has the same technical features as the bidirectional level shifter provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0082] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working process of the electronic device described above can refer to the corresponding process in the foregoing embodiments and will not be described herein again.

[0083] In addition, in the description of the embodiments of the present invention, unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0084] If the above functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0085] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0086] Finally, it should be noted that the above embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A bidirectional level converter, characterized in that The bidirectional level converter includes: a first port, a second port, and a conversion circuit disposed between the first port and the second port; the first port, the conversion circuit, and the second port are arranged in sequence along the signal transmission direction. The first port includes a first input / output port and a first reference level port; the second port includes a second input / output port and a second reference level port. Wherein, the first reference level port and the second reference level port are used to connect to a reference level. The conversion circuit includes: A first Schmitt comparator, the input end of the first Schmitt comparator is connected to the first input / output port, and the output end is connected to a clamping circuit, a pull-up module, and a pull-down module. A second Schmitt comparator, the input end of the second Schmitt comparator is connected to the second input / output port, and the output end is connected to the clamping circuit, the pull-up module, and the pull-down module. The clamping circuit is disposed between the first input / output port and the second input / output port, and is used to prevent overvoltage at the first input / output port and the second input / output port. The pull-up module is used to perform a pull-up process on the first level signal when the first level signal is input to the first input / output port or the second input / output port. The pull-down module is used to perform a pull-down process on the second level signal when the second level signal is input to the first input / output port or the second input / output port; wherein, the first level signal is higher than the second level signal.

2. The bidirectional level converter according to claim 1, wherein, The pull-up module includes: A first pulse circuit, the input end of the first pulse circuit is connected to the output ends of the first Schmitt comparator and the second Schmitt comparator, and the output end is respectively connected to a first control circuit and a second control circuit. The first control circuit, the input end of the first control circuit is connected to the output end of the first pulse circuit, and the output end is connected to the control end of a first pull-up MOS transistor. One end of the first pull-up MOS transistor is connected to the first input / output port, and the other end is connected to the first reference level port. The second control circuit, the input end of the second control circuit is connected to the output end of the first pulse circuit, and the output end is connected to the control end of a second pull-up MOS transistor. One end of the second pull-up MOS transistor is connected to the second input / output port, and the other end is connected to the second reference level port.

3. The bidirectional level converter according to claim 1, wherein The pull-down module includes: A second pulse circuit, the input end of the second pulse circuit is connected to the output ends of the first Schmitt comparator and the second Schmitt comparator, and the output end is respectively connected to a third control circuit and a fourth control circuit. The third control circuit, the input end of the third control circuit is connected to the output end of the second pulse circuit, and the output end is connected to the control end of a first pull-down MOS transistor. One end of the first pull-down MOS transistor is connected to the first input / output port, and the other end is grounded. The fourth control circuit, the input end of the fourth control circuit is connected to the output end of the second pulse circuit, and the output end is connected to the control end of the second pull-down MOS transistor; One end of the second pull-down MOS transistor is connected to the second input / output port, and the other end is grounded.

4. The bidirectional level converter according to claim 2, characterized in that The first pull-up MOS transistor and the second pull-up MOS transistor are PMOS transistors; The gate of the first pull-up MOS transistor is connected to the output end of the first control circuit, the source is connected to the first reference level port, and the drain is connected to the first input / output port; The gate of the second pull-up MOS transistor is connected to the output end of the second control circuit, the source is connected to the second reference level port, and the drain is connected to the second input / output port.

5. The bidirectional level converter according to claim 3, wherein The first pull-down MOS transistor and the second pull-down MOS transistor are NMOS transistors; The gate of the first pull-down MOS transistor is connected to the output end of the third control circuit, the source is grounded, and the drain is connected to the first input / output port; The gate of the second pull-down MOS transistor is connected to the output end of the fourth control circuit, the source is grounded, and the drain is connected to the second input / output port.

6. The bidirectional level converter according to claim 1, characterized in that, The bidirectional level converter further includes: A first pull-up resistor circuit, including a first pull-up resistor and a first switch connected in series; one end of the first pull-up resistor circuit is connected to the first input / output port, and the other end is connected to the first reference level port; A second pull-up resistor circuit, including a second pull-up resistor and a second switch connected in series; one end of the second pull-up resistor circuit is connected to the second input / output port, and the other end is connected to the second reference level port.

7. The bidirectional level converter according to claim 1, wherein The clamping circuit includes: a first switching tube and a second switching tube connected in parallel, and a switching circuit of the first switching tube and the second switching tube; Among them, the switching circuit of the first switching tube is connected to the first input / output port, and the signal input from the first input / output port controls the opening and closing of the first switching tube; The switching circuit of the second switching tube is connected to the second input / output port, and the signal input from the second input / output port controls the opening and closing of the second switching tube.

8. The bidirectional level converter according to claim 1, characterized in that The clamping circuit includes: a first switching tube and a second switching tube connected in series; Among them, the control end of the first switching tube is connected with a switching circuit; the switching circuit is connected to the first input / output port and the second input / output port; The control end of the second switching tube is connected to a current source, and the voltage of the control end of the second switching tube is biased at a preset voltage value.

9. The bidirectional level converter according to claim 1, wherein The clamping circuit includes: a first switching tube, and a switching circuit connected to the control end of the first switching tube; The switching circuit includes a logic port connected to the first input / output port and the second input / output port, and the signal of the first input / output port or the second input / output port is used to turn on the first switching tube.

10. An electronic device, characterized in that, The electronic device is configured with the bidirectional level converter according to any one of claims 1 to 9.

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