Bidirectional level converter and electronic device

Abstract

The present invention provides a bidirectional level converter and electronic equipment, relating to the technical field of analog integrated circuits. The bidirectional level converter includes: a first port, a second port, and a conversion circuit arranged between the first port and the second port; the first port includes a first input / output port and a first reference level port; the second port includes a second input / output port and a second reference level port; the conversion circuit includes: a first Schmitt comparator, a clamping circuit, a pull-up module, a pull-down module, and a second Schmitt comparator. The present invention provides a bidirectional level converter and electronic equipment, which can achieve that when the input signal is converted from high to low, the input stage does not require a particularly strong driving capability, the input and output are in an isolated state, and the load size of the output stage has no effect on the driving capability of the input stage, which is conducive to maintaining signal integrity, is more flexible in system design, and can adapt to more application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a bidirectional level converter and electronic equipment. Background Art

[0002] In today's electronic systems, it is very common for the operating voltage of the processor interface to be incompatible with the operating voltage of peripheral devices, or for the operating voltage of the devices to be incompatible. In this case, a level converter is needed to enable communication between the processor and peripheral devices, or between devices at different operating voltages, thereby solving the problem of normal communication failure caused by different operating voltages or device damage caused by overvoltage problems.

[0003] Since the level converter can achieve a wide range of operating voltages and adapt to designs with different operating frequencies, data widths, and drive types (Open-Drain or Push-pull), the level converter can be used for the transmission of protocol signals such as I2C (Inter-Integrated Circuit), I3C (Improved Inter-Integrated Circuit), SPI (Serial Peripheral Interface, synchronous serial bus), and SD Card. Level converters with automatic bidirectional signal transmission have more advantages in system design. On the one hand, they can simplify software design and do not require real-time distinction of transmission direction in the system. On the other hand, they do not require additional direction control pins in hardware design, simplifying PCB design and saving controller hardware resources.

[0004] However, traditional level converters for automatic bidirectional signal transmission have high requirements for the driving capability of the driver stage when transmitting high-to-low level signals, or have overshoot problems when transmitting signals with a wide range of voltage levels, causing damage to the device, resulting in a decrease in the overall performance of the level converter and making it difficult to adapt to more application scenarios. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a bidirectional level converter and an electronic device to alleviate the above technical problems.

[0006] In a first aspect, an embodiment of the present invention provides a bidirectional level converter, comprising: a first port, a second port, and a conversion circuit arranged between the first port and the second port; the first port, the conversion circuit, and the second port are arranged in sequence along a signal transmission direction; the first port comprises a first input / output port and a first reference level port; the second port comprises a second input / output port and a second reference level port; wherein the first reference level port and the second reference level port are used to connect to a reference level; the conversion circuit comprises: a first Schmitt comparator, wherein the input end of the first Schmitt comparator is connected to the first input / output port, and the output end is connected to a clamping circuit, a pull-up module, and a pull-down module; Two Schmitt comparators, wherein the input end of the second Schmitt comparator is connected to the second input / output port, and the output end is connected to a clamping circuit, a pull-up module, and a pull-down module; the clamping circuit is arranged between the first input / output port and the second input / output port, and is used to prevent overvoltage from occurring at the first input / output port and the second input / output port; the pull-up module is used to pull up the first-level signal when a first-level signal is input to the first input / output port or the second input / output port; the pull-down module is used to pull down the second-level signal when a second-level signal is input to the first input / output port or the second input / output port; wherein the first-level signal is higher than the second-level signal.

[0007] In combination with the first aspect, an embodiment of the present invention provides a first possible implementation method of the first aspect, wherein the above-mentioned pull-up module includes: a first pulse circuit, the input end of the first pulse circuit is connected to the output end of the first Schmitt comparator and the second Schmitt comparator, and the output end is connected to the first control circuit and the second control circuit respectively; the first control circuit, the input end of the first control circuit is connected to the output end of the first pulse circuit, and the output end is connected to the control end of the first pull-up MOS tube; one end of the first pull-up MOS tube is connected to the first input-output port, and the other end is connected to the first reference level port; the second control circuit, the input end of the second control circuit is connected to the output end of the first pulse circuit, and the output end is connected to the control end of the second pull-up MOS tube; one end of the second pull-up MOS tube is connected to the second input-output port, and the other end is connected to the second reference level port.

[0008] In combination with the first aspect, an embodiment of the present invention provides a second possible implementation method of the first aspect, wherein the above-mentioned pull-down module includes: a second pulse circuit, the input end of the second pulse circuit is connected to the output end of the first Schmidt comparator and the second Schmidt comparator, and the output end is respectively connected to the third control circuit and the fourth control circuit; the third control circuit, the input end of the third control circuit is connected to the output end of the second pulse circuit, and the output end is connected to the control end of the first pull-down MOS tube; one end of the first pull-down MOS tube is connected to the first input-output port, and the other end is grounded; the fourth control circuit, the input end of the fourth control circuit is connected to the output end of the second pulse circuit, and the output end is connected to the control end of the second pull-down MOS tube; one end of the second pull-down MOS tube is connected to the second input-output port, and the other end is grounded.

[0009] In combination with the first possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein the above-mentioned first pull-up MOS transistor and the second pull-up MOS transistor are PMOS transistors; the gate of the first pull-up MOS transistor is connected to the output end of the first control circuit, the source is connected to the first reference level port, and the drain is connected to the first input and output port; the gate of the second pull-up MOS transistor is connected to the output end of the second control circuit, the source is connected to the second reference level port, and the drain is connected to the second input and output port.

[0010] In combination with the second possible implementation of the first aspect, an embodiment of the present invention provides a fourth possible implementation of the first aspect, wherein the above-mentioned first pull-down MOS transistor and the second pull-down MOS transistor are NMOS transistors; the gate of the first pull-down MOS transistor is connected to the output end of the third control circuit, the source is grounded, and the drain is connected to the first input and output port; the gate of the second pull-down MOS transistor is connected to the output end of the fourth control circuit, the source is grounded, and the drain is connected to the second input and output port.

[0011] In combination with the first aspect, an embodiment of the present invention provides a fifth possible implementation of the first aspect, wherein the above-mentioned bidirectional level converter further includes: a first pull-up resistor circuit, including a first pull-up resistor and a first switch connected in series; one end of the first pull-up resistor circuit is connected to the first input / output port, and the other end is connected to the first reference level port; a second pull-up resistor circuit, including a second pull-up resistor and a second switch connected in series; one end of the second pull-up resistor circuit is connected to the second input / output port, and the other end is connected to the second reference level port.

[0012] In combination with the first aspect, an embodiment of the present invention provides a sixth possible implementation of the first aspect, wherein the above-mentioned clamping circuit includes: a first switching tube and a second switching tube connected in parallel, and a switching circuit of the first switching tube and the second switching tube; wherein the switching circuit of the first switching tube is connected to the first input / output port, and the signal input by the first input / output port controls the opening and closing of the first switching tube; the switching circuit of the second switching tube is connected to the second input / output port, and the signal input by the second input / output port controls the opening and closing of the second switching tube.

[0013] In combination with the first aspect, an embodiment of the present invention provides a seventh possible implementation of the first aspect, wherein the above-mentioned clamping circuit includes: a first switching tube and a second switching tube connected in series; wherein the control end of the first switching tube is connected to a switching circuit; the switching circuit is connected to the first input / output port and the second input / output port; the control end of the second switching tube is connected to a current source, and the voltage of the control end of the second switching tube is biased at a preset voltage value.

[0014] In combination with the first aspect, an embodiment of the present invention provides an eighth possible implementation of the first aspect, wherein the above-mentioned clamping circuit includes: a first switching tube, and a switching circuit connected to the control end of the first switching tube; the switching circuit includes a logic port connected to the first input / output port and the second input / output port, and the signal of the first input / output port or the second input / output port is used to turn on the first switching tube.

[0015] In a second aspect, an embodiment of the present invention further provides an electronic device, wherein the electronic device is configured with the bidirectional level converter described in the first aspect.

[0016] The embodiments of the present invention bring the following beneficial effects:

[0017] Embodiments of the present invention provide a bidirectional level converter and electronic device. The bidirectional level converter includes: a first port, a second port, and a conversion circuit disposed between the first port and the second port. The conversion circuit includes a first Schmitt comparator, a second Schmitt comparator, and a clamping circuit, wherein the clamping circuit is disposed between the first input / output port and the second input / output port to isolate the loads of the first input / output port and the second input / output port. The conversion circuit further includes a pull-up module for pulling up the first-level signal when a first-level signal is input to the first input / output port or the second input / output port; and a pull-down module for pulling down the second-level signal when a second-level signal is input to the first input / output port or the second input / output port, thereby disabling the clamping circuit. This ensures that when the input signal transitions from high to low, the input stage does not require particularly strong driving capability, the input and output are isolated, and the output stage load has no effect on the driving capability of the input stage. Even with relatively weak driving and pull-down capability, a good signal waveform can be obtained, thereby maintaining signal integrity, providing greater flexibility in system design, and adapting to a wider range of application scenarios.

[0018] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A structural block diagram of a bidirectional level converter provided by an embodiment of the present invention;

[0022] Figure 2 A circuit diagram of a bidirectional level converter provided by an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of a clamping circuit provided by an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of signal transmission provided by an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of another clamping circuit provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of signal transmission provided by an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of a third clamping circuit provided by an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of signal transmission provided by an embodiment of the present invention;

[0029] Figure 9 A circuit diagram of a control circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0031] Currently, traditional level converters for automatic bidirectional signal transmission require high driver capability when transmitting high-to-low level signals. They also consume high power when transmitting signals or when the signal is at a low level, making them unsuitable for battery-powered systems. Furthermore, when transmitting signals with a wide voltage range, there is an overshoot problem when the input signal transitions from low to high. This overshoot voltage can damage the processor interface circuitry and components, making the level converter difficult to adapt to a wide range of application scenarios.

[0032] Based on this, embodiments of the present invention provide a bidirectional level converter and an electronic device to alleviate the above technical problems.

[0033] To facilitate understanding of this embodiment, a bidirectional level converter disclosed in an embodiment of the present invention is first introduced in detail.

[0034] In a possible implementation, an embodiment of the present invention provides a bidirectional level converter, specifically, as Figure 1 The structure block diagram of a bidirectional level converter shown includes a first port 10 , a second port 20 , and a conversion circuit 30 disposed between the first port 10 and the second port 20 .

[0035] Among them, the first port 10, the conversion circuit 30 and the second port 20 are arranged in sequence along the signal transmission direction; and the first port 10 includes a first input / output port 101 and a first reference level port 102; the second port 20 includes a second input / output port 201 and a second reference level port 202; wherein, the first reference level port 102 and the second reference level port 202 are used to connect to the reference level.

[0036] In specific implementation, since the level converter provided by the embodiment of the present invention is a bidirectional level converter, the first input / output port 101 and the second input / output port 201 can be used as both input ports and output ports.

[0037] Furthermore, the conversion circuit 30 includes:

[0038] A first Schmitt comparator 301 , wherein the input end of the first Schmitt comparator is connected to the first input / output port, and the output end of the first Schmitt comparator is connected to the clamp circuit 303 , the pull-up module 304 , and the pull-down module 305 ;

[0039] A second Schmitt comparator 302, wherein the input end of the second Schmitt comparator is connected to the second input / output port, and the output end of the second Schmitt comparator is connected to the clamp circuit 303, the pull-up module 304, and the pull-down module 305;

[0040] The clamp circuit 303 is provided between the first input / output port 101 and the second input / output port 201 to isolate the loads of the first input / output port 101 and the second input / output port 201 and prevent overvoltage from occurring at the first input / output port and the second input / output port;

[0041] The pull-up module 304 is configured to pull up the first level signal when the first input / output port 101 or the second input / output port 201 inputs the first level signal;

[0042] The pull-down module 305 is configured to pull down the second level signal when the first input / output port 101 or the second input / output port 201 inputs the second level signal; wherein the first level signal is higher than the second level signal.

[0043] In actual use, the bidirectional level converter in the embodiment of the present invention can be used between a processor interface and a peripheral device, or between different devices, to enable communication between a processor and a peripheral device, or between devices at different operating voltages.

[0044] Furthermore, the first and second reference level ports are connected to a reference power supply, which is also used to power the bidirectional level shifter. For example, the first reference level port is connected to VCCA, and the second reference level port is connected to VCCB. In this case, the high level of the input signal An at the first I / O port is referenced to the voltage of VCCA, and the high level of the input signal Bn at the second I / O port is referenced to the voltage of VCCB. Furthermore, when the bidirectional level shifter is in use, signals can be transmitted from the first I / O port to the second I / O port, and also from the second I / O port to the first I / O port.

[0045] Specifically, for ease of understanding, Figure 1 On the basis of Figure 2 A circuit diagram of a bidirectional level converter is also shown, which shows an input signal An of a first input / output port, an input signal Bn of a second input / output port, a reference voltage VCCA of a first reference level port, and a reference voltage VCCB of a second reference level port.

[0046] Further, if Figure 2 As shown, the pull-up module in the embodiment of the present invention includes:

[0047] The first pulse circuit 306 has an input terminal connected to the first Schmitt comparator 301 ( Figure 2 301) and a second Schmitt comparator 302 (shown in Figure 2 302) shown in FIG, the output end of the first pulse circuit 306 is connected to the first control circuit 307 and the second control circuit 308 respectively;

[0048] A first control circuit 307, wherein the input end of the first control circuit 307 is connected to the output end of the first pulse circuit 306, and the output end of the first control circuit 307 is connected to the control end of the first pull-up MOS transistor T1;

[0049] One end of the first pull-up MOS transistor T1 is connected to the first input / output port 101 , and the other end is connected to the first reference level port 102 ;

[0050] A second control circuit 308, wherein the input end of the second control circuit 308 is connected to the output end of the first pulse circuit 306, and the output end of the second control circuit 308 is connected to the control end of the second pull-up MOS transistor T2;

[0051] One end of the second pull-up MOS transistor T2 is connected to the second input / output port 201 , and the other end is connected to the second reference level port 202 .

[0052] Further, if Figure 2As shown, the above-mentioned pull-down module in the embodiment of the present invention includes:

[0053] A second pulse circuit 309, wherein the input end of the second pulse circuit 309 is connected to the output end of the first Schmidt comparator 301 and the output end of the second Schmidt comparator 302, and the output end of the second pulse circuit 309 is connected to the third control circuit 310 and the fourth control circuit 311 respectively;

[0054] A third control circuit 310, wherein the input end of the third control circuit 310 is connected to the output end of the second pulse circuit 309, and the output end of the third control circuit 310 is connected to the control end of the first pull-down MOS transistor T3; one end of the first pull-down MOS transistor T3 is connected to the first input / output port, and the other end is grounded;

[0055] The fourth control circuit 311 has an input end connected to the output end of the second pulse circuit 309, and an output end connected to the control end of the second pull-down MOS transistor T4; one end of the second pull-down MOS transistor T4 is connected to the second input / output port, and the other end is grounded.

[0056] Further, if Figure 2 As shown, the first pull-up MOS transistor and the second pull-up MOS transistor in the embodiment of the present invention are PMOS transistors; specifically, the gate of the first pull-up MOS transistor T1 is connected to the output end of the first control circuit, the source is connected to the first reference level port, and the drain is connected to the first input / output port; the gate of the second pull-up MOS transistor T2 is connected to the output end of the second control circuit, the source is connected to the second reference level port, and the drain is connected to the second input / output port.

[0057] further, Figure 2 In the embodiment, the first pull-down MOS transistor and the second pull-down MOS transistor are NMOS transistors; specifically, the gate of the first pull-down MOS transistor T3 is connected to the output end of the third control circuit, the source is grounded, and the drain is connected to the first input / output port; the gate of the second pull-down MOS transistor T4 is connected to the output end of the fourth control circuit, the source is grounded, and the drain is connected to the second input / output port.

[0058] Furthermore, in an embodiment of the present invention, the bidirectional level converter further includes pull-up resistors provided at the first port and the second port.

[0059] Specifically, if Figure 2 As shown, the bidirectional level converter includes a first pull-up resistor circuit, in which the first pull-up resistor R is connected in series. PUaOne end of the first pull-up resistor circuit is connected to the first input / output port, and the other end is connected to the first reference level port; and a second pull-up resistor circuit comprising a second pull-up resistor R connected in series PUb and a second switch Sb; one end of the second pull-up resistor circuit is connected to the second input / output port, and the other end is connected to the second reference level port.

[0060] Further, based on Figure 2 The working process of the bidirectional level converter in the embodiment of the present invention is further described as follows:

[0061] in, Figure 2 In the embodiment of the present invention, it is assumed that the bidirectional level converter in the embodiment of the present invention is powered by VCCA and VCCB, An and Bn are signals of the input and output ports, that is, An and Bn are both input and output, the high level of An is referenced to the VCCA voltage, and the high level of Bn is referenced to the VCCB voltage. In addition, in the embodiment of the present invention, the transmission of a signal from the first input and output port to the second input and output port is taken as an example, that is, Figure 2 An in transmits signal to Bn.

[0062] During the process of An changing from low to high, that is, the voltage changing from low voltage to high voltage, the input end of the bidirectional level converter, that is, the first Schmitt comparator 301 of the first port, is used to detect the input voltage of the first input / output port. When the input voltage is detected to exceed the VIH of the first Schmitt comparator, the first Schmitt comparator outputs a first level signal from low to high. That is, the first level signal is used to represent the process of the first Schmitt comparator detecting that the input voltage of the first input / output port changes from low to high and exceeds the VIH.

[0063] The first level signal is transmitted to the clamp circuit 303 , the pull-up module 304 , and the pull-down module 305 .

[0064] Furthermore, the first pulse circuit 306 of the pull-up module generally refers to a rising edge monostable circuit (also called a rising edge one-shot circuit). After receiving a trigger signal, the rising edge monostable circuit can output a high-level pulse with a fixed width and then automatically restore to a low-level state.

[0065] After the first level signal is input to the first pulse circuit 306, the first pulse circuit 306 receives the low-to-high first level signal through pin A_in, and then A_out and B_out output a pulse signal of about several ns. The time or duty cycle of the pulse signal is determined by the load size of the bidirectional level converter, and this pulse signal turns on the two pull-up PMOS tubes T1 and T2 through the first control circuit 307 and the second control circuit 308.

[0066] In a specific implementation, the first control circuit 307 and the second control circuit 308 are drive circuits with SR control (Slew Rate Control). The drive circuit with SR control can control the output port voltage to change more smoothly, which is beneficial to signal transmission. The specific SR parameters can be set according to actual usage conditions, and the embodiment of the present invention does not limit this.

[0067] At the same time, for the pull-down module, its trigger signal can be configured so that it is not triggered when receiving the first level signal, that is, only the pull-up module works at this time.

[0068] Furthermore, when the two pull-up PMOS transistors T1 and T2 are turned on, An, Bn and VCCA, VCCB are connected by the two pull-up PMOS transistors T1 and T2 with smaller on-resistance, and An, Bn are quickly pulled up to VCCA, VCCB. At the same time, the first pull-up resistor R PUa and the second pull-up resistor R PUb The connected switches Sa and Sb are closed, and the clamping circuit 303 is ready to be closed.

[0069] In actual use, the clamping circuit in the embodiment of the present invention can be a clamped pass gate circuit. A clamping circuit is usually introduced to control the conduction and cutoff of the transmission gate. When the transmission gate needs to be turned on, the clamping circuit will fix the signal at a specific potential so that the transmission gate can work normally; when the transmission gate needs to be cut off, the clamping circuit will clamp the signal at another potential, thereby preventing the signal from passing.

[0070] In the embodiment of the present invention, the clamping circuit 303 may be turned off upon receiving the first level signal.

[0071] After the signal of the first pulse circuit 306 ends, the high level of An and Bn is controlled by R PUa and R PUb The pull-up resistor maintains the clamp circuit 303 in the OFF state, thereby converting the high-level signal in the VCCA voltage domain to the high-level signal in the VCCB voltage domain.

[0072] In actual use, for ease of understanding, Figure 3 A schematic diagram of a clamping circuit is shown, specifically, as Figure 3As shown, the clamping circuit 303 in the embodiment of the present invention includes: a first switch tube N2 and a second switch tube N1 connected in parallel, and a switching circuit of the first switch tube N2 and the second switch tube N1; wherein the switching circuit of the first switch tube N2 is connected to the first input / output port, and the first switch tube is controlled to be turned on and off by the signal input from the first input / output port; the switching circuit of the second switch tube N2 is connected to the second input / output port, and the second switch tube is controlled to be turned on and off by the signal input from the second input / output port.

[0073] Specifically, Figure 3 In the embodiment, P1 is a long-channel PMOS transistor, which realizes a simple current source. The long-channel MOS transistor is also called a long-channel MOS transistor. In the embodiment of the present invention, the long-channel MOS transistor is a P-type MOS transistor, that is, the long-channel PMOS transistor P1 in the embodiment of the present invention. Further, the first switch transistor N2 and the second switch transistor N1 are NMOS transistors and are connected in parallel. The sources of the first switch transistor N2 and the second switch transistor N1 are both connected to the APG_in port, and the drains are both connected to the BPG_in port. In addition, Figure 2 It can be seen that the APG_in port is connected to the input signal An of the first input / output port, and the BPG_in port is connected to the input signal Bn of the second input / output port (in this example, Bn of the second input / output port is an output signal).

[0074] Further, combined Figure 2 , wherein the signal AL_in corresponds to the output terminal of the first Schmitt comparator 301, that is, the signal input by the first input / output port. The signal AL_in passes through a logic gate ( Figure 3 The NOT gate A1 in the circuit is connected to the gate of the first switch tube N2 to control the on and off of the first switch tube N2. At this time, the NOT gate A1 is equivalent to the switching circuit of the first switch tube N2.

[0075] Furthermore, the signal BL_in corresponds to the output terminal of the second Schmitt comparator 302, that is, the signal inputted by the second input / output port. The signal BL_in is passed through a logic gate ( Figure 3 The input of the NOT gate B1 is Figure 3 The third pulse circuit 312 is a monostable circuit with a specific bias voltage, which can output a corresponding pulse signal to the gate of the PMOS tube T5.

[0076] In addition, a ground MOS transistor PG3 is further configured at the port of the signal BL_in. The gate of the ground MOS transistor PG3 is connected to the port of the signal BL_in, the drain is connected to the drain of the PMOS transistor T5, and the source is grounded.

[0077] Therefore, the switching circuit of the second switch transistor N1 actually includes a NOT gate B1 , a third pulse circuit 312 , a PMOS transistor T5 , a grounding MOS transistor PG3 , and a current source implemented by the long-channel PMOS transistor P1 .

[0078] Furthermore, when An changes from low to high, while An and Bn are being pulled high, the gate voltage of the first switch N2 (the first switch N2 and the second switch N1 are also referred to as the Pass Gate) in the clamp circuit will be pulled down to a low level after a certain delay time. This delay time is caused by the logic gate circuit included in the switch circuit. Therefore, at this time, the first switch N2 will be in a ready-to-off state. Therefore, when Bn is pulled high to VCCB, the Pass Gate (N2) is still at the VCCB high level. At this time, the input signal at the An end will be pulled up simultaneously by VCCA through T1 and VCCB through T2 and the second switch N1.

[0079] If the difference between the gate voltage VG_N2 of the first switch N2 and the threshold voltage VTH_N2 of the first switch N2 is greater than VCCA, that is, VG_N2-VTH_N2>VCCA, then the An signal will have a large overshoot. The higher the VCCB, the greater the overshoot. In the embodiment of the present invention, the above-mentioned clamping circuit 303 is added to make Figure 3 The PMOS transistor T5 is limited to near VCCA+VTH. When the An signal is near VCCA, the first switch transistor N2 is in the OFF state. There is no need to wait until the gate voltage of Pass Gate N2 is pulled low by the logic signal. Pass Gate N2 is turned off by an extremely fast logic signal. This is difficult to achieve in related designs. However, in the embodiment of the present invention, this solution can be implemented, thereby alleviating the problem of large overshoot of the An signal.

[0080] and, Figure 3 In the circuit, at the falling edge of the BL_in signal, the gate voltage of the second switch tube N1 will be quickly pulled up to VCCA+VTH by the gate bias pulse signal of PMOS T5 and the third pulse circuit. After the pulse signal of the third pulse circuit ends, the high level is maintained by the current flowing through the long channel PMOS tube P1. This circuit realizes the gate voltage clamping of Pass Gate N2. At the same time, the Figure 3 The circuit design shown is simple and does not require complex additional circuits to implement the logical combination of AL_in and BL_in.

[0081] Furthermore, the above Figure 2 and Figure 3 The process of An changing from low to high is explained below. The process of An changing from high to low is further explained below.

[0082] For the sake of convenience, the example of transmitting a signal from the first input / output port to the second input / output port is also taken, that is, Figure 2 An in transmits signal to Bn.

[0083] At this time, after the first Schmitt comparator 301 at the input end of the bidirectional level converter, i.e., the first port, detects that the input voltage exceeds the VIL of the first Schmitt comparator, it outputs a second level signal that changes from high to low. In other words, the second level signal is used to indicate that the first Schmitt comparator has detected that the input voltage at the first input / output port has changed from high to low and exceeded the voltage value corresponding to VIL. The VIL and VIH of the first Schmitt comparator can be set based on the reference voltage or threshold voltage of the first Schmitt comparator, which is not limited in this embodiment of the present invention.

[0084] The second level signal is also transmitted to the clamp circuit 303 , the pull-up module 304 , and the pull-down module 305 .

[0085] Wherein, for the pull-up module, its trigger signal can be configured so that it is not triggered when receiving the second level signal, that is, only the pull-down module works at this time.

[0086] Furthermore, the second pulse circuit 309 of the pull-down module generally refers to a falling edge monostable circuit (also called a Falling edge One-Shot), which can output a high-level pulse of a fixed width after receiving a trigger signal, and then automatically restore to a low-level state.

[0087] After the second level signal is input to the second pulse circuit 309, the A_in port of the second pulse circuit 309 receives the second level signal. The A_out and B_out ports of the second pulse circuit 309 then output a pulse signal of approximately several nanoseconds. The duration or duty cycle of this pulse signal is determined by the load of the bidirectional level converter. Furthermore, this pulse signal, passing through the third control circuit 310 and the fourth control circuit 311, turns on the two pull-down NMOS transistors T3 and T4. T3 and T4, which have relatively low on-resistance, then connect An and Bn to ground, quickly pulling An and Bn down to a low level.

[0088] Further, based on Figure 3 In the process of An and Bn being pulled low, the gate voltage of the second switch N1 in the clamp circuit, also called Pass Gate N1, will be pulled high, making the entire clamp circuit in the Turning ON state. At the same time, the first pull-up resistor R PUa and the second pull-up resistor R PUbThe connected switches Sa and Sb are disconnected. After the pulse signal of the second pulse circuit 309 ends, because the pass gate N1 is in the ON state, the low levels of An and Bn are simultaneously pulled low by the external driver. This allows the low-level signal in the VCCA voltage domain to be transferred to the low-level signal in the VCCB voltage domain.

[0089] Moreover, in the process of An changing from high to low, the clamping circuit is in the OFF state at the beginning, so the load capacitances at the An and Bn terminals are isolated from each other. The driving input at the An terminal only needs to discharge the charge on the load at the An terminal, and the charge on the load at the Bn terminal is discharged by T4. Therefore, in the embodiment of the present invention, the design of the bidirectional level converter has low requirements on the driving capability of the An terminal, while being able to ensure the speed of the falling edge of the input and output signals.

[0090] When the signal is low, the first pull-up resistor R PUa and the second pull-up resistor R PUb The connected switches Sa and Sb are in the off state, so the bidirectional level converter itself will not have current flowing from VCCA and VCCB to the input driver. Compared with the circuit architecture of the traditional bidirectional level converter, the bidirectional level converter in the embodiment of the present invention saves the power consumption of VCCA and VCCB. That is, in a system where signal transmission does not require an external pull-up resistor, such as the transmission of an SPI signal, when the transmission signal is low, due to R PUa and R PUb In the disconnected state, no additional current flows through the pull-up resistor, thus saving system power consumption.

[0091] And, for ease of understanding, based on the above Figure 2 and Figure 3 , Figure 4 A schematic diagram of signal transmission from An to Bn is also shown, specifically including An, AL_in, the gate voltage of the first switch tube N2, the gate voltage of the second switch tube N1, and a schematic diagram of changes in the signals corresponding to Bn and BL_in during the transmission process.

[0092] Furthermore, in addition to the above Figure 3 In the embodiment of the present invention, the clamping circuit may further include: a first switch tube and a second switch tube connected in series; that is, the clamping circuit may further include: a first switch tube and a second switch tube connected in series; Figure 3 The first switch tube N2 and the second switch tube N1 in the embodiment can also be connected in series. Specifically, Figure 5A schematic diagram of another clamping circuit is shown, namely, including a first switch tube N2 and a second switch tube N1 connected in series, wherein the control end of the first switch tube N2 is connected to a switch circuit, and the switch circuit is connected to the first input / output port and the second input / output port; the control end of the second switch tube N1 is connected to a current source, and the voltage of the control end of the second switch tube N1 is biased at a preset voltage value.

[0093] Specifically, Figure 5 In the circuit, the current source is also implemented by the long-channel PMOS transistor P1, which can simplify the circuit design. The first switch transistor N2 and the second switch transistor N1 are connected in series. The gate voltage of N1 is always biased near VCCA+VTH. The opening and closing of N2 are realized by the AL_in and BL_in signals and logic circuits. Figure 5 It includes a high-speed level conversion unit, also known as High Speed Level-shift, which is used to quickly convert the AL_in signal from the VCCA voltage domain to the VCCB voltage domain. It can be achieved through the unidirectional level conversion circuit in the relevant technology. Its high speed is to minimize the logical gate delay. Figure 5 The series connection method shown requires a larger physical area to achieve a smaller Pass Gate on-resistance.

[0094] And, for ease of understanding, Figure 6 A schematic diagram of signal transmission from An to Bn is also shown, specifically including a schematic diagram of changes in An, AL_in, the gate voltage of the first switch tube N2, the gate voltage of the second switch tube N1, and the signals corresponding to Bn and BL_in during the transmission process.

[0095] further, Figure 7 A schematic diagram of a third clamping circuit is also shown, that is, a third embodiment of the clamping circuit. In this embodiment, the clamping circuit includes only one switch tube, that is, Figure 7 The first switch tube N1 and the switch circuit connected to the control end of the first switch tube N1; specifically, the switch circuit at this time includes a logic port connected to the first input / output port and the second input / output port, and the signal of the first input / output port or the second input / output port is used to turn on the first switch tube N1.

[0096] Specifically, Figure 7 In the embodiment, the logic port included in the switch circuit can be directly connected to AL_in and BL_in. A logic gate circuit is also provided inside the switch circuit. The specific logic gates included can be set according to actual usage, and the embodiment of the present invention does not limit this.

[0097] And, in Figure 7In the circuit, the current source is also realized by the long channel PMOS tube P1, and also includes a high-speed level conversion unit. The falling edge of AL_in or BL_in will turn on the above Figure 7 The first switch tube N1 (also called Pass Gate N1) in the circuit is turned on, and at this time, the gate voltage of the first switch tube N1 is quickly pulled up to VCCA+VTH by the one-pulse signal of PMOS T5 and the third pulse circuit. After the one-pulse signal ends, the high level is maintained by the current flowing through the long-channel PMOS tube P1. This circuit realizes the gate voltage clamping of Pass Gate N1.

[0098] At the same time, the high-speed level conversion unit is a unidirectional level conversion circuit used to quickly convert the AL_in signal from the VCCA voltage domain to the VCCB voltage domain. The high speed is to minimize the gate delay in the logic. This implementation uses only one NMOS as the pass gate in the clamping potential circuit, and the gate voltage is biased at VCCA+VTH. Compared with the two pass gates mentioned above ( Figure 3 When N1 and N2 (in the figure) are connected in parallel and biased at VCCA and VCCB, respectively, the on-resistance achieved with the same layout area is relatively low. Compared to the aforementioned series connection of N1 and N2, the area is significantly smaller, offering a significant advantage. Furthermore, when transmitting low-level signals, if a pull-up resistor is connected to the port of the bidirectional level converter, such as when an external pull-up resistor is required for I2C signal transmission, the clamping circuit's on-resistance must be as low as possible to minimize the difference between the input and output voltages. The bidirectional level converter provided in the embodiments of the present invention effectively meets these design requirements.

[0099] Further, corresponding Figure 7 , Figure 8 A schematic diagram of signal transmission from An to Bn is also shown, specifically including a schematic diagram of changes in An, AL_in, the gate voltage of the first switch tube N1, the gate voltage of the second switch tube N1, and the signals corresponding to Bn and BL_in during the transmission process.

[0100] also, Figure 9 A circuit diagram of a control circuit is also shown, wherein: Figure 9 (a) corresponds to the first control circuit and the second control circuit, which are used to drive the first pull-up MOS transistor and the second pull-up MOS transistor. Figure 9 (b) corresponds to the third control circuit and the fourth control circuit, which are used to drive the first pull-down MOS transistor and the second pull-down MOS transistor.

[0101] Specifically, based on Figure 9In the embodiment shown, PM4, NM4, and PM7, NM7 are used to control the output signal out (out_n, out_p) by combining the input signal in (in_n, in_p) and the voltage An of the input and output ports as feedback signals, wherein in_n or in_p refers to the output signal of the first pulse circuit or the second pulse circuit, which serves as the input of the control circuit, and out_n or out_p is connected to the corresponding pull-up MOS transistor or pull-down MOS transistor ( Figure 2 The gate of one of the four MOS tubes T1, T2, T3 and T4 is connected, so this circuit can effectively control Figure 2 The specific implementation of the control circuit can also be set according to actual usage, and the embodiment of the present invention is not limited to this.

[0102] In summary, the bidirectional level converter provided by the embodiment of the present invention has the following beneficial effects:

[0103] (1) It has automatic two-way transmission of signals and does not require a direction control port;

[0104] (2) When the signal changes from high to low, the input stage does not need a particularly strong driving capability. The input and output are in an isolated state. The load size of the output stage has no effect on the driving capability of the input stage. Even with a weaker driving pull-down capability, a better signal waveform can be obtained, which is conducive to maintaining the integrity of the signal and is more flexible for system design.

[0105] (3) When the signal transmission or input signal is low, the overall power consumption is low, which is more advantageous for battery-powered systems;

[0106] (4) The voltage of VCCB can be a very wide operating voltage. For example, under the condition that VCCA <= VCCB is guaranteed, it can work in the range of 1.2V to 5.5V, which can adapt to more application scenarios.

[0107] (5) In the embodiment of the present invention, on the basis of solving the problems of the prior art, a turn-on rate control circuit for the pull-up PMOS and the pull-down NMOS, namely the first control circuit, the second control circuit, the third control circuit, or the fourth control circuit, is added to optimize the transient current at the moment the pulse circuit is turned on, which can better match the transmission line impedance, ensure signal integrity and reduce electromagnetic interference.

[0108] Furthermore, an embodiment of the present invention provides an electronic device, which is equipped with the bidirectional level converter provided by the above embodiment.

[0109] The electronic device provided by the embodiment of the present invention has the same technical features as the bidirectional level converter provided by the above embodiment, and therefore can solve the same technical problems and achieve the same technical effects.

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the electronic device described above can refer to the corresponding process in the aforementioned embodiment and will not be repeated here.

[0111] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0112] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0113] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0114] Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A bidirectional level converter, characterized in that: The bidirectional level converter comprises: a first port, a second port, and a conversion circuit arranged between the first port and the second port; the first port, the conversion circuit, and the second port are arranged in sequence along the signal transmission direction; The first port includes a first input / output port and a first reference level port; the second port includes a second input / output port and a second reference level port; Wherein, the first reference level port and the second reference level port are used to connect to the reference level; The conversion circuit includes: a first Schmitt comparator, wherein an input end of the first Schmitt comparator is connected to the first input / output port, and an output end of the first Schmitt comparator is connected to the clamping circuit, the pull-up module, and the pull-down module; a second Schmitt comparator, wherein the input end of the second Schmitt comparator is connected to the second input-output port, and the output end of the second Schmitt comparator is connected to the clamping circuit, the pull-up module, and the pull-down module; The clamping circuit is provided between the first input / output port and the second input / output port, and is used to prevent the first input / output port and the second input / output port from overvoltage; The pull-up module is configured to pull up the first level signal when the first input / output port or the second input / output port inputs a first level signal; The pull-down module is configured to pull down the second-level signal when the first input / output port or the second input / output port inputs a second-level signal; wherein the first-level signal is higher than the second-level signal.

2. The bidirectional level converter according to claim 1, wherein: The pull-up module includes: a first pulse circuit, wherein an input end of the first pulse circuit is connected to the output ends of the first Schmidt comparator and the second Schmidt comparator, and an output end of the first pulse circuit is connected to the first control circuit and the second control circuit respectively; The first control circuit, wherein the input end of the first control circuit is connected to the output end of the first pulse circuit, and the output end is connected to the control end of the first pull-up MOS transistor; One end of the first pull-up MOS transistor is connected to the first input / output port, and the other end is connected to the first reference level port; The second control circuit, wherein the input end of the second control circuit is connected to the output end of the first pulse circuit, and the output end of the second control circuit is connected to the control end of the second pull-up MOS transistor; One end of the second pull-up MOS transistor is connected to the second input / output port, and the other end is connected to the second reference level port.

3. The bidirectional level converter according to claim 1, wherein: The pull-down module includes: a second pulse circuit, wherein an input end of the second pulse circuit is connected to the output ends of the first Schmidt comparator and the second Schmidt comparator, and an output end of the second pulse circuit is connected to the third control circuit and the fourth control circuit respectively; The third control circuit has an input end connected to the output end of the second pulse circuit, and an output end connected to the control end of the first pull-down MOS transistor; One end of the first pull-down MOS transistor is connected to the first input / output port, and the other end is grounded; The fourth control circuit has an input end connected to the output end of the second pulse circuit, and an output end connected to the control end of the second pull-down MOS transistor; One end of the second pull-down MOS transistor is connected to the second input / output port, and the other end is grounded.

4. The bidirectional level converter according to claim 2, wherein: The first pull-up MOS transistor and the second pull-up MOS transistor are PMOS transistors; The gate of the first pull-up MOS transistor is connected to the output end of the first control circuit, the source is connected to the first reference level port, and the drain is connected to the first input / output port; The gate of the second pull-up MOS transistor is connected to the output end of the second control circuit, the source is connected to the second reference level port, and the drain is connected to the second input / output port.

5. The bidirectional level converter according to claim 3, wherein: The first pull-down MOS transistor and the second pull-down MOS transistor are NMOS transistors; The gate of the first pull-down MOS transistor is connected to the output end of the third control circuit, the source is grounded, and the drain is connected to the first input / output port; The gate of the second pull-down MOS transistor is connected to the output end of the fourth control circuit, the source is grounded, and the drain is connected to the second input / output port.

6. The bidirectional level converter according to claim 1, wherein: The bidirectional level converter further includes: A first pull-up resistor circuit includes a first pull-up resistor and a first switch connected in series; one end of the first pull-up resistor circuit is connected to the first input / output port, and the other end is connected to the first reference level port; The second pull-up resistor circuit includes a second pull-up resistor and a second switch connected in series; one end of the second pull-up resistor circuit is connected to the second input / output port, and the other end is connected to the second reference level port.

7. The bidirectional level converter according to claim 1, wherein: The clamping circuit includes: a first switching tube and a second switching tube connected in parallel, and a switching circuit of the first switching tube and the second switching tube; The switch circuit of the first switch tube is connected to the first input / output port, and the first switch tube is turned on and off by a signal input from the first input / output port; The switch circuit of the second switch tube is connected to the second input / output port, and the second switch tube is turned on and off by a signal input from the second input / output port.

8. The bidirectional level converter according to claim 1, wherein: The clamping circuit includes: a first switching tube and a second switching tube connected in series; Wherein, the control end of the first switch tube is connected to a switch circuit; the switch circuit is connected to the first input / output port and the second input / output port; The control terminal of the second switch tube is connected to the current source, and the voltage of the control terminal of the second switch tube is biased at a preset voltage value.

9. The bidirectional level converter according to claim 1, wherein: The clamping circuit includes: a first switching tube, and a switching circuit connected to a control terminal of the first switching tube; The switch circuit includes a logic port connected to the first input / output port and the second input / output port, and a signal from the first input / output port or the second input / output port is used to turn on the first switch tube.

10. An electronic device, characterized in that: The electronic device is provided with the bidirectional level converter according to any one of claims 1 to 9.

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