Analog-to-digital converter calibration circuit and method, analog-to-digital converter and electronic equipment
Through time division multiplexing logic and preprocessing technology, the analog-to-digital converter calibration circuit calibrates the multiple channels, solving the problem of increased area and power consumption in the TI-ADC digital calibration system, and achieving efficient reduction of digital circuits.
Patent Information
- Application Number
- CN202311840673.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-08
AI Technical Summary
In the existing TI-ADC digital calibration system, as the number of channels increases, the area of the digital calibration circuit increases exponentially with power consumption, limiting the development of SerDes receivers, and the existing solutions cannot solve the problem from the root.
Using time division multiplexing logic, the multiple analog-to-digital converter channel multiplexes an analog-to-digital converter calibration circuit. By pre-processing the output signal of the target channel, compute the mismatch estimation result with the mismatch intermediate value of the previous processing cycle, and performing calibration to reduce the area and power consumption of the digital circuit.
On the premise of ensuring the calibration convergence time and accuracy, the area and power consumption of the digital calibration circuit are significantly reduced, solving the area and power consumption problems caused by the increase in the number of TI-ADC channels.
Smart Images
Figure CN120281318A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of analog-to-digital signal conversion, and particularly to an analog-to-digital converter calibration circuit, method, analog-to-digital converter, and electronic device. Background Art
[0002] In recent years, with the rapid development of fields such as artificial intelligence and cloud computing, data centers have an increasing demand for bandwidth. To support higher interface rates, it is necessary to increase the operating rate of optical communication or SerDes (Serializer) receivers. Therefore, a receiver architecture based on a Time-Interleaved Analog Digital Converter (TI-ADC) has gradually become the mainstream design. The main factor affecting the performance of a TI-ADC is the mismatch between channels, and a digital calibration circuit needs to be introduced to estimate and calibrate it. As the number of channels of a TI-ADC increases, the area and power consumption of the digital calibration circuit will increase exponentially, which greatly limits the development of SerDes receivers. Summary of the Invention
[0003] The present disclosure provides an analog-to-digital converter calibration circuit, method, analog-to-digital converter, and electronic device.
[0004] In a first aspect, an embodiment of the present disclosure provides an analog-to-digital converter calibration circuit, including:
[0005] A control module, configured to send a calibration instruction to a preprocessing module according to a preset processing period, where the calibration instruction is used to indicate a target channel of the current processing period, and the target channel is one of the channels of the analog-to-digital converter;
[0006] A preprocessing module, configured to receive output signals of each of the channels; according to the calibration instruction, perform preprocessing on the output signal of the target channel of the current processing period to obtain a preprocessing result;
[0007] A storage module, configured to store mismatch intermediate values of each channel of the analog-to-digital converter;
[0008] A calculation module, configured to obtain a first mismatch intermediate value of the target channel from the storage module, and determine a mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result;
[0009] A calibration module, configured to calibrate the output signal of the target channel according to the mismatch estimation result.
[0010] In another aspect, an embodiment of the present disclosure further provides an analog-to-digital converter, including the analog-to-digital converter calibration circuit as described above.
[0011] In another aspect, an embodiment of the present disclosure further provides an electronic device, including the analog-to-digital converter as described above.
[0012] In another aspect, an embodiment of the present disclosure further provides an analog-to-digital converter signal calibration method, the method including:
[0013] Receiving output signals of each channel of the analog-to-digital converter, and calibrating the output signals of each of the channels in sequence according to a preset processing period; wherein, within one said processing period, calibrating the output signal of a target channel of the processing period, the target channel being one of each of the channels;
[0014] The calibrating the output signal of the target channel of the processing period includes:
[0015] Performing preprocessing on the output signal of the target channel of the processing period to obtain a preprocessing result;
[0016] Obtaining a first mismatch intermediate value of the target channel, and determining a mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result;
[0017] Calibrating the output signal of the target channel according to the mismatch estimation result.
[0018] The analog-to-digital converter calibration circuit provided by the embodiment of the present disclosure adopts time-division multiplexing logic to calibrate the output signals of each channel of the analog-to-digital converter in sequence. Among them, for the target channel being currently processed, preprocessing is performed on the output signal of the target channel, and a mismatch estimation result is calculated according to the preprocessing result of the target channel and the first mismatch intermediate value of the previous processing period of the target channel, and the output signal of the target channel is calibrated according to the mismatch estimation result; based on time-division multiplexing logic, the output signals of multiple analog-to-digital converters share the same analog-to-digital converter calibration circuit, which can greatly reduce the area and power consumption overhead of the digital circuit; by performing preprocessing on the output signal of the analog-to-digital converter, the influence on the calibration convergence time and calibration accuracy can be reduced, so as to reduce the area of the digital calibration circuit and lower the power consumption on the premise of ensuring the calibration convergence time and calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is a schematic structural diagram of the analog-to-digital converter calibration circuit provided by the embodiment of the present disclosure;
[0020] Figure 2 is a schematic structural diagram of the analog-to-digital converter provided by the embodiment of the present disclosure;
[0021] Figure 3 is a schematic diagram of the analog-to-digital converter signal calibration process provided by the embodiment of the present disclosure;
[0022] Figure 4 A flowchart for determining a mismatch estimation result provided by an embodiment of the present disclosure. Detailed implementation manners
[0023] Hereinafter, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0024] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0025] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "consists of" are used in this specification, it specifies the presence of the stated features, wholes, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.
[0026] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of ideal schematic diagrams of the present disclosure. Accordingly, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Therefore, the regions illustrated in the drawings have schematic attributes, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be restrictive.
[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.
[0028] In an existing TI-ADC digital calibration system, generally, each channel of the analog-to-digital converter uses an independent calibration circuit. As the number of channels of the TI-ADC increases, the area and power consumption of the digital calibration circuit will increase exponentially, which greatly limits the development of the SerDes receiver. To solve the above problems, the following are several relatively common solutions currently:
[0029] 1. Reduce the area and power consumption overhead of the calibration digital circuit by reducing the calculation accuracy of the calibration algorithm for inter-channel mismatch;
[0030] 2. By improving the accuracy of the analog circuit, the area and power consumption overhead of the calibration digital circuit are reduced.
[0031] Reducing the algorithm accuracy will lead to the performance degradation of the analog-to-digital converter, and improving the accuracy of the analog circuit will bring the problem of excessive power consumption of the analog circuit. Therefore, the above solutions all need to introduce additional costs to ensure the area and power consumption of the digital calibration circuit, and cannot solve the problem at the root.
[0032] To solve the above problems, an embodiment of the present disclosure provides an analog-to-digital converter calibration circuit, as Figure 1 shown. The analog-to-digital converter calibration circuit includes a control module 1, a preprocessing module 2, a storage module 3, a calculation module 4, and a calibration module 5. The control module 1 is configured to send a calibration instruction to the preprocessing module 2 according to a preset processing period. The calibration instruction is used to indicate the target channel of the current processing period, and the target channel is one of the channels of the analog-to-digital converter. The preprocessing module 2 is configured to receive the output signals of each channel and preprocess the output signal of the target channel of the current processing period according to the calibration instruction to obtain a preprocessing result. The storage module 3 is configured to store the mismatch intermediate values of each channel of the analog-to-digital converter. The calculation module 4 is configured to obtain the first mismatch intermediate value of the target channel from the storage module 3 and determine the mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result. The calibration module 5 is configured to calibrate the output signal of the target channel according to the mismatch estimation result.
[0033] All channels of the analog-to-digital converter share one analog-to-digital converter calibration circuit. As Figure 1 shown, the output signals (i.e., sampling signals) of the n channels of the analog-to-digital converter are all input to one analog-to-digital converter calibration circuit, that is, the n channels of the analog-to-digital converter share one analog-to-digital converter calibration circuit, rather than each channel of the analog-to-digital converter corresponding to one analog-to-digital converter calibration circuit. The analog-to-digital converter includes, but is not limited to, a high-speed time-interleaved analog-to-digital converter. In the embodiment of the present disclosure, the high-speed time-interleaved analog-to-digital converter is taken as an example for illustration.
[0034] The control module 1 is configured to control the time-division multiplexing of the output signals of different channels and send them into the preprocessing module 2. The preprocessing module 2 is configured to preprocess the output signal of the target channel of the high-speed time-interleaved analog-to-digital converter within the current period. The calculation module 4 is configured to calculate the signal calibration result of the target channel. The storage module 3 is configured to store the mismatch intermediate values of each channel of the high-speed time-interleaved analog-to-digital converter. The calibration module 5 is configured to calibrate the output signal of the target channel of the high-speed time-interleaved analog-to-digital converter according to the calibration result, that is, perform compensation processing.
[0035] When calibrating an analog-to-digital converter (ADC) circuit solely through time-division multiplexing of multiple channels, although the area of the ADC calibration circuit can be reduced, the calibration convergence time will increase significantly, affecting the calibration accuracy. The analog circuits of each channel in a high-speed time-interleaved ADC are basically the same, and the mismatch characteristics of each channel are also basically the same, only the specific mismatch amounts are different. Based on the above special structure of the high-speed time-interleaved ADC, in the premise of time-division multiplexing an ADC calibration circuit, the output signals of the channels of the high-speed time-interleaved ADC are preprocessed, reducing the area of the calibration circuit while reducing the impact on the calibration convergence time and calibration accuracy.
[0036] The ADC calibration circuit can be implemented with digital circuits or analog circuits. In the embodiments of the present disclosure, a digital circuit is used to implement the ADC calibration circuit.
[0037] The ADC calibration circuit provided by the embodiments of the present disclosure uses time-division multiplexing logic to sequentially calibrate the output signals of each channel of the ADC. Among them, for the target channel being currently processed, the output signal of the target channel is preprocessed, and the mismatch estimation result is calculated based on the preprocessing result of the target channel and the first mismatch intermediate value of the previous processing cycle of the target channel, and the output signal of the target channel is calibrated according to the mismatch estimation result; based on the time-division multiplexing logic, the output signals of multiple ADCs share the same ADC calibration circuit, which can significantly reduce the area and power consumption overhead of the digital circuit; by preprocessing the output signals of the ADC, the impact on the calibration convergence time and calibration accuracy can be reduced, so as to reduce the area of the digital calibration circuit and the power consumption on the premise of ensuring the calibration convergence time and calibration accuracy.
[0038] In some embodiments, the control module 1 is used to send a calibration instruction to the preprocessing module 2 according to a preset number of times. That is to say, the total number of calibration times for the ADC calibration circuit to calibrate the signals of each channel can be preset, and the calibration stops when the total number of calibration times is reached. It should be noted that the preset number of times is the total number of times for calibrating the signals of each channel, rather than the total number of times for calibrating the signals of one channel. Exemplarily, if the high-speed time-interleaved ADC has n channels, the preset number of times is the total number of times for calibrating the signals of the n channels accumulated. In order to ensure the same number of signal calibration times for each channel, in some embodiments, the preset number of times can be m*n, where m is a natural number, that is, the preset number of times can be an integer multiple of the number of channels.
[0039] In some embodiments, the calculation module 4 is used to determine the second mismatch intermediate value of the current processing cycle of the target channel according to the first mismatch intermediate value and the preprocessing result; determine the mismatch estimation result of the target channel according to the second mismatch intermediate value and the mismatch intermediate values of other channels.
[0040] The analog-to-digital converter calibration circuit calibrates the output signals of each channel in sequence according to the processing cycle, and processes the output signal of one channel in each processing cycle. The mismatch intermediate values calculated during the signal calibration process of each channel are all stored in the storage module 3. The first mismatch intermediate value and the second mismatch intermediate value are intermediate values obtained by calculating the mismatch estimation result. When calculating the mismatch estimation result of the target channel in the current processing cycle, the mismatch intermediate value previously stored in the storage module 3 for the target channel, that is, the first mismatch intermediate value, is required.
[0041] It should be noted that in order to ensure that the target channel can be calibrated again later, after calculating the second mismatch intermediate value of the target channel in this processing cycle, the second mismatch intermediate value also needs to be stored in the storage module 3, and the mismatch intermediate value of the target channel is updated according to the second mismatch intermediate value, that is, the mismatch intermediate value of the target channel in the storage module 3 is updated from the first mismatch intermediate value to the second mismatch intermediate value.
[0042] In some embodiments, the preprocessing includes at least one of the following: offset sampling, gain sampling, and phase offset sampling. Correspondingly, the first mismatch intermediate value and the second mismatch intermediate value include at least one of the following: offset mismatch intermediate value, gain mismatch intermediate value, and phase offset mismatch intermediate value. Correspondingly, the mismatch estimation result includes at least one of the following: offset mismatch estimation result, gain mismatch estimation result, and phase offset mismatch estimation result.
[0043] In the case where the preprocessing includes offset sampling, the second mismatch intermediate value calculated by the calculation module 4 includes the offset mismatch intermediate value, and the mismatch estimation result includes the offset mismatch estimation result; in the case where the preprocessing includes gain sampling, the second mismatch intermediate value calculated by the calculation module 4 includes the gain mismatch intermediate value, and the mismatch estimation result includes the gain mismatch estimation result; in the case where the preprocessing includes phase offset sampling, the second mismatch intermediate value calculated by the calculation module 4 includes the phase offset mismatch intermediate value, and the mismatch estimation result includes the phase offset mismatch estimation result.
[0044] The preprocessing module 2 is used to calculate the first moment of the output signal of the target channel in the case where the preprocessing includes offset sampling; calculate the second moment of the output signal of the target channel in the case where the preprocessing includes gain sampling; and calculate the first moment of the phase offset of the target channel according to the output signal of the target channel and the output signal of the adjacent channel of the target channel in the case where the preprocessing includes phase offset sampling.
[0045] It should be noted that bias sampling may further include calculating the approximate first moment of the output signal of the target channel, gain sampling may further include calculating the approximate second moment of the output signal of the target channel, and phase shift sampling may further include calculating the first moment of the approximate phase shift amount of the output signal of the target channel, calculating the approximate first moment of the phase shift amount of the output signal of the target channel, or calculating the approximate first moment of the approximate phase shift amount of the output signal of the target channel.
[0046] In some embodiments, the calculation module 4 is configured to, when the mismatch estimation result includes a bias mismatch estimation result, obtain the bias mismatch intermediate values of each channel from the storage module 3, calculate the first mean value of the bias mismatch intermediate values of each channel, and calculate the difference between the bias mismatch intermediate value of the target channel in the current processing cycle and the first mean value; when the mismatch estimation result includes a gain mismatch estimation result, obtain the gain mismatch intermediate values of each channel from the storage module 3, calculate the reciprocal of the second mean value of the gain mismatch intermediate values of each channel, and calculate the product of the gain mismatch intermediate value of the target channel in the current processing cycle and the reciprocal; when the mismatch estimation result includes a phase shift mismatch estimation result, obtain the phase shift mismatch intermediate values of each channel from the storage module 3, calculate the third mean value of the phase shift mismatch intermediate values of each channel, and calculate the difference between the phase shift mismatch intermediate value of the target channel in the current processing cycle and the third mean value.
[0047] That is, the bias mismatch estimation result = the bias mismatch intermediate value of the target channel in the current processing cycle - the first mean value of the bias mismatch intermediate values of each channel; wherein, the first mean value of the bias mismatch intermediate values of each channel can be calculated based on the bias mismatch intermediate values of each channel stored in the storage module 3.
[0048] The gain mismatch estimation result = the gain mismatch intermediate value of the target channel in the current processing cycle * 1 / the second mean value of the gain mismatch intermediate values of each channel; wherein, the second mean value of the gain mismatch intermediate values of each channel can be calculated based on the gain mismatch intermediate values of each channel stored in the storage module 3.
[0049] The phase shift mismatch estimation result = the phase shift mismatch intermediate value of the target channel in the current processing cycle - the third mean value of the phase shift mismatch intermediate values of each channel; wherein, the third mean value of the phase shift mismatch intermediate values of each channel can be calculated based on the phase shift mismatch intermediate values of each channel stored in the storage module 3.
[0050] In some embodiments, when the mismatch estimation result includes a bias mismatch result, the calibration module 5 may include an adder, and the adder is used to compensate the DC bias according to the bias mismatch result to calibrate the output signal of the target channel. When the mismatch estimation result includes a gain mismatch result, the calibration module 5 may include a multiplier, and the multiplier is used to compensate the gain bias according to the gain mismatch result to calibrate the output signal of the target channel. When the mismatch estimation result includes a phase offset mismatch estimation result, the calibration module 5 may include a phase delay filter, and the phase delay filter is used to compensate the sampling time bias according to the phase offset mismatch result to calibrate the output signal of the target channel.
[0051] An embodiment of the present disclosure also provides an analog-to-digital converter, including the analog-to-digital converter calibration circuit as described above. The analog-to-digital converter includes, but is not limited to, a high-speed time-interleaved analog-to-digital converter.
[0052] The analog-to-digital converter provided by the embodiment of the present disclosure includes an analog-to-digital converter calibration circuit. The analog-to-digital converter calibration circuit adopts time-division multiplexing logic to sequentially calibrate the output signals of each channel of the analog-to-digital converter. Among them, for the target channel being currently processed, the output signal of the target channel is preprocessed, and the mismatch estimation result is calculated according to the preprocessing result of the target channel and the first mismatch intermediate value of the previous processing cycle of the target channel, and the output signal of the target channel is calibrated according to the mismatch estimation result. Based on the time-division multiplexing logic, the output signals of multiple analog-to-digital converters share the same analog-to-digital converter calibration circuit, which can greatly reduce the area and power consumption overhead of the digital circuit. By preprocessing the output signal of the analog-to-digital converter, the influence on the calibration convergence time and calibration accuracy can be reduced, so as to reduce the area of the digital calibration circuit and lower the power consumption on the premise of ensuring the calibration convergence time and calibration accuracy.
[0053] As Figure 2 shown, in addition to including the analog-to-digital converter calibration circuit 10, the analog-to-digital converter may further include an input buffer 20, a sample-and-hold unit 30, and a multi-time-interleaved channel analog-to-digital conversion unit 40. Among them, there will be bias mismatch, gain mismatch, sampling time mismatch, bandwidth mismatch, etc. between the output signals of each channel of the high-speed time-interleaved analog-to-digital converter, which will all affect the performance of the time-interleaved analog-to-digital converter. Therefore, each channel needs to be calibrated separately.
[0054] An embodiment of the present disclosure also provides an electronic device, and the electronic device includes the analog-to-digital converter as described above.
[0055] The electronic device provided by an embodiment of the present disclosure includes a digital-to-analog converter. The analog-to-digital converter includes an analog-to-digital converter calibration circuit. The analog-to-digital converter calibration circuit uses time-division multiplexing logic to sequentially calibrate the output signals of each channel of the analog-to-digital converter. Among them, for the target channel being currently processed, the output signal of the target channel is preprocessed, and a mismatch estimation result is calculated according to the preprocessing result of the target channel and the first mismatch intermediate value of the previous processing cycle of the target channel. Then, the output signal of the target channel is calibrated according to the mismatch estimation result. Based on the time-division multiplexing logic, the output signals of multiple analog-to-digital converters share the same analog-to-digital converter calibration circuit, which can significantly reduce the area and power consumption overhead of the digital circuit. By preprocessing the output signal of the analog-to-digital converter, the influence on the calibration convergence time and calibration accuracy can be reduced, so as to reduce the area of the digital calibration circuit and lower the power consumption on the premise of ensuring the calibration convergence time and calibration accuracy.
[0056] An embodiment of the present disclosure further provides a method for calibrating an analog-to-digital converter signal. The method is applied to an analog-to-digital converter calibration circuit, as Figure 3 shown. The method for calibrating an analog-to-digital converter signal includes the following steps:
[0057] Step S11: Receive the output signals of each channel of the analog-to-digital converter.
[0058] An analog-to-digital converter calibration circuit is connected to the output ends of each channel of the analog-to-digital converter and receives the output signals of each channel respectively.
[0059] Step S12: Calibrate the output signals of each channel in sequence according to a preset processing cycle. Among them, within one processing cycle, calibrate the output signal of the target channel of the processing cycle, and the target channel is one of each channel.
[0060] All channels of the analog-to-digital converter share one analog-to-digital converter calibration circuit through time-division multiplexing, as Figure 1 shown. The output signals (i.e., sampling signals) of n channels of the analog-to-digital converter are all input to one analog-to-digital converter calibration circuit, that is, n channels of the analog-to-digital converter share one analog-to-digital converter calibration circuit, rather than each channel of the analog-to-digital converter corresponding to one analog-to-digital converter calibration circuit. The analog-to-digital converter calibration circuit calibrates the output signal of one channel within one processing cycle, and the channel to which the output signal calibrated in the current processing cycle belongs is the target channel.
[0061] In some embodiments, the total number of times of calibrating the output signals of each channel according to the preset processing cycle is a preset number of times.
[0062] Among them, calibrating the output signal of the target channel of the processing cycle (i.e., step S12) includes the following steps:
[0063] Step S121, preprocess the output signal of the target channel in the processing period to obtain a preprocessing result.
[0064] Step S122, obtain the first mismatch intermediate value of the target channel, and determine the mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result.
[0065] Step S123, calibrate the output signal of the target channel according to the mismatch estimation result.
[0066] In some embodiments, when the mismatch estimation result includes a bias mismatch result, an adder can be used to compensate the DC bias according to the bias mismatch result to calibrate the output signal of the target channel. When the mismatch estimation result includes a gain mismatch result, a multiplier can be used to compensate the gain bias according to the gain mismatch result to calibrate the output signal of the target channel. When the mismatch estimation result includes a phase offset mismatch estimation result, a phase delay filter can be used to compensate the sampling time bias according to the phase offset mismatch result to calibrate the output signal of the target channel.
[0067] The analog-to-digital converter signal calibration method provided by the embodiments of the present disclosure uses time-division multiplexing logic to sequentially calibrate the output signals of each channel of the analog-to-digital converter. Among them, for the target channel being currently processed, the output signal of the target channel is preprocessed, the mismatch estimation result is calculated according to the preprocessing result of the target channel and the first mismatch intermediate value of the previous processing period of the target channel, and the output signal of the target channel is calibrated according to the mismatch estimation result; the embodiments of the present disclosure are based on time-division multiplexing logic, and the output signals of multiple analog-to-digital converters share the same analog-to-digital converter calibration circuit, which can greatly reduce the area and power consumption overhead of the digital circuit; by preprocessing the output signal of the analog-to-digital converter, the influence on the calibration convergence time and calibration accuracy can be reduced, so as to reduce the area of the digital calibration circuit and reduce the power consumption on the premise of ensuring the calibration convergence time and calibration accuracy.
[0068] In some embodiments, as Figure 4 shown, the determining the mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result (i.e., step S122) includes the following steps:
[0069] Step S1221, determine the second mismatch intermediate value of the processing period of the target channel according to the first mismatch intermediate value and the preprocessing result.
[0070] In some embodiments, the preprocessing includes at least one of the following: bias sampling, gain sampling, phase offset sampling; the first mismatch intermediate value and the second mismatch intermediate value include at least one of the following: bias mismatch intermediate value, gain mismatch intermediate value, phase offset mismatch intermediate value.
[0071] In some embodiments, when the preprocessing includes offset sampling, the first moment of the output signal of the target channel is calculated; when the preprocessing includes gain sampling, the second moment of the output signal of the target channel is calculated; when the preprocessing includes phase shift sampling, the first moment of the phase shift amount of the target channel is calculated based on the output signal of the target channel and the output signals of the adjacent channels of the target channel.
[0072] Step S1222: Determine the mismatch estimation result of the target channel according to the second mismatch median and the first mismatch medians of the other channels.
[0073] In some embodiments, the mismatch estimation result includes at least one of the following: offset mismatch estimation result, gain mismatch estimation result, phase shift mismatch estimation result.
[0074] When the mismatch estimation result includes an offset mismatch estimation result, calculate the first mean of the offset mismatch medians of each channel, and calculate the difference between the offset mismatch median of the processing cycle of the target channel and the first mean; when the mismatch estimation result includes a gain mismatch estimation result, calculate the reciprocal of the second mean of the gain mismatch medians of each channel, and calculate the product of the gain mismatch median of the processing cycle of the target channel and the reciprocal; when the mismatch estimation result includes a phase shift mismatch estimation result, calculate the third mean of the phase shift mismatch medians of each channel, and calculate the difference between the phase shift mismatch median of the processing cycle of the target channel and the third mean.
[0075] To clearly illustrate the solutions of the embodiments of the present disclosure, the following is described with two specific examples.
[0076] Specific Example 1 is specifically described by taking the signal calibration of a 16-channel high-speed time-interleaved analog-to-digital converter as an example. The calibration circuit of the 16-channel high-speed time-interleaved analog-to-digital converter is used to compensate for offset mismatch, gain mismatch, and phase shift mismatch to achieve signal calibration.
[0077] Calibrate the output signals of the 16 channels in sequence according to the preset processing cycle. For each target channel, the steps of signal calibration by the calibration circuit of the 16-channel high-speed time-interleaved analog-to-digital converter include:
[0078] Step 1: Preprocess the output signal of the target channel through a preprocessing module, calculate the first moment and the second moment of the target channel respectively to obtain offset mismatch sampling and gain sampling; and calculate the first moment of the phase shift amount of the target channel based on the output signal of the target channel and the output signals of the adjacent channels of the target channel to obtain phase shift sampling. Store the above preprocessing results in a storage module for subsequent use during calibration.
[0079] Step 2: The control module retrieves the bias mismatch intermediate value, gain mismatch intermediate value, and phase offset mismatch intermediate value of the target channel from the storage module, combines them with the preprocessing results of the bias sampling, gain sampling, and phase offset sampling obtained by the preprocessing module in Step 1, and the calculation module calculates the bias mismatch intermediate value, gain mismatch intermediate value, and phase offset mismatch intermediate value of the current processing cycle, and stores them back in the storage module for data update.
[0080] Step 3: The calculation module calculates the difference between the bias mismatch intermediate value of the current processing cycle of the target channel and the first mean value of the bias mismatch intermediate values of 16 channels to obtain the bias mismatch estimation result; calculates the reciprocal of the second mean value of the gain mismatch intermediate values of 16 channels, and calculates the product of the gain mismatch intermediate value of the current processing cycle of the target channel and the reciprocal to obtain the gain mismatch estimation result; calculates the third mean value of the phase offset mismatch intermediate values of 16 channels, and calculates the difference between the phase offset mismatch intermediate value of the processing cycle of the target channel and the third mean value to obtain the phase offset mismatch estimation result.
[0081] Step 4: The calibration module compensates the DC bias of 16 sub-channels through an adder according to the bias mismatch estimation result, compensates the gain bias of 16 sub-channels through a multiplier according to the gain mismatch estimation result, and compensates the sampling time bias of 16 sub-channels through a phase delay filter according to the phase offset mismatch estimation result, and finally completes the digital calibration of the 16-channel high-speed time-interleaved analog-to-digital converter.
[0082] Specific Example 2 is specifically described by taking the signal calibration of a 64-channel high-speed time-interleaved analog-to-digital converter as an example. The calibration circuit of the 64-channel high-speed time-interleaved analog-to-digital converter is used to compensate for bias mismatch and gain mismatch to achieve signal calibration for a preset number of times.
[0083] The differences between Specific Example 2 and Specific Example 1 are as follows: (1) The number of channels of the high-speed time-interleaved analog-to-digital converter is different. Specifically, in the second embodiment, it is a 64-channel high-speed time-interleaved analog-to-digital converter, and in Specific Example 1, it is a 16-channel high-speed time-interleaved analog-to-digital converter; (2) The preprocessing operations are different. Specifically, in Specific Example 2, bias sampling and gain sampling are performed, but phase offset sampling is not performed; (3) Specific Example 2 performs signal calibration for a preset number of times, while Specific Example 1 performs real-time calibration without limiting the number of calibration times.
[0084] Based on the characteristics of a high-speed time-interleaved analog-to-digital converter (ADC), embodiments of the present disclosure utilize the feature that the mismatch characteristics of each channel of the time-interleaved ADC are similar, only the specific mismatch amounts are different. Combining with the special structure of the high-speed time-interleaved ADC, a time-division multiplexing calculation logic is adopted, multiple channels time-division multiplex a calibration circuit, and the mismatch intermediate value (i.e., the historical mismatch intermediate value) calculated during the previous calibration process is stored. The sampling signal of the high-speed time-interleaved ADC is preprocessed, and the current mismatch estimation result is calculated using the historical mismatch intermediate value and the preprocessing result during the current calibration. This can reduce the area and power consumption of the digital calibration circuit while reducing the impact on the calibration convergence time and calibration accuracy. This benefit will increase as the number of channels increases and will play a greater role in future higher-speed applications.
[0085] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the devices, can be implemented as software, firmware, hardware, and their appropriate combinations. In the hardware implementation, the division between the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be executed by several physical components in cooperation. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or a non-transitory medium) and a communication medium (or a transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory, or other memory technologies, CD-ROM, digital versatile disk (DVD), or other optical disk storage, magnetic cassette, tape, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium generally includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.
[0086] Example embodiments have been disclosed herein, and although specific terms are employed, they are used only and should be interpreted only as general illustrative meanings and not for the purpose of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly specified, features, characteristics, and / or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various forms and details may be changed without departing from the scope of the invention as set forth by the appended claims.
Claims
1. An analog-to-digital converter calibration circuit, characterized in that, Comprising: A control module, configured to send a calibration instruction to a preprocessing module according to a preset processing period, where the calibration instruction is used to indicate a target channel of the current processing period, and the target channel is one of the channels of an analog-to-digital converter; A preprocessing module, configured to receive output signals of each of the channels; According to the calibration instruction, preprocess the output signal of the target channel of the current processing period to obtain a preprocessing result; A storage module, configured to store mismatch intermediate values of each channel of the analog-to-digital converter; A calculation module, configured to obtain a first mismatch intermediate value of the target channel from the storage module, and determine a mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result; A calibration module, configured to calibrate the output signal of the target channel according to the mismatch estimation result.
2. The analog-to-digital converter calibration circuit according to claim 1, wherein The calculation module is configured to determine a second mismatch intermediate value of the target channel in the current processing period according to the first mismatch intermediate value and the preprocessing result; Determine a mismatch estimation result of the target channel according to the second mismatch intermediate value and the mismatch intermediate values of the other channels.
3. The analog-to-digital converter calibration circuit according to claim 2, wherein The storage module is further configured to update the mismatch intermediate value of the target channel according to the second mismatch intermediate value.
4. The analog-to-digital converter calibration circuit according to claim 2, wherein The preprocessing includes at least one of the following: bias sampling, gain sampling, phase offset sampling; The first mismatch intermediate value and the second mismatch intermediate value include at least one of the following: bias mismatch intermediate value, gain mismatch intermediate value, phase offset mismatch intermediate value; The mismatch estimation result includes at least one of the following: bias mismatch estimation result, gain mismatch estimation result, phase offset mismatch estimation result.
5. The analog-to-digital converter calibration circuit according to claim 4, wherein The preprocessing module is configured to calculate a first moment of the output signal of the target channel when the preprocessing includes the bias sampling; calculate a second moment of the output signal of the target channel when the preprocessing includes the gain sampling; When the preprocessing includes the phase offset sampling, calculate a first moment of the phase offset amount of the target channel according to the output signal of the target channel and the output signal of an adjacent channel of the target channel.
6. The analog-to-digital converter calibration circuit according to claim 4, wherein, The calculation module is configured to, when the mismatch estimation result includes the bias mismatch estimation result, obtain the bias mismatch intermediate values of each channel from the storage module, calculate a first mean value of the bias mismatch intermediate values of each channel, and calculate a difference between the bias mismatch intermediate value of the target channel in the current processing period and the first mean value; When the mismatch estimation result includes the gain mismatch estimation result, obtain the gain mismatch intermediate values of each channel from the storage module, calculate a reciprocal of a second mean value of the gain mismatch intermediate values of each channel, and calculate a product of the gain mismatch intermediate value of the target channel in the current processing period and the reciprocal; When the mismatch estimation result includes the phase offset mismatch estimation result, obtain the phase offset mismatch intermediate value of each channel from the storage module, calculate the third mean value of the phase offset mismatch intermediate values of each channel, and calculate the difference between the phase offset mismatch intermediate value of the target channel in the current processing cycle and the third mean value.
7. The analog-to-digital converter calibration circuit according to any one of claims 1-6, characterized in that The control module is configured to send a calibration instruction to the preprocessing module according to a preset number of times.
8. An analog-to-digital converter, characterized in that, It includes the analog-to-digital converter calibration circuit according to any one of claims 1-7.
9. An electronic device, characterized in that, It includes the analog-to-digital converter according to claim 8.
10. A method for calibrating an analog-to-digital converter signal, characterized in that, The method includes: Receiving the output signals of each channel of the analog-to-digital converter, and calibrating the output signals of each channel in sequence according to a preset processing cycle; wherein, within one processing cycle, calibrating the output signal of the target channel of the processing cycle, and the target channel is one of each channel; The calibrating the output signal of the target channel of the processing cycle includes: Performing preprocessing on the output signal of the target channel of the processing cycle to obtain a preprocessing result; Obtaining the first mismatch intermediate value of the target channel, and determining the mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result; Calibrating the output signal of the target channel according to the mismatch estimation result.
11. The method according to claim 10, wherein The determining the mismatch estimation result of the target channel according to the first mismatch intermediate value and the preprocessing result includes: Determining the second mismatch intermediate value of the target channel in the processing cycle according to the first mismatch intermediate value and the preprocessing result; Determining the mismatch estimation result of the target channel according to the second mismatch intermediate value and the first mismatch intermediate values of each other channel.
12. The method according to claim 11, wherein The preprocessing includes at least one of the following: offset sampling, gain sampling, phase offset sampling; The first mismatch intermediate value and the second mismatch intermediate value include at least one of the following: offset mismatch intermediate value, gain mismatch intermediate value, phase offset mismatch intermediate value; The mismatch estimation result includes at least one of the following: offset mismatch estimation result, gain mismatch estimation result, phase offset mismatch estimation result.
13. The method according to claim 12, characterized in that, The performing preprocessing on the output signal of the target channel of the processing cycle to obtain a preprocessing result includes: When the preprocessing includes the offset sampling, calculating the first moment of the output signal of the target channel; When the preprocessing includes the gain sampling, calculating the second moment of the output signal of the target channel; When the preprocessing includes the phase offset sampling, calculating the first moment of the phase offset amount of the target channel according to the output signal of the target channel and the output signal of the adjacent channel of the target channel.
14. The method according to claim 12, wherein The determining the mismatch estimation result of the target channel according to the second mismatch intermediate value and the first mismatch intermediate values of each other channel includes: When the mismatch estimation result includes the offset mismatch estimation result, calculating the first mean value of the offset mismatch intermediate values of each channel, and calculating the difference between the offset mismatch intermediate value of the target channel in the processing cycle and the first mean value; In the case where the mismatch estimation result includes the gain mismatch estimation result, calculate the reciprocal of the second mean value of the gain mismatch intermediate values of each of the channels, and calculate the product of the gain mismatch intermediate value of the processing period of the target channel and the reciprocal; In the case where the mismatch estimation result includes the phase offset mismatch estimation result, calculate the third mean value of the phase offset mismatch intermediate values of each of the channels, and calculate the difference between the phase offset mismatch intermediate value of the processing period of the target channel and the third mean value.
15. The method according to any one of claims 10 to 14, characterized in that, The step of calibrating the output signals of each of the channels in sequence according to a preset processing period includes: The total number of times of calibrating the output signals of each of the channels according to a preset processing period is a preset number of times.