Optimized calibration method for error locking loop in assembly line ADC

Abstract

The invention relates to an optimized calibration method for an error locking loop in a pipeline ADC (Analog to Digital Converter), which comprises the following steps of: arranging a reference circuit outside a main circuit to be calibrated, independently calibrating the reference circuit after offline setting, and selectively sharing input of the calibrated reference circuit and the main circuit; and extracting an error between the output of the reference circuit and the output of the main circuit, enabling the output value of the main circuit to approach the output value of the reference circuit by adjusting the adjusting circuit, and when the reference circuit contains an active device, returning to the first stage for calibration, otherwise, directly repeating the calibration of the second stage. The full scale output range of the ADC does not need to be reduced, the dynamic performance of the ADC can be effectively improved, meanwhile, the ADC can operate at low frequency, it is ensured that power consumption is not remarkably increased in the calibration process, and the ADC is suitable for portable equipment and embedded systems which have strict requirements for power consumption.

Description

Technical Field

[0001] The present invention relates to a technology in the field of analog-to-digital conversion, specifically an optimized calibration method for an error locking loop in a pipelined ADC. Background Art

[0002] When a high-speed ADC operates at high frequencies and high bandwidths, it will face the influence of non-ideal factors such as the gain error, offset error of the amplifier, and the common-mode voltage error of the CDAC. These errors will affect the transfer function of the ADC, resulting in a decrease in accuracy. Traditional calibration methods often require complex digital processing or a long convergence process, increasing the complexity and power consumption of the system design. During the operation of the ADC, changes in external environments such as temperature and supply voltage will introduce additional errors. How to maintain stable conversion accuracy in a dynamic environment is another important challenge in the design. With the increasing requirements for low power consumption in applications such as mobile communication and radio frequency systems, how to maintain a high sampling rate and high accuracy while reducing power consumption has become a difficult problem in the design. Existing digital calibration techniques based on dithering require complex digital processing and a long convergence time, and at the same time, they will also reduce the full-scale input range of the ADC and deteriorate the dynamic performance of the ADC. Summary of the Invention

[0003] In view of the above deficiencies of the prior art, the present invention proposes an optimized calibration method for an error locking loop in a pipelined ADC, which does not require reducing the full-scale output range of the ADC, can effectively improve the dynamic performance of the ADC, and can operate at a low frequency to ensure that the calibration process will not significantly increase power consumption, and is suitable for portable devices and embedded systems with strict power consumption requirements.

[0004] The present invention is realized through the following technical solutions:

[0005] The present invention relates to an optimized calibration method for an error locking loop in a pipelined ADC, including:

[0006] Preparation stage: Set a reference circuit outside the main circuit to be calibrated;

[0007] First stage: Calibrate the reference circuit separately after setting it offline;

[0008] Second stage: After selectively sharing the input of the calibrated reference circuit with the main circuit, extract the error between the output of the reference circuit and the main circuit and make the output value of the main circuit approach the output value of the reference circuit by adjusting the adjustment circuit, where: when the reference circuit contains active devices, return to the first stage for calibration, otherwise directly repeat the calibration in the second stage. Technical Effects

[0009] The present invention realizes error extraction and error correction in the analog domain through the error locking loop technology, and can be used to calibrate the amplifier gain error, amplifier offset error, and CDAC common-mode voltage error in a pipelined ADC. This technology realizes real-time calibration by closely integrating a reference circuit with the main signal path. The reference circuit and the main circuit share the input signal, and the output difference is used to indicate the error of the main circuit. Compared with digital calibration technology, the present invention does not require complex digital processing and does not need to reduce the full-scale input range of the ADC, significantly improving the calibration efficiency. Description of the Drawings

[0010] Figure 1 is a flowchart of the present invention;

[0011] Figure 2 is a schematic diagram of the calibration of the reference circuit and the main circuit calibration principle;

[0012] Figure 3 is a timing diagram of the error locking loop technology of the present invention;

[0013] Figure 4 (a) and (b) are schematic diagrams and timing diagrams of the main circuit error extraction;

[0014] Figure 5 (a) and (b) are schematic diagrams of the main circuit error adjustment principle;

[0015] Figure 6 (a) is a circuit diagram of a dynamic amplifier; Figure 6 (b) is a clock logic diagram in the dynamic amplifier;

[0016] Figure 7 is a circuit diagram of an on-chip integrated input buffer;

[0017] Figure 8 (a) and (b) are SNDR result diagrams of the prototype chip experiment. Detailed Embodiments Embodiment 1

[0018] As Figure 1 and Figure 2 shown, this embodiment relates to a method for calibrating the gain error of an error locking loop in a pipelined ADC as shown in Figure 4 (a). Taking amplifier A0 as the main circuit to be calibrated, calibration is performed by setting a reference circuit including switches and capacitors.

[0019] This embodiment includes the following steps:

[0020] Preparation stage: A first capacitor C1 is set at the input end of amplifier A0, and a switch s1 is set between the amplifier and the first capacitor C1; a second capacitor C2 is set at the output end of the amplifier, and a switch s2 is set between the amplifier and the second capacitor C2; a third capacitor C3 is set between the first capacitor C1 and the second capacitor C2, a switch s3 is set between the first capacitor and the third capacitor, and a switch s4 is set between the second capacitor and the third capacitor to form a reference circuit. The switch s1 and the switch s4 are controlled by the clock clk1, and the switch s2 and the switch s3 are controlled by the clock clk2. The amplifier A0 is the main circuit, and the first to fourth switches s1, s2, s3, s4 and the capacitors C1, C2, C3 are the reference circuit.

[0021] First stage, reference circuit calibration: The first and second clocks clk1 and clk2 are at a low level, the first to fourth switches s1, s2, s3, s4 are disconnected, the reference circuit is disconnected from the amplifier A0, and the capacitors are calibrated. Since the capacitors are passive devices, only one reference circuit calibration stage is required. The switches are active devices and the reference circuit calibration stage needs to be repeated.

[0022] Second stage, main circuit gain error calibration: The first to fourth switches s1, s2, s3, s4 are controlled by the first and second clocks clk1 and clk2 to connect the reference circuit to the amplifier for calibration of the amplifier gain error. During the sampling and switching of the first capacitive digital-to-analog converter CDAC1, the first capacitor C1 is connected to the first capacitive digital-to-analog converter CDAC1, and the second capacitor C2 is connected to the second capacitive digital-to-analog converter CDAC2 during the remaining amplification stage of the pipelined ADC, that is, when the clk_da is at a high level. The first capacitor C1 samples the input of the amplifier with the opposite polarity, and the second capacitor C2 samples the output of the amplifier with the same polarity. The charges on the first and second capacitors C1 and C2 are both shared with the third capacitor C3 to generate an error voltage V GE .

[0023] Taking an amplifier with an ideal gain of 4 as an example, when C1 is equal to 4 times C2, VGE is proportional to (4C2 - A0C2)*V DAIN , where A0 is the gain of the amplifier and V DAIN is the output of the amplifier. Considering that the polarity of V DAIN can be detected by the next-stage sub-ADC, the polarity of the amplifier gain error can be estimated by the polarity of V GE . Embodiment 2

[0024] Compared with Embodiment 1, this embodiment is for the offset error calibration of the main circuit, including the following steps:

[0025] Preparation stage: At the output end of amplifier A0, a fifth capacitor C5 is set, and a switch s7 is set between the amplifier and the fifth capacitor C5; at the input end of amplifier A0, switches s7 and s8 are set, which are respectively connected to the common-mode voltage and the amplifier input voltage. Switches s7 and s8 are controlled by clock clk_os. s7 closes when clk_os is at a high level, and s8 closes when clk_os is at a low level. Using switches s7, s8, and capacitor C5 as the reference circuit.

[0026] First stage, reference circuit calibration: clk_os is at a low level, s7 is disconnected and s8 is closed to disconnect the reference circuit from the amplifier and calibrate the capacitor. Since the capacitor is a passive device, only one reference circuit calibration stage is required. The switch is an active device and needs to repeat the reference circuit calibration stage.

[0027] Second stage, main circuit offset error calibration: Control switches s7 and s8 through clk_os to connect the reference circuit to the amplifier and calibrate the amplifier offset error. During the high-level stage of clk_os, the differential inputs are shorted together, and then the amplifier output when the input is zero is sampled to obtain V OS+ and V OS- to indicate the polarity of the offset error. Embodiment 3

[0028] Compared with Embodiment 1, for the CDAC common-mode error calibration of the main circuit in this embodiment, the following steps are included:

[0029] Preparation stage: At the output end of amplifier A0 or the output end of the input buffer, a fourth capacitor C4 is set, a switch s6 is set between the amplifier or the input buffer and the fourth capacitor C4, and a switch s5 is set between the two fourth capacitors C4. Switch s5 is controlled by clock clk1, and switch s6 is controlled by clock clk2. Using the fifth and sixth switches s5, s6, and capacitor C4 as the reference circuit.

[0030] First stage, reference circuit calibration: The first and second clocks clk1 and clk2 are at a low level, the fifth and sixth switches s5 and s6 are disconnected to disconnect the reference circuit from the amplifier, and the capacitor and the switching comparator are calibrated. Since the capacitor is a passive device, only one reference circuit calibration stage is required. The switch is an active device and needs to repeat the reference circuit calibration stage.

[0031] Second stage, CDAC common-mode error calibration: The fifth and sixth switches s5 and s6 are controlled by the first and second clocks clk1 and clk2 to connect the reference circuit to the amplifier or input buffer for CDAC common-mode error calibration. During the operation of the amplifier or input buffer, C4 is connected to the output terminal to sample the common-mode output of the amplifier or input buffer, which is equal to the common-mode voltage of the CDAC. The sampled output will be compared with the common-mode voltage generated by the reference circuit to obtain the polarity of its offset. During the remaining operation of the amplifier or input buffer, C4 is connected to CDAC2 to sample the common-mode output of the amplifier, which is equal to the common-mode voltage of CDAC2. The sampled output will be compared with the common-mode voltage generated by the reference circuit to obtain the polarity of its offset.

[0032] As Figure 5 shown, it is an error cancellation method for the error locking loop technology. Figure 5 (a) is to determine whether the error is greater than the threshold. Figure 5 (b) is to adjust the adjustment circuit to make the main circuit error approach the reference circuit. The polarities of the amplifier gain error, amplifier offset error, and CDAC common-mode error are detected by a switching comparator and an accumulator thereafter. The detection result of the amplifier gain error is used to adjust I2 in Figure 6 alone or to adjust I1 and I2 in Figure 6 simultaneously to correct the gain error. The detection result of the amplifier offset error is used to adjust I 2+ and I 2- to correct the offset error. The detection result of the CDAC common-mode voltage error is used to adjust V CMDA in the dynamic amplifier, and the common-mode voltage is locked to the reference voltage V CMref . Similar calibration is also applied to the first-stage CDAC of the pipelined ADC, which is achieved by adjusting the bias voltages V Figure 7 of the input buffer in b1 , V b2 , V b3 , V b4 .

[0033] As Figure 8 (a)(b) shown, after specific actual experiments on three 12-bit ADC prototype chips applying the above calibration method, under the specific environmental settings of a temperature of 0 - 80 °C and a voltage change of ±10%, the output spectrum results of each chip can be stable after calibration by the present invention, and the fluctuation of the SNDR does not exceed 2 dB. It can be seen that the calibration method can well cover the influence of PVT on the chip, and the power consumption before and after the calibration method is turned on hardly changes.

[0034] Compared with the prior art, the present invention simplifies the calibration process, reduces the dependence on complex digital processing, and is easy to implement and integrate. The technology mentioned in the present invention does not require reducing the full-scale output range of the ADC, and can effectively improve the dynamic performance of the ADC. At the same time, this technology can operate at a low frequency to ensure that the calibration process does not significantly increase power consumption, making it suitable for portable devices and embedded systems with strict power consumption requirements.

[0035] The above specific embodiments can be locally adjusted in different ways by those skilled in the art without departing from the principles and purposes of the present invention. The protection scope of the present invention is subject to the claims and is not limited by the above specific embodiments. All implementation solutions within its scope are subject to the present invention.

Claims

1. An optimized calibration method for an error locking loop in a pipelined ADC, characterized in that Including: Preparation stage: A reference circuit is set outside the main circuit to be calibrated; First stage: The reference circuit is set offline and calibrated separately; Second stage: After selectively sharing the input of the calibrated reference circuit with the main circuit, the error between the output of the reference circuit and the main circuit is extracted, and the output value of the main circuit is made to approach the output value of the reference circuit by adjusting the adjustment circuit, where: when the reference circuit contains active devices, return to the first stage for calibration, otherwise directly repeat the calibration in the second stage.

2. The optimized calibration method for the error locking loop in the pipelined ADC according to claim 1, characterized in that, When calibrating the gain error of the amplifier in the error-locked loop of the pipelined ADC: Preparation stage: A first capacitor is set at the input end of the amplifier, and a first switch is set between the amplifier and the first capacitor; a second capacitor is set at the output end of the amplifier, and a second switch is set between the amplifier and the second capacitor; a third capacitor is set between the first capacitor and the second capacitor, a third switch is set between the first capacitor and the third capacitor, and a fourth switch is set between the second capacitor and the third capacitor. The first and fourth switches are controlled by the first clock clk1, and the second and third switches are controlled by the second clock clk2; First stage, reference circuit calibration: The first and second clocks clk1 and clk2 are at a low level, the first to fourth switches are disconnected, the reference circuit is disconnected from the amplifier, and the capacitors are calibrated; Second stage, main circuit gain error calibration: Control the first to fourth switches through the first and second clocks clk1 and clk2 to connect the reference circuit to the amplifier. During the sampling and switching of the first capacitive digital-to-analog converter CDAC1, connect the first capacitor to the first capacitive digital-to-analog converter CDAC1, and connect the second capacitor to the second capacitive digital-to-analog converter CDAC2 during the remaining amplification stage of the pipelined ADC, that is, during the high level of clk_da; the first capacitor samples the input of the amplifier with opposite polarity, and the second capacitor samples the output of the amplifier with the same polarity. The charges on the first and second capacitors are both shared with the third capacitor, thereby generating an error voltage V GE .

3. The optimized calibration method for the error locking loop in the pipelined ADC according to claim 1, characterized in that, When calibrating the offset error of the amplifier in the error-locked loop of the pipelined ADC: Preparation stage: A fifth capacitor is set at the output end of the amplifier, and a seventh switch is set between the amplifier and the fifth capacitor; seventh and eighth switches are set at the input end of the amplifier, connected to the common-mode voltage and the amplifier input voltage respectively. The seventh and eighth switches are controlled by the clock clk_os. The seventh switch closes when clk_os is at a high level, and the eighth switch closes when clk_os is at a low level; First stage, reference circuit calibration: clk_os is at a low level, the seventh switch is disconnected and the eighth switch is closed, the reference circuit is disconnected from the amplifier, and the capacitors are calibrated; Second stage, main circuit offset error calibration: Control the seventh and eighth switches through clk_os to connect the reference circuit to the amplifier. During the high level stage of clk_os, the differential inputs are shorted together, and then the output of the amplifier with zero input is sampled to obtain V OS+ and V OS- , so as to indicate the polarity of the offset error.

4. The optimized calibration method for the error locking loop in the pipelined ADC according to claim 1, characterized in that, When calibrating the CDAC common-mode error of the amplifier in the error-locked loop of the pipelined ADC: Preparation stage: A fourth capacitor is set at the output end of the amplifier or the output end of the input buffer, a sixth switch is set between the amplifier or the input buffer and the fourth capacitor, a fifth switch is set between the two fourth capacitors, the fifth switch is controlled by the first clock clk1, and the sixth switch is controlled by the second clock clk2; First stage, reference circuit calibration: The first and second clocks clk1 and clk2 are at a low level, the fifth and sixth switches are disconnected, the reference circuit is disconnected from the amplifier, and the capacitors and the switching comparator are calibrated; Second stage, CDAC common-mode error calibration: The fifth and sixth switches are controlled by the first and second clocks clk1 and clk2 to connect the reference circuit to the amplifier or input buffer. During the operation of the amplifier or input buffer, it is connected to the output terminal to sample the common-mode output of the amplifier or input buffer, which is equal to the common-mode voltage of the CDAC. The sampled output will be compared with the common-mode voltage generated by the reference circuit to obtain the polarity of its offset. During the remaining operation of the amplifier or input buffer, it is connected to CDAC2 to sample the common-mode output of the amplifier, which is equal to the common-mode voltage of CDAC2. The sampled output will be compared with the common-mode voltage generated by the reference circuit to obtain the polarity of its offset.

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