Radio frequency integrated circuit

Abstract

A radio frequency (RF) integrated circuit includes: a plurality of front-end circuits, each front-end circuit connected to an antenna and configured to transmit an RF signal; a bias circuit configured to provide a bias to the power amplifiers of the plurality of front-end circuits; and a bias calibration circuit configured to sense a bias current of the power amplifier due to the bias, and perform a calibration operation on the bias current based on a sensing result.

Description

[0001] This application is based on and claims priority to Korean Patent Application Nos. 10-2024-0002342 and 10-2024-0083585, filed with the Korean Intellectual Property Office on January 5, 2024 and June 26, 2024, respectively, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure generally relates to radio frequency (RF) integrated circuits, and more particularly, to an RF integrated circuit configured to calibrate a bias current or a bias voltage of a power amplifier to support stable operation of the power amplifier included in a plurality of transmission channels. Background Art

[0003] In recent wireless communication schemes, phased array and / or beamforming technologies have been used to support millimeter wave bands of new radio (NR) networks. For phased array and beamforming technologies, RF integrated circuits are designed using high-density and digital-compatible processes (e.g., complementary metal oxide semiconductor (CMOS) processes). In this case, constant gain and power characteristics of a power amplifier of an RF integrated circuit are required to improve the equivalent isotropic radiated power (EIRP) of a phased array antenna in a millimeter wave band.

[0004] To address this need, a bandgap reference (BGR) circuit / proportional to absolute temperature (PTAT) circuit has been incorporated to ensure that a bias current flowing into a power amplifier or a bias voltage supplied to a power amplifier is insensitive to process, voltage, and temperature (PVT) changes. Despite these efforts, as the number of transmission channels of an RF integrated circuit increases, the number of required power amplifiers may increase; due to variations in current path resistance of each power amplifier, local device size mismatches, etc., the actual gains of the power amplifiers may be different from each other; or some power amplifiers may not operate properly, which degrades the overall performance of the RF integrated circuit. Summary of the Invention

[0005] Embodiments of the inventive concept provide an RF integrated circuit that calibrates a bias current or a bias voltage of a power amplifier such that the power amplifier performs stable operation with a constant gain.

[0006] According to an aspect of the inventive concept, an RF integrated circuit includes: a plurality of front-end circuits, each front-end circuit connected to an antenna and configured to transmit an RF signal; a bias circuit configured to provide a bias to a power amplifier of the plurality of front-end circuits; and a bias calibration circuit configured to sense a bias current of the power amplifier caused by the bias and perform a calibration operation on the bias current based on a sensing result.

[0007] According to another aspect of the inventive concept, an RF integrated circuit includes: a first power amplifier configured to amplify a first RF signal based on a first bias; a second power amplifier configured to amplify a second RF signal based on a second bias; a bias circuit configured to supply the first bias to the first power amplifier and the second bias to the second power amplifier; a first current sensor configured to sense a first bias current of the first power amplifier caused by the first bias and a second bias current of the second power amplifier caused by the second bias; and a first comparator configured to compare a first sensing result corresponding to the first bias current with a second sensing result corresponding to the second bias current and output a first comparison result, wherein the bias circuit is further configured to adjust the second bias based on the first comparison result.

[0008] According to another aspect of the inventive concept, an RF integrated circuit includes: a first front-end circuit connected to a first antenna and configured to amplify and transmit a first RF signal; a bias calibration circuit configured to perform a calibration operation on a first bias voltage of a first power amplifier of the front-end circuit, the first power amplifier including at least a first stacked amplification stage and a second stacked amplification stage, wherein the bias calibration circuit includes a first operational amplifier connected to the first stacked amplification stage at a first bias node as part of a feedback loop to maintain the first bias node at the first bias voltage during the calibration operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description in conjunction with the drawings.

[0010] Figure 1A and Figure 1B is a block diagram schematically showing a wireless communication device according to an embodiment.

[0011] Figure 2 is a block diagram showing a radio frequency (RF) integrated circuit according to an embodiment.

[0012] Figure 3 is a flowchart for describing a calibration operation of a bias current of a power amplifier of an RF integrated circuit according to an embodiment.

[0013] Figure 4 is a block diagram for describing a calibration operation of an RF integrated circuit according to an embodiment.

[0014] Figure 5 is a block diagram for describing a calibration operation of an RF integrated circuit according to an embodiment.

[0015] Figure 6 shows Figure 5Detailed block diagram of an RF integrated circuit.

[0016] Figure 7 Is a flowchart for describing the operation of calibrating the first bias current of an RF integrated circuit according to an embodiment.

[0017] Figure 8 Is a block diagram for describing the calibration operation of an RF integrated circuit according to an embodiment.

[0018] Figure 9 Is a block diagram for describing the calibration operation of an RF integrated circuit according to an embodiment.

[0019] Figure 10 Is a flowchart for describing the calibration operation according to the mode of an RF integrated circuit according to an embodiment.

[0020] Figure 11 Is a block diagram showing an RF integrated circuit according to an embodiment.

[0021] Figure 12A And Figure 12B Is for describing according to the selected mode Figure 11 Illustration of the operation of the first current sensor of

[0022] Figure 13 Is a table diagram according to an embodiment for describing the number of transistors deactivated in the low-power mode for each current sensor.

[0023] Figure 14A And Figure 14B Is an illustration for describing the method of determining the number of transistors deactivated in the low-power mode for each current sensor according to an embodiment.

[0024] Figure 15 Is a flowchart for describing the calibration operation of the bias current of the power amplifier of an RF integrated circuit according to an embodiment.

[0025] Figure 16 Is a block diagram for describing the calibration operation of an RF integrated circuit according to an embodiment.

[0026] Figure 17 Is a flowchart for describing the method of determining whether to start the calibration operation of an RF integrated circuit according to an embodiment.

[0027] Figure 18 Is a block diagram for describing the calibration operation of an RF integrated circuit according to an embodiment.

[0028] Figure 19 Is an illustration showing an example implementation of the first power amplifier according to an embodiment.

[0029] Figure 20 is a diagram showing Figure 19 an exemplary embodiment of a bias circuit.

[0030] Figure 21 is a diagram showing an exemplary embodiment of a first power amplifier according to an embodiment.

[0031] Figure 22 is a circuit diagram showing exemplary embodiments of a first power amplifier and a bias circuit according to an embodiment.

[0032] Figure 23 is a block diagram showing a wireless communication device according to an embodiment.

[0033] Figure 24 is a conceptual diagram showing an Internet of Things (IoT) network system to which an embodiment is applied. Detailed Embodiments

[0034] Figure 1A and Figure 1B is a block diagram schematically showing a wireless communication device 1 according to an embodiment. The wireless communication device 1 may use a communication service based on at least one of a plurality of wireless networks. For example, the wireless communication device 1 may use a communication service based on at least one of a third generation (3G) network, a fourth generation (4G) network, a fifth generation (5G) network, a sixth generation (6G) network, and a wireless local area network (WLAN).

[0035] In addition, various functions described below may be implemented or supported by artificial intelligence technology or one or more computer programs, each of the one or more computer programs including computer-readable program code and being implemented in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, instruction sets, processes, functions, objects, classes, instances, associated data, or portions thereof that are suitable for implementing appropriate computer-readable program code. The term "computer-readable program code" includes any type of computer code (including source code, object code, and executable code). The term "computer-readable medium" includes any type of medium that can be accessed by a computer (such as read-only memory (ROM), random access memory (RAM), hard disk drive, compact disc (CD), digital video disc (DVD), or any other type of memory). A "non-transitory" computer-readable medium excludes wired communication links, wireless communication links, optical communication links, or other communication links that transmit transient electrical signals or other signals. A non-transitory computer-readable medium includes a medium in which data can be permanently stored, as well as a medium in which data can be stored and then rewritten (such as a rewritable compact disc or an erasable memory device).

[0036] In the embodiments described below, hardware methods are described as examples. However, since the embodiments include techniques using both hardware and software, the embodiments do not exclude software-based methods.

[0037] Referring to Figure 1A , the wireless communication device 1 may include a front-end module 10, a first antenna 20_1 to an Nth antenna 20_N (where N is an integer greater than or equal to 2), a transceiver 30, a baseband processor 40, and a bias circuit 50. The front-end module 10 may include a first front-end circuit 11_1 to an Nth front-end circuit 11_N and a bias calibration circuit 12A. The front-end module 10 may be referred to as a radio frequency (RF) front-end module, and the first front-end circuit 11_1 to the Nth front-end circuit 11_N may be referred to as RF front-end circuits. The first front-end circuit 11_1 to the Nth front-end circuit 11_N may be connected to the first antenna 20_1 to the Nth antenna 20_N in a one-to-one manner. In some embodiments, the first antenna 20_1 to the Nth antenna 20_N may be included in a phased array antenna and may support a beamforming function. The transceiver 30 may convert a digital signal received from the baseband processor 40 into an analog signal, may perform upconversion on the analog signal, and send the result to the first front-end circuit 11_1 to the Nth front-end circuit 11_N. In addition, the transceiver 30 may perform downconversion on the RF signal received from the first front-end circuit 11_1 to the Nth front-end circuit 11_N to obtain a digital signal, and may send the digital signal to the baseband processor 40.

[0038] The first front-end circuit 11_1 to the Nth front-end circuit 11_N may amplify the RF signal received from the transceiver 30 and may send the result to another wireless communication device or a base station through the first antenna 20_1 to the Nth antenna 20_N. The first front-end circuit 11_1 to the Nth front-end circuit 11_N may include a transmit path (or transmit chain) and a receive path (or receive chain). The following will refer to Figure 3 describe an example embodiment of the first front-end circuit 11_1 to the Nth front-end circuit 11_N.

[0039] The first front-end circuit 11_1 to the Nth front-end circuit 11_N may include a power amplifier (PA) for RF signal amplification. For example, the first front-end circuit 11_1 may include a first power amplifier 11_11.

[0040] The first power amplifier 11_11 may be part of the transmission path (or transmission chain) of the first front-end circuit 11_1, and may amplify the input first RF signal based on the bias (i.e., bias voltage and / or bias current) provided from the bias circuit 50 and the supplied first power supply voltage S*VDD. In this case, in the first power amplifier 11_11, the first bias current I1_BIAS may flow from the node to which the first power supply voltage S*VDD is applied to the ground.

[0041] The above-described example embodiments of the first front-end circuit 11_1 may also be applied to the remaining front-end circuits (i.e., 11_2 to 11_N). Specifically, the second front-end circuit 11_2 to the Nth front-end circuit 11_N may include second to Nth power amplifiers, and the second to Nth bias currents may flow through the second to Nth power amplifiers due to the bias provided from the bias circuit 50. In a specific example, the second bias current may flow through the second power amplifier included in the second front-end circuit 11_2, and the Nth bias current may flow through the Nth power amplifier included in the Nth front-end circuit 11_N.

[0042] In one embodiment, the bias calibration circuit 12A may sense the first bias current I1_BIAS and the second to Nth bias currents, and may perform a calibration operation on the first bias current I1_BIAS and the second to Nth bias currents based on the sensing result. The calibration may be achieved via feedback control-based adjustment of transistors within the power amplifier based on the sensing result. For example, the bias currents of the respective power amplifiers may be calibrated such that the bias currents flowing in all the power amplifiers (within the tolerance range) are equal.

[0043] In one embodiment, the bias calibration circuit 12A may sequentially calibrate the bias currents of the second to Nth power amplifiers in the order close to the first power amplifier 11_11 based on the first power amplifier 11_11 selected by at least one criterion. For example, at least one criterion may be the power amplifier closest to the bias circuit 50 or the power amplifier in which a bias current path with the best characteristics (e.g., characteristics least sensitive to process, voltage, and temperature (PVT) changes) is formed. Hereinafter, specific embodiments will be described based on an example in which the second to Nth power amplifiers are adjacent to the first power amplifier 11_11 in this order.

[0044] In one embodiment, the bias calibration circuit 12A can sense the first bias current I1_BIAS of the first power amplifier 11_11 and the second bias current of a second power amplifier adjacent to the first power amplifier 11_11, compare the first sensed result corresponding to the first bias current I1_BIAS with the second sensed result corresponding to the second bias current, and then calibrate the second bias current based on the comparison result. For example, the bias calibration circuit 12A can calibrate the second bias current such that the second bias current and the first bias current I1_BIAS are approximately different by less than a threshold. In some embodiments, the bias calibration circuit 12A can calibrate the second bias current and can also assist in calibrating the first bias current based on a reference bias current (or referred to as "reference current") applied to the first power amplifier 11_11 as described later.

[0045] Next, the bias calibration circuit 12A can sense the calibrated second bias current of the second power amplifier and the third bias current of a third power amplifier adjacent to the second power amplifier, compare the second sensed result corresponding to the calibrated second bias current with the third sensed result corresponding to the third bias current, and then calibrate the third bias current based on the comparison result. Thus, successive calibration of adjacent power amplifiers can be performed in a "daisy chain calibration" manner, in which the calibration of the next power amplifier in the sequence references the calibrated current in the previously calibrated (and adjacent) power amplifier. For example, the bias calibration circuit 12A can calibrate the third bias current such that the third bias current and the calibrated second bias current or the first bias current I1_BIAS are approximately different by less than a threshold. In some embodiments, the bias calibration circuit 12A can use a current sensor to calibrate the third bias current, and the current sensor measures the second bias current assistingly after the second bias current is calibrated.

[0046] In the above manner, the bias calibration circuit 12A can sequentially calibrate the fourth bias current to the Nth bias current. As a result of the calibration operation of the bias calibration circuit 12A, the second bias current to the Nth bias current can each be approximately different from the first bias current by less than a threshold.

[0047] In some embodiments, the bias calibration circuit 12A can calibrate the first bias current I1_BIAS before a full-scale calibration operation such that the first bias current I1_BIAS of the first power amplifier 11_11, which serves as a reference current for the calibration operations of the remaining power amplifiers, has an optimal value during the operation of the first power amplifier 11_11. For example, (e.g., as in Figure 8 and Figure 9In an embodiment, the bias calibration circuit 12A can sense a reference current from the bias circuit 50 and calibrate the first bias current I1_BIAS based on the reference current.

[0048] In one embodiment, the bias calibration circuit 12A can operate according to a mode selected from a general mode and a low power mode during calibration operations of the first bias current I1_BIAS and the second to Nth bias currents. For example, the bias calibration circuit 12A can perform a calibration operation based on the general mode under conditions not affected by the power state of the wireless communication device 1 (e.g., during a test phase for mass production of an RF integrated circuit including the front-end module 10, the bias circuit 50, and the transceiver 30). Additionally, for example, the bias calibration circuit 12A can perform a calibration operation based on the low power mode under conditions where the power state of the wireless communication device 1 needs to be considered (e.g., during a self-calibration phase after shipment of the RF integrated circuit).

[0049] In one embodiment, in the general mode, the bias calibration circuit 12A can perform a calibration operation by activating all elements for sensing the first bias current I1_BIAS and the second to Nth bias currents. Additionally, in one embodiment, in the low power mode, the bias calibration circuit 12A can perform a calibration operation by activating only a part of the elements for sensing the first bias current I1_BIAS and the second to Nth bias currents. As a result, the distinguishable difference between the bias currents supported by the bias calibration circuit 12A in the general mode can be finer than the distinguishable difference between the bias currents supported by the bias calibration circuit 12A in the low power mode, and specific embodiments thereof will be described below with reference to Figure 10 and Figure 11 describe its specific embodiments.

[0050] Herein, the "operation of the bias calibration circuit 12A" can also be considered as the operation of the wireless communication device 1 or the operation of the RF integrated circuit.

[0051] The bias calibration circuit 12A according to an embodiment can support stable operation of the first power amplifier 11_11 and the second to Nth power amplifiers by "uniformly calibrating" (i.e., equalizing) the first bias current I1_BIAS of the first power amplifier 11_11 of the first front-end circuit 11_1 to the Nth front-end circuit 11_N and the second to Nth bias currents of the second to Nth power amplifiers.

[0052] Further referring to Figure 1B, the first power amplifier 11_11 may include a first amplification stage STG_1 and a second amplification stage STG_2 that are "stacked" on each other. Here, "stacked" does not require a vertical stacking of stages in a multi-layer integrated circuit. Thus, the stacked stages may be provided in the same circuit layer or in different circuit layers. For example, the second amplification stage STG_2 may be stacked on the first amplification stage STG_1, and with this structure, the signal amplified by the first amplification stage STG_1 may be additionally amplified by the second amplification stage STG_2. For example, in the example described below (see Figures 19 to 22 ), the first power amplifier 11_11 has a cascode configuration, in which the output stage is "stacked on" the input stage. The first amplification stage STG_1 and the second amplification stage STG_2 may be connected to each other through a first bias node N1_BIAS.

[0053] In one embodiment, the bias calibration circuit 12B may include a first operational amplifier (OPA) ("op-amp") connected to the first power amplifier 11_11 (e.g., Figure 19 403 in Figure 1B , not shown in

[0054] ), such that the voltage of the first bias node N1_BIAS is maintained at a first target level and is configured to perform a calibration operation in which the voltage is calibrated by forming a specific feedback loop. (The feedback loop including the op-amp may be used to stabilize the voltage to the target level such that the first amplification stage STG_1 operates as a stable amplifier stage.) Here, the voltage of the bias node may be referred to as the bias voltage. Figure 19 In one embodiment, the bias calibration circuit 12B may further include a second operational amplifier connected to the second power amplifier of the second front-end circuit 11_2 to the Nth power amplifier of the Nth front-end circuit 11_N (e.g.,

[0055] 403 in Figure 5 , configured in the same manner within the remaining power amplifiers as in the first power amplifier), such that the voltage of the second bias node of the second power amplifier of the second front-end circuit 11_2 to the voltage of the Nth bias node of the Nth power amplifier of the Nth front-end circuit 11_N is maintained at a first target level and is configured to perform a calibration operation by forming a specific feedback loop.

[0056] In one embodiment, the bias calibration circuit 12B may further include a third operational amplifier (e.g., Figure 20 452 in

[0057] ), and the third operational amplifier operates such that the voltage of the node for connecting the first diode-connected transistor to the bias generator is maintained at a second target level (e.g., the level at the gate of the input-stage transistor TR11 in a cascode configuration).

[0058] In one embodiment, the bias calibration circuit 12B may further include a fourth operational amplifier (e.g., Figure 20 452 in

[0059] ), and the fourth operational amplifier operates such that the voltage of the node for connecting the second diode-connected transistor to the bias generator is maintained at the second target level.

[0060] The bias calibration circuit 12B according to an embodiment can support the stable operation of the first power amplifier 11_11 and the second to Nth power amplifiers by calibrating the first bias voltage of the first power amplifier 11_11 of the first front-end circuit 11_1 to the Nth front-end circuit 11_N and the second to Nth bias voltages of the second to Nth power amplifiers to be approximate to the first target level.

[0061] Here, the operation of the bias calibration circuit 12B can also be considered as the operation of the wireless communication device 1 or the operation of the RF integrated circuit.

[0062] Although the bias calibration circuits 12A and 12B are included in the Figure 1A and Figure 1B front-end module 10 in

[0063] In addition, here, the RF integrated circuit may include an antenna module, a front-end module 10, a transceiver 30, and a bias circuit 50. The antenna module includes a first antenna 20_1 to an Nth antenna 20_N. Optionally, the antennas 20_1 to 20_N are not included in the RF integrated circuit, but instead are included in other structures that are mechanically and electrically connected to the RF integrated circuit. The RF integrated circuit may be implemented as a single chip or may be implemented as including multiple chips.

[0064] Figure 2 is a block diagram showing an RF integrated circuit 100 according to an embodiment. Although in Figure 2 the RF integrated circuit 100 includes four front-end circuits, this is only an example for effectively describing the inventive concept. Therefore, the inventive concept can be applied to an RF integrated circuit 100 including a larger number of front-end circuits. In Figure 2 for clarity of illustration, the bias circuit system and the bias calibration circuit system are omitted, but the bias circuit system and the bias calibration circuit system may be included in the RF integrated circuit 100.

[0065] Referring to Figure 2 , the RF integrated circuit 100 may include a front-end module 110, a first antenna 120_1 to a fourth antenna 120_4, and a transceiver 130. The front-end module 110 may include a first front-end circuit 111_1 to a fourth front-end circuit 111_4, a first separator 112_1 to a third separator 112_3 (shown as "S"), a first combiner 113_1 to a third combiner 113_3 (shown as "C"), a first driver (DRV) 114_1, and a second driver 114_2.

[0066] The first front-end circuit 111_1 may include a first switching element 111_11, a first power amplifier 111_21, a first low-noise amplifier (LNA) 111_31, and first phase shifters 111_71 and 111_81. The first power amplifier 111_21 and the first phase shifter 111_71 may form a first transmission path, and the first low-noise amplifier 111_31 and the first phase shifter 111_81 may form a first reception path. Any one of the first transmission path and the first reception path may be selectively connected to the first antenna 120_1.

[0067] The example embodiment of the first front-end circuit 111_1 can also be applied to the second front-end circuit 111_2 to the fourth front-end circuit 111_4. The second front-end circuit 111_2 may include a second transmission path and a second reception path, and any one of the second transmission path and the second reception path may be selectively connected to the second antenna 120_2. The third front-end circuit 111_3 may include a third transmission path and a third reception path, and any one of the third transmission path and the third reception path may be selectively connected to the third antenna 120_3. In addition, the fourth front-end circuit 111_4 may include a fourth transmission path and a fourth reception path, and any one of the fourth transmission path and the fourth reception path may be selectively connected to the fourth antenna 120_4.

[0068] The first transmission path of the first front-end circuit 111_1 and the second transmission path of the second front-end circuit 111_2 may be connected to the first splitter 112_1, and the third transmission path of the third front-end circuit 111_3 and the fourth transmission path of the fourth front-end circuit 111_4 may be connected to the second splitter 112_2. The first splitter 112_1 and the second splitter 112_2 may be connected to the third splitter 112_3. The third splitter 112_3 may separate the RF signal output from the first driver 114_1, and may provide the separated RF signal to the first splitter 112_1 and the second splitter 112_2. The first splitter 112_1 may further separate the separated RF signal, and may provide the first RF signal to the first transmission path of the first front-end circuit 111_1, and may provide the second RF signal to the second transmission path of the second front-end circuit 111_2. In addition, the second splitter 112_2 may further separate the separated RF signal, and may provide the third RF signal to the third transmission path of the third front-end circuit 111_3, and may provide the fourth RF signal to the fourth transmission path of the fourth front-end circuit 111_4.

[0069] The first receiving path of the first front-end circuit 111_1 and the second receiving path of the second front-end circuit 111_2 can be connected to the first combiner 113_1, and the third receiving path of the third front-end circuit 111_3 and the fourth receiving path of the fourth front-end circuit 111_4 can be connected to the second combiner 113_2. The first combiner 113_1 and the second combiner 113_2 can be connected to the third combiner 113_3. The first combiner 113_1 can combine the first RF signal received from the first receiving path of the first front-end circuit 111_1 with the second RF signal received from the second receiving path of the second front-end circuit 111_2, and can provide the result to the third combiner 113_3. The second combiner 113_2 can combine the third RF signal received from the third receiving path of the third front-end circuit 111_3 with the fourth RF signal received from the fourth receiving path of the fourth front-end circuit 111_4, and can provide the result to the third combiner 113_3. The third combiner 113_3 can combine the RF signals received from the first combiner 113_1 and the second combiner 113_2, and can output the result to the second driver 114_2.

[0070] The RF integrated circuit 100 according to an embodiment can perform a calibration operation on the bias current or bias voltage of power amplifiers “including the first power amplifier 111_21 of the first front-end circuit 111_1 and the second to fourth power amplifiers of the second front-end circuit 111_2 to the fourth front-end circuit 111_4”.

[0071] According to the inventive concept, the amplifier-to-amplifier bias current / bias voltage calibration according to the techniques taught herein can also be applied to various other amplifiers (e.g., low-noise amplifiers including the first low-noise amplifier 111_31) in the RF integrated circuit 100.

[0072] Figure 3 is a flowchart for describing the calibration operation of the bias current of the power amplifier of the RF integrated circuit according to an embodiment.

[0073] Referring to Figure 3 , in operation S100, the RF integrated circuit can start the calibration operation. For example, the RF integrated circuit can start the calibration operation by initializing the variable “K” to “1”.

[0074] In operation S110, the RF integrated circuit can perform a calibration operation on the (K + 1)-th bias current of the (K + 1)-th power amplifier based on the K-th bias current of the K-th power amplifier. For example, the RF integrated circuit can sense the K-th bias current and the (K + 1)-th bias current, can compare the sensing result of the K-th bias current with the sensing result of the (K + 1)-th bias current, and can calibrate the (K + 1)-th bias current based on the comparison result.

[0075] In operation S120, the RF integrated circuit may determine whether "K" has reached "(N - 1)". "N" may have a value corresponding to the total number of "power amplifiers included in the RF integrated circuit and to be calibrated based on the bias current measured by additional power amplifiers". (Note that, as described later, the first power amplifier may also be calibrated based on a reference current).

[0076] When the operation S120 is "No", in operation S130, the RF integrated circuit may increment "K", and then may execute operation S110 again.

[0077] When the operation S120 is "Yes", in operation S140, the RF integrated circuit may complete the calibration operation of the bias current of the power amplifier.

[0078] Figure 4 is a block diagram for describing the calibration operation of the RF integrated circuit 100 according to an embodiment.

[0079] Referring to Figure 4 , the RF integrated circuit 100 may include a first power amplifier 111_21 to a fourth power amplifier 111_24, a first current sensor to third current sensors 140_11, 140_21, and 140_31, a first comparator to third comparators 141_12, 141_22, and 141_32, a control circuit 116, and a bias circuit 150 (an example of the bias circuit 50). Figure 1A The bias calibration circuit 12A (or Figure 1B the bias calibration circuit 12B) of

[0080] A first power supply voltage S*VDD may be provided to the first power amplifier 111_21 to the fourth power amplifier 111_24. "S" may be determined according to the number of stacked amplification stages of the first power amplifier 111_21 to the fourth power amplifier 111_24. For example, when the number of stacked amplification stages is 2, "S" may correspond to "2". A second power supply voltage VDD' may be provided to the bias circuit 150, and may have the same or different voltage as VDD.

[0081] The bias circuit 150 can generate a first bias BIAS_1 and provide the first bias BIAS_1 to the first power amplifier 111_21. (Some examples of ways to describe providing a stable first bias BIAS_1 at a target level are described later.) The bias circuit 150 can generate a second bias BIAS_2 and provide the second bias BIAS_2 to the second power amplifier 111_22, can generate a third bias BIAS_3 and provide the third bias BIAS_3 to the third power amplifier 111_23, and can generate a fourth bias BIAS_4 and provide the fourth bias BIAS_4 to the fourth power amplifier 111_24.

[0082] The first power amplifier 111_21 can perform an amplification operation based on the first bias BIAS_1 and the first power supply voltage S*VDD, and in this case, the first bias current I1_BIAS can flow through the first power amplifier 111_21. The second power amplifier 111_22 can perform an amplification operation based on the second bias BIAS_2 and the first power supply voltage S*VDD, and in this case, the second bias current I2_BIAS can flow through the second power amplifier 111_22. The third power amplifier 111_23 can perform an amplification operation based on the third bias BIAS_3 and the first power supply voltage S*VDD, and in this case, the third bias current I3_BIAS can flow through the third power amplifier 111_23. The fourth power amplifier 111_24 can perform an amplification operation based on the fourth bias BIAS_4 and the first power supply voltage S*VDD, and in this case, the fourth bias current I4_BIAS can flow through the fourth power amplifier 111_24.

[0083] Hereinafter, a calibration operation for the second bias current I2_BIAS will be described.

[0084] In one embodiment, the first current sensor 140_11 and the first comparator 141_12 can be located between the first power amplifier 111_21 and the second power amplifier 111_22. The first current sensor 140_11 can sense the first bias current I1_BIAS of the first power amplifier 111_21 and output a first sensing result SR_1, and can sense the second bias current I2_BIAS of the second power amplifier 111_22 and output a second sensing result SR_2.

[0085] In one embodiment, the first comparator 141_12 may receive the first sensing result SR_1 through the negative input terminal and may receive the second sensing result SR_2 through the positive input terminal, and vice versa. The first comparator 141_12 may output a first comparison result CR_1 based on the difference between the first sensing result SR_1 and the second sensing result SR_2. In a specific example, the first comparator 141_12 may output the first comparison result CR_1 including a plurality of bits indicating how much the second sensing result SR_2 differs from the first sensing result SR_1. The control circuit 116 may generate a control signal CS based on the first comparison result CR_1 and may provide the control signal CS to the bias circuit 150. The bias circuit 150 may adjust the second bias BIAS_2 based on the control signal CS.

[0086] In one embodiment, the control circuit 116 may perform the above operations by using the first current sensor 140_11 and the first comparator 141_12 at least once to control the second bias current I2_BIAS to be approximately the same as the first bias current I1_BIAS with a difference less than a threshold.

[0087] Hereinafter, the calibration operation of the third bias current I3_BIAS will be described.

[0088] In one embodiment, the second current sensor 140_21 and the second comparator 141_22 may be located between the second power amplifier 111_22 and the third power amplifier 111_23. The second current sensor 140_21 may sense the calibrated second bias current I2_BIAS of the second power amplifier 111_22 and may output an auxiliary second sensing result SR_2', and may sense the third bias current I3_BIAS of the third power amplifier 111_23 and may output a third sensing result SR_3.

[0089] In one embodiment, the second comparator 141_22 may receive the auxiliary second sensing result SR_2' through the negative input terminal and may receive the third sensing result SR_3 through the positive input terminal, and vice versa. The second comparator 141_22 may output a second comparison result CR_2 based on the difference between the auxiliary second sensing result SR_2' and the third sensing result SR_3. In a specific example, the second comparator 141_22 may output the second comparison result CR_2 including a plurality of bits indicating how much the third sensing result SR_3 differs from the auxiliary second sensing result SR_2'. The control circuit 116 may generate a control signal CS based on the second comparison result CR_2 and may provide the control signal CS to the bias circuit 150. The bias circuit 150 may adjust the third bias BIAS_3 based on the control signal CS.

[0090] In one embodiment, the control circuit 116 may perform the above operations by using the second current sensor 140_21 and the second comparator 141_22 at least once to control the third bias current I3_BIAS to be approximately the same as the calibrated second bias current I2_BIAS with a difference less than the threshold.

[0091] Hereinafter, the calibration operation of the fourth bias current I4_BIAS will be described.

[0092] In one embodiment, the third current sensor 140_31 and the third comparator 141_32 may be located between the third power amplifier 111_23 and the fourth power amplifier 111_24. The third current sensor 140_31 may sense the calibrated third bias current I3_BIAS of the third power amplifier 111_23 and may output an auxiliary third sensing result SR_3', and may sense the fourth bias current I4_BIAS of the fourth power amplifier 111_24 and may output a fourth sensing result SR_4.

[0093] In one embodiment, the third comparator 141_32 may receive the auxiliary third sensing result SR_3' through the negative input terminal and may receive the fourth sensing result SR_4 through the positive input terminal. The third comparator 141_32 may output a third comparison result CR_3 based on the auxiliary third sensing result SR_3' and the fourth sensing result SR_4. In a specific example, the third comparator 141_32 may output a third comparison result CR_3 including a plurality of bits indicating how much the fourth sensing result SR_4 differs from the auxiliary third sensing result SR_3'. The control circuit 116 may generate a control signal CS based on the third comparison result CR_3 and may provide the control signal CS to the bias circuit 150. The bias circuit 150 may adjust the fourth bias BIAS_4 based on the control signal CS.

[0094] In one embodiment, the control circuit 116 may perform the above operations by using the third current sensor 140_31 and the third comparator 141_32 at least once to control the fourth bias current I4_BIAS to be approximately the same as the calibrated third bias current I3_BIAS with a difference less than the threshold.

[0095] As described above, based on the order close to the first power amplifier 111_21, the second bias current I2_BIAS of the second power amplifier 111_22, the third bias current I3_BIAS of the third power amplifier 111_23, and the fourth bias current I4_BIAS of the fourth power amplifier 111_24 may be sequentially calibrated. In this case, the first power amplifier 111_21 may be closest to the bias circuit 150.

[0096] In one embodiment, the control circuit 116 can select either a general mode or a low power mode, and can perform a calibration operation based on the selected mode. For example, the control circuit 116 can control the first current sensor 140_11 to the third current sensor 140_31 such that the power consumption of the first current sensor 140_11 to the third current sensor 140_31 in the low power mode is less than that in the general mode.

[0097] In some embodiments, the control circuit 116 can select either a first amplification mode or a second amplification mode, and can perform a calibration operation based on the selected mode. For example, in the first amplification mode, the control circuit 116 can control the first current sensor 140_11 to the third current sensor 140_31 to sense the first bias current I1_BIAS to the fourth bias current I4_BIAS and output a sensing result corresponding to a specific multiple of the first bias current I1_BIAS to the fourth bias current I4_BIAS. For example, in the second amplification mode, the control circuit 116 can control the first current sensor 140_11 to the third current sensor 140_31 to sense the first bias current I1_BIAS to the fourth bias current I4_BIAS and output a sensing result corresponding to less than 1 times (i.e., a fraction of) the first bias current I1_BIAS to the fourth bias current I4_BIAS. Here, the first amplification mode can correspond to an example implementation of the general mode, and the second amplification mode can correspond to an example implementation of the low power mode.

[0098] The modes will be described in detail below.

[0099] Figure 5 is a block diagram for describing the calibration operation of the RF integrated circuit 100 according to an embodiment. For ease of explanation, in the Figure 5 description, descriptions that are the same as those made with reference to Figure 4 will be omitted.

[0100] Referring to Figure 5 , the bias circuit 150 can include a bias generator 151 and transistors TR51, TR52, TR53, and TR54. In one embodiment, the transistors TR51 to TR54 can be diode-connected transistors, and the transistors TR52 to TR54 can be either variable transistors or diode-connected transistors. Here, the variable transistor can include a circuit for adjusting the width (or length) of the channel. Specific example implementations will be described with reference to Figure 6 the specific implementation examples.

[0101] The first power amplifier 111_21 may include a transistor TR11, the second power amplifier 111_22 may include a transistor TR21, the third power amplifier 111_23 may include a transistor TR31, and the fourth power amplifier 111_24 may include a transistor TR41.

[0102] The bias generator 151 may include at least one of a BGR circuit and a PTAT circuit, and may output a reference current to each of the transistors TR51 to TR54.

[0103] The first power amplifier 111_21 may receive a first bias through a current mirror including transistors TR11 and TR51. Specifically, the reference current output from the bias generator 151 may be copied at a ratio determined by the characteristics of the transistor TR51 and the characteristics of the transistor TR11, such that a first bias current I1_BIAS flows through the first power amplifier 111_21. For example, the ratio for copying the reference current may be determined based on the ratio of the width to the length of the channel of the transistor TR11 and the ratio of the width to the length of the channel of the transistor TR51. For example, as shown, the first bias may be provided to the gate terminal ("gate") of the transistor TR11 through the drain-gate connection of the transistor TR51.

[0104] The second power amplifier 111_22 may receive a second bias through a current mirror including transistors TR21 and TR52. Specifically, the reference current output from the bias generator 151 may be copied at a ratio determined by the characteristics of the transistor TR52 and the characteristics of the transistor TR21, such that a second bias current I2_BIAS flows through the second power amplifier 111_22. For example, the second bias may be provided to the gate of the transistor TR21 through the gate of the transistor TR52. In addition, the control circuit 116 may generate a first control signal CS_1 for adjusting the width or length of the channel of the transistor TR52 based on the first comparison result CR_1, and may provide the first control signal CS_1 to the transistor TR52. As described regarding Figure 6 the above, such channel width / length adjustment may be achieved by selectively switching a plurality of sub-transistors TR52 in parallel into / out of the circuit. Alternatively, a control signal is applied to the body region of a single transistor TR52 for width / length adjustment. As a result, in either case, the ratio between the transistor TR52 and the transistor TR21 (e.g., the ratio of the width or length of the channel of the transistor TR52 to the width or length of the channel of the transistor TR21) may be changed, and thus the second bias current I2_BIAS may be calibrated (e.g., adjusted to be equal to the first bias current I1_BIAS).

[0105] The third power amplifier 111_23 can receive a third bias through a current mirror including transistors TR31 and TR53. Specifically, a reference current output from the bias generator 151 can be copied at a ratio determined by the characteristics of transistor TR53 and the characteristics of transistor TR31, such that a third bias current I3_BIAS flows through the third power amplifier 111_23. For example, the third bias can be provided to the gate terminal of transistor TR31 through the gate terminal of transistor TR53. In addition, the control circuit 116 can generate a second control signal CS_2 for adjusting the width or length of the channel of transistor TR53 based on the second comparison result CR_2, and can provide the second control signal CS_2 to transistor TR53. As a result, the ratio between transistor TR53 and transistor TR31 (e.g., the ratio of the width or length of the channel of transistor TR53 to the width or length of the channel of transistor TR31) can be changed, and thus the third bias current I3_BIAS can be calibrated.

[0106] The fourth power amplifier 111_24 can receive a fourth bias through a current mirror including transistors TR41 and TR54. Specifically, a reference current output from the bias generator 151 can be copied at a ratio determined by the characteristics of transistor TR54 and the characteristics of transistor TR41, such that a fourth bias current I4_BIAS flows through the fourth power amplifier 111_24. For example, the fourth bias can be provided to the gate terminal of transistor TR41 through the gate terminal of transistor TR54. In addition, the control circuit 116 can generate a third control signal CS_3 for adjusting the width or length of the channel of transistor TR54 based on the third comparison result CR_3, and can provide the third control signal CS_3 to transistor TR54. As a result, the ratio between transistor TR54 and transistor TR41 (e.g., the ratio of the width or length of the channel of transistor TR54 to the width or length of the channel of transistor TR41) can be changed, and thus the fourth bias current I4_BIAS can be calibrated.

[0107] Here, the transistor schematically shown with a source terminal arrow pointing away from the gate terminal is an n-type metal oxide semiconductor (NMOS) transistor, and the transistor with a source terminal arrow pointing to the gate terminal is a p-type metal oxide semiconductor (PMOS) transistor. Although Figure 5 the transistors in

[0108] Figure 6 are shown as NMOS transistors (e.g., TR11 to TR41 and TR51 to TR54), this is only an example, and the inventive concept is not limited thereto. In other embodiments, the transistors (e.g., TR11 to TR41 and TR51 to TR54) can be PMOS or other types of transistors.

[0108] Figure 6 shownFigure 5 Detailed block diagram of an exemplary schematic diagram of the RF integrated circuit 100. For ease of explanation, in the Figure 6 description, descriptions that are the same as those made with reference to Figure 4 and Figure 5 will be omitted. In Figure 6 , an RF integration 100 including a configuration for calibrating the second bias current I2_BIAS of the second power amplifier 111_22 is shown, and it will be understood that the embodiments described below can be applied to configurations for calibrating other bias currents.

[0109] Referring to Figure 6 , the first power amplifier 111_21 may include a transistor TR11, a transistor TR12, and a first amplification stage 111_211. The second power amplifier 111_22 may include a transistor TR21, a transistor TR22, and a second amplification stage 111_221. The first current sensor 140_11 may include a transistor TR61 and a transistor TR62.

[0110] In one embodiment, the first current sensor 140_11 may sense the first bias current I1_BIAS through a current mirror including the transistor TR12 and the transistor TR61. Specifically, the first bias current I1_BIAS may be replicated at a ratio determined by the characteristics of the transistor TR12 and the characteristics of the transistor TR61, and a first sensing result may be output. In addition, the second bias current I2_BIAS may be replicated at a ratio determined by the characteristics of the transistor TR22 and the characteristics of the transistor TR62, and a second sensing result may be output. Thus, the first current sensor 140_11 may provide a first sensing result corresponding to the first bias current I1_BIAS and a second sensing result corresponding to the second bias current I2_BIAS to the first comparator 141_12.

[0111] In one embodiment, in the first power amplifier 111_21, the first amplification stage 111_211 and the transistor TR11 operating as an amplification stage may (e.g., in a cascode configuration such as Figure 19 ) constitute amplification stages stacked on each other, and in the second power amplifier 111_22, the second amplification stage 111_221 and the transistor TR21 operating as an amplification stage may (e.g., in a cascode configuration) constitute amplification stages stacked on each other.

[0112] In one embodiment, the first current sensor 140_11 may be connected to a node N_C1 between the node to which the first power amplifier 111_21 is applied with the first power supply voltage 2*VDD and the first amplification stage 111_211 to sense the first bias current I1_BIAS. In addition, the first current sensor 140_11 may be connected to a node N_C2 between the node to which the second power amplifier 111_22 is applied with the first power supply voltage 2*VDD and the second amplification stage 111_221 to sense the second bias current I2_BIAS. That is, the first current sensor 140_11 may be positioned closer to the nodes to which the first power amplifier 111_21 and the second power amplifier 111_22 are applied with the first power supply voltage 2*VDD than the ground nodes of the first power amplifier 111_21 and the second power amplifier 111_22. This may be an arrangement considering the stable operation and effective calibration operation of the first power amplifier 111_21 and the second power amplifier 111_22.

[0113] In one embodiment, the control circuit 116 may generate the 11th control signal CS_11 to the 1Mth control signal CS_1M based on the first comparison result CR_1. The 11th control signal CS_11 to the 1Mth control signal CS_1M are signals included in Figure 5 the first control signal CS_1 and may be referred to as switch control signals.

[0114] In one embodiment, the transistor TR52 may include transistors TR52_1 to TR52_M and switching elements SW_11 to SW_1M (where M is an integer of two or greater).

[0115] The drain terminals of the transistors TR52_1 to TR52_M may be connected to the node to which the reference current is applied, the source terminals of the transistors TR52_1 to TR52_M may be grounded, and the gate terminals of the transistors TR52_1 to TR52_M may be connected to the switching elements SW_11 to SW_1M in a one-to-one manner.

[0116] The switching elements SW_11 to SW_1M may be turned on / off based on the control signals CS_11 to CS_1M received from the control circuit 116. That is, the control circuit 116 may calibrate the second bias current I2_BIAS by adjusting the number of activated transistors (or the number of transistors connected to the transistor TR21) among the transistors TR52_1 to TR52_M based on the first comparison result CR_1.

[0117] Although some transistors (e.g., TR12, TR61, TR62, and TR22) are Figure 6is shown as a PMOS transistor in, but this is only an example, and the inventive concept is not limited thereto, and some transistors (e.g., TR12, TR61, TR62, and TR22) may alternatively be NMOS transistors or other types of transistors.

[0118] In addition, transistors TR61 and TR62 of the first current sensor 140_11 may be variable transistors that can be operated based on a mode selected from a general mode and a low power mode. The following will refer to Figure 11 and Figures 12A to 12B to describe specific embodiments of transistors TR61 and transistor TR62 of the first current sensor 140_11.

[0119] Figure 7 is a flowchart for describing the operation of calibrating the first bias current of a calibration RF integrated circuit according to an embodiment. Figure 7 Operations S101 and S102 of may be included in Figure 3 operation S100 of.

[0120] Referring to Figure 7 , in operation S101, the RF integrated circuit may sense a reference current from a bias circuit and may generate a reference sensing result.

[0121] In operation S102, the RF integrated circuit may perform a calibration operation on the first bias current of the first power amplifier based on the reference sensing result.

[0122] The RF integrated circuit according to an embodiment may calibrate the first bias current such that the first bias current has an optimal value for the operation of the first power amplifier, and the first bias current is a reference for the calibration operation of the second bias current of the second power amplifier to the Kth bias current of the Kth power amplifier (where K is an integer greater than or equal to 2, e.g., in Figure 5 , K = 4).

[0123] Figure 8 is a block diagram for describing the calibration operation of the RF integrated circuit 100' according to an embodiment. For ease of explanation, in the description of Figure 8 , descriptions that are the same as those described with reference to Figure 4 will be omitted.

[0124] Referring to Figure 8 , the RF integrated circuit 100' may include first power amplifiers 111_21 to 111_24, first current sensors 140_11 to 140_31, first comparators 141_12 to 141_32, a control circuit 116', a bias circuit 150', a reference current sensor 111_41, and a reference comparator 141_42.

[0125] In one embodiment, the control circuit 116' may prepare for a full-scale calibration operation by first calibrating the first bias current I1_BIAS before sequentially calibrating the second bias current I2_BIAS to the fourth bias current I4_BIAS.

[0126] In one embodiment, the reference current sensor 111_41 and the reference comparator 141_42 may be located between the bias circuit 150' and the first power amplifier 111_21. The reference current sensor 111_41 may sense the reference current of the bias circuit 150' and may output a reference sensing result SR_REF, and may sense the first bias current I1_BIAS of the first power amplifier 111_21 and may output a first sensing result SR_1.

[0127] In one embodiment, the reference comparator 141_42 may receive the reference sensing result SR_REF through the negative input terminal, and may receive the first sensing result SR_1 through the positive input terminal. The reference comparator 141_42 may output a reference comparison result CR_REF based on the difference between the reference sensing result SR_REF and the first sensing result SR_1. In a specific example, the reference comparator 141_42 may output a reference comparison result CR_REF including multiple bits indicating how much the first sensing result SR_1 differs from the reference sensing result SR_REF. The control circuit 116' may generate a control signal CS based on the reference comparison result CR_REF, and may provide the control signal CS to the bias circuit 150'. The bias circuit 150' may adjust the first bias BIAS_1 based on the control signal CS.

[0128] In one embodiment, the control circuit 116' may perform the above operations by using the reference current sensor 111_41 and the reference comparator 141_42 at least once to control the first bias current I1_BIAS to be approximately equal to the reference current with a difference less than a threshold.

[0129] The calibrated first bias current I1_BIAS may be sensed by the first current sensor 140_11, and may be output as an auxiliary first sensing result SR_1', and the auxiliary first sensing result SR_1' may be used to calibrate the second bias current I2_BIAS.

[0130] Figure 9 is a block diagram for describing the calibration operation of the RF integrated circuit 100' according to an embodiment. For ease of explanation, in Figure 9 the description of, the descriptions identical to those referring to Figure 5 and Figure 8 will be omitted.

[0131] Referring to Figure 9, the bias circuit 150' may include a bias generator 151, a transistor TR51', and transistors TR52 to TR54. The transistor TR51' and the transistors TR52 to TR54 may be diode-connected transistors, and the transistor TR51' and the transistors TR52 to TR54 may be either diode-connected transistors or variable transistors.

[0132] The first power amplifier 111_21 may receive a first bias through a current mirror including transistors TR11 and TR51'. The reference current sensor 111_41 may sense a reference current output from the bias generator 151 through a node connected to the drain terminal of the transistor TR51', and may output a reference sensing result SR_REF. In addition, the reference current sensor 111_41 may sense a first bias current I1_BIAS of the first power amplifier 111_21, and may output a first sensing result SR_1. The reference comparator 141_42 may compare the reference sensing result SR_REF with the first sensing result SR_1, and may output a reference comparison result CR_REF.

[0133] The control circuit 116' may generate a reference control signal CS_REF for adjusting the width or length of the channel of the transistor TR51' based on the reference comparison result CR_REF, and may provide the reference control signal CS_REF to the transistor TR51'. As a result, the ratio between the transistor TR51' and the transistor TR11 (e.g., the ratio between the width or length of the channel of the transistor TR51' and the width or length of the channel of the transistor TR11) may be changed, and thus, the first bias current I1_BIAS may be calibrated.

[0134] Figure 10 is a flowchart for describing a calibration operation according to the mode of an RF integrated circuit according to an embodiment.

[0135] Referring to Figure 10 , in operation S200, the RF integrated circuit may select either a general mode or a low power mode. For example, in a test phase for mass production of the RF integrated circuit or mass production of a wireless communication device including the RF integrated circuit, the RF integrated circuit may be set to select the general mode. In addition, in a self-calibration phase after shipment of the RF integrated circuit or the wireless communication device including the RF integrated circuit, the RF integrated circuit may be set to select the low power mode. In some embodiments, the RF integrated circuit may adaptively select either the general mode or the low power mode based on the power state of the wireless communication device.

[0136] In operation S210, the RF integrated circuit may perform a calibration operation on the bias currents of multiple power amplifiers based on the selected mode. For example, when the general mode is selected, the RF integrated circuit may control the current sensor such that the sensing performance for the bias currents of the multiple power amplifiers is maximized, and then the RF integrated circuit may perform the calibration operation. In addition, when the low power mode is selected, the RF integrated circuit may control the current sensor such that the sensing performance for the bias currents of the multiple power amplifiers is limited to a preset amount, and then the RF integrated circuit may perform the calibration operation.

[0137] Figure 11 is a block diagram showing the RF integrated circuit 100'' according to an embodiment. In Figure 11 which, an RF integrated circuit 100'' including a configuration for calibrating the second bias current I2_BIAS of the second power amplifier 111_22 is shown, and it will be understood that the embodiments described below can be applied to configurations for calibrating other bias currents. In addition, for ease of explanation, in Figure 11 the description of, descriptions identical to those made with reference to Figure 6 will be omitted.

[0138] Referring to Figure 11 , the RF integrated circuit 100'' may include a first power amplifier 111_21, a second power amplifier 111_22, a first current sensor 140_11', a first comparator 141_12, and a control circuit 116''.

[0139] In one embodiment, the first current sensor 140_11' may include transistors TR61_1 to TR61_L (where L is an integer of two or greater), switching elements SW_21 to SW_2L, transistors TR62_1 to TR62_L, and switching elements SW_31 to SW_3L. The transistors TR61_1 to TR61_L and the switching elements SW_21 to SW_2L may be configured to sense the first bias current of the first power amplifier 111_21, and the transistors TR62_1 to TR62_L and the switching elements SW_31 to SW_3L may be configured to sense the second bias current of the second power amplifier 111_22. In one embodiment, the transistors TR61_1 to TR61_L may be connected in parallel, and the transistors TR62_1 to TR62_L may be connected in parallel.

[0140] The source terminals of the transistors TR61_1 to TR61_L may be connected to a node to which the first power supply voltage 2*VDD is applied, the drain terminals of the transistors TR61_1 to TR61_L may be connected to the negative input terminal of the first comparator 141_12, and the gate terminals of the transistors TR61_1 to TR61_L may be connected to the switching elements SW_21 to SW_2L in a one-to-one manner.

[0141] The source terminals of transistors TR62_1 to TR62_L can be connected to a node to which a first power supply voltage 2*VDD is applied, the drain terminals of transistors TR62_1 to TR62_L can be connected to the positive input terminal of the first comparator 141_12, and the gate terminals of transistors TR62_1 to TR62_L can be connected to switching elements SW_31 to SW_3L in a one-to-one manner.

[0142] The control circuit 116'' can generate a first mode control signal MCS_1 and a second mode control signal MCS_2 based on a mode selected from a general mode and a low power mode. The first mode control signal MCS_1 can include mode control signals MCS_11 to MCS_1L, and the second mode control signal MCS_2 can include mode control signals MCS_21 to MCS_2L. The mode control signals MCS_11 to MCS_1L and the mode control signals MCS_21 to MCS_2L can also be referred to as mode switching control signals.

[0143] The switching elements SW_21 to SW_2L can be turned on / off based on the mode control signals MCS_11 to MCS_1L received from the control circuit 116''. That is, the control circuit 116'' can adjust the number of activated transistors among transistors TR61_1 to TR61_L (or the number of transistors connected to transistor TR12) based on the selected mode.

[0144] In one embodiment, the switching elements SW_31 to SW_3L can be turned on / off based on the mode control signals MCS_21 to MCS_2L received from the control circuit 116''. That is, the control circuit 116'' can adjust the number of activated transistors among transistors TR62_1 to TR62_L (or the number of transistors connected to transistor TR22) based on the selected mode.

[0145] In the low power mode, the number of activated transistors among the transistors (e.g., TR61_1 to TR61_L and TR62_1 to TR62_L) of the first current sensor 140_11' can be less than the number of activated transistors among the transistors (e.g., TR61_1 to TR61_L and TR62_1 to TR62_L) of the first current sensor 140_11' in the general mode.

[0146] In one embodiment, the number of activated transistors according to the selected mode can be preset, and specific embodiments thereof will be described with reference to Figure 12A and Figure 12B its specific embodiments will be described.

[0147] Figure 12AAnd Figure 12B is a diagram for describing the operation of the first current sensor 140_11' according to a selected mode. Figure 11

[0148] Referring to Figure 12A , the first current sensor 140_11' can perform a calibration operation based on a general mode. The switching elements SW_21 to SW_2L can be turned on in response to the mode control signals MCS_11A to MCS_1LA received from the control circuit 116'' (see Figure 11 ). Therefore, in order to sense the first bias current of the first power amplifier 111_21 (see Figure 11 ), all the transistors TR61_1 to TR61_L can be used. In addition, the switching elements SW_31 to SW_3L can be turned on in response to the mode control signals MCS_21A to MCS_2LA received from the control circuit 116'' (see Figure 11 ). Therefore, in order to sense the second bias current of the second power amplifier 111_22 (see Figure 11 ), all the transistors TR62_1 to TR62_L can be used.

[0149] In some embodiments, the lengths or widths of the channels of the transistors TR61_1 to TR61_L and the transistors TR62_1 to TR62_L can be designed such that the first bias current is sensed and a first sensing result corresponding to a specific multiple of the first bias current is output, and the second bias current is sensed and a large second sensing result corresponding to a specific multiple of the second bias current is output. In this case, the general mode can be referred to as an amplification mode.

[0150] Further referring to Figure 12B , the first current sensor 140_11' can perform a calibration operation based on a low-power mode. In response to the mode control signals MCS_11B to MCS_1LB received from the control circuit 116'' (see Figure 11 ), only the switching element SW_21 among the switching elements SW_21 to SW_2L can be turned on. Therefore, in order to sense the first bias current of the first power amplifier 111_21 (see Figure 11 ), only the transistor TR61_1 can be used. In addition, in response to the mode control signals MCS_21B to MCS_2LB received from the control circuit 116'' (see Figure 11 ), only the switching element SW_31 among the switching elements SW_31 to SW_3L can be turned on. Therefore, in order to sense the second bias current of the second power amplifier 111_22 (see Figure 11 ), only the transistor TR62_1 can be used.

[0151] However, this is only an example, and the inventive concept is not limited thereto. In the low power mode, a larger number of transistors can be preset to sense the first bias current of the first power amplifier 111_21 (see Figure 11 ) and the second bias current of the second power amplifier 111_22 (see Figure 11 ). In addition, the low power mode can be further subdivided and can be adaptively operated according to the power state of the wireless communication device.

[0152] Figure 13 is a table graph according to an embodiment for describing the number of transistors deactivated in the low power mode for each current sensor.

[0153] Referring to Figure 13 's first table graph TB1, in the first current sensor #1 to the third current sensor #3, the same number ("X1") of transistors can be deactivated in the low power mode.

[0154] For better understanding, further referring to Figure 4 , the first current sensor 140_11 (#1) to the third current sensor 140_31 (#3) can include the same number of transistors to sense the first bias current of the first power amplifier 111_21 to the fourth bias current of the fourth power amplifier 111_24, and the number of transistors deactivated in the low power mode can be "X1", and can be the same in all the first current sensor 140_11 (#1) to the third current sensor 140_31 (#3).

[0155] Figure 14A And Figure 14B are diagrams for describing the method according to an embodiment for determining the number of transistors deactivated in the low power mode for each current sensor.

[0156] Referring to Figure 14A , in operation S300, the characteristics of the bias current paths of multiple power amplifiers of the RF integrated circuit can be identified.

[0157] In operation S310, the number of transistors deactivated in the low power mode can be set for each current sensor based on the identification result.

[0158] In one embodiment, because when the characteristics of the bias current path through which the bias current of any power amplifier to be calibrated flows are poor, accurate current sensing is required for effective calibration, the number of transistors deactivated in the low power mode of the current sensor sensing the bias current of any power amplifier can be less than the general number.

[0159] Referring to Figure 14BFor the second table graph TB2, among the first current sensor #1 and the second current sensor #2, "X1" transistors can be deactivated in the low power mode, and among the third current sensor #3, "X2" transistors can be deactivated in the low power mode.

[0160] For better understanding, further refer to Figure 4 , when the characteristics of the bias current path of the fourth power amplifier 111_24 are worse than those of the bias current paths of the first power amplifier 111_21 to the third power amplifier 111_23, calibration needs to be performed by accurately sensing the fourth bias current I4_BIAS of the fourth power amplifier 111_24. Therefore, the number (X2) of transistors deactivated in the low power mode in the third current sensor 140_31 (#3) for sensing the fourth bias current I4_BIAS of the fourth power amplifier 111_24 can be less than the number (X1) of transistors deactivated in the low power mode in the first current sensor 140_11 (#1) and the second current sensor 140_21 (#2).

[0161] However, this is only an example, and the number of transistors deactivated in the low power mode for each current sensor can be set in various ways.

[0162] Figure 15 is a flowchart for describing the calibration operation of the bias current of the power amplifier of the RF integrated circuit according to an embodiment.

[0163] Refer to Figure 15 , in operation S400, the RF integrated circuit can sense the bias currents of multiple power amplifiers and generate a sensing result.

[0164] In operation S410, the RF integrated circuit can generate the average value of the sensing results.

[0165] In operation S420, the RF integrated circuit can perform a calibration operation on the bias currents of multiple power amplifiers based on the average value.

[0166] Figure 16 is a block diagram for describing the calibration operation of the RF integrated circuit 200 according to an embodiment. For ease of explanation, in the Figure 16 description, the description identical to that in reference to Figure 4 will be omitted.

[0167] Refer to Figure 16, the RF integrated circuit 200 may include a first power amplifier 211_21 to a fourth power amplifier 211_24, a first current sensor 240_11 to a fourth current sensor 240_41, a first comparator 241_12 to a fourth comparator 241_42, a control circuit 216, an average value calculator 217, and a bias circuit 250. Herein, Figure 1A The bias calibration circuit 12A may include a first current sensor 240_11 to a fourth current sensor 240_41, a first comparator 241_12 to a fourth comparator 241_42, a control circuit 216, and an average value calculator 217.

[0168] In one embodiment, the first current sensor 240_11 may sense a first bias current I1_BIAS of the first power amplifier 211_21 and output a first sensing result SR_1, the second current sensor 240_21 may sense a second bias current I2_BIAS of the second power amplifier 211_22 and output a second sensing result SR_2, the third current sensor 240_31 may sense a third bias current I3_BIAS of the third power amplifier 211_23 and output a third sensing result SR_3, and the fourth current sensor 240_41 may sense a fourth bias current I4_BIAS of the fourth power amplifier 211_24 and output a fourth sensing result SR_4.

[0169] In one embodiment, the average value calculator 217 may output an average value I_AVG of the first sensing result SR_1 to the fourth sensing result SR_4.

[0170] In one embodiment, the first comparator 241_12 may receive the first sensing result SR_1 through a positive input terminal and receive the average value I_AVG through a negative input terminal. The first comparator 241_12 may output a first comparison result CR_1 including a plurality of bits indicating how much the first sensing result SR_1 differs from the average value I_AVG.

[0171] In one embodiment, the second comparator 241_22 may receive the second sensing result SR_2 through a positive input terminal and receive the average value I_AVG through a negative input terminal. The second comparator 241_22 may output a second comparison result CR_2 including a plurality of bits indicating how much the second sensing result SR_2 differs from the average value I_AVG.

[0172] In one embodiment, the third comparator 241_32 may receive the third sensing result SR_3 through a positive input terminal and may receive the average value I_AVG through a negative input terminal. The third comparator 241_32 may output a third comparison result CR_3 including a plurality of bits indicating how much the third sensing result SR_3 differs from the average value I_AVG.

[0173] In one embodiment, the fourth comparator 241_42 may receive the fourth sensing result SR_4 through a positive input terminal and may receive the average value I_AVG through a negative input terminal. The fourth comparator 241_42 may output a fourth comparison result CR_4 including a plurality of bits indicating how much the fourth sensing result SR_4 differs from the average value I_AVG.

[0174] In one embodiment, the control circuit 216 may generate a control signal CS based on the first comparison result CR_1 to the fourth comparison result CR_4. The bias circuit 250 may adjust the first bias current I1_BIAS to the fourth bias current I4_BIAS based on the control signal CS. Accordingly, the first bias current I1_BIAS to the fourth bias current I4_BIAS may be calibrated to have a difference less than a threshold.

[0175] Figure 17 is a flowchart for describing a method of determining whether to start a calibration operation of an RF integrated circuit according to an embodiment.

[0176] Referring to Figure 17 , in operation S500, the RF integrated circuit may periodically or aperiodically generate a monitoring result for a power amplifier to be monitored.

[0177] In operation S510, the RF integrated circuit may determine whether the monitoring result satisfies a specific condition.

[0178] When the result of operation S510 is "yes", in operation S520, the RF integrated circuit may start a calibration operation of the bias currents of a plurality of power amplifiers.

[0179] When the result of operation S510 is "no", the RF integrated circuit may re-execute operation S500.

[0180] Figure 18 is a block diagram for describing a calibration operation of an RF integrated circuit 300 according to an embodiment.

[0181] Referring to Figure 18, the RF integrated circuit 300 may include a first power amplifier 311_21 to a Yth power amplifier 311_2Y (where Y is an integer greater than or equal to 2), a first current sensor 340_11 to a (Y - 1)th current sensor 340_(Y - 1)1, and a first comparator 341_12 to a (Y - 1)th comparator 341_(Y - 1)2.

[0182] In one embodiment, the (Y - 1)th power amplifier 311_2(Y - 1) and the Yth power amplifier 311_2Y may be set as power amplifiers to be monitored. The (Y - 1)th current sensor 340_(Y - 1)1 may sense the bias current of the (Y - 1)th power amplifier 311_2(Y - 1) and the bias current of the Yth power amplifier 311_2Y, and may output the sensing result to the (Y - 1)th comparator 341_(Y - 1)2. The (Y - 1)th comparator 341_(Y - 1)2 may output the comparison result between the sensing results as the monitoring result.

[0183] In one embodiment, the RF integrated circuit may determine whether to start the calibration operation of the bias currents of the first power amplifier 311_21 to the Yth power amplifier 311_2Y based on the monitoring result. When the monitoring result meets a specific condition (for example, when the monitoring result exceeds a specific reference value), the RF integrated circuit may determine to start the calibration operation.

[0184] Figure 19 is a diagram showing an example of an embodiment of a first power amplifier 400 according to an embodiment.

[0185] Referring to Figure 19 , the first power amplifier 400 may include a first matching network 401, a second matching network 402, a first terminal T1, a second terminal T2, a first operational amplifier 403, transistors TR11 and TR71, a first capacitor C1, and a first resistor R1. Here, Figure 1B the bias calibration circuit 12B may include the first operational amplifier 403.

[0186] In one embodiment, the first power amplifier 400 may include two amplification stages stacked on each other to form a cascode amplifier configuration, where the amplification stages may include a lower transistor TR11 operating as a first stage (input stage) and a transistor TR71 operating as a second stage (output stage). The first power amplifier 400 may receive a first power supply voltage 2*VDD and may perform an amplification operation.

[0187] In one embodiment, a first RF signal RF_IN input from a first terminal T1 may be applied to the gate terminal of a transistor TR11 through a first matching network 401. In addition, a first bias may be applied to the gate terminal of the transistor TR11 through a bias circuit 450. The source terminal of the transistor TR11 may be grounded, and the drain terminal of the transistor TR11 may be connected to a first bias node N1_BIAS.

[0188] In one embodiment, the gate terminal of a transistor TR71 may be connected to one end of a first resistor R1 and one end of a first capacitor C1, the drain terminal of the transistor TR71 may be connected to a second matching network 402, and the source terminal of the transistor TR71 may be connected to the first bias node N1_BIAS. A bias V1_BIAS may be applied to the gate terminal of the transistor TR71 through the other end of the first resistor R1, and the other end of the first capacitor C1 may be grounded.

[0189] In one embodiment, the first RF signal RF_IN amplified by the transistor TR11 and the transistor TR71 may be output as a first RF output signal RF_OUT through the second matching network 402 and a second terminal T2.

[0190] In one embodiment, a first reference voltage V1_REF may be input to the positive input terminal of a first operational amplifier 403, the negative input terminal of the first operational amplifier 403 may be connected to the first bias node N1_BIAS, and the voltage V1 (or the first bias voltage V1) of the first bias node N1_BIAS may be input to the negative input terminal of the first operational amplifier 403. The output terminal of the first operational amplifier 403 may be connected to the gate terminal of the transistor TR71.

[0191] In one embodiment, the first operational amplifier 403 may form a specific feedback loop and may calibrate the first bias voltage V1 such that the first bias voltage V1 is maintained close to the first reference voltage V1_REF. That is, the level of the first reference voltage V1_REF may correspond to the target level of the first bias voltage V1. In a specific example, the first reference voltage V1_REF may correspond to "VDD" and may be 1 / 2 times the first power supply voltage 2*VDD.

[0192] Since the first bias voltage V1 is fixed at "VDD" by the first operational amplifier 403 according to the embodiment, the transistor TR11 may perform a stable operation as an amplification stage. In addition, the source-drain current of each core transistor (transistors TR11 and TR71) may be controlled via a calibration operation so as not to exceed the breakdown voltage.

[0193] The above combination Figures 1A to 18 The described bias current calibration operation may be combinedFigure 19 The bias voltage calibration of Figure 19 is applied. In addition, each of the remaining power amplifiers 111_22 to 111_24 of the RF integrated circuits 100, 100', or 100'' may also include Figure 19 a circuit arrangement of Figure 19 so as to calibrate the bias voltage therein in a similar manner. Moreover, each of the remaining power amplifiers 111_22 to 111_24 may also include the Figures 20 to 22 circuit arrangement described below.

[0194] Figure 20 is a diagram showing Figure 19 an exemplary embodiment of the bias circuit 450 of Figure 19 . For ease of explanation, in the Figure 20 description of Figure 20 , the description identical to that made with reference to Figure 19 will be omitted.

[0195] With further reference to Figure 20 , the bias circuit 450 may include a bias generator 451, a second operational amplifier 452, and a transistor TR51. Here, Figure 1B the bias calibration circuit 12B of Figure 1B may include a first operational amplifier 403 and a second operational amplifier 452.

[0196] In one embodiment, the bias generator 451 may generate a reference current based on the supplied second power supply voltage VDD', and may be connected to the drain terminal of the transistor TR51 through a second bias node N2_BIAS.

[0197] In one embodiment, a first reference voltage V1_REF may be input to the negative input terminal of the second operational amplifier 452, the positive input terminal of the second operational amplifier 452 may be connected to the second bias node N2_BIAS, and the voltage V2 (or "second bias voltage V2") of the second bias node N2_BIAS may be input to the positive input terminal of the second operational amplifier 452.

[0198] In one embodiment, the second operational amplifier 452 may form a specific feedback loop, and may calibrate the second bias voltage V2 such that the second bias voltage V2 is maintained close to the first reference voltage V1_REF. That is, the level of the first reference voltage V1_REF may correspond to the target level of the second bias voltage V2. In a specific example, the first reference voltage V1_REF may correspond to "VDD" and may have a level lower than the second power supply voltage VDD'.

[0199] Since, according to an embodiment, the second bias voltage V2 is fixed as "VDD" by the second operational amplifier 452, the transistor TR51 can perform stable current mirroring. In addition, the source-drain current of each core transistor (transistors TR11 and TR71) can be controlled via a calibration operation so as not to exceed the breakdown voltage.

[0200] Figure 21 FIG. 4 is a diagram illustrating an exemplary embodiment of a first power amplifier 400' according to an embodiment. For ease of explanation, in the Figure 21 description, descriptions identical to those made with reference to Figure 20 will be omitted.

[0201] Referring to Figure 21 , the first power amplifier 400' may include a first matching network 401, a second matching network 402, a first terminal T1, a second terminal T2, a first operational amplifier 403, a third operational amplifier 404, transistors TR11, TR71, TR81, a first capacitor C1, a first resistor R1, a second capacitor C2, and a second resistor R2. Here, Figure 1B the bias calibration circuit 12B of

[0202] In one embodiment, the first power amplifier 400' may include three amplification stages stacked on one another, and the amplification stages may include transistors TR11, TR71, and TR81. The first power amplifier 400' may receive a first power supply voltage 3*VDD and may perform an amplification operation.

[0203] In one embodiment, the gate terminal of the transistor TR81 may be connected to one end of the second resistor R2 and one end of the second capacitor C2, the drain terminal of the transistor TR81 may be connected to the second matching network 402, and the source terminal of the transistor TR81 may be connected to a third bias node N3_BIAS. A bias V2_BIAS may be applied to the gate terminal of the transistor TR81 through the other end of the second resistor R2, and the other end of the second capacitor C2 may be grounded. In addition, the drain terminal of the transistor TR71 may be connected to the third bias node N3_BIAS.

[0204] In one embodiment, the first RF signal RF_IN amplified by the transistors TR11, TR71, and TR81 may be output as a first RF output signal RF_OUT through the second matching network 402 and the second terminal T2.

[0205] In one embodiment, a second reference voltage V2_REF may be input to the positive input terminal of a third operational amplifier 404. The negative input terminal of the third operational amplifier 404 may be connected to a third bias node N3_BIAS, and a voltage V3 (or a third bias voltage V3) of the third bias node N3_BIAS may be input to the negative input terminal of the third operational amplifier 404. The output terminal of the third operational amplifier 404 may be connected to the gate terminal of a transistor TR81.

[0206] In one embodiment, the third operational amplifier 404 may form a specific feedback loop and may calibrate the third bias voltage V3 such that the third bias voltage V3 is maintained close to the second reference voltage V2_REF. That is, the level of the second reference voltage V2_REF may correspond to the target level of the third bias voltage V3. In a specific example, the second reference voltage V2_REF may correspond to "2*VDD" and may be 2 / 3 times the first power supply voltage 3*VDD. In addition, the first reference voltage V1_REF may correspond to "VDD" and may be 1 / 3 times the first power supply voltage 3*VDD.

[0207] Since the third bias voltage V3 is fixed at "2*VDD" by the third operational amplifier 404 according to the embodiment, the transistor TR71 may perform a stable operation as an amplification stage. In addition, the source-drain current of each core transistor (transistors TR11, TR71, and TR81) may be controlled via a calibration operation so as not to exceed the breakdown voltage.

[0208] Figure 22 is a circuit diagram showing an exemplary implementation of a first power amplifier 500 and a bias circuit 550 according to an embodiment. Figure 22 The first power amplifier 500 may be a differential amplifier.

[0209] Referring to Figure 22 , the first power amplifier 500 may include a plurality of inductors (e.g., L11 to L14 and L21 to L24), a plurality of transistors (e.g., TR11_1, TR11_2, TR71_1, TR71_2, TR81_1, and TR81_2), a plurality of capacitors (e.g., C11, C12, C21, C22, C3, C41, C42, C51, C52, and C6), a plurality of resistors (e.g., R11, R12, R21, R22, R31, R32, R41, R42, and R5), a first operational amplifier 503, and a third operational amplifier 504.

[0210] The inductors L11 to L14 may form a first matching network to which a first RF signal RF_IN is input. The transistors TR11_1, the transistor TR11_2, the capacitor C41, and the capacitor C42 may form a first amplification stage. The transistors TR71_1, the transistor TR71_2, the capacitor C11, the capacitor C12, the resistor R11, the resistor R12, the resistor R31, and the resistor R32 may form a second amplification stage. The transistors TR81_1, the transistor TR81_2, the capacitor C21, the capacitor C22, the capacitor C51, the capacitor C52, the resistor R21, the resistor R22, the resistor R41, and the resistor R42 may form a third amplification stage. And the inductors L21 to L24 may form a second matching network for outputting a first RF output signal RF_OUT. In one embodiment, the first power amplifier 500 may receive a first power supply voltage 3*VDD through a fourth node N4.

[0211] In one embodiment, a first reference voltage V1_REF, which is "VDD", may be input to the positive input terminal of the first operational amplifier 503. The voltage of a first bias node N1_BIAS may be input to the negative input terminal of the first operational amplifier 503. And the output terminal of the first operational amplifier 503 may be connected to the gate terminal of the transistor TR71_1 through the resistor R11 and to the gate terminal of the transistor TR71_2 through the resistor R12. Accordingly, the first operational amplifier 503 may calibrate the voltage of the first bias node N1_BIAS and fix the voltage to "VDD".

[0212] In one embodiment, a second reference voltage V2_REF, which is "2*VDD", may be input to the positive input terminal of the third operational amplifier 504. The voltage of a third bias node N3_BIAS may be input to the negative input terminal of the third operational amplifier 504. And the output terminal of the third operational amplifier 504 may be connected to the gate terminal of the transistor TR81_1 through the resistor R21 and to the gate terminal of the transistor TR81_2 through the resistor R22. Accordingly, the third operational amplifier 504 may calibrate the voltage of the third bias node N3_BIAS and may fix the voltage to "2*VDD".

[0213] In one embodiment, the bias circuit 550 may include a reference current source IREF, a second operational amplifier 552, and a transistor TR51.

[0214] In one embodiment, a first reference voltage V1_REF, which is "VDD", may be input to a negative input terminal of a second operational amplifier 552, a voltage of a second bias node N2_BIAS may be input to a positive input terminal of the second operational amplifier 552, and an output terminal of the second operational amplifier 552 may be connected to a third node N3 through a fifth resistor R5. Accordingly, the second operational amplifier 552 may calibrate the voltage of the second bias node N2_BIAS and may fix the voltage as "VDD".

[0215] However, Figure 22 the embodiments are merely examples, and the inventive concept is not limited thereto, and various example embodiments based on the inventive concept may be applied to a power amplifier and a bias circuit of an RF integrated circuit.

[0216] Figure 23 is a block diagram illustrating a wireless communication device 600 according to an embodiment.

[0217] Referring to Figure 23 , the wireless communication device 600 may include a modem chip 610, an RF chip 620, a first communication chip 630, and a second communication chip 640. The modem chip 610 may support various communication networks by using the RF chip 620, the first communication chip 630, and the second communication chip 640.

[0218] In one embodiment, the RF chip 620 may include a bias calibration circuit 621. The RF chip 620 may include an RF integrated circuit configured to support communication in a millimeter wave band, and the calibration operation described with reference to Figures 1A to 22 may be performed by the bias calibration circuit 621 on a bias current or a bias voltage of a power amplifier of the RF chip 620.

[0219] In one embodiment, the first communication chip 630 may include an integrated circuit configured to support additional network communication with the RF chip 620, and a calibration operation may be performed on a bias current or a bias voltage of a power amplifier of the first communication chip 630 based on the inventive concept.

[0220] In addition, in one embodiment, the second communication chip 640 may include an integrated chip configured to support additional network communication with the RF chip 620, and a calibration operation may be performed on a bias current or a bias voltage of a power amplifier of the second communication chip 640 based on the inventive concept.

[0221] Figure 24 is a conceptual diagram illustrating an Internet of Things (IoT) network system 1000 to which an embodiment is applied.

[0222] Referring to Figure 24, the IoT network system 1000 may include a plurality of IoT devices 1100, 1120, 1140, and 1160, an access point 1200, a gateway 1250, a wireless network 1300, and a server 1400. IoT may represent a network between objects using wired / wireless communication.

[0223] Each of the IoT devices 1100, 1120, 1140, and 1160 may form a group according to the characteristics of each IoT device. For example, the IoT devices may be grouped into a home accessories group 1100, a household appliances / furniture group 1120, an entertainment group 1140, and / or a vehicle group 1160. A plurality of IoT devices 1100, 1120, and 1140 may be connected to a communication network or may be connected to other IoT devices through the access point 1200. The access point 1200 may be provided in one IoT device. The gateway 1250 may change the protocol to connect the access point 1200 to an external wireless network. The IoT devices 1100, 1120, and 1140 may be connected to an external communication network through the gateway 1250. The wireless network 1300 may include the Internet and / or a public network. A plurality of IoT devices 1100, 1120, 1140, and 1160 may be connected to the server 1400 that provides a specific service through the wireless network 1300, and a user may use the service through at least one of the plurality of IoT devices 1100, 1120, 1140, and 1160.

[0224] According to an embodiment, a plurality of IoT devices 1100, 1120, 1140, and 1160 may include a bias calibration circuit, and may perform a calibration operation on a bias current or a bias voltage of a power amplifier included therein by using the bias calibration circuit.

[0225] Embodiments have been described with reference to the drawings and the specification. Although the embodiments have been described by using specific terms, these terms are only for explaining the inventive concept and should not be construed as limiting the scope of the inventive concept defined by the claims. Therefore, those of ordinary skill in the art will understand that various modifications can be made from the embodiments and other equivalent embodiments can be obtained. Therefore, the technical scope of the inventive concept should be defined by the appended claims.

[0226] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A radio frequency integrated circuit, comprising: A plurality of front-end circuits, each front-end circuit being connected to an antenna and configured to transmit radio frequency signals; A bias circuit configured to provide a bias to a power amplifier of the plurality of front-end circuits; And A bias calibration circuit configured to sense a bias current of the power amplifier caused by the bias and perform a calibration operation on the bias current based on a result of the bias current sensing.

2. The radio frequency integrated circuit according to claim 1, wherein, The bias calibration circuit is further configured to: sequentially calibrate bias currents of remaining power amplifiers in the power amplifiers based on an order close to a first power amplifier among the power amplifiers.

3. The radio frequency integrated circuit according to claim 2, wherein, The first power amplifier is the power amplifier closest to the bias circuit among the power amplifiers.

4. The radio frequency integrated circuit according to claim 2, wherein, The bias calibration circuit is further configured to: sense a reference current from the bias circuit and calibrate a first bias current of the first power amplifier based on the reference current.

5. The radio frequency integrated circuit according to claim 2, wherein Through the calibration operation, each of the bias currents of the remaining power amplifiers in the power amplifiers has a difference less than a threshold from the first bias current of the first power amplifier.

6. The radio frequency integrated circuit according to claim 1, wherein, The power amplifier includes a first power amplifier and a second power amplifier adjacent to each other, wherein the bias calibration circuit is further configured to: calibrate the second bias current based on a difference between first sensing results generated by sensing a first bias current of the first power amplifier and a second bias current of the second power amplifier.

7. The radio frequency integrated circuit according to claim 6, wherein, The power amplifier further includes a third power amplifier adjacent to the second power amplifier, wherein the bias calibration circuit is further configured to: calibrate the third bias current based on a difference between second sensing results generated by sensing the calibrated second bias current and a third bias current of the third power amplifier.

8. The radio frequency integrated circuit according to claim 1, wherein, The first power amplifier among the power amplifiers includes: A first node to which a power supply voltage is applied; and An amplification stage configured to amplify a first radio frequency signal, wherein the bias calibration circuit is further configured to: use a current mirror circuit arrangement to sense a first bias current of the first power amplifier through a second node between the first node and the amplification stage.

9. The radio frequency integrated circuit according to claim 1, wherein, The bias calibration circuit is further configured to: perform the calibration operation based on a mode selected from a common mode and a low power mode.

10. The radio frequency integrated circuit according to claim 1, wherein, The first power amplifier among the power amplifiers includes amplification stages stacked on each other, wherein the bias calibration circuit includes: a first operational amplifier configured to calibrate a voltage of a first bias node for connecting the amplification stages to be maintained at a first target level.

11. The radio frequency integrated circuit according to claim 10, wherein, The bias circuit includes: A bias generator configured to generate a reference current; and A diode-connected transistor configured to output a first bias among the biases provided to the first power amplifier based on the reference current, wherein the bias calibration circuit further includes: a second operational amplifier configured to calibrate a voltage of a node for connecting the diode-connected transistor to the bias generator to be maintained at a second target level.

12. A radio frequency integrated circuit, comprising: A first power amplifier configured to amplify a first radio frequency signal based on a first bias; A second power amplifier configured to amplify a second radio frequency signal based on a second bias; A bias circuit configured to provide a first bias to a first power amplifier and a second bias to a second power amplifier; A first current sensor configured to sense a first bias current of the first power amplifier caused by the first bias and a second bias current of the second power amplifier caused by the second bias; And A first comparator configured to compare a first sensing result corresponding to the first bias current with a second sensing result corresponding to the second bias current and output a corresponding first comparison result, wherein the bias circuit is further configured to adjust the second bias based on the first comparison result.

13. The radio frequency integrated circuit according to claim 12, further comprising: A third power amplifier configured to amplify a third radio frequency signal based on a third bias; A second current sensor configured to sense a third bias current of the third power amplifier caused by the third bias provided from the bias circuit and a fourth bias current of the second power amplifier caused by the adjusted second bias; And A second comparator configured to compare a third sensing result corresponding to the third bias current with a fourth sensing result corresponding to the fourth bias current and output a second comparison result, wherein the bias circuit is further configured to adjust the third bias based on the second comparison result.

14. The radio frequency integrated circuit according to claim 12, wherein, The first current sensor includes: a plurality of first transistors connected in parallel to sense the first bias current; and a plurality of second transistors connected in parallel to sense the second bias current.

15. The radio frequency integrated circuit according to claim 14, wherein, Some of the plurality of first transistors and some of the plurality of second transistors are deactivated.

16. The radio frequency integrated circuit according to claim 12 further comprises: A first operational amplifier configured to maintain the voltage of a first bias node between amplification stages included in the first power amplifier and stacked on each other at a first target level, wherein the amplification stages include: A first amplification stage configured to receive the first bias and a first radio frequency signal; and A second amplification stage configured to receive the third bias.

17. The radio frequency integrated circuit according to claim 16, wherein, The output terminal of the first operational amplifier is connected to the node of the second amplification stage to which the third bias is applied, The negative input terminal of the first operational amplifier is connected to the first bias node, and The positive input terminal of the first operational amplifier is connected to the node to which a reference voltage having the first target level is applied.

18. A radio frequency integrated circuit, comprising: A first front-end circuit connected to a first antenna and configured to amplify and transmit a first radio frequency signal; And A bias calibration circuit configured to perform a calibration operation on a first bias voltage of a first power amplifier of the first front-end circuit, the first power amplifier including at least a first stacked amplification stage and a second stacked amplification stage, wherein the bias calibration circuit includes: a first operational amplifier connected to the first stacked amplification stage at a first bias node as part of a feedback loop to maintain the first bias node at the first bias voltage during the calibration operation.

19. The radio frequency integrated circuit according to claim 18, wherein, The first stacked amplification stage and the second stacked amplification stage respectively include a first transistor and a second transistor; In a first transistor, a first gate terminal is configured to receive a first radio frequency signal and a first bias, a first source terminal is grounded, and a first drain terminal is connected to a first bias node, and in a second transistor, a second gate terminal is configured to receive a second bias, and a second source terminal is connected to the first bias node.

20. The radio frequency integrated circuit according to claim 18, further comprising: a second front-end circuit, connected to a second antenna and configured to amplify and transmit a second radio frequency signal; and a bias circuit configured to provide the first bias to a first power amplifier and provide the second bias to a second power amplifier included in the second front-end circuit, wherein the bias calibration circuit is further configured to perform a calibration operation on the second bias current based on a difference between sensed results generated by sensing a first bias current due to the first bias of the first power amplifier and a second bias current due to the second bias of the second power amplifier.

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