Pseudo-random sequence generator based on non-degenerate hyperchaotic system and generation method thereof

Abstract

The invention relates to the field of chaos cryptography, and discloses a pseudo-random sequence generator based on a non-degenerate hyperchaotic system and a generation method thereof.The pseudo-random sequence generator comprises a top layer module, an input module, a sequence calculation module and a clock management module, and the input module is used for inputting system parameters and initial values to the sequence calculation module; the clock management module is used for generating all clocks used in the whole hardware implementation process, the sequence calculation module is used for calculating and generating a pseudorandom sequence, and the top layer module is used for integrating all the modules. By utilizing the parallel processing capability of hardware platforms such as an FPGA (Field Programmable Gate Array), the operation speed and the data processing capability of the hyper-chaotic system are remarkably improved, an efficient resource management strategy is developed, and the allocation and utilization of hardware resources are optimized, so that the hardware cost is reduced, the overall performance of the system is improved, and the hardware implementation process of the hyper-chaotic system is simplified; the difficulty of system design and debugging is reduced, and the reliability and stability of the system are improved.

Description

Technical Field

[0001] The present invention relates to the field of chaotic cryptography, and particularly to a pseudo-random sequence generator based on a non-degenerate hyperchaotic system and a method for generating the same. Background Art

[0002] In the past few decades, with the rapid development of computer science, electronic engineering, and information technology, the research and application of various complex systems have increased day by day. Especially for hyperchaotic systems, due to their rich dynamic behaviors and good pseudo-random characteristics, they are widely used in fields such as communication, cryptography, information security, and system simulation. The non-degenerate chaotic system is different from the traditional chaotic system. It has more positive Lyapunov exponents, which means that the dynamics inside the system are more complex, making it show greater application potential in fields such as secure communication and cryptography.

[0003] However, although the non-degenerate hyperchaotic system has superior performance in theory, its implementation in practical applications faces many challenges. On the one hand, the complexity of the non-degenerate hyperchaotic system means that a large amount of calculation is required to simulate and predict the behavior of the system, which often leads to slow processing speed in a traditional serial computing environment and is difficult to meet the requirements of real-time processing. On the other hand, the hardware implementation of the system usually requires relying on high-performance computing resources, such as professional devices like FPGA (Field Programmable Gate Array), which not only increases the cost but also limits its application in resource-constrained environments.

[0004] Currently, the hardware implementation of the non-degenerate hyperchaotic system mainly faces several major problems: Low operation efficiency: Traditional hardware implementation methods are difficult to fully utilize the parallel processing capabilities of platforms such as FPGA, resulting in low operation efficiency of the system and being unable to achieve high-speed data processing and transmission; Insufficient resource utilization: Existing technologies cannot effectively utilize hardware resources, especially in the configuration and management of parallel computing resources, which limits the further improvement of system performance; High system complexity: Due to the complexity of the hyperchaotic system itself, existing hardware implementation methods are often difficult to accurately simulate the system behavior, resulting in increased difficulties in system design and debugging. Summary of the Invention

[0005] To make up for the above deficiencies, the present invention provides a pseudo-random sequence generator based on a non-degenerate hyperchaotic system and a method for generating the same, aiming to implement an efficient and economical pseudo-random sequence generator based on a non-degenerate hyperchaotic system, enabling it to better meet the requirements for operation speed, cost, and complexity in practical applications.

[0006] To achieve the above object, the present invention provides the following technical solutions: A pseudo-random sequence generator based on a non-degenerate hyperchaotic system, including a top-level module, an input module, a sequence calculation module, and a clock management module. The input module is used to input system parameters and initial values to the sequence calculation module. The clock management module is used to generate all the clocks used in the entire hardware implementation process. The sequence calculation module is used to calculate and generate a pseudo-random sequence. The top-level module is used to integrate all modules, and the calculation result of the sequence calculation module is input to the DAC conversion module after cross-clock domain processing through the FIFO IP core, and then the data is transmitted to the oscilloscope through the BNC connection line for display.

[0007] Preferably, during the operation of the sequence calculation module, multiplication operations involving parameters are performed through an adder and a signed shift register, and the parameter settings except for the memristor are all integers.

[0008] Preferably, the equation of the non-degenerate hyperchaotic system is as follows: Wherein, a, b, c, d, e are the control parameters of the system, k is a positive parameter representing the memristive strength; x, y, z, w, u are the 5 state variables of the system.

[0009] Preferably, the generation method of the pseudo-random sequence generator based on the non-degenerate hyperchaotic system includes the following steps: Discretize the continuous-time dynamic equation of the non-degenerate hyperchaotic system using the fourth-order Runge-Kutta method; Use the fixed-point number form to represent the decimals involved in the operation process, and the bit widths occupied by the integer part and the decimal part of the data are determined according to the data volume and data size in the operation process of the implemented non-degenerate hyperchaotic system; Set all system parameters except the memristor coupling parameter to integers, and implement the multiplication operation involving parameters through an adder and a signed shift register; Use the method of state machine jumping to split the entire complex calculation process into multiple calculation steps for calculation.

[0010] Preferably, discretize the continuous-time dynamic equation of the non-degenerate hyperchaotic system using the fourth-order Runge-Kutta method, and the specific process formula is as follows: 。

[0011] Preferably, the entire complex calculation process is divided into multiple calculation steps by using the state machine jump method, and the operation steps are as follows: S0: Yes Five state variables are stored; S1: Determine the value of stste to determine the next state variable to jump to. Perform calculations; S2: Calculation , , , , , ; S3: Compute , , , , , ; S4: Calculation , , , , , ; S5: Calculation ; S6: Calculation ( ); S7: Calculation .

[0012] Among them, in terms of computing efficiency, the present invention discretizes the non-degenerate hyperchaotic system by adopting the fourth-order Runge-Kutta method, combines the technical means of combinatorial logic and sequential logic, and cleverly decomposes the entire computing process into multiple steps that can be executed in parallel. The core advantage of this method is that it can give full play to the parallel processing capabilities of modern hardware platforms, especially FPGAs. Compared with traditional methods, this design greatly improves the computing speed and data processing capabilities. When processing complex data or performing high-speed data exchange, the method of the present invention can maintain efficient computing performance, significantly shorten the data processing time, and provide feasibility guarantees for real-time data processing. In addition, this efficient computing method also effectively improves the anti-interference ability and stability of the system, and provides solid technical support for the reliable operation of the system.

[0013] In terms of resource optimization, the present invention not only takes into account the improvement of computing efficiency, but also focuses on the rational use of hardware resources and cost control. Through carefully designed algorithms and optimized hardware configurations, this technology can maximize the efficiency of hardware resource utilization without increasing additional hardware costs. This resource optimization strategy not only reduces the overall cost of the system, but also improves the applicability and competitiveness of the system in resource-constrained environments. Especially in application scenarios that require a large amount of parallel computing and high-speed data processing, the present invention achieves a higher cost-effectiveness ratio by effectively managing and allocating computing resources, significantly improving the market competitiveness of hyperchaotic systems.

[0014] In terms of reducing system complexity, the present invention effectively reduces the difficulty of system development and maintenance by simplifying system design and optimizing the implementation process. By adopting a modular design concept, the complex system process is split into several relatively independent and easy-to-manage and maintain modules. This technology not only reduces the complexity of system implementation, but also improves the maintainability and scalability of the system. The implementation of this design method makes the upgrade and maintenance of the system more convenient and quick, greatly reducing the cost and risk of long-term operation. In addition, by simplifying the system architecture and optimizing the design process, the present invention also facilitates the operation and use of non-professionals, expanding the application scope and user group of the system.

[0015] In terms of promotion and application, the technical advantages and positive effects of the present invention provide a solid foundation for its application in multiple fields. Especially in key technical fields such as communications, information security, and data encryption, the implementation of the present invention not only improves the security and reliability of data processing, but also provides new impetus for technological progress and innovation in these fields. By providing an efficient, reliable, and cost-effective technical solution, the present invention helps to promote the widespread application of non-degenerate hyperchaotic systems and promote the development and progress of related scientific and technological fields.

[0016] In summary, the present invention not only demonstrates its advancement and foresight in theory through a series of innovative designs and implementation strategies, but also proves its huge application potential and practical value in practice. The comprehensive manifestation of these advantages and positive effects makes the present invention an important breakthrough in the field of hardware implementation of hyperchaotic systems, opens up a new path for the development of related technologies and application fields, and brings extensive social and economic benefits.

[0017] The pseudo-random sequence generator based on a non-degenerate hyperchaotic system proposed in the present invention has the following beneficial effects: 1. The present invention improves the computing efficiency: by optimizing the computing method and hardware structure design, the parallel processing capability of hardware platforms such as FPGA is fully utilized to significantly improve the computing speed and data processing capability of the hyperchaotic system.

[0018] 2. The present invention optimizes resource utilization: develops an efficient resource management strategy, optimizes the allocation and utilization of hardware resources to reduce hardware costs and improve the overall system performance.

[0019] 3. The present invention reduces system complexity: adopts an innovative design scheme to simplify the hardware implementation process of the hyperchaotic system, reduces the difficulty of system design and debugging, and improves the reliability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is the phase diagram of the non-degenerate hyperchaotic system; Figure 2 is the bifurcation diagram of the non-degenerate hyperchaotic system; Figure 3 is the Lyapunov exponent spectrum of the non-degenerate hyperchaotic system; Figure 4 is the schematic diagram of the data structure; Figure 5 is the schematic diagram of state transition; Figure 6 is the overall architecture diagram of the FPGA; Figure 7 is the internal architecture diagram of the FPGA; Figure 8 is the hardware implementation circuit of sequence X; Figure 9 is the hardware implementation circuit of sequence Y; Figure 10 is the hardware implementation circuit of sequence Z; Figure 11 is the hardware implementation circuit of sequence W; Figure 12 is the hardware implementation circuit of sequence U; Figure 13 is the x-y analog simulation phase diagram of the pseudo-random sequence generator; Figure 14 is the x-u analog simulation phase diagram of the pseudo-random sequence generator; Figure 15 is the y-z analog simulation phase diagram of the pseudo-random sequence generator; Figure 16 is the RTL-level view of the hardware implementation of the FPGA development platform; Figure 17 is the oscilloscope display x-y phase diagram when the circuit runs stably for 3000 seconds; Figure 18 is the oscilloscope display x-u phase diagram when the circuit runs stably for 3000 seconds; Figure 19 is the oscilloscope display y-z phase diagram when the circuit runs stably for 3000 seconds; Figure 20Schematic diagram of the connection between the FPGA development board and the DAC conversion module; Figure 21 Schematic diagram of the connection between the FPGA hardware implementation platform and the oscilloscope. Specific implementation manner

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0022] Refer to Figures 1 - 20 , a pseudo-random sequence generator based on a non-degenerate hyperchaotic system provided by the present invention, the FPGA hardware implementation of which includes a top-level module, an input module, a sequence calculation module, and a clock management module. The input module is used to input system parameters and initial values to the sequence calculation module. The clock management module is used to generate all the clocks used in the entire hardware implementation process. The sequence calculation module is used to calculate and generate pseudo-random sequences. The top-level module is used to integrate all modules, and the calculation results of the sequence calculation module are input to the DAC conversion module through the FIFO IP core for cross-clock domain processing, and then the data is transmitted to the oscilloscope through the BNC connection line for display. The overall architecture diagram and internal architecture diagram of the system are as Figure 6 and Figure 7 shown.

[0023] Among them, during the operation of the sequence calculation module, in order to facilitate the FPGA implementation of the system, the parameters of the system except the memristor are set to integers. Therefore, the multiplication operation involving parameters can be implemented by an adder and a signed shift register. For example, to calculate 40y(n), it can be split into 32y(n)+8y(n), that is, 2 42-bit shift registers and 1 42-bit adder can be used to implement a 42-bit multiplication operation, saving hardware resources. The specific hardware implementation circuit is as Figures 8 - 12 shown, and the analog simulation output of the data on the oscilloscope is as Figures 13 - 15 shown.

[0024] Through this design, the entire calculation process is decomposed into a series of steps that can be processed in parallel, and each step has its own data path and control logic. This method not only optimizes the calculation process, reduces the occupation of hardware resources, but also improves the flexibility of data processing and the scalability of the system.

[0025] In the FPGA implementation, this structure allows the use of parallel processing and pipelining techniques, thus greatly improving the computational efficiency and performance of the hyperchaotic system. At the same time, due to the programmable nature of the FPGA, this structure can be adjusted and optimized according to different application requirements to adapt to various implementations of hyperchaotic systems.

[0026] The equation of the non-degenerate hyperchaotic system is as follows; Among them, a, b, c, d, and e are the control parameters of the system, k is a positive parameter representing the memristor strength; x, y, z, w, and u are the five state variables of the system.

[0027] To further verify the complexity and good chaotic performance of the non-degenerate hyperchaotic system, the present invention uses MATLAB 2020a software to analyze the dynamic characteristics of the system. The Lyapunov exponent is one of the key parameters used to describe the dynamic characteristics of a chaotic system. It can be used to measure the stability of the system under small perturbations and thus predict its long-term behavior. The more positive Lyapunov exponents there are, the more chaotic characteristics the system has, and the complexity of the system is positively correlated with the degree of chaos of its dynamic properties.

[0028] When the system parameters are selected as a = 40, k = 40, m = 1, n = 0.01, b = 5, c = 20, d = 5, e = 25, and the initial value of the system is (0, 5.1, 0, 0, 6), the phase diagram of the system attractor can be obtained through numerical simulation as Figure 1 shown. The corresponding five Lyapunov exponents are LE1 = 1.6893, LE2 = 0.613, LE3 = 0.0603, LE4 = -0.1885, LE5 = -38.7198. It can be seen that the chaotic system has three positive Lyapunov exponents, which means that the system has three independent manifolds at this section, and the orbits on each manifold are chaotic, that is, the system is a non-degenerate five-dimensional hyperchaotic system. The dimension DL of the Lyapunov exponent calculated according to the wolf algorithm is: Select e as the variable parameter of the system, keep other system parameters and the initial value of the system unchanged, and the bifurcation diagram and Lyapunov exponent spectrum of the system state variable z evolving within the parameter are as shown in Figure 2 、 Figure 3 shown.

[0029] The newly constructed system after It remains unchanged after transformation, so the newly constructed system is symmetric about the Z-axis. From the above analysis, it can be seen that the chaotic system has symmetry, its degeneracy is 0, and the dimension DL of the Lyapunov exponent is a fractional dimension. Therefore, the constructed system is non-degenerate hyperchaotic and has rich dynamical behaviors.

[0030] The present invention uses the fourth-order Runge-Kutta method to discretize the continuous-time dynamical equations of the non-degenerate hyperchaotic system, converting the continuous dynamic system into a discrete system suitable for implementation on a digital hardware platform. By optimizing this discretization algorithm, the present invention not only improves the accuracy of numerical calculations but also significantly speeds up the calculation speed. The specific discrete algorithm process is shown in the following formulas.

[0031] In terms of hardware implementation, since using FPGA for floating-point operations will consume a large amount of hardware board resources, the present invention uses fixed-point numbers to represent the decimals involved in the operation process. The bit widths occupied by the integer part and the decimal part of the data are determined according to the data volume and data size in the operation process of the implemented non-degenerate hyperchaotic system. Its specific data structure is as Figure 1 shown. Generally, the Y value should be at least three times the X value to ensure sufficient data accuracy of the calculation results.

[0032] At the same time, a large number of multiplication operations and addition operations are involved in the implementation process of the system. Among them, multiplication operations will consume a large amount of hardware logic resources. The present invention sets all system parameters except the memristor coupling parameter to integers, and it can implement the multiplication operations involving parameters through adders and signed shift registers. For example, for the operation 40y(n), it can be split into 32y(n)+8y(n), and one multiplication operation can be implemented using 2 shift registers and 1 adder, saving hardware resources.

[0033] In addition, the present invention designs an execution structure that combines combinational logic and sequential logic, making full use of the parallel processing ability of the FPGA development platform. Essentially, it means using the method of state machine jumping to split the entire complex calculation process into multiple calculation steps for calculation. In this structure, each state represents a specific operation stage of the hyperchaotic system, and the transition between states is controlled by the state machine, ensuring the correct order and data dependence of the operation steps. The jumping process of the state machine is as Figure 5 shown.

[0034] Example: Taking a non - degenerate five - dimensional memristive hyperchaotic system as an example, the specific equations of the system and the parameter settings are as follows: Among them, the system parameters are \(a = 40\), \(k = 40\), \(m = 1\), \(n = 0.01\), \(b = 5\), \(c = 20\), \(d = 5\), \(e = 25\), and the initial values of the system are \((0,5,0,0,6)\). The above - mentioned system is discretized using the fourth - order Runge - Kutta method, and the process is as follows: , During the operation process, due to the multiple iterative operations of recursive parameters, problems such as competition and hazard caused by misaligned clocks in iterative data are very likely to occur. Therefore, the present invention uses a state machine to regulate the entire calculation process, and its jump rules are as Figure 5 shown, and the specific operations of each state are as follows: S0: Store the five state variables; S1: Judge the value of stste to determine the next state variable to jump to, and at the same time calculate ; S2: Calculate , , , , , ; S3: Calculate , , , , , ; S4: Calculate , , , , , ; S5: Calculate ; S6: Calculate ( ); S7: Calculate .

[0035] ​After performing the above processing on the system, Verilog code is written on the FPGA development platform. After synthesis and placement and routing, a bitstream file is generated. The RTL-level view of the development platform is as shown in Figure 16 Figure 2. The development board selected for this invention is the XC7A35T-2FGG484 of the ARTIX-7 series from Xilinx. The DAC conversion module uses the AN9767 type DAC chip, and the oscilloscope uses the RIGOL HDO4804 type digital oscilloscope. First, the generated bitstream file is burned into the FPGA development board by the host computer through the JTAG interface. Since the clock source provided on the board is a 50MHz active clock crystal oscillator, and the highest rate of the used DAC conversion module is 125MHz, in order to ensure the sampling rate of the DAC conversion module, the phase-locked loop IP core in the board is used to generate a 125MHz clock and input it into the DAC conversion module. At the same time, since the internal operation clock of the system is also a 50M active clock crystal oscillator, which is not synchronized with the sampling clock of the DAC chip, in order to ensure the accuracy of the transmitted data, this invention performs cross-clock domain processing on the project through an asynchronous clock FIFO, so that the data can be synchronized with the sampling clock. Finally, the data is transmitted to the oscilloscope through a BNC connection line to observe the phenomenon. The connection of the hardware circuit is as shown in Figure 20 and Figure 21 Figure 3, and the oscilloscope display result is as shown in Figures 17 - 19 Figure 4.

[0036] By comparing the phase diagrams shown in the oscilloscope with the phase diagrams of the MATLAB R2020a simulation and the hardware implementation circuit simulation in the previous invention content ( Figure 1 , Figure 13 , Figure 14 and Figure 15 ), it can be seen that in the hardware implementation, there are no obvious distortions and errors in the signal transmission and processing process, and the displayed phase diagrams are basically the same, thus verifying the correctness and practicality of this invention. This provides strong support for further research and application, and at the same time provides a reliable hardware implementation solution for engineers and technicians in related fields.

[0037] 1. High-efficiency operation and fast response Facing the problem of low efficiency in the implementation of traditional hyperchaotic systems, this invention deeply studies the non-degenerate hyperchaotic system and develops algorithms and structures that can make full use of the parallel processing capabilities of modern hardware. This technology can effectively shorten the data processing time and improve the system's ability to process large amounts of data. In addition, by optimizing the algorithms and hardware structures, this invention reduces the system's sensitivity to external interference and further enhances the stability and reliability of the system.

[0038] 2. Resource optimization and cost control The existing technology has many deficiencies in the use of hardware resources, resulting in high costs and low efficiency. The present invention optimizes the allocation and use of resources in the hyperchaotic system. This includes not only the optimized use of hardware resources, but also the efficient management of computing resources and storage resources, thereby significantly reducing the implementation cost of the system without sacrificing performance. This is intended to promote the widespread application of hyperchaotic systems, especially in resource-constrained environments, and to provide an economical and efficient solution.

[0039] 3. Reduction of system complexity The high complexity of hyperchaotic systems is an important factor that limits their widespread application. Therefore, the present invention reduces the difficulty of system design, implementation and maintenance by simplifying the system architecture, optimizing the design process and improving the system modularization level. In this way, not only can the time and cost of system development be reduced, but also the reliability and ease of use of the system can be improved, promoting its application and promotion in more fields.

[0040] 4. Promote the development of multi-field applications Finally, the research purpose of this invention is to promote the application and development of hyperchaotic systems in multiple fields such as communication, information security, and data encryption through these technological innovations and optimizations. This invention aims to provide a more efficient, reliable, and economical technical solution for these fields by improving computing efficiency, optimizing resource utilization, and reducing system complexity, so as to solve the needs that cannot be effectively met by existing technologies.

[0041] 1. In general, the present invention not only provides solutions to the problems existing in the prior art, but also aims to promote the application of hyperchaotic systems in a wider range of fields through its innovative technical means, and promote the progress and development of related science and technology. Through these efforts, the present invention is expected to open up new paths for the research and application of non-degenerate hyperchaotic systems and bring more extensive social and economic benefits.

[0042] In the present invention, the pseudo-random sequence generator based on the non-degenerate hyperchaotic system proposed in the present invention shows significant advantages and positive effects compared with the prior art, especially in terms of computing efficiency, resource optimization, system complexity reduction and promotion and application. Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A pseudo-random sequence generator based on a non-degenerate hyperchaotic system, characterized in that: It includes a top-level module, an input module, a sequence calculation module, and a clock management module. The input module is used to input system parameters and initial values to the sequence calculation module. The clock management module is used to generate all the clocks used in the entire hardware implementation process. The sequence calculation module is used to calculate and generate a pseudo-random sequence. The top-level module is used to integrate all modules, and the calculation result of the sequence calculation module is input to the DAC conversion module after cross-clock domain processing through the FIFO IP core, and then the data is transmitted to the oscilloscope through the BNC connection line for display.

2. The pseudo-random sequence generator based on a non-degenerate hyperchaotic system according to claim 1, characterized in that: During the operation process, the sequence calculation module performs multiplication operations involving parameters through an adder and a signed shift register, and the parameter settings except for the memristor are all integers.

3. The pseudo-random sequence generator based on a non-degenerate hyperchaotic system according to claim 1, wherein: The equation of the non-degenerate hyperchaotic system is as follows: Among them, a, b, c, d, and e are the control parameters of the system, k is a positive parameter representing the memristance strength; x, y, z, w, and u are the five state variables of the system.

4. A generation method of a pseudo-random sequence generator based on a non-degenerate hyperchaotic system, characterized in that: Using the pseudo-random sequence generator based on the non-degenerate hyperchaotic system according to any one of claims 1-3, it includes the following steps: Discretize the continuous-time dynamic equation of the non-degenerate hyperchaotic system using the fourth-order Runge-Kutta method; Use the fixed-point number form to represent the decimals involved in the operation process, and the bit widths occupied by the integer part and the decimal part of the data are determined according to the data volume and data size in the operation process of the implemented non-degenerate hyperchaotic system; Set all system parameters except the memristor coupling parameter to integers, and implement the multiplication operation involving parameters through an adder and a signed shift register; Use the method of state machine jumping to split the entire complex calculation process into multiple calculation steps for calculation.

5. The generation method of the pseudo-random sequence generator based on the non-degenerate hyperchaotic system according to claim 4, characterized in that: Discretize the continuous-time dynamic equation of the non-degenerate hyperchaotic system using the fourth-order Runge-Kutta method, and the specific process formula is as follows: 。 6. The generation method of the pseudo-random sequence generator based on a non-degenerate hyperchaotic system according to claim 4, characterized in that: Use the method of state machine jumping to split the entire complex calculation process into multiple calculation steps for calculation, and the operation steps are as follows: S0: Store five state variables S1: Determine the value of stste to identify the next state variable for jumping, and at the same time perform calculations on ; S2: Calculate , , , , , ; S3: Calculate , , , , , ; S4: Calculate , , , , , ; S5: Calculate ; S6: Calculate ( ) S7: Calculate .

Images