Continuous time linear equalizer

Abstract

The invention discloses a continuous time linear equalizer which is arranged in a receiver. The input end of the alternating current coupling module is electrically connected with the output end of an impedance matching module of a receiver, and the alternating current coupling module is used for receiving a differential signal output by the impedance matching module, isolating a direct current signal in the differential signal to obtain a differential alternating current voltage signal, and carrying out voltage division processing on a voltage signal output by a direct current power supply to obtain a differential alternating current voltage signal; generating a direct-current common-mode voltage signal; the input end of the linear equalization module is electrically connected with the output end of the alternating-current coupling module, the output end of the linear equalization module is electrically connected with the input end of a comparator of the receiver, and the linear equalization module is used for receiving the differential alternating-current voltage signal and the direct-current common-mode voltage signal and amplifying a high-frequency signal in the differential alternating-current voltage signal; high-frequency signal attenuation caused by a low-pass channel is compensated, and the offset voltage of the circuit is calibrated based on the direct-current common-mode voltage signal. According to the invention, the bandwidth of the circuit can be expanded without increasing the power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a continuous-time linear equalizer. Background Art

[0002] In the design of traditional signal equalization circuits, a large load capacitance needs to be driven. To achieve a higher bandwidth, the value of the load resistance needs to be reduced. To avoid the gain loss caused by reducing the load resistance, more power consumption is required. Therefore, the power consumption of high-bandwidth linear equalization modules is very high. Summary of the Invention

[0003] In view of this, the present invention provides a continuous-time linear equalizer, mainly aiming to solve the problem of high power consumption caused by the current linear equalization module during the process of expanding the bandwidth.

[0004] To solve the above problems, the present application provides a continuous-time linear equalizer, including:

[0005] An AC coupling module: The input end of the AC coupling module is electrically connected to the output end of the impedance matching module of the receiver, and is used to receive the differential signal output by the impedance matching module, isolate the DC signal in the differential signal to obtain a differential AC voltage signal, and perform voltage division processing on the voltage signal output by the DC power supply to generate a DC common-mode voltage signal;

[0006] A linear equalization module: The input end of the linear equalization module is electrically connected to the output end of the AC coupling module, and the output end of the linear equalization module is electrically connected to the input end of the comparator of the receiver. The linear equalization module is used to receive the differential AC voltage signal and the DC common-mode voltage signal, amplify the high-frequency signal in the differential AC voltage signal, compensate for the high-frequency signal attenuation caused by the low-pass channel, and calibrate the circuit offset voltage based on the DC common-mode voltage signal.

[0007] Optionally, the AC coupling module includes:

[0008] A first AC coupling unit, the input end of the first AC coupling unit is electrically connected to the positive output end of the impedance matching module, and the output end of the first AC coupling unit is electrically connected to the positive input end of the linear equalization module, and is used to receive the positive differential signal in the differential voltage signal output by the impedance matching module, process the positive differential signal to obtain the positive output end differential AC voltage signal in the differential AC voltage signal, and perform voltage division processing on the DC voltage to generate a positive output end DC common-mode voltage signal;

[0009] A second AC coupling unit, the input end of the second AC coupling unit is electrically connected to the negative output end of the impedance matching module, and the output end of the second AC coupling unit is electrically connected to the negative input end of the linear equalization module, for receiving the negative differential signal in the differential voltage signal output by the impedance matching module, and processing the negative differential signal to obtain the negative output terminal differential AC voltage signal in the differential AC voltage signal and performing voltage division processing on the DC voltage to generate a negative output terminal DC common mode voltage signal.

[0010] Optionally, the first AC coupling unit includes: a first isolation capacitor, a first voltage dividing resistor, a second voltage dividing resistor, a third voltage dividing resistor, a fourth voltage dividing resistor, and a first switch resistor array, where,

[0011] The first end of the first isolation capacitor is electrically connected to the positive output end of the impedance matching module, the first end of the first voltage dividing resistor is electrically connected to the positive power supply terminal, the second end of the first voltage dividing resistor is respectively electrically connected to the second end of the first isolation capacitor, the first end of the second voltage dividing resistor, and the positive input end of the linear equalization module, the second end of the second voltage dividing resistor is electrically connected to the first end of the first switch resistor array, the second end of the first switch resistor array is electrically connected to the first end of the third voltage dividing resistor, the second end of the third voltage dividing resistor is electrically connected to the ground terminal, the first end of the fourth voltage dividing resistor is electrically connected to the positive input end of the linear equalization module, and the second end of the fourth voltage dividing resistor is electrically connected to the ground terminal.

[0012] Optionally, the second AC coupling unit includes: a second isolation capacitor, a fifth voltage dividing resistor, a sixth voltage dividing resistor, a seventh voltage dividing resistor, an eighth voltage dividing resistor, and a second switch resistor array, where,

[0013] The first end of the second isolation capacitor is electrically connected to the negative output end of the impedance matching module, the first end of the fifth voltage dividing resistor is electrically connected to the positive power supply terminal, the second end of the fifth voltage dividing resistor is respectively electrically connected to the second end of the second isolation capacitor, the first end of the sixth voltage dividing resistor, and the negative input end of the linear equalization module, the second end of the sixth voltage dividing resistor is electrically connected to the first end of the second switch resistor array, the second end of the second switch resistor array is electrically connected to the first end of the seventh voltage dividing resistor, the second end of the seventh voltage dividing resistor is electrically connected to the ground terminal, the first end of the eighth voltage dividing resistor is electrically connected to the negative input end of the linear equalization module, and the second end of the eighth voltage dividing resistor is electrically connected to the ground terminal.

[0014] Optionally, the linear equalization module includes: a passive load unit, a differential amplification unit, a source negative feedback unit, a bias network unit, and an inductive series peaking unit, where,

[0015] Differential amplification unit, the input end of the differential amplification unit is electrically connected to the output end of the AC coupling module, and the output end of the differential amplification unit is connected in series between the passive load unit and the bias network unit, for receiving the differential AC voltage signal, DC common-mode voltage signal output by the AC coupling module, and the DC bias current signal of the bias network unit, making the differential amplification unit work in the saturation region through the DC common-mode voltage signal and the DC bias current signal, and converting the differential AC voltage signal into a differential AC current signal;

[0016] Passive load unit, the passive load unit is connected between the power input terminal and the first output terminal of the differential amplification unit and between the power input terminal and the second output terminal of the differential amplification unit, for receiving the differential AC current signal and converting the differential AC current signal into a differential voltage amplification signal;

[0017] Source negative feedback unit, the source negative feedback unit is connected between the third output terminal and the fourth output terminal of the differential amplification unit, for controlling the signal transfer function of the linear equalization module to generate zero-poles and adjusting the zero-pole positions to compensate for the loss of the channel;

[0018] Bias network unit, the bias network unit is electrically connected to the source negative feedback unit, for adjusting the magnitude of the DC bias current signal by controlling the number of conducting MOS transistors in the bias network unit;

[0019] Inductor series peaking unit, the inductor series peaking unit is electrically connected to the drain output terminal of the differential amplification unit, for reducing the influence of the input parasitic capacitance of the comparator of the receiver on the circuit bandwidth to improve the circuit bandwidth.

[0020] Optionally, the differential amplification unit includes: a first MOS transistor and a second MOS transistor, where,

[0021] The gate terminal of the first MOS transistor is electrically connected to the positive output terminal of the AC coupling module, the drain terminal of the first MOS transistor is respectively electrically connected to the input terminal of the passive load unit and the first input terminal of the inductor series peaking unit, and the source terminal of the first MOS transistor is respectively electrically connected to the first input terminal of the bias network unit and the first terminal of the source negative feedback unit;

[0022] The gate terminal of the second MOS transistor is electrically connected to the negative output terminal of the AC coupling module. The drain terminal of the second MOS transistor is electrically connected to the input terminal of the passive load unit and the second input terminal of the inductive series peaking unit respectively. The source terminal of the second MOS transistor is electrically connected to the second input terminal of the bias network unit and the second terminal of the source negative feedback unit;

[0023] Among them, the drain terminal of the first MOS transistor serves as the first output terminal of the differential amplification unit, the drain terminal of the second MOS transistor serves as the second output terminal of the differential amplification unit, the source terminal of the first MOS transistor serves as the third output terminal of the differential amplification unit, and the source terminal of the second MOS transistor serves as the fourth output terminal of the differential amplification unit.

[0024] Optionally, the passive load unit includes: a first load resistor array and a second load resistor array, where,

[0025] The first load resistor array includes a plurality of first load sub-units. Each of the first load sub-units is connected in parallel between the positive power supply terminal and the first output terminal of the differential amplification unit. Each of the first load sub-units includes a third MOS transistor and a first load resistor connected in series. The source terminal of each of the third MOS transistors is electrically connected to the positive power supply terminal. The gate terminals of each of the third MOS transistors are electrically connected to each of the first control code terminals respectively; the drain terminals of each of the third MOS transistors are electrically connected to the first ends of each of the first load resistors; the second ends of each of the first load resistors are electrically connected to the first output terminal of the differential amplification unit respectively;

[0026] The second load resistor array includes a plurality of second load sub-units. Each of the second load sub-units is connected in parallel between the positive power supply terminal and the second output terminal of the differential amplification unit. Each of the second load sub-units includes a fourth MOS transistor and a second load resistor connected in series. The source terminal of each of the fourth MOS transistors is electrically connected to the positive power supply terminal. The gate terminals of each of the fourth MOS transistors are electrically connected to each of the second control code terminals respectively; the drain terminals of each of the fourth MOS transistors are electrically connected to the first ends of each of the second load resistors; the second ends of each of the second load resistors are electrically connected to the second output terminal of the differential amplification unit respectively.

[0027] Optionally, the source negative feedback unit includes a negative feedback resistor array and a negative feedback capacitor array connected in parallel between the third output terminal and the fourth output terminal of the differential amplification unit, where,

[0028] The negative feedback resistor array includes a plurality of load MOS transistors connected in parallel; the source terminals of the load MOS transistors are electrically connected to the source terminal of the first MOS transistor, the drain terminals of the load MOS transistors are electrically connected to the source terminal of the second MOS transistor, and the gate terminals of the load MOS transistors are respectively electrically connected to the third control codeword terminals;

[0029] The negative feedback capacitor array includes a plurality of negative feedback capacitor sub-units connected in parallel between the third output terminal and the fourth output terminal of the differential amplification unit; each of the negative feedback capacitor sub-units includes: a first negative feedback MOS transistor, a second negative feedback MOS transistor, a third negative feedback MOS transistor, a fourth negative feedback MOS transistor, a fifth negative feedback MOS transistor, a first negative feedback capacitor, and a second negative feedback capacitor; a first end of the first negative feedback capacitor is electrically connected to the third output terminal of the differential amplification unit, and a second end of the first negative feedback capacitor is electrically connected to the drain terminal of the first negative feedback MOS transistor, the drain terminal of the second negative feedback MOS transistor, and the source terminal of the third negative feedback MOS transistor;

[0030] The source terminal of the first negative feedback MOS transistor is electrically connected to the positive power supply terminal, and the gate terminal of the first negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the first negative feedback MOS transistor is located;

[0031] The source terminal of the second negative feedback MOS transistor is electrically connected to the ground terminal, and the gate terminal of the second negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the second negative feedback MOS transistor is located;

[0032] The drain terminal of the third negative feedback MOS transistor is electrically connected to the drain terminal of the fourth negative feedback MOS transistor, the first end of the second negative feedback capacitor, and the drain terminal of the fifth negative feedback MOS transistor, and the gate terminal of the third negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the third negative feedback MOS transistor is located;

[0033] The gate terminal of the fourth negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the fourth negative feedback MOS transistor is located, and the source terminal of the fourth negative feedback MOS transistor is electrically connected to the positive power supply terminal; a second end of the second negative feedback capacitor is electrically connected to the fourth output terminal of the differential amplification unit;

[0034] The gate terminal of the fifth negative feedback MOS transistor is electrically connected to the control codeword corresponding to the negative feedback capacitor sub-unit where the fifth negative feedback MOS transistor is located, and the source terminal of the fifth negative feedback MOS transistor is electrically connected to the ground terminal.

[0035] Optionally, the bias network unit includes a first bias current source connected between the third output terminal of the differential amplification unit and the ground terminal, and a second bias current source connected between the fourth output terminal of the differential amplification unit and the ground terminal, where,

[0036] The first bias current source includes a plurality of first bias sub-current sources connected in parallel between the third output terminal of the differential amplification unit and the ground terminal: each of the first bias sub-current sources includes: a first bias MOS transistor, a second bias MOS transistor, and a third bias MOS transistor; the source terminal of the first bias MOS transistor is electrically connected to the bias module of the receiver, the gate terminal of the first bias MOS transistor is electrically connected to the first bias control codeword terminal of the first bias sub-current source where the first bias MOS transistor is located, the drain terminal of the first bias MOS transistor is electrically connected to the drain terminal of the second bias MOS transistor and the gate terminal of the third bias MOS transistor; the gate terminal of the second bias MOS transistor is electrically connected to the second bias control codeword terminal of the first bias sub-current source where the second bias MOS transistor is located, the source terminal of the second bias MOS transistor is electrically connected to the ground terminal; the drain terminal of the third bias MOS transistor is electrically connected to the third output terminal of the differential amplification unit, and the source terminal of the third bias MOS transistor is electrically connected to the ground terminal;

[0037] The second bias current source includes a plurality of second bias sub-current sources connected in parallel between the fourth output terminal of the differential amplification unit and the ground terminal: each of the second bias sub-current sources includes: a fourth bias MOS transistor, a fifth bias MOS transistor, and a sixth bias MOS transistor; the source terminal of the fourth bias MOS transistor is electrically connected to the bias module of the receiver, the gate terminal of the fourth bias MOS transistor is electrically connected to the third bias control codeword terminal of the second bias sub-current source where the fourth bias MOS transistor is located, the drain terminal of the fourth bias MOS transistor is electrically connected to the drain terminal of the fifth bias MOS transistor and the gate terminal of the fifth bias MOS transistor; the gate terminal of the fifth bias MOS transistor is electrically connected to the fourth bias control codeword terminal of the first bias sub-current source where the fifth bias MOS transistor is located, the source terminal of the fifth bias MOS transistor is electrically connected to the ground terminal; the drain terminal of the sixth bias MOS transistor is electrically connected to the fourth output terminal of the differential amplification unit, and the source terminal of the sixth bias MOS transistor is electrically connected to the ground terminal.

[0038] Optionally, the inductance series peaking unit includes a first inductance series peaking sub-unit connected between the first output terminal of the differential amplification unit and the negative input terminal of the comparator of the receiver, and a second inductance series peaking sub-unit connected between the second output terminal of the differential amplification unit and the positive input terminal of the comparator of the receiver, where,

[0039] The first inductive peaking sub-unit includes: a first parasitic capacitor, a second parasitic capacitor, and a first inductor. A first end of the first parasitic capacitor is electrically connected to a negative input terminal of a comparator of the receiver and a first end of the first inductor. A second end of the first parasitic capacitor is electrically connected to a ground terminal. A second end of the first inductor is electrically connected to a first end of the second parasitic capacitor and a first output terminal of the differential amplification unit. A second end of the second parasitic capacitor is electrically connected to the ground terminal;

[0040] The second inductive peaking sub-unit includes: a third parasitic capacitor, a fourth parasitic capacitor, and a second inductor. A first end of the third parasitic capacitor is electrically connected to a second output terminal of the differential amplification unit and a first end of the second inductor. A second end of the third parasitic capacitor is electrically connected to the ground terminal. A second end of the second inductor is electrically connected to a first end of the fourth parasitic capacitor and a positive input terminal of the comparator of the receiver. A second end of the fourth parasitic capacitor is electrically connected to the ground terminal.

[0041] The beneficial effect in this application is that the continuous-time linear equalizer is constructed by using an AC coupling module and a linear equalization module, and the inductive series peaking technology is used to expand the bandwidth of the circuit without increasing power consumption.

[0042] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are specifically described below. Description of the Drawings

[0043] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0044] Figure 1 shows a circuit structure diagram of a continuous-time linear equalizer provided by an embodiment of the present application;

[0045] Figure 2 shows a circuit structure diagram of an AC coupling module of a continuous-time linear equalizer provided by another embodiment of the present application;

[0046] Figure 3 shows a circuit structure diagram of an AC coupling module of a continuous-time linear equalizer provided by another embodiment of the present application;

[0047] Figure 4Shows the circuit structure diagram of the linear equalization module of a continuous-time linear equalizer provided by another embodiment of the present application;

[0048] Figure 5 Shows the circuit diagram of the linear equalization module of a continuous-time linear equalizer provided by another embodiment of the present application;

[0049] Figure 6 Shows the circuit diagram of the first load resistor array of the passive load unit provided by another embodiment of the present application;

[0050] Figure 7 Shows the circuit diagram of the second load resistor array of the passive load unit provided by another embodiment of the present application;

[0051] Figure 8 Shows the circuit structure diagram of the negative feedback resistor array of the source negative feedback unit provided by another embodiment of the present application;

[0052] Figure 9 Shows the circuit structure diagram of the negative feedback capacitor array of the source negative feedback unit provided by another embodiment of the present application;

[0053] Figure 10 Shows the circuit structure diagram of the bias network unit provided by another embodiment of the present application;

[0054] Figure 11 Shows the equivalent circuit diagram of the first inductive series peaking sub-unit and the second inductive series peaking sub-unit provided by another embodiment of the present application;

[0055] Figure 12 Shows the schematic layout diagram of the planar spiral inductor wound with the sub-top metal provided by another embodiment of the present application;

[0056] Figure 13a Shows the amplitude-frequency response curve diagram of the linear equalization module under different control codewords of the negative feedback resistor array after inductive series peaking provided by another embodiment of the present application;

[0057] Figure 13b Shows the amplitude-frequency response curve diagram of the linear equalization module under different control codewords of the existing negative feedback resistor array without the inductive series peaking unit provided by another embodiment of the present application. Detailed implementation manners

[0058] Reference is made herein to the various solutions and features of the present application with reference to the accompanying drawings.

[0059] It should be understood that various modifications can be made to the embodiments applied herein. Therefore, the above description should not be construed as a limitation, but only as an example of the embodiments. Those skilled in the art will think of other modifications within the scope and spirit of the present application.

[0060] The drawings included in and forming a part of the specification illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, are used to explain the principles of the present application.

[0061] These and other features of the present application will become apparent from the following description of the preferred forms of the embodiments given by way of non-limiting examples with reference to the drawings.

[0062] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present application.

[0063] When combined with the drawings, the above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description.

[0064] Specific embodiments of the present application will be described hereinafter with reference to the drawings; however, it should be understood that the claimed embodiments are merely examples of the present application and can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present application with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but are merely used as a basis for the claims and a representative basis for teaching those skilled in the art to use the present application in substantially any suitable detailed structure in a variety of ways.

[0065] This specification may use the phrases "in one embodiment", "in another embodiment", "in yet another embodiment" or "in other embodiments", each of which may refer to one or more of the same or different embodiments according to the present application.

[0066] An embodiment of the present application provides a continuous-time linear equalizer 10, as Figure 1 shown, comprising:

[0067] An AC coupling module 20: The input end of the AC coupling module is electrically connected to the output end of the impedance matching module of the receiver, and is configured to receive the differential signal output by the impedance matching module, isolate the DC signal in the differential signal to obtain a differential AC voltage signal, and perform voltage division processing on the voltage signal output by the DC power supply to generate a DC common-mode voltage signal;

[0068] Linear equalization module 30: The input end of the linear equalization module is electrically connected to the output end of the AC coupling module, and the output end of the linear equalization module is electrically connected to the input end of the comparator of the receiver. The linear equalization module is configured to receive the differential AC voltage signal and the DC common-mode voltage signal, amplify the high-frequency signal in the differential AC voltage signal, compensate for the attenuation of the high-frequency signal caused by the low-pass channel, and calibrate the circuit offset voltage based on the DC common-mode voltage signal.

[0069] This application uses an AC coupling module and a linear equalization module to construct a continuous-time linear equalizer. The inductive series peaking technique is used to expand the bandwidth of the circuit without increasing power consumption.

[0070] In the specific implementation process, as Figure 2 shown, the AC coupling module 20 includes: a first AC coupling unit 21. The input end of the first AC coupling unit 21 is electrically connected to the positive output end of the impedance matching module, and the output end of the first AC coupling unit 21 is electrically connected to the positive input end of the linear equalization module 30. It is configured to receive the positive differential signal in the differential voltage signal output by the impedance matching module, process the positive differential signal to obtain the positive output terminal differential AC voltage signal in the differential AC voltage signal, and perform voltage division processing on the DC voltage to generate a positive output terminal DC common-mode voltage signal. A second AC coupling unit 22. The input end of the second AC coupling unit 22 is electrically connected to the negative output end of the impedance matching module 30, and the output end of the second AC coupling unit 22 is electrically connected to the negative input end of the linear equalization module. It is configured to receive the negative differential signal in the differential voltage signal output by the impedance matching module, process the negative differential signal to obtain the negative output terminal differential AC voltage signal in the differential AC voltage signal and perform voltage division processing on the DC voltage to generate a negative output terminal DC common-mode voltage signal.

[0071] In the specific implementation process, as Figure 3 shown: The first AC coupling unit 21 includes: a first isolation capacitor C AC1 , a first voltage dividing resistor R1, a second voltage dividing resistor R3, a third voltage dividing resistor R 15 , a fourth voltage dividing resistor R 17 and a first switch resistor array. Among them, the first end of the first isolation capacitor C AC1 is electrically connected to the positive output end of the impedance matching module, the first end of the first voltage dividing resistor R1 is electrically connected to the positive power supply terminal, and the second end of the first voltage dividing resistor R1 is respectively connected to the first isolation capacitor C ACThe second end of, the first end of the second voltage dividing resistor R3, and the positive input terminal of the linear equalization module 30 are electrically connected. The second end of the second voltage dividing resistor R3 is electrically connected to the first end of the first switch resistor array. The second end of the first switch resistor array is electrically connected to the first end of the third voltage dividing resistor R 15 The second end of the third voltage dividing resistor R 15 is electrically connected to the ground terminal. The first end of the fourth voltage dividing resistor R 17 is electrically connected to the positive input terminal of the linear equalization module. The second end of the fourth voltage dividing resistor R 17 is electrically connected to the ground terminal. Wherein the first switch resistor array includes a plurality of first switches connected in parallel and a first resistor sub-unit. The plurality of first switches and the first resistor sub-unit are connected in series between the second voltage dividing resistor R3 and the third voltage dividing resistor R 15 . Each first switch is electrically connected to the control code terminal for controlling each first switch. For example: the first switch controlling the first resistor R5 is electrically connected to the control code terminal offset_n_<4>; the first switch controlling the first resistor R7 is electrically connected to the control code terminal offset_n_<3>; the first switch controlling the first resistor R9 is electrically connected to the control code terminal offset_n_<2>; the first switch controlling the first resistor R 11 is electrically connected to the control code terminal offset_n_<1>; the first switch controlling the first resistor R 13 is electrically connected to the control code terminal offset_n_<0>.

[0072] In a specific implementation process, the second AC coupling unit includes: a second isolation capacitor C AC2 , a fifth voltage dividing resistor R2, a sixth voltage dividing resistor R4, a seventh voltage dividing resistor R 16 , an eighth voltage dividing resistor R 18 , and a second switch resistor array. Wherein, the first end of the second isolation capacitor C AC2 is electrically connected to the negative output terminal of the impedance matching module. The first end of the fifth voltage dividing resistor R2 is electrically connected to the positive power supply terminal. The second end of the fifth voltage dividing resistor R2 is respectively electrically connected to the second end of the second isolation capacitor, the first end of the sixth voltage dividing resistor R4, and the negative input terminal of the linear equalization module. The second end of the sixth voltage dividing resistor R4 is electrically connected to the first end of the second switch resistor array. The second end of the second switch resistor array is electrically connected to the first end of the seventh voltage dividing resistor R 16 . The second end of the seventh voltage dividing resistor R 16 is electrically connected to the ground terminal. The first end of the eighth voltage dividing resistor R 18 is electrically connected to the negative input terminal of the linear equalization module. The eighth voltage dividing resistor R18 The second end of which is electrically connected to the ground end. The second switching resistor array includes a plurality of second switches connected in parallel and a second resistor sub-unit. The plurality of second switches and the second resistor sub-unit are connected in series between the sixth voltage-dividing resistor R4 and the seventh voltage-dividing resistor R 16 ..., and each second switch is electrically connected to the control code sub-terminal for controlling each second switch; for example: the second switch for controlling the second resistor R6 is electrically connected to the control code sub-terminal offset_p_<4>; the second switch for controlling the second resistor R8 is electrically connected to the control code sub-terminal offset_p_<3>; the second switch for controlling the second resistor R 10 is electrically connected to the control code sub-terminal offset_p_<2>; the second switch for controlling the second resistor R 12 is electrically connected to the control code sub-terminal offset_p_<1>; the second switch for controlling the second resistor R 14 is electrically connected to the control code sub-terminal offset_p_<0>. In the first AC coupling unit and the second AC coupling unit circuits, through the design of the switching resistor array, the common-mode level can be adjusted. At the same time, different control codewords are respectively set at the positive and negative ends of the first AC coupling unit and the second AC coupling unit circuits to realize independent adjustment of the common-mode levels at the positive and negative ends of the linear equalization module. By setting different common-mode levels at the positive and negative ends of the linear equalization module, calibration of the offset voltage of the linear equalization module circuit is realized.

[0073] In the specific implementation process, such as Figure 4As shown, the linear equalization module 30 includes: a passive load unit 301, a differential amplification unit 302, a source negative feedback unit 303, a bias network unit 304, and an inductance series peaking unit 305. Among them, the input end of the differential amplification unit 302 is electrically connected to the output end of the AC coupling module 20, and the output end of the differential amplification unit is connected in series between the passive load unit and the bias network unit, and is used to receive the differential AC voltage signal, the DC common mode voltage signal, and the DC bias current signal of the bias network unit output by the AC coupling module. The differential amplification unit is made to work in the saturation region through the DC common mode voltage signal and the DC bias current signal, and the differential AC voltage signal is converted into a differential AC current signal; the passive load unit 301 is connected between the power input end and the first output end of the differential amplification unit 302 and between the power input end and the second output end of the differential amplification unit 302, and is used to receive the differential AC current signal and convert the differential AC current signal into a differential voltage amplification signal; the source negative feedback unit 303 is connected between the third output end and the fourth output end of the differential amplification unit, and is used to control the signal transfer function of the linear equalization module 30 to generate zero-poles and adjust the positions of the zero-poles to compensate for the loss of the channel; the bias network unit 304 is electrically connected to the source negative feedback unit 303, and is used to adjust the magnitude of the DC bias current signal by controlling the number of conducting MOS transistors in the bias network unit 304; the inductance series peaking unit 305 is electrically connected to the drain output end of the differential amplification unit 302, and is used to reduce the influence of the input parasitic capacitance of the comparator of the receiver on the circuit bandwidth to improve the circuit bandwidth..

[0074] In the specific implementation process, such as Figure 5As shown, the differential amplification unit includes: a first MOS transistor M1 and a second MOS transistor M2. Among them, the gate terminal of the first MOS transistor M1 is electrically connected to the positive output terminal of the AC coupling module 20. The drain terminal of the first MOS transistor M1 is respectively electrically connected to the input terminal of the passive load unit 301 and the first input terminal of the inductive series peaking unit 305. The source terminal of the first MOS transistor M1 is respectively electrically connected to the first input terminal of the bias network unit 304 and the first terminal of the source negative feedback unit 303. The gate terminal of the second MOS transistor M2 is electrically connected to the negative output terminal of the AC coupling module. The drain terminal of the second MOS transistor M2 is respectively electrically connected to the input terminal of the passive load unit 301 and the second input terminal of the inductive series peaking unit 305. The source terminal of the second MOS transistor is electrically connected to the second input terminal of the bias network unit and the second terminal of the source negative feedback unit 303. Among them, the drain terminal of the first MOS transistor M1 serves as the first output terminal of the differential amplification unit. The drain terminal of the second MOS transistor M2 serves as the second output terminal of the differential amplification unit 302. The source terminal of the first MOS transistor M1 serves as the third output terminal of the differential amplification unit 302. The source terminal of the second MOS transistor M2 serves as the fourth output terminal of the differential amplification unit.

[0075] In the specific implementation process, as Figure 5 shown, the passive load unit includes: a first load resistor array R L1 and a second load resistor array R L2 , among which, the first load resistor array R L1 includes a plurality of first load sub-units. Each of the first load sub-units is connected in parallel between the positive power supply terminal and the first output terminal of the differential amplification unit. Each of the first load sub-units includes a third MOS transistor and a first load resistor connected in series. The source terminal of each of the third MOS transistors is electrically connected to the positive power supply terminal. The gate terminal of each of the third MOS transistors is respectively electrically connected to each first control code terminal. The drain terminal of each of the third MOS transistors is electrically connected to the first end of each of the first load resistors. The second end of each of the first load resistors is respectively electrically connected to the first output terminal of the differential amplification unit. Specifically, as Figure 6 shown, it is the first load resistor array R L1 ; among them, M3, M4, M5, M6 are third MOS transistors. In specific applications, the number of third MOS transistors can be set according to actual needs. R 19 , R 20 , R 21 , R 22 are first load resistors. In specific applications, the number of first load sub-units can be set according to actual needs.

[0076] In the specific implementation process, such as Figure 5 shown, the second load resistance array R L2 includes a number of second load sub-units, and each of the second load sub-units is connected in parallel between the positive power supply terminal and the second output terminal of the differential amplification unit. Each of the second load sub-units includes a fourth MOS transistor and a second load resistor connected in series. The source terminal of each of the fourth MOS transistors is electrically connected to the positive power supply terminal, and the gate terminal of each of the fourth MOS transistors is electrically connected to each second control codeword terminal; the drain terminal of each of the fourth MOS transistors is electrically connected to the first end of each of the second load resistors; the second end of each of the second load resistors is electrically connected to the second output terminal of the differential amplification unit. Specifically, as Figure 7 shown, it is the second load resistance array R L2 ; where M 21 |, M 22 , M 23 , M 24 are the fourth MOS transistors. In specific applications, the number of the fourth MOS transistors can be set according to actual needs. R 23 , R 24 , R 25 , R 26 are the second load resistors. In specific applications, the number of the second load sub-units can be set according to actual needs.

[0077] In the specific implementation process, such as Figure 5 shown, the source negative feedback unit 303 includes a negative feedback resistance array R S and a negative feedback capacitance array C S connected in parallel between the third output terminal and the fourth output terminal of the differential amplification unit. Among them, the negative feedback resistance array R S includes a number of load MOS transistors connected in parallel; the source terminal of each of the load MOS transistors is electrically connected to the source terminal of the first MOS transistor, the drain terminal of each of the load MOS transistors is electrically connected to the source terminal of the second MOS transistor, and the gate terminal of each of the load MOS transistors is electrically connected to each third control codeword terminal; specifically, as Figure 8 shown, M7 - M 12 are the load MOS transistors. In specific applications, the number of the load MOS transistors can be set according to actual needs. Rs_ctrl<0>_Rs_ctrl<5> are the third control codeword terminals. Each of the third control codeword terminals can be set in the form of a button, and by manually controlling the third control codeword terminal, the position of the zero-pole generated in the circuit can be adjusted to form different-shaped equalization curves to cope with the changing attenuation characteristics of the channel.

[0078] The negative feedback capacitance array C sIncluding a plurality of negative feedback capacitor sub-units connected in parallel between the third output terminal and the fourth output terminal of the differential amplification unit; as Figure 9 shown, each of the negative feedback capacitor sub-units includes: a first negative feedback MOS transistor M 13 , a second negative feedback MOS transistor M 15 , a third negative feedback MOS transistor M 17 , a fourth negative feedback MOS transistor M 14 , a fifth negative feedback MOS transistor M 16 , a first negative feedback capacitor C1 and a second negative feedback capacitor C2; a first end of the first negative feedback capacitor c1 is electrically connected to the third output terminal of the differential amplification unit, and a second end of the first negative feedback capacitor C1 is electrically connected to the drain terminal of the first negative feedback MOS transistor, the drain terminal of the second negative feedback MOS transistor M 15 and the source terminal of the third negative feedback MOS transistor M 17 ; the source terminal of the first negative feedback MOS transistor is electrically connected to the positive power supply terminal, and the gate terminal of the first negative feedback MOS transistor M 13 is electrically connected to the control codeword terminal C 13 corresponding to the negative feedback capacitor sub-unit where the first negative feedback MOS transistor M s _ctrl<0>; C s _ctrl<0> is the control codeword terminal corresponding to one of the negative feedback capacitor sub-units. This application includes a plurality of negative feedback capacitor sub-units, and the control codeword terminals are C s _ctrl<0>-C s _ctrl<5>. Specifically, the source terminal of the second negative feedback MOS transistor M 15 is electrically connected to the ground terminal, and the gate terminal of the second negative feedback MOS transistor M 15 is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the second negative feedback MOS transistor M 15 is located; the drain terminal of the third negative feedback MOS transistor M 17 is electrically connected to the drain terminal of the fourth negative feedback MOS transistor M 14 , the first end of the second negative feedback capacitor C2 and the drain terminal of the fifth negative feedback MOS transistor, and the gate terminal of the third negative feedback MOS transistor M 17 is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the third negative feedback MOS transistor M 17 is located; the gate terminal of the fourth negative feedback MOS transistor M 17 is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the fourth negative feedback MOS transistor M 14 is located, and the gate terminal of the fourth negative feedback MOS transistor M 14The source extreme of is electrically connected to the positive extreme of the power supply; the second end of the second negative feedback capacitor C2 is electrically connected to the fourth output end of the differential amplification unit; the gate extreme of the fifth negative feedback MOS transistor M 16 is electrically connected to the control codeword end corresponding to the negative feedback capacitor sub-unit where the fifth negative feedback MOS transistor M 16 is located, and the source extreme of the fifth negative feedback MOS transistor M 16 is electrically connected to the ground end.

[0079] In the specific implementation process, as Figure 5 shown, the bias network unit 304 includes a first bias current source I B1 connected between the third output end of the differential amplification unit and the ground end, and a second bias current source I B2 connected between the fourth output end of the differential amplification unit and the ground end, where

[0080] as Figure 10 shown, the first bias current source I B1 includes a plurality of first bias sub-current sources connected in parallel between the third output end of the differential amplification unit and the ground end: each of the first bias sub-current sources includes: a first bias MOS transistor M 18 , a second bias MOS transistor M 20 and a third bias MOS transistor M19; the source extreme of the first bias MOS transistor is electrically connected to the bias module of the receiver, the gate extreme of the first bias MOS transistor M 18 is electrically connected to the first bias control codeword end of the first bias sub-current source where the first bias MOS transistor is located, the drain extreme of the first bias MOS transistor is electrically connected to the drain extreme of the second bias MOS transistor and the gate extreme of the third bias MOS transistor; the gate extreme of the second bias MOS transistor is electrically connected to the second bias control codeword end of the first bias sub-current source where the second bias MOS transistor is located, the source extreme of the second bias MOS transistor is electrically connected to the ground end; the drain extreme of the third bias MOS transistor is electrically connected to the third output end of the differential amplification unit, and the source extreme of the third bias MOS transistor is electrically connected to the ground end; where the first bias control codeword end is Bias_ctrl<0>_H_Bias_ctrl<4>_H; the second bias control codeword end is Bias_ctrl<0>_L_Bias_ctrl<4>_L.

[0081] as Figure 10As shown, the second bias current source includes a plurality of second bias sub-current sources connected in parallel between the fourth output terminal of the differential amplification unit and the ground terminal: each of the second bias sub-current sources includes: a fourth bias MOS transistor, a fifth bias MOS transistor, and a sixth bias MOS transistor; the source terminal of the fourth bias MOS transistor is electrically connected to the bias module of the receiver, the gate terminal of the fourth bias MOS transistor is electrically connected to the third bias control codeword terminal of the second bias sub-current source where the fourth bias MOS transistor is located, and the drain terminal of the fourth bias MOS transistor is electrically connected to the drain terminal of the fifth bias MOS transistor and the gate terminal of the fifth bias MOS transistor; the gate terminal of the fifth bias MOS transistor is electrically connected to the fourth bias control codeword terminal of the first bias sub-current source where the fifth bias MOS transistor is located, and the source terminal of the fifth bias MOS transistor is electrically connected to the ground terminal; the drain terminal of the sixth bias MOS transistor is electrically connected to the fourth output terminal of the differential amplification unit, and the source terminal of the sixth bias MOS transistor is electrically connected to the ground terminal.

[0082] In a specific implementation process, as Figure 5 shown, the inductive series peaking unit 305 includes a first inductive series peaking sub-unit connected between the first output terminal of the differential amplification unit 302 and the negative input terminal of the comparator of the receiver, and a second inductive series peaking sub-unit connected between the second output terminal of the differential amplification unit and the positive input terminal of the comparator of the receiver. Among them, the first inductive series peaking sub-unit includes: a first parasitic capacitor C L1 , a second parasitic capacitor C p1 , and a first inductor L1. The first end of the first parasitic capacitor C L1 is electrically connected to the negative input terminal of the comparator of the receiver and the first end of the first inductor L1. The second end of the first parasitic capacitor C L1 is electrically connected to the ground terminal. The second end of the first inductor L1 is electrically connected to the first end of the second parasitic capacitor C p1 and the first output terminal of the differential amplification unit. The second end of the second parasitic capacitor c p1 is electrically connected to the ground terminal;

[0083] The second inductive series peaking sub-unit includes: a third parasitic capacitor C p2 , a fourth parasitic capacitor C L2 , and a second inductor L2. The first end of the third parasitic capacitor C p2 is electrically connected to the second output terminal of the differential amplification unit and the first end of the second inductor L2. The second end of the third parasitic capacitor C p2 is electrically connected to the ground terminal. The second end of the second inductor L2 is electrically connected to the fourth parasitic capacitor C L2is electrically connected to the first end of and the positive input terminal of the comparator of the receiver, and the second end of the fourth parasitic capacitor C L2 is electrically connected to the ground terminal.

[0084] In the specific implementation process, the equivalent circuit diagrams of the first inductive peaking sub-unit and the second inductive peaking sub-unit are as shown in Figure 11 shown. When considering the parasitic effects of the actual inductor in the design of inductive peaking, the transfer function including the parasitic resistance of the inductor itself is shown in the following formula (1):

[0085] The transfer function is a second-order system, and the natural frequency ω n and the damping coefficient ε are respectively shown in the following formula (2):

[0086]

[0087] When the parasitic resistance of the inductor is 0 and the damping coefficient is 0.707, the circuit has the flattest amplitude-frequency characteristic, and the inductance value of the inductor at this time can be obtained as shown in the following formula (3):

[0088]

[0089] At this time, the bandwidth of the circuit is equal to the natural frequency of the second-order system. Substituting it, the bandwidth of the circuit is shown in the following formula (4):

[0090]

[0091] At this time, the bandwidth of the circuit is expanded to 1.414 times the original. When the parasitic resistance of the inductor is not 0, the numerator of the damping coefficient increases. In order to achieve a damping coefficient of 0.707, the value of the inductor needs to increase. At this time, the natural frequency of the second-order system decreases, and the bandwidth of the circuit decreases, thereby affecting the bandwidth expansion effect of inductive peaking. Therefore, the design of the inductor needs to minimize the parasitic resistance of the inductor coil.

[0092] The present invention proposes a design method for a planar spiral inductor wound with the second top metal layer. By using the thick metal layer of the second top metal layer to replace the ultra-thick metal layer of the top metal layer, the line width and spacing of the traces are reduced to achieve a small-area inductor design; at the same time, using the second top metal layer to replace the bottom metal traces can effectively reduce the parasitic resistance of the inductor coil and achieve a better bandwidth expansion effect. The inductor layout designed in this application is as shown in Figure 12 shown. The main body of the inductor is wound with the second top metal layer. At the intersection of the windings, three layers of bottom metal are used to bypass from below to avoid excessive parasitic resistance. A guard ring is wound around the inductor with the bottommost metal layer to ground, so as to reduce the electromagnetic coupling between the inductor and the nearby circuits.

[0093] The present application uses the "amplitude-frequency response curve of the linear equalization module under different control codewords of the negative feedback resistor array Rs after inductor series peaking" Figure 13a and the amplitude-frequency response curve of the linear equalization module without inductor series peaking Figure 13b for comparison. It can be seen that both the circuit bandwidth and the equalization ability of the present application have been greatly improved. For the amplitude-frequency response curve of the linear equalization module under different control codewords, the coordinates of the highest point of the amplitude-frequency curve of the linear equalization module are shown in the upper right corner, where the abscissa represents the equalization bandwidth of the linear equalization module, and the ordinate represents the highest point of the equalization curve of the linear equalization module. After using the inductor series peaking unit, the coordinates of this point change from (11.2 GHz, 3.38 dB) to (16.7 GHz, 5.68 dB). On the one hand, it shows that the equalization bandwidth of the linear equalization module has become larger, that is, from 11.2 GHz to 16.7 GHz. On the other hand, the highest point of the equalization curve of the linear equalization module has also increased from 3.38 dB to 5.68 dB, indicating that the equalization ability of the linear equalization module has also been improved.

[0094] The present application uses an AC coupling module and a linear equalization module to construct a continuous-time linear equalizer, and uses the inductor series peaking technology to expand the circuit bandwidth without increasing power consumption.

[0095] The above embodiments are only exemplary embodiments of the present application and are not used to limit the present application. The protection scope of the present application is defined by the claims. Those skilled in the art can make various modifications or equivalent replacements within the essence and protection scope of the present application, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of the present application.

Claims

1. A continuous-time linear equalizer, which is arranged in a receiver, is characterized in that Comprising: An AC coupling module: The input end of the AC coupling module is electrically connected to the output end of the impedance matching module of the receiver, and is used to receive the differential signal output by the impedance matching module, isolate the DC signal in the differential signal to obtain a differential AC voltage signal, and perform voltage division processing on the voltage signal output by the DC power supply to generate a DC common-mode voltage signal; A linear equalization module: The input end of the linear equalization module is electrically connected to the output end of the AC coupling module, and the output end of the linear equalization module is electrically connected to the input end of the comparator of the receiver. The linear equalization module is used to receive the differential AC voltage signal and the DC common-mode voltage signal, amplify the high-frequency signal in the differential AC voltage signal, compensate for the attenuation of the high-frequency signal caused by the low-pass channel, and calibrate the circuit offset voltage based on the DC common-mode voltage signal.

2. The continuous-time linear equalizer according to claim 1, characterized in that, The AC coupling module includes: A first AC coupling unit, the input end of the first AC coupling unit is electrically connected to the positive output end of the impedance matching module, and the output end of the first AC coupling unit is electrically connected to the positive input end of the linear equalization module, and is used to receive the positive differential signal in the differential voltage signal output by the impedance matching module, process the positive differential signal to obtain the positive output terminal differential AC voltage signal in the differential AC voltage signal, and perform voltage division processing on the DC voltage to generate a positive output terminal DC common-mode voltage signal; A second AC coupling unit, the input end of the second AC coupling unit is electrically connected to the negative output end of the impedance matching module, and the output end of the second AC coupling unit is electrically connected to the negative input end of the linear equalization module, and is used to receive the negative differential signal in the differential voltage signal output by the impedance matching module, process the negative differential signal to obtain the negative output terminal differential AC voltage signal in the differential AC voltage signal and perform voltage division processing on the DC voltage to generate a negative output terminal DC common-mode voltage signal.

3. The continuous-time linear equalizer according to claim 2, wherein The first AC coupling unit includes: a first isolation capacitor, a first voltage dividing resistor, a second voltage dividing resistor, a third voltage dividing resistor, a fourth voltage dividing resistor, and a first switch resistor array, wherein, The first end of the first isolation capacitor is electrically connected to the positive output end of the impedance matching module, the first end of the first voltage dividing resistor is electrically connected to the positive power supply terminal, the second end of the first voltage dividing resistor is respectively electrically connected to the second end of the first isolation capacitor, the first end of the second voltage dividing resistor, and the positive input end of the linear equalization module, the second end of the second voltage dividing resistor is electrically connected to the first end of the first switch resistor array, the second end of the first switch resistor array is electrically connected to the first end of the third voltage dividing resistor, the second end of the third voltage dividing resistor is electrically connected to the ground terminal, the first end of the fourth voltage dividing resistor is electrically connected to the positive input end of the linear equalization module, and the second end of the fourth voltage dividing resistor is electrically connected to the ground terminal.

4. The continuous-time linear equalizer according to claim 2, characterized in that, The second AC coupling unit includes: a second isolation capacitor, a fifth voltage-dividing resistor, a sixth voltage-dividing resistor, a seventh voltage-dividing resistor, an eighth voltage-dividing resistor, and a second switch resistor array, where, The first end of the second isolation capacitor is electrically connected to the negative output end of the impedance matching module. The first end of the fifth voltage-dividing resistor is electrically connected to the positive power supply terminal. The second end of the fifth voltage-dividing resistor is respectively electrically connected to the second end of the second isolation capacitor, the first end of the sixth voltage-dividing resistor, and the negative input end of the linear equalization module. The second end of the sixth voltage-dividing resistor is electrically connected to the first end of the second switch resistor array. The second end of the second switch resistor array is electrically connected to the first end of the seventh voltage-dividing resistor. The second end of the seventh voltage-dividing resistor is electrically connected to the ground terminal. The first end of the eighth voltage-dividing resistor is electrically connected to the negative input end of the linear equalization module. The second end of the eighth voltage-dividing resistor is electrically connected to the ground terminal.

5. The continuous-time linear equalizer according to claim 1, wherein The linear equalization module includes: a passive load unit, a differential amplification unit, a source negative feedback unit, a bias network unit, and an inductance series peaking unit, where, A differential amplification unit, the input end of the differential amplification unit is electrically connected to the output end of the AC coupling module. The output end of the differential amplification unit is connected in series between the passive load unit and the bias network unit, and is used to receive the differential AC voltage signal, the DC common-mode voltage signal, and the DC bias current signal of the bias network unit output by the AC coupling module. The differential amplification unit is made to work in the saturation region through the DC common-mode voltage signal and the DC bias current signal, and the differential AC voltage signal is converted into a differential AC current signal; A passive load unit, the passive load unit is connected between the power input terminal and the first output terminal of the differential amplification unit and between the power input terminal and the second output terminal of the differential amplification unit, and is used to receive the differential AC current signal and convert the differential AC current signal into a differential voltage amplification signal; A source negative feedback unit, the source negative feedback unit is connected between the third output terminal and the fourth output terminal of the differential amplification unit, and is used to control the signal transfer function of the linear equalization module to generate zero-poles and adjust the zero-pole positions to compensate for the loss of the channel; A bias network unit, the bias network unit is electrically connected to the source negative feedback unit, and is used to adjust the magnitude of the DC bias current signal by controlling the number of conducting MOS transistors in the bias network unit; An inductance series peaking unit, the inductance series peaking unit is electrically connected to the drain output terminal of the differential amplification unit, and is used to reduce the influence of the input parasitic capacitance of the comparator of the receiver on the circuit bandwidth to improve the circuit bandwidth.

6. The continuous-time linear equalizer according to claim 5, wherein, The differential amplification unit includes: a first MOS transistor and a second MOS transistor, where, The gate terminal of the first MOS transistor is electrically connected to the positive output terminal of the AC coupling module. The drain terminal of the first MOS transistor is electrically connected to the input terminal of the passive load unit and the first input terminal of the inductive series peaking unit respectively. The source terminal of the first MOS transistor is electrically connected to the first input terminal of the bias network unit and the first terminal of the source negative feedback unit respectively; The gate terminal of the second MOS transistor is electrically connected to the negative output terminal of the AC coupling module. The drain terminal of the second MOS transistor is electrically connected to the input terminal of the passive load unit and the second input terminal of the inductive series peaking unit respectively. The source terminal of the second MOS transistor is electrically connected to the second input terminal of the bias network unit and the second terminal of the source negative feedback unit respectively; Wherein, the drain terminal of the first MOS transistor serves as the first output terminal of the differential amplification unit, the drain terminal of the second MOS transistor serves as the second output terminal of the differential amplification unit, the source terminal of the first MOS transistor serves as the third output terminal of the differential amplification unit, and the source terminal of the second MOS transistor serves as the fourth output terminal of the differential amplification unit.

7. The continuous-time linear equalizer according to claim 6, wherein The passive load unit includes: a first load resistor array and a second load resistor array, wherein, The first load resistor array includes a plurality of first load sub-units. Each of the first load sub-units is connected in parallel between the positive power supply terminal and the first output terminal of the differential amplification unit. Each of the first load sub-units includes a third MOS transistor and a first load resistor connected in series. The source terminal of each of the third MOS transistors is electrically connected to the positive power supply terminal. The gate terminal of each of the third MOS transistors is electrically connected to each first control codeword terminal respectively; the drain terminal of each of the third MOS transistors is electrically connected to the first terminal of each of the first load resistors; the second terminal of each of the first load resistors is electrically connected to the first output terminal of the differential amplification unit respectively; The second load resistor array includes a plurality of second load sub-units. Each of the second load sub-units is connected in parallel between the positive power supply terminal and the second output terminal of the differential amplification unit. Each of the second load sub-units includes a fourth MOS transistor and a second load resistor connected in series. The source terminal of each of the fourth MOS transistors is electrically connected to the positive power supply terminal. The gate terminal of each of the fourth MOS transistors is electrically connected to each second control codeword terminal respectively; the drain terminal of each of the fourth MOS transistors is electrically connected to the first terminal of each of the second load resistors; the second terminal of each of the second load resistors is electrically connected to the second output terminal of the differential amplification unit respectively.

8. The continuous-time linear equalizer according to claim 6, wherein The source negative feedback unit includes a negative feedback resistor array and a negative feedback capacitor array connected in parallel between the third output terminal and the fourth output terminal of the differential amplification unit, wherein, The negative feedback resistor array includes a plurality of load MOS transistors connected in parallel; the source terminal of each of the load MOS transistors is electrically connected to the source terminal of the first MOS transistor, the drain terminal of each of the load MOS transistors is electrically connected to the source terminal of the second MOS transistor, and the gate terminal of each of the load MOS transistors is electrically connected to each third control codeword terminal respectively; The negative feedback capacitor array includes a plurality of negative feedback capacitor sub-units connected in parallel between the third output terminal and the fourth output terminal of the differential amplification unit; each of the negative feedback capacitor sub-units includes: a first negative feedback MOS transistor, a second negative feedback MOS transistor, a third negative feedback MOS transistor, a fourth negative feedback MOS transistor, a fifth negative feedback MOS transistor, a first negative feedback capacitor, and a second negative feedback capacitor; a first end of the first negative feedback capacitor is electrically connected to the third output terminal of the differential amplification unit, and a second end of the first negative feedback capacitor is electrically connected to the drain terminal of the first negative feedback MOS transistor, the drain terminal of the second negative feedback MOS transistor, and the source terminal of the third negative feedback MOS transistor; the source terminal of the first negative feedback MOS transistor is electrically connected to the positive power supply terminal, and the gate terminal of the first negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the first negative feedback MOS transistor is located; the source terminal of the second negative feedback MOS transistor is electrically connected to the ground terminal, and the gate terminal of the second negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the second negative feedback MOS transistor is located; the drain terminal of the third negative feedback MOS transistor is electrically connected to the drain terminal of the fourth negative feedback MOS transistor, the first end of the second negative feedback capacitor, and the drain terminal of the fifth negative feedback MOS transistor, and the gate terminal of the third negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the third negative feedback MOS transistor is located; the gate terminal of the fourth negative feedback MOS transistor is electrically connected to the control codeword terminal corresponding to the negative feedback capacitor sub-unit where the fourth negative feedback MOS transistor is located, and the source terminal of the fourth negative feedback MOS transistor is electrically connected to the positive power supply terminal; a second end of the second negative feedback capacitor is electrically connected to the fourth output terminal of the differential amplification unit; the gate terminal of the fifth negative feedback MOS transistor is electrically connected to the control codeword corresponding to the negative feedback capacitor sub-unit where the fifth negative feedback MOS transistor is located, and the source terminal of the fifth negative feedback MOS transistor is electrically connected to the ground terminal.

9. The continuous-time linear equalizer according to claim 6, wherein The bias network unit includes a first bias current source connected between the third output terminal of the differential amplification unit and the ground terminal and a second bias current source connected between the fourth output terminal of the differential amplification unit and the ground terminal, where, The first bias current source includes a plurality of first bias sub-current sources connected in parallel between the third output terminal of the differential amplification unit and the ground terminal: each of the first bias sub-current sources includes: a first bias MOS transistor, a second bias MOS transistor, and a third bias MOS transistor; the source terminal of the first bias MOS transistor is electrically connected to the bias module of the receiver, the gate terminal of the first bias MOS transistor is electrically connected to the first bias control codeword terminal of the first bias sub-current source where the first bias MOS transistor is located, and the drain terminal of the first bias MOS transistor is electrically connected to the drain terminal of the second bias MOS transistor and the gate terminal of the third bias MOS transistor; the gate terminal of the second bias MOS transistor is electrically connected to the second bias control codeword terminal of the first bias sub-current source where the second bias MOS transistor is located, the source terminal of the second bias MOS transistor is electrically connected to the ground terminal; the drain terminal of the third bias MOS transistor is electrically connected to the third output terminal of the differential amplification unit, and the source terminal of the third bias MOS transistor is electrically connected to the ground terminal; The second bias current source includes a plurality of second bias sub-current sources connected in parallel between the fourth output terminal of the differential amplification unit and the ground terminal: each of the second bias sub-current sources includes: a fourth bias MOS transistor, a fifth bias MOS transistor, and a sixth bias MOS transistor; the source terminal of the fourth bias MOS transistor is electrically connected to the bias module of the receiver, the gate terminal of the fourth bias MOS transistor is electrically connected to the third bias control codeword terminal of the second bias sub-current source where the fourth bias MOS transistor is located, and the drain terminal of the fourth bias MOS transistor is electrically connected to the drain terminal of the fifth bias MOS transistor and the gate terminal of the fifth bias MOS transistor; the gate terminal of the fifth bias MOS transistor is electrically connected to the fourth bias control codeword terminal of the first bias sub-current source where the fifth bias MOS transistor is located, the source terminal of the fifth bias MOS transistor is electrically connected to the ground terminal; the drain terminal of the sixth bias MOS transistor is electrically connected to the fourth output terminal of the differential amplification unit, and the source terminal of the sixth bias MOS transistor is electrically connected to the ground terminal.

10. The continuous-time linear equalizer according to claim 6, wherein The inductive series peaking unit includes a first inductive series peaking sub-unit connected between the first output terminal of the differential amplification unit and the negative input terminal of the comparator of the receiver and a second inductive series peaking sub-unit connected between the second output terminal of the differential amplification unit and the positive input terminal of the comparator of the receiver, where, The first inductive series peaking sub-unit includes: a first parasitic capacitor, a second parasitic capacitor, and a first inductor. The first end of the first parasitic capacitor is electrically connected to the negative input terminal of the comparator of the receiver and the first end of the first inductor. The second end of the first parasitic capacitor is electrically connected to the ground terminal. The second end of the first inductor is electrically connected to the first end of the second parasitic capacitor and the first output terminal of the differential amplification unit. The second end of the second parasitic capacitor is electrically connected to the ground terminal; The second inductive peaking sub-unit includes: a third parasitic capacitor, a fourth parasitic capacitor, and a second inductor. A first end of the third parasitic capacitor is electrically connected to a second output end of the differential amplification unit and a first end of the second inductor. A second end of the third parasitic capacitor is electrically connected to a ground terminal. A second end of the second inductor is electrically connected to a first end of the fourth parasitic capacitor and a positive input terminal of a comparator of the receiver. A second end of the fourth parasitic capacitor is electrically connected to the ground terminal.

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