Capacitor structure and manufacturing method thereof

Abstract

The invention discloses a capacitor structure and a manufacturing method thereof, and the capacitor structure comprises a substrate which is provided with a first surface, a groove structure is formed on the first surface, the groove structure at least comprises a first side wall which is obliquely arranged relative to the first surface, and a groove is formed in the inner wall of the groove structure; the layer stacking structure comprises odd electrode layers and even electrode layers which are alternately stacked and dielectric layers formed between the odd electrode layers and the even electrode layers, and the layer stacking structure covers the first surface, the inner walls of the groove structures and the inner walls of the grooves; a first insulating layer covering the layer stack structure; and the metal interconnection layer is formed on the first insulating layer and comprises a first metal interconnection layer electrically connected with the odd-numbered electrode layers and a second metal interconnection layer electrically connected with the substrate and / or the even-numbered electrode layers. According to the capacitor structure and the manufacturing method thereof, the crosstalk and the manufacturing difficulty can be reduced while the capacitance density is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a capacitor structure and a manufacturing method thereof. Background Art

[0002] As an important passive device in integrated circuits, the capacitance density and manufacturing process of silicon capacitors directly affect the performance and integration of devices. Traditional silicon capacitors usually adopt a planar structure or a simple deep trench structure, and their capacitance density is limited by the substrate surface area, and the manufacturing process is complex, and the electrode crosstalk is relatively large.

[0003] In the prior art, although there are some methods to increase the capacitance density by increasing the surface area, such as multi-layer stacking structures or complex deep trench etching, these methods often have problems such as complex manufacturing processes, large electrode crosstalk, and high etching difficulty.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a capacitor structure and a manufacturing method thereof, which can increase the capacitance density while reducing crosstalk and manufacturing difficulty.

[0006] In order to achieve the above purpose, the technical solutions provided by a specific embodiment of the present invention are as follows:

[0007] A capacitor structure, comprising:

[0008] A substrate having a first surface, on which a groove structure is formed, the groove structure at least includes a first sidewall inclined relative to the first surface, and a groove is formed on the inner wall of the groove structure;

[0009] A layer stacking structure, including an odd electrode layer and an even electrode layer stacked alternately and a dielectric layer formed between the odd electrode layer and the even electrode layer, the layer stacking structure covers the first surface, the inner wall of the groove structure and the inner wall of the groove;

[0010] A first insulating layer covering the layer stacking structure; and

[0011] A metal interconnection layer formed on the first insulating layer, the metal interconnection layer includes a first metal interconnection layer electrically connected to the odd electrode layer, and a second metal interconnection layer electrically connected to the substrate and / or the even electrode layer.

[0012] In one or more embodiments of the present invention, the included angle between the first sidewall of the groove structure and the first surface is an obtuse angle.

[0013] In one or more embodiments of the present invention, a first via hole exposing the odd-numbered electrode layer and a second via hole exposing the substrate and / or the even-numbered electrode layer are formed on the first insulating layer. The first metal interconnect layer is electrically connected to the odd-numbered electrode layer through the first via hole, and the second metal interconnect layer is electrically connected to the substrate and / or the even-numbered electrode layer through the second via hole.

[0014] In one or more embodiments of the present invention, the depth of the first via hole exposing the odd-numbered electrode layer located in the upper layer in the first insulating layer is greater than the depth of the first via hole exposing the odd-numbered electrode layer located in the lower layer in the first insulating layer;

[0015] The depth of the second via hole exposing the even-numbered electrode layer located in the upper layer in the first insulating layer is greater than the depth of the second via hole exposing the even-numbered electrode layer located in the lower layer in the first insulating layer;

[0016] In adjacent odd-numbered and even-numbered electrode layers, the depth of the second via hole exposing the even-numbered electrode layer located in the upper layer in the first insulating layer is greater than the depth of the first via hole exposing the odd-numbered electrode layer located in the lower layer in the first insulating layer.

[0017] In one or more embodiments of the present invention, the trench structure further includes a bottom wall.

[0018] In one or more embodiments of the present invention, grooves are formed on the bottom wall and / or the first side wall of the trench structure.

[0019] In one or more embodiments of the present invention, the layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer that are sequentially stacked;

[0020] In the depth direction of the trench structure, the first side wall of the trench structure sequentially includes a first region and a second region in a direction away from the first surface;

[0021] A first via hole exposing the first electrode layer is formed in the first insulating layer of the first region of the first side wall;

[0022] A first via hole exposing the third electrode layer is formed in the first insulating layer in the region where the bottom wall of the trench structure is located;

[0023] A second via hole exposing the substrate is formed in the first insulating layer on the first surface of the substrate;

[0024] A second via hole exposing the second electrode layer is formed in the first insulating layer of the second region of the first side wall;

[0025] Alternatively, the layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, a third dielectric layer, and a fourth electrode layer that are stacked in sequence;

[0026] In the depth direction of the groove structure, the first sidewall of the groove structure sequentially includes a first region and a second region in a direction away from the first surface;

[0027] A first through hole exposing the first electrode layer is formed in the first insulating layer on the first surface of the substrate;

[0028] A first through hole exposing the third electrode layer is formed in the first insulating layer in the second region of the first sidewall;

[0029] A second through hole exposing the second electrode layer is formed in the first insulating layer in the first region of the first sidewall;

[0030] A second through hole exposing the fourth electrode layer is formed in the first insulating layer in the region where the bottom wall of the groove structure is located.

[0031] In one or more embodiments of the present invention, the groove structure further includes a second sidewall opposite to the first sidewall, and the second sidewall is inclined relative to the first surface.

[0032] In one or more embodiments of the present invention, the included angle between the second sidewall of the groove structure and the first surface is an obtuse angle.

[0033] In one or more embodiments of the present invention, the groove structure further includes a bottom wall located between the first sidewall and the second sidewall.

[0034] In one or more embodiments of the present invention, grooves are formed on the first sidewall and / or the second sidewall and / or the bottom wall of the groove structure.

[0035] In one or more embodiments of the present invention, the layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer that are stacked in sequence;

[0036] In the depth direction of the groove structure, the first sidewall of the groove structure sequentially includes a first region and a second region in a direction away from the first surface, and the second sidewall of the groove structure includes a third region corresponding to the first region and a fourth region corresponding to the second region;

[0037] A first through hole exposing the first electrode layer is formed in the first insulating layer in the third region of the second sidewall;

[0038] A first through-hole exposing the third electrode layer is formed in the first insulating layer in the region where the bottom wall of the groove structure is located;

[0039] A second through-hole exposing the substrate is formed in the first insulating layer on the first surface of the substrate;

[0040] A second through-hole exposing the second electrode layer is formed in the first insulating layer in the second region of the first side wall and / or the fourth region of the second side wall;

[0041] Alternatively, the layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, a third dielectric layer, and a fourth electrode layer that are sequentially stacked;

[0042] In the depth direction of the groove structure, the first side wall of the groove structure sequentially includes a first region and a second region in a direction away from the first surface, and the second side wall of the groove structure includes a third region corresponding to the first region and a fourth region corresponding to the second region;

[0043] A first through-hole exposing the first electrode layer is formed in the first insulating layer on the first surface of the substrate;

[0044] A first through-hole exposing the third electrode layer is formed in the first insulating layer in the second region of the first side wall and / or the fourth region of the second side wall;

[0045] A second through-hole exposing the second electrode layer is formed in the first insulating layer in the third region of the second side wall;

[0046] A second through-hole exposing the fourth electrode layer is formed in the first insulating layer in the region where the bottom wall of the groove structure is located.

[0047] In one or more embodiments of the present invention, a second insulating layer is further provided between the first surface of the substrate and the layer stack structure.

[0048] In one or more embodiments of the present invention, a plurality of the groove structures are arranged periodically on the first surface of the substrate.

[0049] A manufacturing method of a capacitor structure includes:

[0050] Providing a substrate having a first surface;

[0051] Forming a groove structure on the first surface, the groove structure including a first side wall inclined relative to the first surface;

[0052] Forming a groove on the inner wall of the groove structure;

[0053] A layer stack structure covering the first surface, the inner wall of the groove structure, and the inner wall of the trench is formed. The layer stack structure includes alternately stacked odd electrode layers and even electrode layers, and dielectric layers formed between the odd electrode layers and the even electrode layers;

[0054] A first insulating layer covering the layer stack structure is formed;

[0055] Holes are opened in the first insulating layer, and a first metal interconnect layer electrically connected to the odd electrode layer and a second metal interconnect layer electrically connected to the substrate and / or the even electrode layer are formed on the first insulating layer.

[0056] In one or more embodiments of the present invention, the groove structure is formed by a wet etching process or a dry etching process; and / or,

[0057] A plurality of groove structures arranged periodically are formed on the first surface.

[0058] In one or more embodiments of the present invention, the groove structure further includes a bottom wall;

[0059] Forming a trench on the inner wall of the groove structure includes:

[0060] Forming a trench at least on the first side wall and / or the bottom wall of the groove structure.

[0061] In one or more embodiments of the present invention, the first side wall of the groove structure includes a first region close to the first surface and a second region close to the bottom wall;

[0062] Opening holes in the first insulating layer includes:

[0063] Opening a first through hole exposing the odd electrode layer in the first insulating layer in the first region of the first side wall and in the first insulating layer in the region where the bottom wall of the groove structure is located;

[0064] Opening a second through hole exposing the substrate and / or the even electrode layer in the first insulating layer on the first surface of the substrate and in the first insulating layer in the second region of the first side wall.

[0065] In one or more embodiments of the present invention, the groove structure includes a second side wall opposite to the first side wall, and the second side wall is inclined relative to the first surface;

[0066] Forming a trench on the inner wall of the groove structure includes:

[0067] Forming a trench at least on the second side wall of the groove structure.

[0068] In one or more embodiments of the present invention, the first sidewall of the groove structure includes a first region disposed close to the first surface and a second region disposed close to the bottom wall, and the second sidewall of the groove structure includes a third region corresponding to the first region and a fourth region corresponding to the second region;

[0069] Opening holes in the first insulating layer includes:

[0070] Opening first through-holes exposing the odd-numbered electrode layers in the first insulating layer in the third region of the second sidewall and in the first insulating layer in the region where the bottom wall of the groove structure is located;

[0071] Opening second through-holes exposing the substrate and / or the even-numbered electrode layers in the first insulating layer in the second region of the first sidewall and / or the fourth region of the second sidewall and in the first insulating layer on the first surface of the substrate.

[0072] In one or more embodiments of the present invention, the depth of the first through-holes exposing the odd-numbered electrode layers in the upper layer in the first insulating layer is greater than the depth of the first through-holes exposing the odd-numbered electrode layers in the lower layer in the first insulating layer;

[0073] The depth of the second through-holes exposing the even-numbered electrode layers in the upper layer in the first insulating layer is greater than the depth of the second through-holes exposing the even-numbered electrode layers in the lower layer in the first insulating layer;

[0074] In adjacent odd-numbered electrode layers and even-numbered electrode layers, the depth of the second through-holes exposing the even-numbered electrode layers in the upper layer in the first insulating layer is greater than the depth of the first through-holes exposing the odd-numbered electrode layers in the lower layer in the first insulating layer.

[0075] In one or more embodiments of the present invention, the etching depth difference between the first through-holes and the second through-holes in the first insulating layer is used to compensate for the etching rate difference caused by different materials of the electrode layers and the dielectric layers, so as to complete the etching of the first through-holes and the second through-holes in the same time in a synchronous etching process.

[0076] In one or more embodiments of the present invention, forming a first metal interconnection layer electrically connected to the odd-numbered electrode layers and a second metal interconnection layer electrically connected to the substrate and / or the even-numbered electrode layers on the first insulating layer includes:

[0077] Forming a metal interconnection layer on the first insulating layer, and patterning the metal interconnection layer to form electrically isolated first and second metal interconnection layers.

[0078] In one or more embodiments of the present invention, after the step of forming a groove on the first sidewall of the groove structure, it further includes the step of forming a second insulating layer covering the first surface, the inner wall of the groove structure, and the inner wall of the groove.

[0079] Compared with the prior art, the capacitor structure and its manufacturing method of the present invention combine a groove structure and a groove within the groove structure to further increase the specific surface area and significantly improve the capacitance density.

[0080] The capacitor structure and its manufacturing method of the present invention use the same-layer metal interconnection to separately lead out the even electrode layer and / or the substrate, and the odd electrode layer, reducing the crosstalk between the electrodes, simplifying the manufacturing process, and improving the manufacturability.

[0081] The capacitor structure and its manufacturing method of the present invention, through the setting of the groove structure, utilize the height difference to compensate for the etching rate difference caused by different layer structure materials, achieve the same-time synchronous etching to complete the opening of CT (contact holes), optimize the CT opening, reduce the process difficulty, and improve the etching accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0083] Figure 1 It is a partial top view of the capacitor structure in Embodiment 1 of the present invention;

[0084] Figure 2 It is a cross-sectional view taken along line A-A of the capacitor structure in Embodiment 1 of the present invention;

[0085] Figures 3a - 3e It is a process step diagram of the manufacturing method of the capacitor structure in Embodiment 1 of the present invention;

[0086] Figure 4 It is a partial top view of the capacitor structure in Embodiment 2 of the present invention;

[0087] Figure 5 It is a cross-sectional view taken along line B-B of the capacitor structure in Embodiment 2 of the present invention;

[0088] Figure 6 It is a cross-sectional view taken along line C-C of the capacitor structure in Embodiment 2 of the present invention;

[0089] Figure 7 It is a partial cross-sectional view of the capacitor structure in Embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0090] To enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0091] The present invention provides a capacitive structure, including:

[0092] A substrate having a first surface, on which a groove structure is formed. The groove structure at least includes a first sidewall inclined relative to the first surface, and a groove is formed on the inner wall of the groove structure;

[0093] A layer stack structure including alternately stacked odd-numbered electrode layers and even-numbered electrode layers and a dielectric layer formed between the odd-numbered electrode layers and the even-numbered electrode layers. The layer stack structure covers the first surface, the inner wall of the groove structure, and the inner wall of the groove;

[0094] A first insulating layer covering the layer stack structure; and

[0095] A metal interconnect layer formed on the first insulating layer. The metal interconnect layer includes a first metal interconnect layer electrically connected to the odd-numbered electrode layer, and a second metal interconnect layer electrically connected to the substrate and / or the even-numbered electrode layer.

[0096] In one embodiment, the groove structure further includes a second sidewall opposite to the first sidewall, and the second sidewall is inclined relative to the first surface.

[0097] In one embodiment, the angle between the first sidewall of the groove structure and the first surface is an obtuse angle, and the angle between the second sidewall of the groove structure and the first surface is an obtuse angle.

[0098] In one embodiment, the groove structure further includes a bottom wall located between the first sidewall and the second sidewall.

[0099] In one embodiment, the groove is provided on the first sidewall and / or the second sidewall and / or the bottom wall.

[0100] In one embodiment, a second insulating layer is further provided between the first surface of the substrate and the layer stack structure.

[0101] In one embodiment, a first via hole exposing the odd-numbered electrode layer and a second via hole exposing the substrate and / or the even-numbered electrode layer are formed on the first insulating layer. The first metal interconnection layer is electrically connected to the odd-numbered electrode layer through the first via hole, and the second metal interconnection layer is electrically connected to the substrate and / or the even-numbered electrode layer through the second via hole. The depth of the first via hole exposing the odd-numbered electrode layer in the upper layer in the first insulating layer is greater than the depth of the first via hole exposing the odd-numbered electrode layer in the lower layer in the first insulating layer; the depth of the second via hole exposing the even-numbered electrode layer in the upper layer in the first insulating layer is greater than the depth of the second via hole exposing the even-numbered electrode layer in the lower layer in the first insulating layer; in adjacent odd-numbered and even-numbered electrode layers, the depth of the second via hole exposing the even-numbered electrode layer in the upper layer in the first insulating layer is greater than the depth of the first via hole exposing the odd-numbered electrode layer in the lower layer in the first insulating layer.

[0102] In the above embodiment, due to the presence of the groove structure, the first via hole and the second via hole can be etched synchronously within the same time, simplifying the process steps.

[0103] The capacitor structure of the present invention combines the groove structure and the grooves in the groove structure to further increase the specific surface area and significantly improve the capacitance density; the even-numbered electrode layer and / or the substrate and the odd-numbered electrode layer are respectively led out by the same-layer metal interconnection, reducing the crosstalk between the electrodes, simplifying the manufacturing process, and improving the manufacturability; through the setting of the groove structure, the height difference is used to make up for the etching rate difference caused by different layer structure materials, realizing the synchronous etching of the CT (contact hole) opening within the same time, optimizing the CT opening, reducing the process difficulty, and improving the etching accuracy.

[0104] The present invention also provides a method for manufacturing a capacitor structure, including:

[0105] Providing a substrate having a first surface;

[0106] Forming a groove structure on the first surface, the groove structure including a first side wall inclined relative to the first surface;

[0107] Forming grooves on the inner wall of the groove structure;

[0108] Forming a layer stack structure covering the first surface, the inner wall of the groove structure, and the inner wall of the grooves, the layer stack structure including alternately stacked odd-numbered and even-numbered electrode layers and a dielectric layer formed between the odd-numbered and even-numbered electrode layers;

[0109] Forming a first insulating layer covering the layer stack structure;

[0110] Opening holes in the first insulating layer, and forming a first metal interconnection layer electrically connected to the odd-numbered electrode layer and a second metal interconnection layer electrically connected to the substrate and / or the even-numbered electrode layer on the first insulating layer.

[0111] The present invention will be further described below with specific examples.

[0112] Example 1:

[0113] As Figures 1 to 2 shown, the capacitor structure in this embodiment includes a substrate 10, a second insulating layer 20, a layer stack structure 30, a first insulating layer 40, and a metal interconnect layer 50.

[0114] The substrate 10 is selected from a highly doped (such as boron-doped or phosphorus-doped) silicon substrate or a polysilicon substrate. Among them, the doping depth can be about 3 μm - 5 μm from the substrate surface into the substrate interior. Alternatively, the substrate 10 is selected from a low-resistance substrate, such as a gallium arsenide substrate (GaAs), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), etc. The resistivity of the substrate 10 is 10 -3 -10 -1 Ω·cm. The low-resistivity substrate 10 can act as the bottom electrode of the capacitor structure, further improving the capacitance density of the capacitor structure.

[0115] The substrate 10 has a first surface 10a. A groove structure 11 is formed on the first surface 10a of the substrate 10. The number of groove structures 11 can be multiple, and they are arranged periodically on the first surface 10a of the substrate 10. The depth of the groove structure 11 is 1 μm - 10 μm, and the spacing (period) between adjacent groove structures 11 is 0.5 μm - 5 μm. Deep trenches 12 are formed on the inner walls of one or more groove structures 11.

[0116] It can be understood that in other embodiments, the depth and spacing of the groove structure 11 can be optimized according to the capacitance density requirements. The deep trenches 12 can also be formed on the first surface 10a of the substrate 10 simultaneously or only.

[0117] In this embodiment, the groove structure 11 includes a first sidewall 111 and a second sidewall 112 that are oppositely arranged, and a bottom wall 113 located between the first sidewall 111 and the second sidewall 112. The first sidewall 111 is inclined relative to the first surface 10a, and the angle α1 between the first sidewall 111 and the first surface 10a is an obtuse angle. The second sidewall 112 is also inclined relative to the first surface 10a, and the angle α2 between the second sidewall 112 and the first surface 10a is also an obtuse angle, as Figure 3a shown.

[0118] In this embodiment, in the depth direction of the groove structure 11, the first sidewall 111 of the groove structure 11 sequentially includes a first region 111a and a second region 111b in a direction away from the first surface 10a. The second sidewall 112 of the groove structure 11 includes a third region 112a corresponding to the first region 111a and a fourth region 112b corresponding to the second region 111b. The division of the first region 111a, the second region 111b, the third region 112a, and the fourth region 112b enables the through holes for electrode lead-out formed in different regions to have different depths in the subsequently deposited first insulating layer 40. In the depth direction of the groove structure 11, the etching time required for the depth difference of adjacent through holes in the first insulating layer 40 can be compensated by using the etching rate of the multiple layer structures (electrode layer, dielectric layer, second insulating layer) that need to be etched in the through hole with a relatively smaller depth among the two; or rather, the etching depth difference of adjacent through holes in the first insulating layer 40 is used to compensate for the etching rate difference caused by the different materials of the electrode layer, the dielectric layer, and the second insulating layer, so as to synchronize the etching time.

[0119] Deep grooves 12 are formed on the first sidewall 111 and / or the second sidewall 112 and / or the bottom wall 113 of the groove structure 11. The depth of the deep grooves 12 is 5 μm - 50 μm, and the width of the deep grooves 12 is 0.5 μm - 5 μm.

[0120] The second insulating layer 20 covers the first surface 10a of the substrate 10, the inner walls of the groove structure 11, and the inner walls of the deep grooves 12. The material of the second insulating layer 20 may include but is not limited to SiO2 and Si3N4. When the substrate 10 is used as a bottom electrode, the second insulating layer 20 can be used as a capacitive dielectric layer. The thickness of the second insulating layer 20 is 5 nm - 50 nm.

[0121] The layer stack structure 30 includes alternately stacked odd-numbered electrode layers and even-numbered electrode layers and a dielectric layer 33 formed between the odd-numbered electrode layers and the even-numbered electrode layers. The materials of the odd-numbered electrode layers and the even-numbered electrode layers include but are not limited to polysilicon or metal, and the material of the dielectric layer 33 includes but is not limited to SiO2 or Si3N4. The layer stack structure 30 is formed on the surface of the second insulating layer 20 and also covers the first surface 10a of the substrate 10, the inner walls of the groove structure 11, and the inner walls of the deep grooves 12.

[0122] In this embodiment, the layer stack structure 30 includes a first electrode layer 31a, a first dielectric layer, a second electrode layer 32a, a second dielectric layer, and a third electrode layer 31b stacked in sequence. The first electrode layer 31a and the second electrode layer 32a are odd-numbered electrode layers; the second electrode layer 32a is an even-numbered electrode layer.

[0123] The first insulating layer 40 covers the layer stack structure 30. The material of the first insulating layer 40 may include, but is not limited to, SiO2, Si3N4, High-k materials (high dielectric constant materials such as hafnium oxide - HfO2, zirconium oxide - ZrO2, aluminum oxide - Al2O3, etc.), and polymer materials (polyimide - PI, benzocyclobutene BCB, etc.).

[0124] A first via 41 exposing the odd - numbered electrode layer and a second via 42 exposing the substrate 10 and the even - numbered electrode layer are formed on the first insulating layer 40.

[0125] In this embodiment, a first via 41a exposing the first electrode layer 31a is formed in the first insulating layer 40, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, and the first dielectric layer in the third region 112a of the second sidewall 112 of the trench structure 11; a first via 41b exposing the third electrode layer 31b is formed in the first insulating layer 40 in the region where the bottom wall 113 of the trench structure 11 is located; a second via 42a exposing the substrate 10 is formed in the first insulating layer 40, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, the first dielectric layer, and the first electrode layer 31a on the first surface 10a of the substrate 10; a second via 42b exposing the second electrode layer 32a is formed in the first insulating layer 40, the third electrode layer 31b, and the second dielectric layer in the second region 111b of the first sidewall 111 of the trench structure 11, as Figure 3e shown.

[0126] It can be understood that deep trenches 12 may be formed in the first surface 10a of the substrate 10, the first region 111a and the second region 111b of the first sidewall 111, the third region 112a and the fourth region 112b of the second sidewall 112. The opening positions of the first via 41 and the second via 42 are preferably avoided from the positions where the deep trenches 12 are located.

[0127] In the above embodiments, the depth of the first via hole 41b exposing the odd-numbered electrode layer (the third electrode layer 31b) located in the upper layer in the first insulating layer 40 is greater than the depth of the first via hole 41a exposing the odd-numbered electrode layer (the first electrode layer 31a) located in the lower layer in the first insulating layer 40. The depth of the second via hole 42b exposing the even-numbered electrode layer (the second electrode layer 32a) located in the upper layer in the first insulating layer 40 is greater than the depth of the second via hole 42a exposing the even-numbered electrode layer (the substrate 10) located in the lower layer in the first insulating layer 40. The depth of the first via hole 41b exposing the odd-numbered electrode layer (the third electrode layer 31b) located in the uppermost layer in the first insulating layer 40 is greater than the depth of the second via hole 42b exposing the even-numbered electrode layer (the second electrode layer 32a) located in the uppermost layer in the first insulating layer 40; the depth of the second via hole 42a exposing the even-numbered electrode layer (the substrate 10) located in the lowermost layer in the first insulating layer 40 is greater than the depth of the first via hole 41a exposing the odd-numbered electrode layer (the first electrode layer 31a) located in the lowermost layer in the first insulating layer 40; in adjacent odd-numbered and even-numbered electrode layers (the second electrode layer 32a and the first electrode layer 31a), the depth of the second via hole exposing the even-numbered electrode layer (the second electrode layer 32a) located in the upper layer in the first insulating layer 40 is greater than the depth of the first via hole exposing the odd-numbered electrode layer (the first electrode layer 31a) located in the lower layer in the first insulating layer 40.

[0128] In this embodiment, by determining the etching rate of the first insulating layer, the etching selectivity ratio of the multiple layer structure materials covered by the corresponding via holes can be obtained, so as to deduce the corresponding etching height ratio (of the first insulating layer and each layer structure) and the etching thickness of the multiple layer structure materials, thereby determining the deposition thickness of each layer structure and obtaining the above capacitance structure.

[0129] It can be understood that the etching time of the via hole is related to both the etching rate of the material to be etched and the depth to be etched. Therefore, the above technical solution enables, in the synchronous etching process, the use of the etching depth difference between the first via hole and the second via hole in the first insulating layer to compensate for the etching rate difference caused by the different materials of the electrode layer, the dielectric layer, and the second insulating layer, so as to complete the etching of the first via hole and the second via hole at the same time in the synchronous etching process.

[0130] The metal interconnection layer 50 is formed on the first insulating layer 40 and in the first via hole 41 and the second via hole 42. The metal interconnection layer 50 includes a first metal interconnection layer 51 electrically connected to the odd-numbered electrode layer, and a second metal interconnection layer 52 electrically connected to the substrate 10 and the even-numbered electrode layer. Specifically, the first metal interconnection layer 51 is electrically connected to the odd-numbered electrode layer through the first via hole 41. The second metal interconnection layer 52 is electrically connected to the substrate 10 and the even-numbered electrode layer through the second via hole 42.

[0131] It can be understood that, in order to prevent the first metal interconnection layer 51 from being electrically connected to other layer structures within the first through-hole 41, an insulating layer can be formed on the sidewall of the first through-hole 41. Similarly, in order to prevent the second metal interconnection layer 52 from being electrically connected to other layer structures within the second through-hole 42, an insulating layer can also be formed on the sidewall of the second through-hole 42.

[0132] It can be understood that, in Embodiment 1, both the first sidewall and the second sidewall of the groove structure 11 are inclined with respect to the first surface of the substrate, maximizing the specific surface area. At the same time, the first through-hole and the second through-hole can be correspondingly distributed on the first sidewall, the second sidewall, the first surface, and the bottom wall as needed. In other embodiments, only one of the sidewalls may be inclined with respect to the first surface of the substrate. In this embodiment, the first through-hole and the second through-hole can be correspondingly distributed only on the first surface and the inclined sidewall as needed, or only on the first surface, the bottom wall, and the inclined sidewall.

[0133] As Figures 3a - 3e shown, the manufacturing method of the capacitor structure in this embodiment specifically includes the following steps:

[0134] As Figure 3a shown, a substrate 10 is provided, and the substrate 10 has a first surface 10a. The substrate 10 is selected from a highly doped (such as boron-doped or phosphorus-doped) silicon substrate or a polysilicon substrate, wherein the doping depth can be about 3 μm - 5 μm from the substrate surface into the substrate. Alternatively, the substrate 10 is selected from a low-resistance substrate, such as a gallium arsenide substrate (GaAs), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), etc. The resistivity of the substrate 10 is within the range of 10 -3 -10 -1 Ω·cm. The low-resistivity substrate 10 can serve as the bottom electrode of the capacitor structure, further increasing the capacitance density of the capacitor structure.

[0135] An anisotropic wet etching process (such as a KOH solution) or a dry etching process (such as RIE - reactive ion etching) is used to form a groove structure 11 on the first surface 10a of the substrate 10. The number of groove structures 11 can be multiple, and they are arranged periodically on the first surface 10a of the substrate 10. The depth of the groove structure 11 is 1 μm - 10 μm, and the spacing (period) between adjacent groove structures 11 is 0.5 μm - 5 μm.

[0136] It can be understood that, in other embodiments, the depth and spacing of the groove structure 11 can be optimized according to the capacitance density requirements.

[0137] The groove structure 11 includes a first side wall 111 and a second side wall 112 which are oppositely arranged, and a bottom wall 113 located between the first side wall 111 and the second side wall 112. The first side wall 111 is inclined relative to the first surface 10a, and the included angle α1 between the first side wall 111 and the first surface 10a is an obtuse angle. The second side wall 112 is also inclined relative to the first surface 10a, and the included angle α2 between the second side wall 112 and the first surface 10a is also an obtuse angle.

[0138] In this embodiment, in the depth direction of the groove structure 11, the first side wall 111 of the groove structure 11 sequentially includes a first region 111a and a second region 111b in the direction away from the first surface 10a. The second side wall 112 of the groove structure 11 includes a third region 112a corresponding to the first region 111a and a fourth region 112b corresponding to the second region 111b. The division of the first region 111a, the second region 111b, the third region 112a, and the fourth region 112b enables the through holes for electrode lead-out opened in different regions to have different depths in the first insulating layer 40 deposited subsequently. In the depth direction of the groove structure 11, the etching time required for the depth difference between adjacent through holes in the first insulating layer 40 can be compensated by using the etching rates of multiple layer structures (electrode layer, dielectric layer, second insulating layer) required to be etched in the through hole with a relatively smaller depth among the two; or rather, the etching depth difference between adjacent through holes in the first insulating layer 40 is used to compensate for the etching rate difference caused by the different materials of the electrode layer, the dielectric layer, and the second insulating layer, so as to synchronize the etching time.

[0139] Deep silicon etching is performed on the first side wall 111, the second side wall 112, and the bottom wall 113 of the groove structure 11 by using deep reactive ion etching (DRIE) technology to form deep trenches 12. The depth of the deep trenches 12 is 5 μm - 50 μm, and the width of the deep trenches 12 is 0.5 μm - 5 μm.

[0140] As Figure 3b shown, the deposition of the second insulating layer 20 is carried out. The second insulating layer 20 covering the first surface 10a of the substrate 10, the inner wall of the groove structure 11, and the inner wall of the deep trenches 12 is formed by using chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology. The material of the second insulating layer 20 may include but is not limited to SiO2 and Si3N4. The thickness of the second insulating layer 20 is 5 nm - 50 nm. When the substrate 10 is used as a bottom electrode, the second insulating layer 20 can be used as a capacitive dielectric layer.

[0141] As Figure 3cAs shown, the deposition of the layer stack structure 30 is performed. The electrode layer and the dielectric layer 33 are sequentially deposited by sputtering or chemical vapor deposition (CVD). The electrode layer includes an odd electrode layer and an even electrode layer stacked alternately, and the dielectric layer 33 is formed between the odd electrode layer and the even electrode layer. The materials of the odd electrode layer and the even electrode layer include, but are not limited to, polysilicon or metal, and the material of the dielectric layer 33 includes, but is not limited to, SiO2 or Si3N4.

[0142] In this embodiment, the electrode layer includes a first electrode layer 31a, a first dielectric layer, a second electrode layer 32a, a second dielectric layer, and a third electrode layer 31b stacked in sequence. The first electrode layer 31a and the second electrode layer 32a are odd electrode layers; the second electrode layer 32a is an even electrode layer.

[0143] As Figure 3d shown, a first insulating layer 40 covering the layer stack structure 30 is formed. The material of the first insulating layer 40 may include, but is not limited to, SiO2, Si3N4, High-k materials (high dielectric constant materials such as hafnium oxide - HfO2, zirconium oxide - ZrO2, aluminum oxide - Al2O3, etc.), and polymer materials (polyimide - PI, benzocyclobutene BCB, etc.).

[0144] As Figure 3e shown, openings are formed in the first insulating layer 40 by photolithography and etching processes, forming a first via hole 41 exposing the odd electrode layer and a second via hole 42 exposing the substrate 10 and the even electrode layer.

[0145] Specifically, a first via hole 41a exposing the first electrode layer 31a is formed in the first insulating layer 40, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, and the first dielectric layer in the third region 112a of the second sidewall 112 of the groove structure 11. A first via hole 41b exposing the third electrode layer 31b is formed in the first insulating layer 40 in the region where the bottom wall 113 of the groove structure 11 is located. A second via hole 42a exposing the substrate 10 is formed in the first insulating layer 40, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, the first dielectric layer, the first electrode layer 31a, and the second insulating layer 20 on the first surface 10a of the substrate 10. A second via hole 42b exposing the second electrode layer 32a is formed in the first insulating layer 40, the third electrode layer 31b, and the second dielectric layer in the second region 111b of the first sidewall 111 of the groove structure 11.

[0146] In this embodiment, by determining the etching rate of the first insulating layer, the etching selectivity ratio of the materials of the multiple layer structures covered by the corresponding via holes can be obtained, so as to deduce the corresponding etching height ratio (between the first insulating layer and each layer structure), the etching thickness of the materials of the multiple layer structures, and thus determine the deposition thickness of each layer structure to obtain the above - mentioned capacitance structure.

[0147] It is understandable that the etching time of the through-holes is related to both the etching rate of the material to be etched and the depth to be etched. Therefore, the above technical solution enables, in the synchronous etching process, the use of the etching depth difference between the first through-hole and the second through-hole in the first insulating layer to compensate for the etching rate difference caused by the different materials of the electrode layer, the dielectric layer, and the second insulating layer, so as to complete the etching of the first through-hole and the second through-hole at the same time in the synchronous etching process.

[0148] As Figure 2 shown, on the first insulating layer 40 and within the first through-hole 41 and the second through-hole 42, a metal (such as Al or Cu) is deposited, and through photolithography and etching, a first metal interconnection layer 51 electrically connected to the odd-numbered electrode layer, and a second metal interconnection layer 52 electrically connected to the substrate 10 and the even-numbered electrode layer are formed.

[0149] It is understandable that, in order to prevent the first metal interconnection layer 51 from being electrically connected to other layer structures within the first through-hole 41, an insulating layer can be formed on the sidewall of the first through-hole 41. Similarly, in order to prevent the second metal interconnection layer 52 from being electrically connected to other layer structures within the second through-hole 42, an insulating layer can also be formed on the sidewall of the second through-hole 42.

[0150] The capacitor structure and its manufacturing method of this embodiment, through the combination of the groove structure and the trenches within the groove structure, further increase the specific surface area and significantly improve the capacitance density. The use of the same-layer metal interconnection to separately lead out the even-numbered electrode layer and / or the substrate and the odd-numbered electrode layer reduces the crosstalk between the electrodes, simplifies the manufacturing process, and improves the manufacturability. Through the setting of the groove structure, the height difference is used to compensate for the etching rate difference caused by the different materials of different layer structures, realizing the synchronous etching to complete the CT (contact hole) opening at the same time, optimizing the CT opening, reducing the process difficulty, and improving the etching accuracy.

[0151] Embodiment 2:

[0152] As Figures 4 to 6 shown, in this embodiment, the substrate 10 still serves as the bottom electrode of the capacitor structure. The layer stack structure 30 still includes a first electrode layer 31a, a first dielectric layer, a second electrode layer 32a, a second dielectric layer, and a third electrode layer 31b stacked in sequence. The first electrode layer 31a and the second electrode layer 32a are odd-numbered electrode layers; the second electrode layer 32a is an even-numbered electrode layer.

[0153] The difference between this embodiment and Embodiment 1 is that, in this embodiment:

[0154] As Figure 5As shown, a second through hole 42a exposing the substrate 10 is formed in the first insulating layer 40, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, the first dielectric layer, and the first electrode layer 31a on the first surface 10a of the substrate 10; a second through hole 42b exposing the second electrode layer 32a is formed in the first insulating layer 40, the third electrode layer 31b, and the second dielectric layer in the second region 111b of the first sidewall 111 and the fourth region 112b of the second sidewall 112 of the groove structure 11.

[0155] As Figure 6 As shown, a first through hole 41a exposing the first electrode layer 31a is formed in the first insulating layer 40, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, and the first dielectric layer in the first region 111a of the first sidewall 111 and the third region 112a of the second sidewall 112 of the groove structure 11; a first through hole 41b exposing the third electrode layer 31b is formed in the first insulating layer 40 in the region where the bottom wall 113 of the groove structure 11 is located.

[0156] As Figure 4 As shown, in order to electrically isolate the first metal interconnection layer 51 and the second metal interconnection layer 52 on the first insulating layer 40, the first metal interconnection layer 51 and the second metal interconnection layer 52 are distributed in a finger-like electrode shape.

[0157] It can be understood that in Embodiment 1 and Embodiment 2, the number of layers of the odd electrode layers is two, the number of layers of the even electrode layers is two, and the substrate serves as the bottom electrode and belongs to the even electrode layers. In other embodiments, the number of layers of the odd electrode layers can also be 1, 3, or more than 3, and the number of layers of the even electrode layers can be 1, 3, or more than 3.

[0158] Thus, the two sidewalls of the groove structure may also include a plurality of regions distributed in the direction away from the first surface of the substrate according to the number of odd electrode layers and even electrode layers, and are defined as follows: the depth of the first through hole exposing the odd electrode layer in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer in the lower layer in the first insulating layer; the depth of the second through hole exposing the even electrode layer in the upper layer in the first insulating layer is greater than the depth of the second through hole exposing the even electrode layer in the lower layer in the first insulating layer; the depth of the first through hole exposing the odd electrode layer in the uppermost layer in the first insulating layer is greater than the depth of the second through hole exposing the even electrode layer in the uppermost layer in the first insulating layer; the depth of the second through hole exposing the even electrode layer in the lowermost layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer in the lowermost layer in the first insulating layer; in adjacent even and odd electrode layers (where the odd electrode layer is below the even electrode layer), the depth of the second through hole exposing the even electrode layer in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer in the lower layer in the first insulating layer. Corresponding first through holes and second through holes are formed in the first insulating layer, electrode layer, and dielectric layer in the plurality of regions on the two sidewalls of the groove structure.

[0159] Embodiment 3:

[0160] As Figure 7 shown, the capacitor structure in this embodiment includes a substrate 10, a second insulating layer 20, a layer stack structure 30, a first insulating layer 40, and a metal interconnect layer 50.

[0161] The substrate 10 is selected from a high-resistivity silicon substrate or a common silicon substrate. The resistivity of the substrate 10 is in the range of 10 to 1000 Ω·cm. The high-resistivity substrate 10 or the common silicon substrate does not act as the bottom electrode of the capacitor structure.

[0162] The substrate 10 has a first surface 10a. A groove structure 11 is formed on the first surface 10a of the substrate 10. The number of groove structures 11 can be multiple, and they are arranged periodically on the first surface 10a of the substrate 10. The depth of the groove structure 11 is 1 μm - 10 μm, and the spacing (period) between adjacent groove structures 11 is 0.5 μm - 5 μm. Deep trenches 12 are formed on the inner walls of one or more groove structures 11.

[0163] It can be understood that in other embodiments, the depth and spacing of the groove structure 11 can be optimized according to the capacitance density requirements.

[0164] In this embodiment, the groove structure 11 includes a first sidewall 111 and a second sidewall 112 which are oppositely arranged, and a bottom wall 113 located between the first sidewall 111 and the second sidewall 112. The first sidewall 111 is inclined relative to the first surface 10a, and the angle between the first sidewall 111 and the first surface 10a is an obtuse angle. The second sidewall 112 is also inclined relative to the first surface 10a, and the angle between the second sidewall 112 and the first surface 10a is also an obtuse angle.

[0165] In this embodiment, in the depth direction of the groove structure 11, the first sidewall 111 of the groove structure 11 sequentially includes a first region 111a and a second region 111b in a direction away from the first surface 10a. The second sidewall 112 of the groove structure 11 includes a third region 112a corresponding to the first region 111a and a fourth region 112b corresponding to the second region 111b. The division of the first region 111a, the second region 111b, the third region 112a, and the fourth region 112b enables the through holes for electrode lead-out formed in different regions to have different depths in the first insulating layer 40 deposited subsequently. In the depth direction of the groove structure 11, the etching time required for the depth difference of adjacent through holes in the first insulating layer 40 can be compensated by using the etching rate of the multiple layer structures (electrode layer, dielectric layer, second insulating layer) required to be etched in the through hole with a relatively smaller depth among the two; or rather, the etching depth difference of adjacent through holes in the first insulating layer 40 is used to compensate for the etching rate difference caused by the different materials of the electrode layer, the dielectric layer, and the second insulating layer, so as to synchronize the etching time.

[0166] The deep groove 12 is formed on the first sidewall 111 and / or the second sidewall 112 and / or the bottom wall 113 of the groove structure 11. The depth of the deep groove 12 is 5 μm - 50 μm, and the width of the deep groove 12 is 0.5 μm - 5 μm.

[0167] The second insulating layer 20 covers the first surface 10a of the substrate 10, the inner wall of the groove structure 11, and the inner wall of the deep groove 12. Here, the second insulating layer 20 does not act as a dielectric layer either, but is used to isolate the substrate 10 from the layer stack structure 30. The material of the second insulating layer 20 may include but is not limited to SiO2 and Si3N4. The thickness of the second insulating layer 20 is 10 nm - 100 nm.

[0168] The layer stack structure 30 includes alternately stacked odd electrode layers and even electrode layers and a dielectric layer 33 formed between the odd electrode layers and the even electrode layers. The materials of the odd electrode layers and the even electrode layers include but are not limited to polysilicon or metal, and the material of the dielectric layer 33 includes but is not limited to SiO2 or Si3N4. The layer stack structure 30 is formed on the surface of the second insulating layer 20, and also covers the first surface 10a of the substrate 10, the inner wall of the groove structure 11, and the inner wall of the deep groove 12.

[0169] In this embodiment, the layer stack structure 30 includes a first electrode layer 31a, a first dielectric layer, a second electrode layer 32a, a second dielectric layer, a third electrode layer 31b, a third dielectric layer, and a fourth electrode layer 32b that are stacked in sequence. The first electrode layer 31a and the second electrode layer 32a are odd-numbered electrode layers; the second electrode layer 32a and the fourth electrode layer 32b are even-numbered electrode layers.

[0170] The first insulating layer 40 covers the layer stack structure 30. The material of the first insulating layer 40 may include, but is not limited to, SiO2, Si3N4, High-k materials (high dielectric constant materials such as hafnium oxide - HfO2, zirconium oxide - ZrO2, aluminum oxide - Al2O3, etc.), and polymer materials (polyimide - PI, benzocyclobutene BCB, etc.).

[0171] A first through hole 41 exposing the odd-numbered electrode layer and a second through hole 42 exposing the substrate 10 and the even-numbered electrode layer are formed on the first insulating layer 40.

[0172] In this embodiment, a first through hole 41a exposing the first electrode layer 31a is formed in the first insulating layer 40, the fourth electrode layer 32b, the third dielectric layer, the third electrode layer 31b, the second dielectric layer, the second electrode layer 32a, and the first dielectric layer on the first surface 10a of the substrate 10; a first through hole 41b exposing the third electrode layer 31b is formed in the first insulating layer 40, the fourth electrode layer 32b, and the third dielectric layer in the second region 111b of the first sidewall 111 of the groove structure 11; a second through hole 42a exposing the second electrode layer 32a is formed in the first insulating layer 40, the fourth electrode layer 32b, the third dielectric layer, the third electrode layer 31b, and the second dielectric layer in the third region 112a of the second sidewall 112 of the groove structure 11; a second through hole 42b exposing the fourth electrode layer 32b is formed in the first insulating layer 40 in the region where the bottom wall 113 of the groove structure 11 is located.

[0173] In the above embodiments, the depth of the first via hole 41b exposing the odd-numbered electrode layer (the third electrode layer 31b) located in the upper layer in the first insulating layer 40 is greater than the depth of the first via hole 41a exposing the odd-numbered electrode layer (the first electrode layer 31a) located in the lower layer in the first insulating layer 40. The depth of the second via hole 42b exposing the even-numbered electrode layer (the fourth electrode layer 32b) located in the upper layer in the first insulating layer 40 is greater than the depth of the second via hole 42a exposing the even-numbered electrode layer (the second electrode layer 32a) located in the lower layer in the first insulating layer 40. In adjacent odd-numbered and even-numbered electrode layers (the third electrode layer 31b and the fourth electrode layer 32b), the depth of the second via hole exposing the even-numbered electrode layer (the fourth electrode layer 32b) located in the upper layer in the first insulating layer 40 is greater than the depth of the first via hole exposing the odd-numbered electrode layer (the third electrode layer 31b) located in the lower layer in the first insulating layer 40.

[0174] In this embodiment, by determining the etching rate of the first insulating layer, the etching selectivity ratio of the multiple layer structure materials covered by the corresponding via holes can be obtained, so as to deduce the corresponding etching height ratio (of the first insulating layer and each layer structure) and the etching thickness of the multiple layer structure materials, thereby determining the deposition thickness of each layer structure and obtaining the above-mentioned capacitor structure.

[0175] It can be understood that the etching time of the via hole is related to both the etching rate of the material to be etched and the depth to be etched. Therefore, the above technical solution enables, in the synchronous etching process, the use of the etching depth difference between the first via hole and the second via hole in the first insulating layer to compensate for the etching rate difference caused by the different materials of the electrode layer, the dielectric layer, and the second insulating layer, so as to complete the etching of the first via hole and the second via hole at the same time in the synchronous etching process.

[0176] The metal interconnection layer 50 is formed on the first insulating layer 40 and in the first via hole 41 and the second via hole 42. The metal interconnection layer 50 includes a first metal interconnection layer 51 electrically connected to the odd-numbered electrode layer, and a second metal interconnection layer 52 electrically connected to the substrate 10 and the even-numbered electrode layer. Specifically, the first metal interconnection layer 51 is electrically connected to the odd-numbered electrode layer through the first via hole 41. The second metal interconnection layer 52 is electrically connected to the substrate 10 and the even-numbered electrode layer through the second via hole 42.

[0177] It can be understood that, in order to prevent the first metal interconnection layer 51 from being electrically connected to other layer structures in the first via hole 41, an insulating layer can be formed on the side wall of the first via hole 41. Similarly, in order to prevent the second metal interconnection layer 52 from being electrically connected to other layer structures in the second via hole 42, an insulating layer can also be formed on the side wall of the second via hole 42.

[0178] It can be understood that in Embodiment 3, the number of odd electrode layers is two, the number of even electrode layers is two, and the substrate does not serve as an even electrode layer. In other embodiments, the number of odd electrode layers can also be 1, 3, or more than 3, and the number of even electrode layers can be 1, 3, or more than 3.

[0179] Thus, the two sidewalls of the groove structure can also include a plurality of regions distributed in the direction away from the first surface of the substrate according to the number of odd electrode layers and even electrode layers, and are defined as follows: the depth of the first through hole exposing the odd electrode layer located in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer located in the lower layer in the first insulating layer; the depth of the second through hole exposing the even electrode layer located in the upper layer in the first insulating layer is greater than the depth of the second through hole exposing the even electrode layer located in the lower layer in the first insulating layer; the depth of the first through hole exposing the odd electrode layer located in the uppermost layer in the first insulating layer is greater than the depth of the second through hole exposing the even electrode layer located in the uppermost layer in the first insulating layer; the depth of the second through hole exposing the even electrode layer located in the lowermost layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer located in the lowermost layer in the first insulating layer; in adjacent even and odd electrode layers (where the odd electrode layer is below the even electrode layer), the depth of the second through hole exposing the even electrode layer located in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer located in the lower layer in the first insulating layer. Corresponding first through holes and second through holes are formed in the first insulating layer, electrode layer, and dielectric layer in the plurality of regions on the two sidewalls of the groove structure.

[0180] Embodiment 4:

[0181] The difference between this embodiment and Embodiment 1 is that in this embodiment, the groove structure can be set as a V-shaped groove structure. The groove structure does not include a bottom wall between the first sidewall and the second sidewall.

[0182] In this embodiment, the through hole exposing the electrode layer (which can be an odd electrode layer or an even electrode layer) located in the uppermost layer can be opened in the region of the first sidewall farthest from the first surface, or opened in the region of the second sidewall farthest from the first surface. That is, the depth of the through hole exposing the electrode layer (which can be an odd electrode layer or an even electrode layer) located in the uppermost layer in the first insulating layer is the deepest.

[0183] It should be noted that the above embodiments can be combined with each other on the premise of not being contradictory.

[0184] Compared with the prior art, the capacitor structure and its manufacturing method of the present invention further increase the specific surface area and significantly improve the capacitance density by combining the groove structure and the grooves in the groove structure.

[0185] The capacitive structure and its manufacturing method of the present invention respectively lead out the even electrode layer and / or the substrate and the odd electrode layer by using the same-layer metal interconnection, reducing the crosstalk between electrodes, simplifying the manufacturing process, and improving the manufacturability.

[0186] The capacitive structure and its manufacturing method of the present invention, through the setting of the groove structure, utilize the height difference to make up for the etching rate difference caused by different layer structure materials, realize the simultaneous etching of CT (contact hole) opening in the same time, optimize the CT opening, reduce the process difficulty, and improve the etching precision.

[0187] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0188] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A capacitive structure, characterized in that, Comprising: A substrate having a first surface on which a groove structure is formed. The groove structure at least includes a first sidewall inclined with respect to the first surface, and a groove is formed on the inner wall of the groove structure; A layer stack structure including alternately stacked odd electrode layers and even electrode layers and a dielectric layer formed between the odd electrode layers and the even electrode layers. The layer stack structure covers the first surface, the inner wall of the groove structure, and the inner wall of the groove; A first insulating layer covering the layer stack structure; And A metal interconnect layer formed on the first insulating layer. The metal interconnect layer includes a first metal interconnect layer electrically connected to the odd electrode layer, and a second metal interconnect layer electrically connected to the substrate and / or the even electrode layer.

2. The capacitive structure according to claim 1, characterized in that, The included angle between the first sidewall of the groove structure and the first surface is an obtuse angle.

3. The capacitive structure according to claim 1, wherein A first through hole exposing the odd electrode layer and a second through hole exposing the substrate and / or the even electrode layer are formed on the first insulating layer. The first metal interconnect layer is electrically connected to the odd electrode layer through the first through hole, and the second metal interconnect layer is electrically connected to the substrate and / or the even electrode layer through the second through hole.

4. The capacitive structure according to claim 3, wherein, The depth of the first through hole exposing the odd electrode layer in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer in the lower layer in the first insulating layer; The depth of the second through hole exposing the even electrode layer in the upper layer in the first insulating layer is greater than the depth of the second through hole exposing the even electrode layer in the lower layer in the first insulating layer; In adjacent odd electrode layer and even electrode layer, the depth of the second through hole exposing the even electrode layer in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer in the lower layer in the first insulating layer.

5. The capacitive structure according to claim 1, wherein The groove structure further includes a bottom wall.

6. The capacitive structure according to claim 5, wherein A groove is formed on the bottom wall and / or the first sidewall of the groove structure.

7. The capacitive structure according to claim 5, wherein The layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer stacked in sequence; in the depth direction of the groove structure, the first sidewall of the groove structure sequentially includes a first region and a second region along the direction away from the first surface; a first through hole exposing the first electrode layer is formed in the first insulating layer of the first region of the first sidewall; a first through hole exposing the third electrode layer is formed in the first insulating layer of the region where the bottom wall of the groove structure is located; a second through hole exposing the substrate is formed in the first insulating layer of the first surface of the substrate; a second through hole exposing the second electrode layer is formed in the first insulating layer of the second region of the first sidewall; Or, The layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, a third dielectric layer, and a fourth electrode layer that are stacked in sequence; in the depth direction of the groove structure, the first sidewall of the groove structure sequentially includes a first region and a second region in a direction away from the first surface; a first through hole exposing the first electrode layer is formed in the first insulating layer on the first surface of the substrate; a first through hole exposing the third electrode layer is formed in the first insulating layer in the second region of the first sidewall; a second through hole exposing the second electrode layer is formed in the first insulating layer in the first region of the first sidewall; a second through hole exposing the fourth electrode layer is formed in the first insulating layer in the region where the bottom wall of the groove structure is located.

8. The capacitive structure according to claim 1, wherein The groove structure further includes a second sidewall disposed opposite to the first sidewall, and the second sidewall is inclined with respect to the first surface.

9. The capacitive structure according to claim 8, wherein, The included angle between the second sidewall of the groove structure and the first surface is an obtuse angle.

10. The capacitive structure according to claim 8, wherein The groove structure further includes a bottom wall located between the first sidewall and the second sidewall.

11. The capacitive structure according to claim 10, wherein, Grooves are formed on the first sidewall and / or the second sidewall and / or the bottom wall of the groove structure.

12. The capacitive structure according to claim 11, characterized in that, The layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer that are stacked in sequence; in the depth direction of the groove structure, the first sidewall of the groove structure sequentially includes a first region and a second region in a direction away from the first surface, and the second sidewall of the groove structure includes a third region corresponding to the first region and a fourth region corresponding to the second region; a first through hole exposing the first electrode layer is formed in the first insulating layer in the third region of the second sidewall; a first through hole exposing the third electrode layer is formed in the first insulating layer in the region where the bottom wall of the groove structure is located; a second through hole exposing the substrate is formed in the first insulating layer on the first surface of the substrate; a second through hole exposing the second electrode layer is formed in the first insulating layer in the second region of the first sidewall and / or the fourth region of the second sidewall. Or, The layer stack structure at least includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, a third dielectric layer, and a fourth electrode layer that are stacked in sequence; in the depth direction of the groove structure, the first sidewall of the groove structure sequentially includes a first region and a second region in a direction away from the first surface, and the second sidewall of the groove structure includes a third region corresponding to the first region and a fourth region corresponding to the second region; a first through hole exposing the first electrode layer is formed in the first insulating layer on the first surface of the substrate; a first through hole exposing the third electrode layer is formed in the first insulating layer in the second region of the first sidewall and / or the fourth region of the second sidewall; a second through hole exposing the second electrode layer is formed in the first insulating layer in the third region of the second sidewall; a second through hole exposing the fourth electrode layer is formed in the first insulating layer in the region where the bottom wall of the groove structure is located.

13. The capacitive structure according to claim 1, characterized in that, A second insulating layer is further disposed between the first surface of the substrate and the layer stack structure.

14. The capacitive structure according to claim 1, wherein A plurality of the groove structures are arranged periodically on the first surface of the substrate.

15. A manufacturing method of a capacitor structure, characterized in that, Including: Providing a substrate having a first surface; Forming a groove structure on the first surface, the groove structure including a first sidewall inclined relative to the first surface; Forming a groove on the inner wall of the groove structure; Forming a layer stack structure covering the first surface, the inner wall of the groove structure, and the inner wall of the groove, the layer stack structure including alternately stacked odd electrode layers and even electrode layers and a dielectric layer formed between the odd electrode layers and the even electrode layers; Forming a first insulating layer covering the layer stack structure; Opening holes in the first insulating layer, and forming a first metal interconnection layer electrically connected to the odd electrode layer and a second metal interconnection layer electrically connected to the substrate and / or the even electrode layer on the first insulating layer.

16. The manufacturing method of the capacitive structure according to claim 15, characterized in that, The groove structure is formed by a wet etching process or a dry etching process; and / or Forming a plurality of groove structures arranged periodically on the first surface.

17. The manufacturing method of the capacitive structure according to claim 15, characterized in that, The groove structure further includes a bottom wall; Forming a groove on the inner wall of the groove structure, including: Forming a groove at least on the first sidewall and / or the bottom wall of the groove structure.

18. The manufacturing method of the capacitive structure according to claim 17, wherein The first sidewall of the groove structure includes a first region close to the first surface and a second region close to the bottom wall; Opening holes in the first insulating layer, including: Opening a first through hole exposing the odd electrode layer in the first insulating layer in the first region of the first sidewall and in the first insulating layer in the region where the bottom wall of the groove structure is located; Opening a second through hole exposing the substrate and / or the even electrode layer in the first insulating layer on the first surface of the substrate and in the first insulating layer in the second region of the first sidewall.

19. The manufacturing method of the capacitive structure according to claim 17, characterized in that, The groove structure includes a second sidewall opposite to the first sidewall, and the second sidewall is inclined relative to the first surface; Forming a groove on the inner wall of the groove structure, including: Forming a groove at least on the second sidewall of the groove structure.

20. The manufacturing method of the capacitive structure according to claim 19, characterized in that, The first sidewall of the groove structure includes a first region close to the first surface and a second region close to the bottom wall, and the second sidewall of the groove structure includes a third region corresponding to the first region and a fourth region corresponding to the second region; Opening holes in the first insulating layer, including: Opening a first through hole exposing the odd electrode layer in the first insulating layer in the third region of the second sidewall and in the first insulating layer in the region where the bottom wall of the groove structure is located; Opening a second through hole exposing the substrate and / or the even electrode layer in the first insulating layer in the second region of the first sidewall and / or the fourth region of the second sidewall and in the first insulating layer on the first surface of the substrate.

21. The manufacturing method of the capacitive structure according to claim 18 or 20, characterized in that, The depth of the first through hole exposing the odd electrode layer in the upper layer in the first insulating layer is greater than the depth of the first through hole exposing the odd electrode layer in the lower layer in the first insulating layer; The depth of the second vias exposing the even electrode layer located in the upper layer within the first insulating layer is greater than the depth of the second vias exposing the even electrode layer located in the lower layer within the first insulating layer; In adjacent odd and even electrode layers, the depth of the second vias exposing the even electrode layer located in the upper layer within the first insulating layer is greater than the depth of the first vias exposing the odd electrode layer located in the lower layer within the first insulating layer.

22. The method for manufacturing a capacitive structure according to claim 18 or 20, wherein Utilize the etching depth difference of the first vias and the second vias within the first insulating layer to compensate for the etching rate difference caused by the different materials of the electrode layers and dielectric layers, so as to complete the etching of the first vias and the second vias at the same time in the synchronous etching process.

23. The manufacturing method of the capacitor structure according to claim 15, characterized in that, Form a first metal interconnect layer electrically connected to the odd electrode layer and a second metal interconnect layer electrically connected to the substrate and / or the even electrode layer on the first insulating layer, including: Form a metal interconnect layer on the first insulating layer, pattern the metal interconnect layer to form electrically isolated first and second metal interconnect layers.

24. The manufacturing method of the capacitive structure according to claim 15, characterized in that, After the step of forming trenches on the first sidewall of the trench structure, it further includes the step of forming a second insulating layer covering the first surface, the inner wall of the trench structure, and the inner wall of the trenches.

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