Three-dimensional MIM capacitor plate forming method

Abstract

The invention discloses a three-dimensional MIM capacitor plate forming method, which comprises the steps of providing a semiconductor device, forming a metal connecting wire in a first dielectric layer of the semiconductor device, and sequentially forming a dielectric barrier layer and a second dielectric layer on the first dielectric layer; forming a through hole in the second dielectric layer, and exposing a metal connecting wire at the bottom of the through hole; growing a first WN thin film layer, wherein the first WN thin film layer covers the bottom of the through hole and the surface of the second dielectric layer; forming an insulating layer on the first WN thin film layer; forming a second WN thin film layer on the insulating layer; a metal layer is formed on the second WN thin film layer, and the through hole is filled with the metal layer; and performing planarization treatment to remove the first WN thin film layer, the insulating layer, the second WN thin film layer and the metal layer outside the through hole. By means of the scheme, efficient formation of the capacitor plates in the three-dimensional MIM can be achieved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor manufacturing, and particularly relates to a method for forming the electrodes of a three-dimensional MIM device. Background Art

[0002] TiN has advantages such as high temperature resistance and chemical stability, and is widely used in the MIM (Metal-Insulator-Metal) structure of semiconductor devices. The common deposition methods of TiN are PVD deposition, MOCVD deposition, and ALD deposition. The film formation rate of PVD deposition is fast and suitable for thick film deposition. However, due to its lack of filling ability, it is commonly found in planar MIM structures. The latter two have better filling ability, but the film formation rate is very slow and is only suitable for thin film deposition.

[0003] In related technologies, in order to increase the volume of a single capacitor, a three-dimensional MIM capacitor is proposed. The three-dimensional MIM capacitor is a planar stacked MIM capacitor set in a cylindrical or cubic shape. The cylindrical and cubic shapes successively include a first electrode, a capacitive dielectric, and a second electrode from the outside to the inside. The metal contact hole connected to the second electrode is wrapped by the second electrode. To ensure the stability of the device, thick films need to be deposited on the electrodes of the three-dimensional MIM capacitor.

[0004] Different from the planar MIM structure, the three-dimensional MIM capacitor requires good filling ability and step coverage for the deposition of both the electrodes and the dielectric, while the above three deposition methods of TiN cannot simultaneously meet the requirements of the three-dimensional MIM capacitor. Summary of the Invention

[0005] To solve the above problems, this application provides a method for forming the electrodes of a three-dimensional MIM capacitor.

[0006] An embodiment of this application provides a method for forming the electrodes of a three-dimensional MIM capacitor, including: Providing a semiconductor device, in which metal wires are formed in a first dielectric layer of the semiconductor device, and a dielectric barrier layer and a second dielectric layer are successively formed on the first dielectric layer; Forming a through hole in the second dielectric layer to expose the metal wire at the bottom of the through hole; Growing a first WN thin film layer, which covers the bottom of the through hole and the surface of the second dielectric layer; Forming an insulating layer on the first WN thin film layer; Forming a second WN thin film layer on the insulating layer; Forming a metal layer on the second WN thin film layer, and the metal layer fills the through hole; Performing planarization treatment to remove the first WN thin film layer, the insulating layer, the second WN thin film layer, and the metal layer located outside the through hole.

[0007] In some embodiments, growing the first WN thin film layer includes: Growing a first WN thin film layer on the bottom of the through hole and the surface of the second dielectric layer through a pulsed nucleation layer process.

[0008] In some embodiments, the thickness of the first WN thin film layer is 150 - 300 angstroms.

[0009] In some embodiments, forming an insulating layer on the first WN thin film layer includes: Depositing Al2O3 on the first WN thin film layer through atomic layer deposition to form the insulating layer.

[0010] In some embodiments, the thickness of the deposited Al2O3 is 200 - 500 angstroms.

[0011] In some embodiments, the thickness of the second WN thin film layer is 150 - 300 angstroms.

[0012] In some embodiments, the metal layer is a copper layer.

[0013] In some embodiments, forming a metal layer on the second WN thin film layer includes: Sequentially forming a metal barrier layer and a copper seed layer on the second WN thin film layer; Forming an electroplated copper layer on the copper seed layer through electroplating, and the copper seed layer and the electroplated copper layer constitute the metal layer.

[0014] The technical solution of this application has at least the following advantages: Since WN has advantages such as no plasma participation, good barrier ability, and good thermal stability, the MIM capacitor electrodes formed by the first WN thin film layer and the second WN thin film layer have good performance; By using the pulsed nucleation layer process to form the first WN thin film layer and the second WN thin film layer, excellent step coverage can be achieved while completing thick film deposition, and production capacity can be improved. Description of the Drawings

[0015] In order to more clearly illustrate the specific embodiments of this application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1It is a flowchart of a method for forming a three-dimensional MIM capacitor electrode plate provided by an exemplary embodiment of the present application; Figures 2-7 It is a schematic diagram of a device structure during the implementation of a method for forming a three-dimensional MIM capacitor electrode plate provided by an exemplary embodiment of the present application.

[0017] Explanation of reference numerals: 1. First dielectric layer; 11. Metal connection; 2. Dielectric barrier layer; 3. Second dielectric layer; 4. Through hole; 5. First WN thin film layer; 6. Insulating layer; 7. Second WN thin film layer; 8. Metal barrier layer; 9. Metal layer. Detailed implementation manners

[0018] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0019] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0020] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0021] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0022] The present application provides a method for forming a three-dimensional MIM capacitor electrode plate. Referring to Figure 1 , the method includes the following steps: S1: Provide a semiconductor device in which metal interconnects are formed in a first dielectric layer, and a dielectric barrier layer and a second dielectric layer are sequentially formed on the first dielectric layer.

[0023] Exemplarily, referring to Figure 2 , a semiconductor device is provided, in which metal interconnects 11 are formed in a first dielectric layer 1 of the semiconductor device, and a dielectric barrier layer 2 and a second dielectric layer 3 are sequentially formed on the first dielectric layer 1. Among them, the first dielectric layer 1 and the second dielectric layer 3 may be oxide layers, such as silicon dioxide layers, and the dielectric barrier layer 2 may be a doped silicon carbide thin film (nitride doped silicon carbide, NDC).

[0024] S2: Form a via hole in the second dielectric layer to expose the metal interconnect at the bottom of the via hole.

[0025] Exemplarily, referring to Figure 2 , a via hole 4 is etched and formed in the second dielectric layer 3, and the via hole 4 penetrates through the underlying dielectric barrier layer 2 to expose the underlying metal interconnect 11. Thereafter, the inner wall of the via hole 4 can be pre-cleaned to remove the residues therein.

[0026] S3: Grow a first WN thin film layer, which covers the bottom of the via hole and the surface of the second dielectric layer.

[0027] Exemplarily, referring to Figure 3 , a first WN thin film layer 5 is grown, which covers the bottom of the via hole 4 and the surface of the second dielectric layer 3 and contacts the exposed part of the metal interconnect layer 11. Among them, the thickness of the first WN thin film layer 5 can be 150 - 300 angstroms.

[0028] Furthermore, in this step, the first WN thin film layer 5 can be grown by a pulsed nucleation layer (PNL) process. For example, several cycles of thin film deposition can be carried out in the reaction chamber of an atomic layer deposition tool. In a single cycle, B2H6 (diborane) gas, WF6 (tungsten hexafluoride) gas, and NH3 (ammonia) gas are sequentially pulsed, and finally the first WN thin film layer 5 is obtained.

[0029] S4: Form an insulating layer on the first WN thin film layer.

[0030] Exemplarily, referring to Figure 4 , an insulating layer 6 is formed on the first WN thin film layer 5.

[0031] Among them, the insulating layer 6 can be an Al2O3 layer, and can be obtained by depositing Al2O3 on the first WN thin film layer 5 through an atomic layer deposition process. The thickness of the insulating layer 6 can be 200 - 500 angstroms.

[0032] S5: Form a second WN thin film layer on the insulating layer.

[0033] Exemplarily, referring to Figure 5 , grow a second WN thin film layer 7 on the insulating layer 6. The thickness of the second WN thin film layer 7 can be 150 - 300 angstroms.

[0034] Among them, the formation process of the second WN thin film layer 7 is similar to the process of forming the first WN thin film layer 5 in step S3, which will not be elaborated here.

[0035] S6: Form a metal layer on the second WN thin film layer, and the metal layer fills the through - hole.

[0036] Exemplarily, referring to Figure 6 , form a metal layer 9 on the second WN thin film layer 7, and the metal layer 9 fills the through - hole 4.

[0037] Furthermore, the metal layer 9 can be a copper layer. The formation process of the metal layer 9 can be as follows: S61: Sequentially form a metal barrier layer and a copper seed layer on the second WN thin film layer.

[0038] Exemplarily, referring to Figure 6 , a metal barrier layer 8 can be formed on the second WN thin film layer 7 through physical vapor deposition process. The metal barrier layer 8 can be a TaN / Ta layer, which is used to block the diffusion of the subsequently formed copper. Then, a copper seed layer is formed on the metal barrier layer 8 through physical vapor deposition process.

[0039] S62: Form an electroplated copper layer on the copper seed layer through electroplating process. The copper seed layer and the electroplated copper layer constitute the metal layer 9.

[0040] Exemplarily, referring to Figure 6 , process the copper seed layer through electroplating process, so as to form an electroplated copper layer on the copper seed layer. The copper seed layer and the electroplated copper layer together constitute the metal layer 9.

[0041] S7: Perform planarization treatment to remove the first WN thin film layer, insulating layer, second WN thin film layer, and metal layer located outside the through - hole.

[0042] Exemplarily, referring to Figure 7 , planarization treatment can be performed through CMP process, so as to remove the first WN thin film layer 5, insulating layer 6, second WN thin film layer 7, metal layer 9, and metal barrier layer 8 located outside the through - hole 4, and expose the surface of the second dielectric layer 3. The remaining first WN thin film layer 5 constitutes the lower electrode plate, the remaining second WN thin film layer 7 constitutes the upper electrode plate, and the remaining insulating layer 6 is isolated between the upper electrode plate and the lower electrode plate, thus obtaining the MIM capacitor electrode structure.

[0043] In the method for forming a three-dimensional MIM capacitor electrode plate provided by the embodiments of the present application, on the one hand, since WN has the advantages of no plasma participation, good blocking ability, good thermal stability, etc., the MIM capacitor electrode plate formed by the first WN thin film layer 5 and the second WN thin film layer 7 has good performance. On the other hand, by using the pulsed nucleation layer process to form the first WN thin film layer 5 and the second WN thin film layer 7, excellent step coverage can be achieved while the thick film deposition is completed, and the production capacity can be improved.

[0044] Obviously, the above embodiments are merely examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for forming a three-dimensional MIM capacitor electrode plate, characterized in that Including: Provided is a semiconductor device, in which metal interconnects are formed in a first dielectric layer of the semiconductor device, and a dielectric barrier layer and a second dielectric layer are sequentially formed on the first dielectric layer; A through hole is formed in the second dielectric layer to expose the metal interconnect at the bottom of the through hole; A first WN thin film layer is grown, and the first WN thin film layer covers the bottom of the through hole and the surface of the second dielectric layer; An insulating layer is formed on the first WN thin film layer; A second WN thin film layer is formed on the insulating layer; A metal layer is formed on the second WN thin film layer, and the metal layer fills the through hole; A planarization process is performed to remove the first WN thin film layer, the insulating layer, the second WN thin film layer, and the metal layer located outside the through hole.

2. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 1, wherein, The growing of the first WN thin film layer includes: Growing a first WN thin film layer on the bottom of the through hole and the surface of the second dielectric layer by a pulsed nucleation layer process.

3. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 1, wherein The thickness of the first WN thin film layer is 150 - 300 angstroms.

4. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 1, wherein The forming of the insulating layer on the first WN thin film layer includes: Depositing Al2O3 on the first WN thin film layer by atomic layer deposition to form the insulating layer.

5. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 4, wherein The thickness of the deposited Al2O3 is 200 - 500 angstroms.

6. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 1, wherein The thickness of the second WN thin film layer is 150 - 300 angstroms.

7. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 1, characterized in that, The metal layer is a copper layer.

8. The method for forming a three-dimensional MIM capacitor electrode plate according to claim 7, characterized in that, The forming of the metal layer on the second WN thin film layer includes: Sequentially forming a metal barrier layer and a copper seed layer on the second WN thin film layer; Forming an electroplated copper layer on the copper seed layer by electroplating, and the copper seed layer and the electroplated copper layer constitute the metal layer.

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