IGBT device structure and preparation method thereof

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure and a preparation method thereof, the IGBT device structure is suitable for an IGBT device with the repetitive unit size of 0.6-1.6 mu m, a thick first dielectric layer is arranged at the bottom of a first groove in an active region, so that the breakdown voltage of gate oxide is improved, the area of gate-drain capacitance is reduced, the switching delay time is shortened, the switching dynamic loss of the device is reduced, and the reliability of the device is improved. The switching characteristic of the device is improved; a thick first dielectric layer is arranged in a second groove in a transition region, the influence of internal high field intensity in the transition region on the service life of gate oxide in the second groove is reduced, the reliability and firmness of the device are improved, the depth of the second groove in the transition region is increased by using the load effect of etching the first groove and the second groove, and the device performance is improved. Therefore, diffusion of P-type doping of the terminal region to the active region can be reduced, reduction of the size of the transition region and reduction of the chip area are facilitated, in addition, the source region contact hole, the first contact hole, the second contact hole and the third contact hole are formed only through one photoetching process, and the photoetching level and the manufacturing cost are reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to an IGBT device structure and a preparation method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor), as a composite fully controlled voltage-driven power semiconductor device composed of BJT (Bipolar Junction Transistor) and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), has the advantages of high input impedance of MOSFET, small power of the drive circuit, simple drive, fast switching speed, and small switching loss, and also has the advantages of large current density of BJT, strong current handling capacity, and low on-state saturation voltage. With the strong support of China for the IGBT (Insulated Gate Bipolar Transistor) industry, domestic manufacturers have made remarkable breakthroughs in the fields of chip design, manufacturing process, and reliability optimization. Domestic IGBTs have continuously increased their market penetration rate due to faster customer response speed, cost advantages, and flexible services adapted to local demands, and the trend of domestic substitution has become increasingly significant. However, in high-reliability application scenarios such as new energy vehicles, rail transit, and smart grids, the robustness of the device under extreme working conditions (such as short-circuit resistance and dynamic turn-off stability) is still the core challenge restricting its large-scale application. How to optimize the IGBT structure to balance conduction loss, switching speed, and reliability has become a hot research issue at home and abroad.

[0003] Since the advent of IGBT technology, its structure has undergone multiple iterative upgrades. For example, advanced structures such as carrier storage trench IGBT (CSTBT) and micro-trench IGBT (MPT) have significantly reduced the on-state voltage drop and improved the switching efficiency by introducing carrier storage layers, refined trench designs, and other means. However, the optimization of the internal electric field distribution and carrier dynamic behavior in IGBT chips by existing technologies still has limitations. Especially in the design of the transition region structure of the chip, the problems of current concentration and local high electric field strength have long existed, seriously affecting the reliability of IGBT devices.

[0004] Specifically, an IGBT chip is usually divided into an active region, a transition region, and a termination region. When the device is turned on, holes are injected from the back collector P + layer into the drift region. When the device is turned off, all electrons and holes in the drift region need to be extracted. Among them, the holes in the active region can directly flow out through the openings in the front electrode, but the termination region lacks a direct hole extraction channel, and its holes need to be discharged through the openings in the transition region. This will cause the current in the transition region to be too concentrated, and at the same time, the high electric field strength in the body is often in the transition region. The large current and high electric field strength concentration regions are prone to induce dynamic avalanche breakdown, resulting in permanent failure of the device. Therefore, how to optimize the structure design of the transition region is crucial for improving the reliability and robustness of IGBTs.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide an IGBT device structure and a preparation method thereof, which are used to realize an IGBT device with low feedback capacitance and low switching loss, and at the same time solve the problem that when the IGBT chip is turned off in the prior art, due to the lack of a direct hole extraction channel in the terminal region, the current concentration in the transition region is caused, thereby affecting the reliability of the IGBT device structure.

[0007] To achieve the above object and other related objects, the present invention provides a preparation method of an IGBT device structure, and the preparation method at least includes the following steps:

[0008] Provide a substrate, the substrate is provided with an active region, a transition region and a terminal region arranged in sequence, form a first oxide layer on the top of the terminal region, form a cutoff ring doping region on the edge of the terminal region, and form a carrier storage layer on the top of the active region by ion implantation;

[0009] Form a plurality of first trenches arranged at intervals in the active region and form a plurality of second trenches arranged at intervals in the transition region, and the depths of the first trenches and the second trenches are greater than the depth of the carrier storage layer;

[0010] Form a first dielectric layer on the surface of the substrate, the first dielectric layer completely fills the first trenches and the second trenches, and etch the first dielectric layer in the first trenches and the second trenches to remove part of the first dielectric layer;

[0011] Form a gate oxide layer on the side walls of the first trenches and form a polysilicon layer in the first trenches and on the surface of the substrate;

[0012] Form a first mask layer on the polysilicon layer, and etch the polysilicon layer based on the first mask layer to form a first groove in the polysilicon layer in the first trenches;

[0013] Form a second oxide layer on the bottom and side walls of the first groove, the surface of the active region and the surface of the cutoff ring doping region;

[0014] A front metal layer is formed on the front side of the substrate, and ion implantation is performed on the back side of the substrate to form a collector region and multiple hydrogen ion implantations are performed to form a buffer layer, and then a back metal layer is formed on the back side of the substrate.

[0015] Optionally, before forming the carrier storage layer, it further includes the step of forming a laterally graded doping region by ion implantation, wherein the laterally graded doping region spans across the transition region and the terminal region.

[0016] Optionally, before forming the first trench, it further includes the step of forming a dielectric protection layer on the surface of the substrate, wherein the dielectric protection layer includes a silicon nitride layer, a silicon dioxide layer or the dielectric protection layer includes a composite layer stacked with a silicon dioxide layer and a silicon nitride layer.

[0017] Optionally, the material for forming the first dielectric layer includes at least one of SiO2, SiON, Si3N4 or high-k dielectric materials, and the thickness of the first dielectric layer is 600 - 1000 nm.

[0018] Optionally, the depth of the first trench is 2.5 - 5 μm, the depth of the second trench is 2.5 - 5 μm and the depth of the first trench is less than the depth of the second trench.

[0019] Optionally, after patterning and etching the first dielectric layer in the first trench and the second trench, the height of the remaining first dielectric layer in the first trench is 0.5 - 2 μm, and the height of the first dielectric layer in the second trench is flush with the surface of the substrate.

[0020] Optionally, the depth of the first groove is 0.4 - 0.55 μm.

[0021] Optionally, before forming the second oxide layer, it further includes the steps of performing P-type ion implantation in the active region and the transition region to form a first doped region, and performing N-type ion implantation on the top of the first doped region in the active region to form a second doped region, and the bottom of the first doped region is higher than the top of the first dielectric layer, and the bottom of the second doped region is lower than the top of the polysilicon layer in the first trench.

[0022] Optionally, after forming the second oxide layer, it further includes the step of forming an isolation layer on the surface of the substrate, and performing a photolithography process on the isolation layer to form a source contact hole in the substrate in the active region, a first contact hole and a second contact hole in the GateBus structure and the field plate structure, and a third contact hole on the cutoff ring doping region, wherein the top of the polysilicon layer is exposed by the first contact hole and the second contact hole, and the cutoff ring doping region is exposed by the third contact hole.

[0023] Optionally, before forming the front metal layer, ion implantation is also performed at the bottoms of the source region contact holes, the first contact hole, the second contact hole, and the third contact hole to form contact hole P + type implantation layer.

[0024] Optionally, the angle of the source region contact hole is 80 - 86°, and the depth of the source region contact hole is 0.7 - 1.2 μm.

[0025] The present invention also provides an IGBT device structure, which is prepared by using the preparation method of the IGBT device structure described in any one of the above - mentioned solutions.

[0026] As described above, the present invention provides an IGBT device structure and its preparation method, which have the following beneficial effects:

[0027] In the present invention, by providing a first dielectric layer with a thickness of 0.5 - 2 μm in the first trench in the active region of the IGBT device, the weakness that the gate oxide layer at the bottom of the first trench is easily broken down is eliminated, and the robustness of the gate oxide breakdown voltage is improved. At the same time, the gate - drain capacitance is also reduced, the switching delay time is decreased, the switching dynamic loss of the device is reduced, and the switching characteristics of the device are improved; meanwhile, the second trench in the transition region is completely filled with the first dielectric layer or a first dielectric layer with a thickness of 0.5 - 2 μm is provided at the bottom of the second trench, reducing the influence of the high in - body field strength at the transition region on the gate oxide lifetime in the second trench, thereby enhancing the reliability and robustness of the device. In addition, by increasing the width of the second trench in the transition region and utilizing the loading effect during the etching of the first trench and the second trench, the depth of the second trench in the transition region can be made greater than the depth of the first trench in the active region, so as to reduce the diffusion of the P - type doping in the terminal region into the active region, which helps to reduce the size of the transition region and the chip area. In addition, the source region contact holes, the first contact hole, the second contact hole, and the third contact hole are formed only through one photolithography process, thereby reducing the photolithography levels and manufacturing costs. Description of the Drawings

[0028] Figure 1 It shows the process flow chart of the preparation method of the IGBT device structure in the present invention.

[0029] Figures 2 to 17 It shows the schematic diagrams of the device structures corresponding to the respective steps of the preparation method of the IGBT device structure in the embodiment of the present invention.

[0030] Description of the Reference Numerals

[0031] 10. Substrate; 11. Lateral variable doping region; 12. Cut-off ring doping region; 13. First oxide layer; 14. Carrier storage layer; 15. Dielectric protection layer; 151. Bottom layer; 152. Intermediate layer; 153. Top layer; 16. First trench; 17. Second trench; 18. First dielectric layer; 19. Gate oxide layer; 20. Polysilicon layer; 21. First mask layer; 211. Thermal oxide layer; 212. Silicon nitride layer; 23. First groove; 24. Gate Bus structure; 25. Field plate structure; 26. First doping region; 27. Second doping region; 28. Second oxide layer; 29. Isolation layer; 30. Source region contact hole; 31. First contact hole; 32. Second contact hole; 33. Third contact hole; 34. Contact hole P + type injection layer; 35. Front metal layer; 36. Buffer layer; 361. First N-type doping peak; 362. Second N-type doping peak; 363. Third N-type doping peak; 364. Fourth N-type doping peak; 37. Collector region; 38. Back metal layer; S1 to S7: Steps. Detailed implementation mode

[0032] The following describes the implementation modes of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole parts, steps or components, but does not exclude the presence or addition of one or more other features, whole parts, steps or components.

[0034] Features described and / or shown for one implementation mode can be used in the same or similar manner in one or more other implementation modes, combined with the features in other implementation modes, or replace the features in other implementation modes.

[0035] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions of length, width and depth should be included.

[0036] For ease of description, spatially relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to another element or feature. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0037] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0039] As Figures 1 to 17 shown, this embodiment provides a method for manufacturing an IGBT device structure, and the manufacturing method at least includes the following steps:

[0040] S1: Provide a substrate 10, the substrate 10 is provided with an active region, a transition region, and a termination region arranged in sequence. A first oxide layer 13 is formed on the top of the termination region, a cutoff ring doping region 12 is formed at the edge of the termination region, and a carrier storage layer 14 is formed on the top of the active region by ion implantation;

[0041] S2: Form a plurality of first trenches 16 arranged at intervals in the active region and a plurality of second trenches 17 arranged at intervals in the transition region. The depths of the first trenches 16 and the second trenches 17 are greater than the depth of the carrier storage layer 14;

[0042] S3: Form a first dielectric layer 18 on the surface of the substrate 10. The first dielectric layer 18 completely fills the first trenches 16 and the second trenches 17, and the first dielectric layer 18 in the first trenches 16 and the second trenches 17 is etched to remove part of the first dielectric layer 18;

[0043] S4: Form a gate oxide layer 19 on the sidewalls of the first trenches 16 and form a polysilicon layer 20 in the first trenches 16 and on the surface of the substrate 10;

[0044] S5: Form a first mask layer 21 on the polysilicon layer 20, and etch the polysilicon layer 20 based on the first mask layer 21 to form a first groove 23 in the polysilicon layer 20 within the first trench 16;

[0045] S6: Form a second oxide layer 28 on the bottom and sidewalls of the first groove 23, the surface of the active region, and the surface of the cutoff ring doping region 12;

[0046] S7: Form a front metal layer 35 on the front surface of the substrate 10, perform ion implantation on the back surface of the substrate 10 to form a collector region 37, and perform multiple hydrogen ion implantations to form a buffer layer 36, and then form a back metal layer 38 on the back surface of the substrate 10.

[0047] The preparation method of the IGBT device structure is further introduced below in conjunction with the accompanying drawings, specifically as follows:

[0048] In step S1, please refer to Figure 1 and Figure 2 , provide a substrate 10, the substrate 10 is provided with an active region, a transition region, and a terminal region arranged in sequence, form a first oxide layer 13 on the top of the terminal region, form a cutoff ring doping region 12 on the edge of the terminal region, and form a carrier storage layer 14 on the top of the active region by ion implantation.

[0049] In one embodiment, the substrate 10 can be a common silicon substrate 10, germanium-silicon substrate 10, silicon carbide substrate 10, etc. The substrate 10 can be doped, and its doping concentration and thickness can be set according to the breakdown voltage requirement of the IGBT device. Preferably, in this embodiment, the substrate 10 selects a doped silicon substrate 10, and its doping type is N-type doping.

[0050] As Figure 2 shown, form a first oxide layer 13 on the top of the terminal region, form a cutoff ring doping region 12 on the edge of the terminal region, and form a carrier storage layer 14 on the top of the active region by ion implantation.

[0051] Specifically, form a field oxide layer on the top of the terminal region. For example, a field oxide layer can be formed on the surface of the substrate 10 through a thermal oxidation process, and then a first oxide layer 13 is formed on the surface of the terminal region through photolithography and etching processes; P-type ions (such as boron, etc.) can be implanted in the transition region and the terminal region through a mask plate, and the implantation dose can be 1e12 cm -2 ~5e13 cm -2 , the implantation energy can be 60 keV to 200 keV. Then, N-type ions (such as phosphorus, etc.) are implanted in the edge region of the terminal region through a mask plate, and the implantation dose is 1e15 cm -2~1e16 cm -2 The implantation energy is 60 keV to 200 keV, and a thermal process is carried out once (such as an annealing process). The annealing temperature is 1050 °C to 1250 °C, and the time is 30 min to 300 min, so as to form an N-type doped cutoff ring doping region 12 at the edge of the terminal region. Of course, in other embodiments, the cutoff ring doping region 12 may not be fabricated additionally to save process costs; the carrier storage layer 14 is implanted through a mask or generally implanted without a mask. The implanted ions can be phosphorus, and the implantation dose can be 1e12 cm -2 ~5e13 cm -2 The implantation energy can be 80 keV to 2 MeV, and a thermal process is carried out once (such as an annealing process). The annealing temperature is 1050 °C to 1250 °C, and the time is 30 min to 300 min. In another embodiment, the formation of the carrier storage layer 14 can also be carried out before the formation of the first doping region 26. The process sequence of forming the carrier storage layer 14 does not affect the performance of the IGBT device structure.

[0052] In another embodiment, before forming the carrier storage layer 14, it further includes the step of forming a laterally graded doping region 11 by ion implantation. Specifically, P-type ions (such as boron, etc.) can be implanted in the transition region and the terminal region through a mask to make the formed laterally graded doping region 11 span the transition region and the terminal region. The implantation dose can be 1e13 cm -2 ~5e13 cm -2 The implantation energy can be 60 keV to 200 keV. Then, N-type ions (such as phosphorus, etc.) are implanted in the edge region of the terminal region through a mask, and the implantation dose is 1e15 cm -2 ~1e16 cm -2 The implantation energy is 60 keV to 200 keV, and a thermal process is carried out once (such as an annealing process). The advancing temperature is 1050 °C to 1250 °C, and the time is 30 min to 300 min, so as to form a P-type doped field limiting ring (JTE) or a laterally graded doping region 112 (VLD) terminal in the P-type ion implantation region.

[0053] In step S2, please refer to Figure 1 、 Figure 3 and Figure 4 Multiple first trenches 16 arranged at intervals are formed in the active region, and multiple second trenches 17 arranged at intervals are formed in the transition region. The depths of the first trenches 16 and the second trenches 17 are greater than the depth of the carrier storage layer 14.

[0054] In one embodiment, such as Figure 3As shown, before forming the first trench 16, it further includes the step of forming a dielectric protection layer 15 on the surface of the substrate 10. Among them, the dielectric protection layer 15 is selected as a material having a high etching selectivity ratio with respect to the material of the substrate 10. The dielectric protection layer 15 serves as an etching stop layer when forming the first dielectric layer 18 subsequently, and can protect the first oxide layer 13 on the surface of the terminal region from being accidentally etched. The high etching selectivity ratio can be, for example, substrate 10: dielectric protection layer 15 being greater than or equal to 10:1. For example, when the substrate 10 is a silicon substrate 10, the dielectric protection layer 15 can be silicon nitride or silicon dioxide, or the dielectric protection layer 15 can be a composite sandwich structure stacked with silicon dioxide and silicon nitride. For example, the bottom layer 151 is silicon dioxide, the intermediate layer 152 is silicon nitride, and the top layer 153 is also silicon dioxide. Among them, the thickness of the bottom layer 151 The thickness of the intermediate layer 152 The thickness of the top layer 153

[0055] In one embodiment, as Figure 4 shown, the dielectric protection layer 15 and the substrate 10 can be etched through a mask plate, so as to form a plurality of first trenches 16 arranged at intervals in the active region and a plurality of second trenches 17 arranged at intervals in the transition region. Among them, the depth of the first trench 16 is greater than the depth of the carrier storage layer 14, and the depth of the second trench 17 is greater than the depth of the carrier storage layer 14.

[0056] In another embodiment, the depth of the first trench 16 is 2.5 - 5 μm, the depth of the second trench 17 is 2.5 - 5 μm and the depth of the first trench 16 is less than that of the second trench 17. The size of the repeating unit of the plurality of spaced-apart first trenches 16 is 0.6 - 1.6 μm, and the size of the repeating unit of the plurality of spaced-apart second trenches 17 is 0.6 - 1.6 μm. Here, the size of the repeating unit refers to the sum of the width of the first trench 16 and the width to the next adjacent first trench 16, or the sum of the width of the second trench 17 and the width to the next adjacent second trench 17. Specifically, when etching the dielectric protection layer 15 and the substrate 10 to form the first trench 16 and the second trench 17, since the designed width of the second trench 17 is greater than that of the first trench 16, due to the etching loading effect, the depth of the second trench 17 finally formed in the transition region will be greater than that of the first trench 16 formed in the active region, thereby reducing the diffusion of the P-type doping in the terminal region into the active region. Moreover, the widths of the plurality of second trenches 17 in the transition region can be set to be the same or different. For example, the widths of the plurality of second trenches 17 gradually decrease from the side close to the active region towards the terminal region, or the widths of the plurality of second trenches 17 gradually increase from the side close to the active region towards the terminal region. There is no special limitation here.

[0057] In step S3, please refer to Figure 1 , Figure 5 and Figure 6 , a first dielectric layer 18 is formed on the surface of the substrate 10. The first dielectric layer 18 completely fills the first trench 16 and the second trench 17, and the first dielectric layer 18 in the first trench 16 and the second trench 17 is etched to remove a part of the first dielectric layer 18.

[0058] In one embodiment, as Figure 5 shown, a first dielectric layer 18 is deposited on the top of the dielectric protection layer 15. The material forming the first dielectric layer 18 includes at least one of SiO2, SiON, Si3N4 or high-k dielectric materials. The thickness of the first dielectric layer 18 on the surface of the substrate 10 can be 600 - 1000 nm. Among them, the first dielectric layer 18 also needs to completely fill the first trench 16 and the second trench 17.

[0059] In one embodiment, taking the material of the first dielectric layer 18 as SiO2 as an example, as Figure 6 shown in a, first, the first dielectric layer 18 in the active region is etched using a mask plate, and the first dielectric layer 18 in the first trench 16 in the active region is etched to the top of the first trench 16, or the first dielectric layer 18 in the first trench 16 in the active region is etched to be lower than the top of the first trench 16; as Figure 6As shown in Fig. b, continue to etch the first dielectric layer 18 in the active region and the transition region, etch the first dielectric layer 18 in the first trench 16 in the active region until the remaining height is 0.5 - 2 μm, and the height of the first dielectric layer 18 in the second trench 17 is flush with the surface of the substrate 10. Then, remove the dielectric protection layer 15 through a dry etching process.

[0060] In another embodiment, taking the material of the first dielectric layer 18 as Si3N4 as an example, at this time, as Figure 7 shown, a wet etching process can be used to etch the first dielectric layer 18 in the active region and the transition region simultaneously, etch the first dielectric layer 18 in the first trench 16 in the active region until the remaining height is 0.5 - 2 μm, and at the same time, etch the first dielectric layer 18 in the second trench 17 in the transition region until the remaining height is 0.5 - 2 μm. Then, remove the dielectric protection layer 15 through a dry etching process.

[0061] In step S4, please refer to Figure 1 and Figure 8 , form a gate oxide layer 19 on the sidewall of the first trench 16 and form a polysilicon layer 20 in the first trench 16 and on the surface of the substrate 10.

[0062] In one embodiment, taking the material of the first dielectric layer 18 as SiO2 as an example, as Figure 8 shown, specifically, a thermal oxidation process (such as heating through a furnace tube in an oxygen atmosphere, etc.) is used to form a gate oxide layer 19 on the sidewall of the first trench 16 and on the surface of the substrate 10, and the thickness of the gate oxide layer 19 is Then, a polysilicon layer 20 is formed in the first trench 16 and on the surface of the substrate 10 through a deposition process. The thickness of the polysilicon layer 20 is 600 - 1000 nm, and the polysilicon layer 20 covers the gate oxide layer 19 on the surface of the substrate 10 and the cutoff ring doping region 12 at the edge of the terminal region.

[0063] In step S5, please refer to Figure 1 , Figure 9 and Figure 10 , form a first mask layer 21 on the polysilicon layer 20, and etch the polysilicon layer 20 based on the first mask layer 21 to form a first groove 23 in the polysilicon layer 20 in the first trench 16.

[0064] In one embodiment, as Figure 9As shown, the polysilicon layer 20 is subjected to an annealing process. The annealing temperature is 900 - 1100 °C, and the annealing time is 10 - 60 min. Meanwhile, oxygen is introduced during annealing to grow a thermal oxide layer 211 on the surface of the polysilicon layer 20. After the annealing process is completed, a silicon nitride layer 212 is deposited on the thermal oxide layer 211. Among them, the thickness of the thermal oxide layer 211 is The thickness of the silicon nitride layer 212 is And the thermal oxide layer 211 and the silicon nitride layer 212 together form the first hard mask layer 21, which facilitates the subsequent formation of the active region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 300. Meanwhile, the annealing process after the formation of the polysilicon layer 20 is beneficial to improving the depth uniformity and stability of the formed first groove 23. Preferably, the annealing temperature is set to 1100 °C, and the annealing time is set to 20 min.

[0065] In one embodiment, the first mask layer 21 and the polysilicon layer 20 are etched to form a first groove 23 in the polysilicon layer 20 within the first trench 16. Specifically, as Figure 10 shown, the polysilicon layer 20 on the first trench 16 and the second trench 17 is completely removed, and the polysilicon layer 20 and the gate oxide layer 19 within the first trench 16 are partially removed to form the first groove 23. The depth of the first groove 23 can be 0.4 - 0.55 μm. For example, it can be 0.4 μm, 0.45 μm, 0.5 μm, or 0.55 μm. Meanwhile, a Gate Bus structure 24 and a field plate structure 25 are formed on the top of the transition region and the terminal region. Specifically, as Figure 10 shown, a part of the polysilicon layer 20 and the first mask layer 21 on the top of the transition region and the terminal region are completely etched away, exposing the top of the first oxide layer 13 and the cutoff ring doping region 12. Among them, the Gate Bus structure 24 straddles the transition region and the terminal region, and the field plate structure 25 is close to the edge of the terminal region and is completely located within the terminal region. In step S6, please refer to Figure 1 、 Figures 11 to 13 , a second oxide layer 28 is formed on the bottom and sidewalls of the first groove 23, the surface of the active region, the surface of the cutoff ring doping region 12, and the side surfaces of the polysilicon layer 20 in the Gate Bus structure 24 and the field plate structure 25.

[0066] In one embodiment, as Figure 11As shown, before forming the second oxide layer 28, it also includes steps of performing P-type ion implantation in the active region and the transition region to form a first doped region 26, and performing N-type ion implantation on the top of the first doped region 26 in the active region to form a second doped region 27. Specifically, general implantation of the first doped region 26 is performed on the top of the active region and the transition region. The implanted ions can be boron, the implantation dose is 6e13 cm -2 ~1.5e14 cm -2 , the implantation energy is 60 - 200 keV, the driving temperature can be 1050 - 1250 °C, the time is 10 - 120 min. Then, through a mask plate, implantation of the second doped region 27 is performed on the top of the first doped region 26 in the active region. The implanted ions can be arsenic, the implantation dose can be 8e15 cm -2 ~2e16 cm -2 , the implantation energy can be 60 - 600 keV, the driving temperature can be 900 - 1000 °C, the time can be 1 - 30 min, so that the bottom of the finally formed first doped region 26 is at least 0.5 μm higher than the top of the first dielectric layer 18, and at least 0.3 μm higher than the bottom of the carrier storage layer 14, and the bottom of the second doped region 27 is at least 0.2 μm lower than the top of the polysilicon layer 20 in the first trench 16.

[0067] Then, as Figure 12 shown, a second oxide layer 28 is formed on the bottom and sidewalls of the first groove 23, the surface of the active region, the surface of the isolation ring doped region 12, and the sides of the polysilicon layer 20 in the Gate Bus structure 24 and the field plate structure 25. For example, the growth of the second oxide layer 28 can be carried out in a furnace tube, the growth temperature can be 950 - 1150 °C, and the thickness of the second oxide layer 28 can be Then, an isolation layer 29 is deposited and formed on the substrate 10. As Figure 13 shown, then etching is performed based on the isolation layer 29. By setting the etching selectivity between the substrate 10 and the isolation layer 29, a part of the substrate 10 at the active region is removed to form a source contact hole 30, a first contact hole 31 and a second contact hole 32 are respectively formed in the Gate Bus structure 24 and the field plate structure 25, and a third contact hole 33 is formed on the isolation ring doped region 12.

[0068] In one embodiment, as Figure 12 shown, depositing and forming the isolation layer 29 on the substrate 10 includes steps: depositing a borophosphosilicate glass layer (BPSG) on the substrate 10, and then performing a reflow process on the borophosphosilicate glass layer (BPSG) to form the isolation layer 29. Specifically, the thickness of the deposited borophosphosilicate glass layer (BPSG) can be The reflow temperature of the borophosphosilicate glass layer (BPSG) can be 900 - 1000 °C, and the time can be 30 - 240 min.

[0069] In one embodiment, as Figure 13 shown, after forming the isolation layer 29, it further includes performing a photolithography process on the isolation layer 29 to form a source region contact hole 30 in the substrate 10 in the active region, a first contact hole 31 and a second contact hole 32 in the Gate Bus structure 24 and the field plate structure 25 respectively, and a third contact hole 33 on the cutoff ring doping region 12. Specifically, the isolation layer 29 is etched through a mask plate. In the active region, based on the etching selectivity between the second oxide layer 28 in the first groove 23, the isolation layer 29 and the substrate 10 (such as the silicon substrate 10) exposed between the isolation layer 29 and the first groove 23, a part of the substrate 10 is etched away to form the source region contact hole 30. The angle of the source region contact hole 30 is 80 - 86°, and the depth of the source region contact hole 30 is 0.7 - 1.2 μm. The preparation method provided by the present invention can ensure the distance between the source region contact hole 30 and the first trench 16, thereby ensuring the consistency of the saturation voltage drop of each IGBT device in the wafer. At the same time, the cutoff ring doping region 12 is etched based on the isolation layer 29 to form a third contact hole 33 in the cutoff ring doping region 12, and the bottom of the third contact hole 33 exposes the cutoff ring doping region 12. After forming the source region contact hole 30 and the third contact hole 33, it further includes the step of etching and forming the first contact hole 31 and the second contact hole 32 in the Gate Bus structure 24 and the field plate structure 25. Among them, the bottoms of the first contact hole 31 and the second contact hole 32 expose the polysilicon layer 20. Specifically, the Gate Bus structure 24 and the field plate structure 25 are etched based on the isolation layer 29 to remove the first mask layer 21 in the Gate Bus structure 24 and the field plate structure 25, thereby forming the first contact hole 31 and the second contact hole 32, and the bottoms of the first contact hole 31 and the second contact hole 32 expose the polysilicon layer 20.

[0070] In another embodiment, as Figure 14 shown, contact holes can also be added on the side of the second trench 17 closest to the terminal region at the outermost periphery of the transition region, thereby improving the reliability of the IGBT device during turn-off. The contact holes can be one or more strip-shaped contact holes.

[0071] In another embodiment, the first hard mask layer 21 may also only include a thermal oxide layer 211. At this time, in order to ensure that the polysilicon layer 20 at the Gate Bus structure 24 and the field plate structure 25 is not completely etched when forming the source region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33 by lithography, it is also necessary to increase the thickness of the polysilicon layer 20 to or more. Specifically, a photoresist masking layer is first formed on the thermal oxide layer 211, and then an etching process is performed on the active region, the Gate Bus structure 24, the field plate structure 25, and the cutoff ring doping region 12, so as to form the source region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33. And because the thickness of the polysilicon layer 20 set in this embodiment is greater than it can ensure that the thickness of the remaining polysilicon layer at the above contact holes after etching can still be maintained at or more. Finally, the photoresist masking layer is removed by an ashing process.

[0072] In step S7, please refer to Figure 1 、 Figures 15 to 17 , a front metal layer 35 is formed on the front surface of the substrate 10, ion implantation is performed on the back surface of the substrate 10 to form a collector region 37, and multiple hydrogen ion implantations are performed to form a buffer layer 36, and then a back metal layer 38 is formed on the back surface of the substrate 10.

[0073] In one embodiment, as Figure 16 shown, metal (such as Ti, TiN, or W) is deposited in the source region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33 by a metal deposition process and then etched back. Then, metal (such as Al, Cu) is deposited on the surface of the substrate 10 by a metal deposition process to form a front metal layer 35.

[0074] Before forming the front metal layer 34, it also includes the step of forming a contact hole P + type implantation layer 34 by ion implantation at the bottom of the source region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33. Specifically, as Figure 15 shown, an implantation barrier layer is formed on the sidewalls and the bottom of the source region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33; the implantation barrier layer at the bottom of the source region contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33 is removed by an etching-back process; a contact hole P +P-type implantation layer 34; then the implantation barrier layer is removed by a wet process. Specifically, considering that when ion implantation is performed in the source contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33 to form the contact hole P + type implantation layer 34, the implantation on the sidewall of the source contact hole 30 will affect the doping of the second doped region 27. Therefore, before implanting into the source contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33, a thickness of silicon nitride is deposited first, and then the silicon nitride is etched back. The silicon nitride remaining on the sidewalls can prevent P-type ions from being implanted into the sidewall regions of the source contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33. Then, boron or BF2 implantation is performed, and finally, a contact hole P + type implantation layer 34 is formed at the bottom of the source contact hole 30, the first contact hole 31, the second contact hole 32, and the third contact hole 33. Among them, the implantation energy of BF2 can be 20 - 50 keV, and the implantation dose can be 1e15 cm -2 ~4e15 cm -2 , or the implantation energy of boron can be 40 - 100 keV, and the implantation dose can be 5e12 cm -2 ~5e14 cm -2 . Finally, the silicon nitride on the sidewalls is removed by a wet process. It should be noted that the implantation of the contact hole P + type implantation layer 34 can also be performed after the subsequent wet removal of the isolation layer 29, and is not limited to the examples listed here.

[0075] In one embodiment, as Figure 17 shown, the substrate 10 is flipped, and the substrate 10 is thinned to a certain thickness. The thinned thickness depends on the breakdown voltage requirement of the IGBT device. Then, a boron ion implantation is performed once, with an implantation energy of 60 - 200 KeV and an implantation dose of 3e12 cm -2 ~1e14 cm -2 to form a P-type collector region 35. Then, a laser annealing device is used to activate the implanted boron ions; then, 4 hydrogen implantations are performed from the back of the substrate 10 and annealed to form a buffer layer 36 (for example: after 4 hydrogen implantations, a total of four hydrogen doping peaks are formed, namely the first N-type doping peak 361; the second N-type doping peak 362; the third N-type doping peak 363; the fourth N-type doping peak 364, and the concentrations of the four doping peaks can gradually increase from top to bottom). It should be noted that the number of hydrogen implantations can also be 5 times, 3 times, 2 times, or 1 time, and is not limited to the examples listed here. Finally, a back metal layer 38 is deposited on the back of the substrate 10. The back metal layer 38 can be Al / Ti / Ni / Ag. In another embodiment, the buffer layer 36 can also be formed by phosphorus implantation and laser annealing.

[0076] As Figure 17 shown, in one embodiment, an IGBT device structure is further provided. The IGBT device structure is fabricated by using the fabrication method of the IGBT device structure described in any of the above embodiments.

[0077] As described above, the IGBT device structure and its fabrication method of the present invention are applicable to IGBT devices with a repeating unit size of 0.6 - 1.6 μm. By providing a first dielectric layer with a thickness of 0.5 - 2 μm in the first trench in the active region of the IGBT device, the vulnerability of the gate oxide layer at the bottom of the first trench to breakdown is eliminated, and the robustness of the gate oxide breakdown voltage is improved. At the same time, the gate-drain capacitance is reduced, the switching delay time is decreased, the switching dynamic loss of the device is reduced, and the switching characteristics of the device are improved. At the same time, the second trench in the transition region is completely filled with the first dielectric layer or a first dielectric layer with a thickness of 0.5 - 2 μm is provided at the bottom of the second trench, reducing the influence of the high in-body field strength at the transition region on the gate oxide lifetime in the second trench, thereby enhancing the reliability and ruggedness of the device.

[0078] In addition, by increasing the width of the second trench in the transition region and utilizing the loading effect during the etching of the first trench and the second trench, the depth of the second trench in the transition region can be made greater than the depth of the first trench in the active region, thereby reducing the diffusion of the P-type doping in the terminal region into the active region, helping to reduce the size of the transition region and the chip area. In addition, the source contact hole, the first contact hole, the second contact hole, and the third contact hole are formed by only one photolithography process, thereby reducing the photolithography level and the manufacturing cost. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0079] The above embodiments merely illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing an IGBT device structure, characterized in that, The preparation method at least includes the following steps: Provide a substrate, which is provided with an active region, a transition region, and a terminal region arranged in sequence. Form a first oxide layer on the top of the terminal region, form a cutoff ring doping region on the edge of the terminal region, and form a carrier storage layer on the top of the active region by ion implantation; Form a plurality of first trenches arranged at intervals in the active region and form a plurality of second trenches arranged at intervals in the transition region. The depths of the first trenches and the second trenches are greater than the depth of the carrier storage layer; Form a first dielectric layer on the surface of the substrate. The first dielectric layer completely fills the first trenches and the second trenches, and etch the first dielectric layer in the first trenches and the second trenches to remove part of the first dielectric layer; Form a gate oxide layer on the sidewalls of the first trenches and form a polysilicon layer in the first trenches and on the surface of the substrate; Form a first mask layer on the polysilicon layer, and etch the polysilicon layer based on the first mask layer to form a first groove in the polysilicon layer in the first trenches; Form a second oxide layer on the bottom and sidewalls of the first groove, the surface of the active region, and the surface of the cutoff ring doping region; Form a front metal layer on the front of the substrate, perform ion implantation on the back of the substrate to form a collector region, and perform multiple hydrogen ion implantations to form a buffer layer, and then form a back metal layer on the back of the substrate.

2. The manufacturing method of the IGBT device structure according to claim 1, characterized in that: Before forming the carrier storage layer, it further includes the step of forming a laterally graded doping region by ion implantation, wherein the laterally graded doping region straddles the transition region and the terminal region.

3. The manufacturing method of the IGBT device structure according to claim 1, characterized in that: Before forming the first trenches, it further includes the step of forming a dielectric protection layer on the surface of the substrate, wherein the dielectric protection layer includes a silicon nitride layer, a silicon dioxide layer, or the dielectric protection layer includes a composite layer of a stacked silicon dioxide layer and a silicon nitride layer.

4. The manufacturing method of the IGBT device structure according to claim 1, wherein: The material for forming the first dielectric layer at least includes one of SiO2, SiON, Si3N4, or a high-k dielectric material, and the thickness of the first dielectric layer is 600 - 1000 nm.

5. The manufacturing method of the IGBT device structure according to claim 1, characterized in that: The depth of the first trenches is 2.5 - 5 μm, the depth of the second trenches is 2.5 - 5 μm, and the depth of the first trenches is less than the depth of the second trenches.

6. The manufacturing method of the IGBT device structure according to claim 1, characterized in that: After patterning and etching the first dielectric layer in the first trenches and the second trenches, the height of the remaining first dielectric layer in the first trenches is 0.5 - 2 μm, and the height of the first dielectric layer in the second trenches is flush with the surface of the substrate.

7. The manufacturing method of the IGBT device structure according to claim 1, characterized in that The depth of the first groove is 0.4 - 0.55 μm.

8. The manufacturing method of the IGBT device structure according to claim 1, characterized in that: Before forming the second oxide layer, it further includes the steps of performing P-type ion implantation in the active region and the transition region to form a first doped region, and performing N-type ion implantation on the top of the first doped region in the active region to form a second doped region, and the bottom of the first doped region is higher than the top of the first dielectric layer, and the bottom of the second doped region is lower than the top of the polysilicon layer in the first trenches.

9. The manufacturing method of the IGBT device structure according to claim 1, characterized in that: After forming the second oxide layer, it further includes the steps of forming an isolation layer on the surface of the substrate, and performing a first photolithography process on the isolation layer to form source region contact holes in the substrate in the active region, forming first contact holes and second contact holes in the Gate Bus structure and the field plate structure, and forming third contact holes on the cutoff ring doping region, wherein the top of the polysilicon layer is exposed by the first contact holes and the second contact holes, and the cutoff ring doping region is exposed by the third contact holes.

10. The manufacturing method of the IGBT device structure according to claim 9, characterized in that: Before forming the front metal layer, it further includes a step of performing ion implantation at the bottoms of the source region contact hole, the first contact hole, the second contact hole, and the third contact hole to form a contact hole P + -type implantation layer.

11. The manufacturing method of the IGBT device structure according to claim 9, characterized in that: The angle of the source region contact holes is 80 to 86°, and the depth of the source region contact holes is 0.7 to 1.2 μm.

12. An IGBT device structure, characterized in that, The IGBT device structure is fabricated by using the fabrication method of the IGBT device structure according to any one of claims 1 to 11.

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