Chip, manufacturing method thereof and electronic equipment

Abstract

The invention provides a chip, a manufacturing method thereof and electronic equipment, the chip comprises a semiconductor substrate, a grid electrode, a covering part and a first side wall, the semiconductor substrate comprises a first semiconductor material, the semiconductor substrate is provided with a groove in a source and drain electrode region, the groove is filled with a second semiconductor material, and the second semiconductor material is filled with a second semiconductor material; a lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. The covering part covers the surface of the semiconductor substrate, and the covering part is located at the position between the edge of the groove and the grid electrode. The cover portion includes any insulating material other than an oxide of the first semiconductor material. In the embodiment of the invention, the covering part is arranged on the surface of the semiconductor substrate, and the covering part can always cover the surface of the semiconductor substrate in the epitaxial growth process of the second semiconductor material, so that the second semiconductor material is prevented from growing on the surface of the semiconductor substrate; therefore, the second semiconductor material formed by epitaxy in the groove has a relatively good morphology, and the service life of the chip is relatively long.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a chip, a manufacturing method thereof, and an electronic device. Background Art

[0002] In the field of semiconductor technology, for a metal oxide semiconductor field effect transistor (MOSFET) device, among them, the carriers of an N-type metal oxide semiconductor field effect transistor (NMOS) are electrons, and the carriers of a P-type metal oxide semiconductor field effect transistor (PMOS) are holes. Since the effective mass of holes is larger than that of electrons, the mobility of holes is much smaller than that of electrons. In order to maintain the carrier balance in the MOSFET device and improve the speed of the PMOS, it is necessary to increase the mobility of holes.

[0003] In the related art, in order to increase the mobility of holes, a germanium silicon (SiGe) material is epitaxially grown in the source-drain electrode region of a semiconductor substrate. The lateral compressive stress generated by the germanium silicon material squeezes the channel, making the lattice constant in the channel smaller, thereby increasing the mobility of holes. However, during the manufacturing process of the related art, the epitaxially grown germanium silicon material will have abnormal morphology, affecting the service life of the MOSFET device. Summary of the Invention

[0004] Embodiments of this application provide a chip, a manufacturing method thereof, and an electronic device, to solve the problem of abnormal morphology of the epitaxially grown germanium silicon material in the related art and improve the service life of the chip.

[0005] In a first aspect, embodiments of this application further provide a chip. The chip provided by the embodiments of this application can be a MOSFET device. Specifically, the chip can specifically include a P-type field effect transistor or an N-type field effect transistor. Alternatively, the chip in the embodiments of this application can be a logic chip, a digital logic circuit, a memory (such as a static random access memory), a microprocessor, etc. that include MOSFET devices.

[0006] The chip provided in the embodiment of the present application may include: a semiconductor substrate, a gate, a covering portion, and a first sidewall. The semiconductor substrate has a channel region and a source-drain electrode region, and the semiconductor substrate includes a first semiconductor material. For example, the first semiconductor material may be a semiconductor material such as silicon or germanium. The semiconductor substrate is provided with a groove in the source-drain electrode region, and the groove is filled with a second semiconductor material, and the lattice constant of the second semiconductor material is greater than the lattice constant of the first semiconductor material. The second semiconductor material filled in the groove may generate a lateral compressive stress to squeeze the channel region so that the lattice constant of the channel region becomes smaller, thereby improving the mobility of holes. For example, the first semiconductor material may be silicon, and the second semiconductor material may be an alloy semiconductor material, for example, the second semiconductor material may be a germanium silicon (SiGe) material. Of course, the first semiconductor material and the second semiconductor material may also be other semiconductor materials, for example, the second semiconductor material may also be a material such as silicon carbide (SiC), silicon phosphide (SiP), etc. In a possible implementation, the second semiconductor material may fill the groove and protrude from the surface of the semiconductor substrate. The gate is located at a position corresponding to the channel region on the semiconductor substrate, and a gate insulating layer is provided between the gate and the semiconductor substrate. The covering portion and the first side wall are connected to each other, the covering portion covers the surface of the semiconductor substrate, the first side wall is located on the side of the covering portion away from the semiconductor substrate, and the covering portion is located between the edge of the trench and the gate, and the covering portion may include: any insulating material other than the oxide of the first semiconductor material. For example, when the first semiconductor material is a silicon material, the covering layer may be made of any insulating material other than silicon oxide, so that during the process, it can be avoided that the covering portion is lost or removed during the process of removing the oxide layer in the trench. Exemplarily, the covering portion may be made of insulating materials such as metal oxides, polymer materials or silicon nitride. Alternatively, the covering portion may also be made of other materials that are not easily removed and difficult to etch during the process of removing the oxide layer in the trench. In a specific implementation, the thickness of the covering portion may be in the range of 0.5nm to 20nm, for example, the thickness of the covering portion may be about 5nm, 10nm or 15nm.

[0007] In the chip provided by the embodiment of the present application, a covering portion is disposed on the surface of the semiconductor substrate. The covering portion is located at a position between the edge of the trench and the gate. Moreover, the semiconductor substrate includes a first semiconductor material, and the covering portion includes any insulating material other than the oxide of the first semiconductor material. In this way, during the manufacturing process, the covering portion can always cover the surface of the semiconductor substrate during the epitaxial growth of the second semiconductor material, preventing the second semiconductor material from growing on the surface of the semiconductor substrate, so that the second semiconductor material epitaxially formed inside and outside the trench has a normal morphology. Furthermore, the reliability of the chip is improved, the probability of breakdown failure during the use of the chip is reduced, and thus the service life of the chip is prolonged. In addition, a first sidewall is located on the side of the covering portion away from the semiconductor substrate. During the ion implantation process, the distance between the ion implantation and the channel region can be controlled by the first sidewall, reducing the influence of doping on the channel region and improving the electrical performance of the chip.

[0008] In the embodiment of the present application, the covering portion and the first sidewall may be an integral structure, that is, the covering portion and the first sidewall may be connected as one component. In a possible implementation manner, the first sidewall may be located at a position between the edge of the trench and the gate, and the material of the first sidewall may be the same as that of the covering portion, that is, the first sidewall may include: any insulating material other than the oxide of the first semiconductor material. Exemplarily, the first sidewall may be made of an insulating material such as metal oxide, polymer material, or silicon nitride. Alternatively, the first sidewall may also be made of other materials that are not easily removed and difficult to etch during the process of removing the oxide layer in the trench.

[0009] In the embodiment of the present application, the trench may protrude toward the channel region, so that the second semiconductor material filled in the trench can squeeze the channel region, reducing the lattice constant of the channel region and improving the hole mobility. Specifically, the trench may have a first cross-section, and the area of the first cross-section is larger than the opening area of the trench. The first cross-section is the cross-section of the trench in the direction parallel to the surface of the semiconductor substrate, and the first cross-section is located between the opening and the bottom surface of the trench. In specific implementation, the trench may protrude toward the channel region at one or more positions, and the position of the first cross-section in the trench may be set according to actual needs. Exemplarily, the trench in the embodiment of the present application may be a sigma trench, and the cross-section of the trench in the direction perpendicular to the surface of the semiconductor substrate is a hexagon.

[0010] In a possible implementation, the chip provided by the embodiments of the present application may further include: a second sidewall, the second sidewall is located above the semiconductor substrate, and the second sidewall is located between the first sidewall and the gate, and the covering portion is located at a position between the edge of the trench and the second sidewall. By providing the second sidewall on the side of the gate, during the light doped drain process, the distance between the ion implantation and the channel region can be controlled through the second sidewall, reducing the influence of doping on the channel region, thereby reducing the electric field between the source and the drain. In a possible implementation, the materials of the first sidewall and the second sidewall may be different. Exemplarily, the first sidewall may include a metal oxide material, and the second sidewall may include a silicon nitride material.

[0011] Further, the chip in the embodiments of the present application may further include: a third sidewall, the third sidewall is located above the semiconductor substrate, and the first sidewall is located between the third sidewall and the gate, and the third sidewall covers at least a part of the covering portion. That is, a part of the upper surface of the covering portion (the surface of the covering portion facing away from the semiconductor substrate) is connected to the first sidewall, and the other part is covered by the third sidewall. Exemplarily, the third sidewall may be made of a silicon nitride material. During the subsequent process of heavily doping the source-drain electrode region, the distance between the ion implantation and the channel region can be controlled through the third sidewall, reducing the influence of doping on the channel region. The first sidewall is located between the third sidewall and the second sidewall, and the distance between the ion implantation and the channel region can also be controlled through the first sidewall, reducing the influence of doping on the channel region. During the manufacturing process, before manufacturing the third sidewall, a layer of silicon oxide layer may be formed on the side of the first sidewall, that is, there may be a layer of silicon oxide layer between the third sidewall and the first sidewall.

[0012] In specific implementation, methods such as focused ion beam (FIB) detection and transmission electron microscope (TEM) detection can be used to determine the specific structure in the chip. In the embodiments of the present application, the first sidewall is located between the second sidewall and the third sidewall, the second sidewall may have a different material from the first sidewall, and there may be a silicon oxide layer between the third sidewall and the first sidewall. Therefore, each sidewall on the side of the gate can be distinguished by the position, material, and structure of each sidewall.

[0013] The chip in the embodiments of the present application may further include: a first contact hole, a second contact hole, and an interlayer dielectric layer, wherein the first contact hole is electrically connected to the second semiconductor material, and the second contact hole is electrically connected to the gate, facilitating the extraction of the source-drain electrodes and the gate of the chip. The source-drain electrode regions in the semiconductor substrate correspond to the positions of the source or the drain. Each transistor in the chip may include: a channel region and two source-drain electrode regions on both sides of the channel region. In specific implementation, one or more transistors may be provided in the chip, which can be set according to actual needs.

[0014] In a second aspect, an embodiment of the present application further provides an electronic device. The electronic device in the embodiment of the present application can be a smart phone, a smart TV, a desktop computer, a tablet computer, a laptop computer, a wearable device, or the like. The electronic device provided by the embodiment of the present application may include: any one of the chips in the first aspect above and a circuit board, and the chip is electrically connected to the circuit board. Since the chips in the first aspect above have high reliability, the electronic device including any one of the chips in the first aspect also has high reliability.

[0015] In a third aspect, an embodiment of the present application provides a method for manufacturing a chip. The method for manufacturing the chip provided by the embodiment of the present application may include:

[0016] Step 1: Provide a semiconductor substrate; the semiconductor substrate has a channel region and source-drain electrode regions, a gate is provided at a position corresponding to the channel region above the semiconductor substrate, and the semiconductor substrate includes a first semiconductor material;

[0017] Step 2: Use any insulating material other than the oxide of the first semiconductor material to form a covering layer on the surface of the semiconductor substrate; the covering layer covers at least the region between the position for forming the trench and the gate, and the covering layer includes: a covering portion and a first sidewall connected to each other, and the first sidewall is located on the side of the covering portion away from the semiconductor substrate;

[0018] Step 3: Form a trench in the source-drain electrode region of the semiconductor substrate, and epitaxially grow a second semiconductor material in the trench; the lattice constant of the second semiconductor material is greater than the lattice constant of the first semiconductor material.

[0019] In the method for manufacturing a chip provided by the embodiment of the present application, by forming a covering layer on the surface of the semiconductor substrate, the covering layer covers at least the region between the position for forming the trench and the gate. Moreover, the semiconductor substrate includes a first semiconductor material, and the covering layer uses any insulating material other than the oxide of the first semiconductor material. For example, when the semiconductor substrate includes a silicon material, the covering layer uses any insulating material other than silicon oxide. In this way, during the process of removing the oxide layer on the inner wall of the trench, the covering layer will not be removed, enabling the covering layer to always cover the surface of the semiconductor substrate during the process of epitaxially growing the second semiconductor material, avoiding growing the second semiconductor material on the surface of the semiconductor substrate. Thus, the morphology of the second semiconductor material epitaxially formed in the trench is effectively improved, the reliability of the chip is high, the probability of breakdown failure during the use of the chip is reduced, and the service life of the chip is increased.

[0020] In the above step one, the semiconductor substrate includes a first semiconductor material. Exemplarily, the first semiconductor material can be a semiconductor material such as silicon or germanium. The semiconductor substrate has a channel region and source-drain electrode regions. A gate is provided at a position corresponding to the channel region above the semiconductor substrate, and a gate insulating layer is provided between the gate and the semiconductor substrate. The source-drain electrode regions are regions where the source or drain will be formed. In one possible implementation, a source-drain electrode region can be provided on each side of each channel region.

[0021] After forming the gate, a second sidewall can be formed on the side of the gate. In one possible implementation, a material different from the capping layer can be used to make the second sidewall. Exemplarily, a metal oxide can be used to make the capping layer, and a silicon nitride material can be used to make the second sidewall. Then, ions are implanted into the semiconductor substrate using the lightly doped drain (LDD) process. With the development of semiconductor technology, the distance between the source and the drain is getting closer and closer, making the electrode between the source and the drain stronger. By providing the second sidewall on the side of the gate, during the LDD process, the distance between the ion implantation and the channel region can be controlled through the second sidewall, reducing the influence of doping on the channel region, and thus reducing the electric field between the source and the drain. Specifically, the LDD process can include steps such as ion implantation, photoresist ashing, and cleaning. Due to the oxidation effect during the photoresist ashing process, a natural oxide layer with a certain thickness will be formed on the surface of the semiconductor substrate.

[0022] After the above step one and before the above step two, it can also include: removing the natural oxide layer on the surface of the semiconductor substrate. Specifically, a hydrofluoric acid solution can be used to wet-etch the natural oxide layer on the surface of the semiconductor substrate.

[0023] In the above step two, any insulating material other than the oxide of the first semiconductor material is used to form a capping layer on the surface of the semiconductor substrate. The capping layer covers at least the region between the position for forming the trench and the gate. Any insulating material other than the oxide of the first semiconductor material is used to make the capping layer. For example, when the first semiconductor material is a silicon material, the capping layer can be made of any insulating material other than silicon oxide. In this way, during the subsequent process of removing the oxide layer in the trench, the capping layer can be prevented from being lost or removed. Exemplarily, the capping layer can be made of an insulating material such as a metal oxide, a polymer material, or silicon nitride. Of course, the capping layer can also be made of other materials that are not easily removed and difficult to etch during the process of removing the oxide layer in the trench. In specific implementation, the thickness of the capping layer can be in the range of 0.5 nm to 20 nm. For example, the thickness of the capping layer can be about 5 nm, 10 nm, or 15 nm.

[0024] In a possible implementation, a gate hard mask with a certain thickness is retained during the process of fabricating the gate, which is hereinafter referred to as the protective layer.

[0025] In the above step three, forming a trench in the source-drain electrode region of the semiconductor substrate may specifically include:

[0026] A buffer layer and a hard mask are sequentially formed on the film layer where the covering layer is located. Specifically, the buffer layer can be fabricated by atomic layer deposition process, and the hard mask can be fabricated by furnace tube process. Exemplarily, the buffer layer can be made of silicon oxide material, and the hard mask can be made of silicon nitride material. The thickness of the buffer layer can be between 1 nm and 6 nm. For example, the thickness of the buffer layer can be about 2 nm, 3 nm or 4 nm. The thickness of the hard mask can be between 5 nm and 30 nm. For example, the thickness of the hard mask can be about 10 nm, 15 nm or 20 nm.

[0027] After that, the buffer layer and the hard mask on the area where the trench is to be formed and the top surface of the gate are removed. Using the hard mask and the protective layer as a shield, the semiconductor substrate is etched to form a trench in the source-drain electrode region of the semiconductor substrate. When removing the buffer layer and the hard mask in the area where the trench is to be formed, the buffer layer and the hard mask on the top surface of the gate will also be removed. The protective layer can protect the gate and prevent the gate from being damaged during the trench etching process.

[0028] In a possible implementation, the trench in the embodiments of the present application can protrude towards the channel region, so that the second semiconductor material filled in the trench subsequently can squeeze the channel region, making the lattice constant of the channel region smaller and improving the hole mobility. Specifically, the trench can have a first cross-section, and the area of the first cross-section is larger than the opening area of the trench. Herein, the first cross-section is the cross-section of the trench in the direction parallel to the surface of the semiconductor substrate, and the first cross-section is located between the opening and the bottom surface of the trench. In specific implementation, the trench can protrude towards the channel region at one or more positions, and the position of the first cross-section in the trench can be set according to actual needs. Exemplarily, the trench in the embodiments of the present application can be a sigma trench, and the cross-section of the trench in the direction perpendicular to the surface of the semiconductor substrate is a hexagon.

[0029] During the process of forming the trench, the semiconductor substrate can first be treated by a dry etching process to form an opening on the surface of the semiconductor substrate. Specifically, it can be treated with chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, nitrogen trifluoride, etc. for 50 s to 150 s. Then, a wet etching process is used to treat the inner wall of the opening formed in the semiconductor substrate to form a trench with a specific shape. Specifically, it can be treated with tetramethylammonium hydroxide for 100 s to 400 s.

[0030] In some embodiments of the present application, after removing the buffer layer and the hard mask in the region where the trench is to be formed and the top surface of the gate, and before etching the semiconductor substrate with the hard mask and the protective layer as shielding, the following steps may also be included:

[0031] The covering layer in the area where the groove is to be formed and the top surface of the gate are etched to obtain a covering portion and a first sidewall connected to each other, wherein the first sidewall is located on the side of the covering portion away from the semiconductor substrate. In other words, in addition to covering the surface of the semiconductor substrate to prevent the second semiconductor material from growing on the surface of the semiconductor substrate, the covering layer can also serve as a sidewall, and the distance between the ion implantation and the channel region can be controlled through the first sidewall to reduce the influence of doping on the channel region.

[0032] In the above step three, after the groove is formed and before the second semiconductor material is epitaxially grown in the groove, it also includes: removing the oxide layer on the inner wall of the groove (when the semiconductor substrate includes silicon material, the oxide layer can be a silicon oxide layer). Specifically, an epitaxial in-situ cleaning process can be used to treat the inner wall of the groove. Exemplarily, hydrogen fluoride (HF) and ammonia (NH3) can be used to treat the inner wall of the groove. In the process of removing the oxide layer on the inner wall of the groove, the exposed part of the edge of the buffer layer will also be lost. Since the covering portion can cover the edge of the groove on the semiconductor substrate, the semiconductor substrate at the edge of the groove will not be exposed.

[0033] In the above step three, a second semiconductor material is epitaxially grown in the groove, and the lattice constant of the second semiconductor material is greater than the lattice constant of the first semiconductor material. In this way, the second semiconductor material filled in the groove can generate lateral compressive stress to squeeze the channel region so that the lattice constant of the channel region becomes smaller, thereby improving the mobility of holes. Exemplarily, the first semiconductor material can be silicon, and the second semiconductor material can be an alloy semiconductor material, for example, the second semiconductor material can be a silicon germanium (SiGe) material. Of course, the first semiconductor material and the second semiconductor material can also be other semiconductor materials, for example, the second semiconductor material can also be silicon carbide (SiC), silicon phosphide (SiP) and other materials. In a possible implementation, the second semiconductor material can fill the groove and protrude from the surface of the semiconductor substrate. Since the covering layer covers the surface of the semiconductor substrate at the edge of the groove, the second semiconductor material can be avoided from growing on the surface of the semiconductor substrate during the epitaxial growth of the second semiconductor material, and then, a second semiconductor material with normal morphology can be obtained, so that the reliability of the chip is normal, the probability of breakdown failure of the chip during use is reduced, and the service life of the chip is improved.

[0034] After the above step three, it may further include: removing the hard mask, buffer layer and protective layer, and forming a third sidewall on the side of the gate. Exemplarily, the third sidewall can be made of silicon nitride material. During the subsequent process of heavily doping the source-drain electrode region, the distance between the ion implantation and the channel region can be controlled through the third sidewall, reducing the influence of doping on the channel region. The first sidewall is located between the third sidewall and the second sidewall, and the distance between the ion implantation and the channel region can also be controlled through the first sidewall, reducing the influence of doping on the channel region.

[0035] After forming the third sidewall, a first contact hole, a second contact hole and an interlayer dielectric layer may also be formed, wherein the first contact hole is electrically connected to the second semiconductor material, and the second contact hole is electrically connected to the gate. Description of the Drawings

[0036] Figure 1 is a schematic diagram of the manufacturing process of an epitaxial germanium-silicon material in the related art;

[0037] Figure 2 is a schematic structural diagram of a chip provided by an embodiment of the present application;

[0038] Figure 3 is another schematic structural diagram of a chip provided by an embodiment of the present application;

[0039] Figure 4 is a flowchart of the manufacturing method of a chip provided by an embodiment of the present application;

[0040] Figures 5 to 12 is a schematic structural diagram corresponding to each step in the manufacturing method of a chip provided by an embodiment of the present application.

[0041] 10 - semiconductor substrate; 11 - gate; 12 - gate insulating layer; 13 - second sidewall; 14 - native oxide layer; 15 - covering layer; 151 - covering portion; 152 - first sidewall; 16 - protective layer; 17 - buffer layer; 18 - hard mask; 19 - second semiconductor material; 20 - third sidewall; 21 - first contact hole; 22 - second contact hole; 23 - interlayer dielectric layer; 101 - hard mask silicon oxide layer; 102 - hard mask silicon nitride layer; 103 - germanium-silicon material; W - trench; U - longitudinal opening; Q1 - channel region; Q2 - source-drain electrode region; S1 - first cross-section. Detailed Embodiments

[0042] In the related art, in order to improve the hole mobility, a germanium-silicon (SiGe) material is epitaxially grown in the source-drain electrode region of a semiconductor substrate. Since the lattice constant of germanium (Ge) is greater than the lattice constant of silicon (Si) The SiGe material in the source-drain electrode region generates a lateral compressive stress. By squeezing the channel with the lateral compressive stress generated by the SiGe material, the lattice constant in the channel can be reduced, thereby improving the hole mobility.

[0043] Figure 1 It is a schematic diagram of the manufacturing process of the epitaxial SiGe material in the related art. As shown in (1) of Figure 1 , the pre-layer process of epitaxial SiGe deposition generally includes a lightly doped drain (LDD) process, which specifically includes steps such as ion implantation, photoresist ashing, and cleaning. Due to the oxidation effect during the photoresist ashing process, a natural oxide layer with a certain thickness will be formed on the surface of the semiconductor substrate 10. After that, a hard mask silicon oxide layer 101 and a hard mask silicon nitride layer 102 are sequentially deposited. A trench W for growing the epitaxial SiGe material is formed in the source-drain electrode region by dry and wet etching. The inner wall of the trench W is cleaned by epitaxial in-situ cleaning to remove the oxide layer on the inner wall of the trench W. As shown in (2) of Figure 1 , the epitaxial growth process is used to grow the SiGe material 103 in the trench W.

[0044] Since both the natural oxide layer on the surface of the semiconductor substrate 10 and the hard mask silicon oxide layer 101 are silicon oxide materials, the superposition of the two oxide film layers from different sources will increase the thickness of the silicon oxide film layer on the surface of the semiconductor substrate 10. Furthermore, after the silicon oxide film layer on the surface of the semiconductor substrate 10 is removed during the epitaxial in-situ cleaning process, the longitudinal opening U formed at the edge of the trench W will be increased. During the epitaxial process, the gas will diffuse into the longitudinal opening U, and the exposed semiconductor substrate 10 inside the longitudinal opening U will serve as a nucleation site for growing the SiGe material 103, eventually resulting in an abnormal morphology of the SiGe material 103 protruding outward, as shown in (2) of Figure 1 . The morphology of the SiGe material 103 is very important for the reliability of the MOSFET device. For example, as shown in (2) of Figure 1 , the abnormal morphology of the SiGe material 103 will cause the distance between the SiGe source-drain and the gate 11 to become shorter, easily resulting in breakdown between the source-drain electrode and the gate 11, seriously affecting the service life of the MOSFET device.

[0045] Based on this, in order to solve the problem of abnormal morphology in the epitaxially grown germanium-silicon material in the related art and improve the service life of MOSFET devices, the embodiments of the present application provide a chip, a manufacturing method thereof, and an electronic device. The chip in the embodiments of the present application can be a MOSFET device. Specifically, the chip can specifically include: a P-type field-effect transistor or an N-type field-effect transistor. Alternatively, the chip in the embodiments of the present application can be a logic chip, a digital logic circuit, a memory (such as a static random access memory), a microprocessor, etc. that include MOSFET devices. The chip in the embodiments of the present application can be applied to various electronic devices such as smart phones, smart TVs, desktop computers, tablet computers, laptop computers, and wearable devices.

[0046] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0047] It should be noted that the same reference numerals in the drawings of the present application represent the same or similar structures, and thus the repeated description thereof will be omitted. The words expressing positions and directions described in the present application are all illustrated by taking the drawings as examples, but can be changed according to needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are only used to illustrate the relative position relationship and do not represent the actual proportion.

[0048] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0049] Figure 2 It is a schematic structural diagram of the chip provided by the embodiment of the present application, as Figure 2As shown, the chip provided in the embodiment of the present application may include: a semiconductor substrate 10, a gate 11, a covering portion 151 and a first sidewall 152. The semiconductor substrate 10 has a channel region Q1 and a source-drain electrode region Q2. The semiconductor substrate 10 includes a first semiconductor material. For example, the first semiconductor material may be a semiconductor material such as silicon or germanium. The semiconductor substrate 10 is provided with a trench W in the source-drain electrode region Q2, and the trench W is filled with a second semiconductor material 19. The lattice constant of the second semiconductor material 19 is greater than the lattice constant of the first semiconductor material. The second semiconductor material 19 filled in the trench W may generate a lateral compressive stress to squeeze the channel region Q1 so that the lattice constant of the channel region Q1 becomes smaller, thereby improving the mobility of holes. For example, the first semiconductor material may be silicon, and the second semiconductor material 19 may be an alloy semiconductor material. For example, the second semiconductor material may be a silicon germanium (SiGe) material. Of course, the first semiconductor material and the second semiconductor material 19 may also be other semiconductor materials. For example, the second semiconductor material may also be silicon carbide (SiC), silicon phosphide (SiP) and other materials. In a possible implementation, the second semiconductor material 19 can fill the trench W and protrude from the surface of the semiconductor substrate 10. The gate 11 is located on the semiconductor substrate 10 at a position corresponding to the channel region Q1, and a gate insulating layer 12 is provided between the gate 11 and the semiconductor substrate 10. The covering portion 152 and the first sidewall 152 are connected to each other, the covering portion 151 covers the surface of the semiconductor substrate 10, the first sidewall 152 is located on the side of the covering portion 151 away from the semiconductor substrate 10, and the covering portion 151 is located between the edge of the trench W and the gate 11, and the covering portion 151 may include: any insulating material other than the oxide of the first semiconductor material. For example, when the first semiconductor material is a silicon material, the covering portion 151 may be made of any insulating material other than silicon oxide, so that in the manufacturing process, the covering portion 151 can be prevented from being lost or removed during the process of removing the oxide layer in the trench W. Exemplarily, the covering portion 151 may be made of insulating materials such as metal oxides, polymer materials or silicon nitride. Alternatively, the covering portion 151 may also be made of other materials that are not easily removed and difficult to etch during the process of removing the oxide layer in the trench W. In a specific implementation, the thickness of the covering portion 151 may be in the range of 0.5 nm to 20 nm, for example, the thickness of the covering portion 151 may be about 5 nm, 10 nm or 15 nm.

[0050] In the chip provided by the embodiment of the present application, by providing a covering portion 151 on the surface of the semiconductor substrate 10, the covering portion 151 is located at a position between the edge of the trench W and the gate 11, and the semiconductor substrate 10 includes a first semiconductor material, and the covering portion 151 includes any insulating material other than the oxide of the first semiconductor material. In this way, during the manufacturing process, the covering portion 151 can always cover the surface of the semiconductor substrate 10 during the epitaxial growth of the second semiconductor material 19, avoiding the growth of the second semiconductor material 19 on the surface of the semiconductor substrate 10, so that the second semiconductor material 19 epitaxially formed inside and outside the trench W has a normal morphology. Furthermore, the reliability of the chip is improved, the probability of breakdown failure during the use of the chip is reduced, and the service life of the chip is increased. In addition, the first sidewall 152 is located on the side of the covering portion 151 away from the semiconductor substrate 10. During the ion implantation process, the distance between the ion implantation and the channel region Q1 can be controlled through the first sidewall 152, reducing the influence of doping on the channel region and improving the electrical performance of the chip.

[0051] In the embodiment of the present application, the covering portion 151 and the first sidewall 152 can be an integral structure, that is, the covering portion 151 and the first sidewall 152 can be connected as one component. In a possible implementation manner, the first sidewall 152 can be located at a position between the edge of the trench W and the gate 11, and the material of the first sidewall 152 can be the same as the material of the covering portion 151, that is, the first sidewall 152 can include: any insulating material other than the oxide of the first semiconductor material. Exemplarily, the first sidewall 152 can adopt insulating materials such as metal oxides, polymer materials, or silicon nitride. Or, the first sidewall 152 can also adopt other materials that are not easily removed and difficult to etch during the process of removing the oxide layer in the trench W.

[0052] Continue to refer to Figure 2 , in the embodiment of the present application, the trench W can protrude towards the channel region Q1, so that the second semiconductor material 19 filled in the trench W can squeeze the channel region Q1, making the lattice constant of the channel region Q1 smaller and improving the hole mobility. Specifically, the trench W can have a first cross-section S1, and the area of the first cross-section S1 is larger than the opening area of the trench W. Wherein, the first cross-section S1 is the cross-section of the trench W in the direction parallel to the surface of the semiconductor substrate 10, and the first cross-section S1 is located between the opening and the bottom surface of the trench W. Figure 2 Taking the example that the trench W protrudes towards the channel region Q1 at a position approximately in the middle is shown for illustration. In specific implementation, the trench W can also protrude towards the channel region Q1 at other positions, and the trench W can also have multiple positions protruding towards the channel region Q1. Exemplarily, the trench W in the embodiment of the present application can be a sigma trench, and the cross-section of the trench W in the direction perpendicular to the surface of the semiconductor substrate 10 is a hexagon.

[0053] Continue to refer to Figure 2 In a possible implementation, the chip provided by the embodiments of the present application may further include: a second sidewall 13, the second sidewall 13 is located above the semiconductor substrate 10, and the second sidewall 13 is located between the first sidewall 152 and the gate 11, and the covering portion 151 is located at a position between the edge of the trench W and the second sidewall 13. By providing the second sidewall 13 on the side of the gate 11, during the light doping drain process, the distance between the ion implantation and the channel region can be controlled by the second sidewall 13, reducing the influence of doping on the channel region, and thus reducing the electric field between the source and the drain. In a possible implementation, the materials of the first sidewall 152 and the second sidewall 13 may be different. Exemplarily, the first sidewall 152 may include a metal oxide material, and the second sidewall 13 may include a silicon nitride material.

[0054] Furthermore, the chip in the embodiments of the present application may further include: a third sidewall 20, the third sidewall 20 is located above the semiconductor substrate 10, and the first sidewall 152 is located between the third sidewall 20 and the gate 11, and the third sidewall 20 covers at least a part of the covering portion 151. That is, a part of the upper surface of the covering portion 151 (the surface of the covering portion 151 facing away from the semiconductor substrate 10) is connected to the first sidewall 152, and the other part is covered by the third sidewall 20. Exemplarily, the third sidewall 20 may be made of a silicon nitride material. During the subsequent process of heavily doping the source-drain electrode region Q2, the distance between the ion implantation and the channel region Q1 can be controlled by the third sidewall 20, reducing the influence of doping on the channel region Q1. The first sidewall 152 is located between the third sidewall 20 and the second sidewall 13, and the distance between the ion implantation and the channel region Q1 can also be controlled by the first sidewall 152, reducing the influence of doping on the channel region Q1. During the manufacturing process, before manufacturing the third sidewall 20, a layer of silicon oxide layer may be formed on the side of the first sidewall 152, that is, there may be a layer of silicon oxide layer between the third sidewall 20 and the first sidewall 152.

[0055] In specific implementation, methods such as focused ion beam (FIB) detection and transmission electron microscope (TEM) detection can be used to determine the specific structure in the chip. In the embodiments of the present application, the first sidewall 152 is located between the second sidewall 13 and the third sidewall 20, the material of the second sidewall 13 may be different from that of the first sidewall 152, and there may be a silicon oxide layer between the third sidewall 20 and the first sidewall 152. Therefore, the sidewalls on the side of the gate 11 can be distinguished by the positions, materials, and structures of the sidewalls.

[0056] Such as Figure 2As shown, the chip in the embodiment of the present application may further include: a first contact hole 21, a second contact hole 22 and an interlayer dielectric layer 23, wherein the first contact hole 21 is electrically connected to the second semiconductor material 19, and the second contact hole 22 is electrically connected to the gate 11, so as to facilitate the extraction of the source and drain electrodes of the chip and the gate 11. The source and drain electrode region Q2 in the semiconductor substrate 10 corresponds to the position of the source or drain.

[0057] exist Figure 2 In the example, a chip including a transistor is used for illustration, that is, the transistor includes: a channel region Q1 and two source-drain electrode regions Q2 on both sides of the channel region Q1. In specific implementation, more transistors can be set in the chip, which can be set according to actual needs. For example, in Figure 3 middle, Figure 3 Another schematic diagram of the structure of the chip provided in the embodiment of the present application, the chip may also include two transistors, Figure 3 The two channel regions Q1 shown in FIG. 1 may belong to different transistors respectively, and the two transistors may share a source-drain electrode region Q2 .

[0058] Based on the same technical concept, an embodiment of the present application also provides an electronic device, and the electronic device in the embodiment of the present application can be a smart phone, a smart TV, a desktop computer, a tablet computer, a laptop computer, a wearable device, etc. The electronic device provided in the embodiment of the present application may include: any of the above chips and a circuit board, and the chip is electrically connected to the circuit board. Since the reliability of the above chips is high, the reliability of the electronic device including any of the above chips is also high.

[0059] Based on the same technical concept, an embodiment of the present application also provides a method for manufacturing a chip. Figure 4 A flow chart of a chip manufacturing method provided in an embodiment of the present application, such as Figure 4 As shown, the chip manufacturing method provided in the embodiment of the present application may include:

[0060] S201, providing a semiconductor substrate; the semiconductor substrate has a channel region and a source-drain electrode region, a gate is provided at a position corresponding to the channel region on the semiconductor substrate, and the semiconductor substrate includes a first semiconductor material;

[0061] S202, using any insulating material other than the oxide of the first semiconductor material to form a covering layer on the surface of the semiconductor substrate; the covering layer at least covers the area between the position for forming the trench and the gate, and the covering layer includes: a covering portion and a first sidewall connected to each other, the first sidewall being located on a side of the covering portion away from the semiconductor substrate;

[0062] S203. Form a trench in the source-drain electrode region of the semiconductor substrate, and epitaxially grow a second semiconductor material inside and outside the trench; the lattice constant of the second semiconductor material is greater than that of the first semiconductor material.

[0063] In the method for manufacturing a chip provided by the embodiment of the present application, by forming a covering layer on the surface of the semiconductor substrate, the covering layer covers at least the area between the position for forming the trench and the gate. And, the semiconductor substrate includes a first semiconductor material, and the covering layer is made of any insulating material other than the oxide of the first semiconductor material. For example, when the semiconductor substrate includes a silicon material, the covering layer is made of any insulating material other than silicon oxide. In this way, during the process of removing the oxide layer on the inner wall of the trench, the covering layer will not be removed, enabling the covering layer to always cover the surface of the semiconductor substrate during the process of epitaxially growing the second semiconductor material, avoiding growing the second semiconductor material on the surface of the semiconductor substrate. Thus, the morphology of the second semiconductor material epitaxially formed inside and outside the trench is effectively improved, the reliability of the chip is relatively high, the probability of breakdown failure during the use of the chip is reduced, and the service life of the chip is increased.

[0064] Figures 5 to 12 FIG. is a schematic structural diagram corresponding to each step in the method for manufacturing a chip provided by the embodiment of the present application. Hereinafter, with reference to the accompanying drawings, the method for manufacturing a chip provided by the embodiment of the present application will be described in detail.

[0065] As Figure 5 shown, in the above step S201, the semiconductor substrate 10 includes a first semiconductor material. Exemplarily, the first semiconductor material may be a semiconductor material such as silicon or germanium. The semiconductor substrate 10 has a channel region Q1 and a source-drain electrode region Q2. A gate 11 is provided at a position corresponding to the channel region Q1 on the semiconductor substrate 10, and a gate insulating layer 12 is provided between the gate 11 and the semiconductor substrate 10. The source-drain electrode region Q2 is a region where a source or a drain is to be formed. In a possible implementation manner, a source-drain electrode region Q2 may be provided on each side of each channel region Q1.

[0066] After forming the gate 11, a second sidewall 13 can be formed on the side of the gate 11. In one possible implementation, a material different from that of the capping layer 15 can be used to fabricate the second sidewall 13. Exemplarily, a metal oxide can be used to fabricate the capping layer 15, and a silicon nitride material can be used to fabricate the second sidewall 13. Thereafter, ions are implanted into the semiconductor substrate 10 using a lightly doped drain (LDD) process. With the development of semiconductor technology, the distance between the source and the drain has become closer and closer, making the electrode between the source and the drain stronger. By providing the second sidewall 13 on the side of the gate 11, during the LDD process, the distance between the ion implantation and the channel region Q1 can be controlled by the second sidewall, reducing the impact of doping on the channel region Q1, thereby reducing the electric field between the source and the drain. Specifically, the LDD process can include steps such as ion implantation, photoresist ashing, and cleaning. Due to the oxidation effect during the photoresist ashing process, a natural oxide layer 14 with a certain thickness is formed on the surface of the semiconductor substrate 10.

[0067] Referring to Figure 5 and Figure 6 , after the above step S201 and before the above step S202, it may further include: removing the natural oxide layer 14 on the surface of the semiconductor substrate 10 to obtain the structure as Figure 6 shown. Specifically, a hydrofluoric acid solution can be used to wet-etch the natural oxide layer 14 on the surface of the semiconductor substrate 10.

[0068] As Figure 7 shown, in the above step S202, any insulating material other than the oxide of the first semiconductor material is used to form a capping layer 15 on the surface of the semiconductor substrate 10. The capping layer 15 covers at least the region between the position for forming the trench and the gate 11. Using any insulating material other than the oxide of the first semiconductor material to fabricate the capping layer 15. For example, when the first semiconductor material is silicon, the capping layer 15 can be made of any insulating material other than silicon oxide. In this way, during the subsequent process of removing the oxide layer in the trench, the capping layer 15 can be prevented from being lost or removed. Exemplarily, the capping layer 15 can be made of insulating materials such as metal oxides, polymer materials, or silicon nitride. Of course, the capping layer 15 can also be made of other materials that are not easily removed and difficult to etch during the process of removing the oxide layer in the trench. In a specific implementation, the thickness of the capping layer 15 can be in the range of 0.5 nm to 20 nm. For example, the thickness of the capping layer 15 can be about 5 nm, 10 nm, or 15 nm.

[0069] As Figure 5 shown, a certain thickness of gate hard mask, hereinafter referred to as the protective layer 16, is retained during the process of fabricating the gate 11.

[0070] AsFigure 8 and Figure 9 As shown in Figure 9 , in the above step S203, forming a trench in the source-drain electrode region of the semiconductor substrate may specifically include:

[0071] As Figure 8 shown in Figure 8 , a buffer layer 17 and a hard mask 18 are sequentially formed on the film layer where the covering layer 15 is located. Specifically, the buffer layer 17 can be fabricated by an atomic layer deposition process, and the hard mask 18 can be fabricated by a furnace tube process. Exemplarily, the buffer layer 17 can be made of silicon oxide material, and the hard mask 18 can be made of silicon nitride material. The thickness of the buffer layer 17 can be between 1 nm and 6 nm. For example, the thickness of the buffer layer 17 can be about 2 nm, 3 nm, or 4 nm. The thickness of the hard mask 18 can be between 5 nm and 30 nm. For example, the thickness of the hard mask 18 can be about 10 nm, 15 nm, or 20 nm.

[0072] As Figure 9 shown in Figure 9 , the buffer layer 17 and the hard mask 18 on the top surface of the gate 11 and in the region where the trench W is to be formed are removed. Using the hard mask 18 and the protective layer 16 as a shield, the semiconductor substrate 10 is etched to form a trench W in the source-drain electrode region Q2 of the semiconductor substrate 10. When removing the buffer layer 17 and the hard mask 18 in the region where the trench W is to be formed, the buffer layer 17 and the hard mask 18 on the top surface of the gate 11 are also removed. The protective layer 16 can protect the gate 11 to prevent the gate 11 from being damaged during the etching of the trench W.

[0073] In a possible implementation manner, the trench W in the embodiment of the present application may protrude toward the channel region Q1, so that the second semiconductor material filled in the trench W subsequently can squeeze the channel region Q1, making the lattice constant of the channel region Q1 smaller and improving the hole mobility. Specifically, the trench W may have a first cross-section S1, and the area of the first cross-section S1 is larger than the opening area of the trench W, where the first cross-section S1 is the cross-section of the trench W in the direction parallel to the surface of the semiconductor substrate 10 and the first cross-section S1 is located between the opening and the bottom surface of the trench W. Figure 9 The case where the trench W protrudes toward the channel region Q1 at a position approximately in the middle is taken as an example for illustration in Figure 9 . In specific implementation, the trench W may also protrude toward the channel region Q1 at other positions, and the trench W may also have multiple positions protruding toward the channel region Q1. Exemplarily, the trench W in the embodiment of the present application may be a sigma trench, and the cross-section of the trench W in the direction perpendicular to the surface of the semiconductor substrate 10 is a hexagon.

[0074] In the process of forming the trench W, the semiconductor substrate 10 can be first processed by a dry etching process to form an opening on the surface of the semiconductor substrate 10. Specifically, chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, nitrogen trifluoride, etc. can be used for 50 s to 150 s. Then, a wet etching process is used to process the inner wall of the opening formed in the semiconductor substrate 10 to form a trench W with a specific shape. Specifically, tetramethylammonium hydroxide can be used for 100 s to 400 s.

[0075] Continue to refer to Figure 9 , in some embodiments of the present application, after removing the buffer layer and the hard mask on the area where the trench is to be formed and the top surface of the gate, before etching the semiconductor substrate with the hard mask and the protective layer as a shield, it may further include:

[0076] Etch the covering layer 15 on the area where the trench W is to be formed and the top surface of the gate 11 to obtain a connected covering portion 151 and a first sidewall 152, wherein the first sidewall 152 is located on the side of the covering portion 151 away from the semiconductor substrate 10. That is to say, in addition to covering the surface of the semiconductor substrate 10 to prevent the growth of the second semiconductor material on the surface of the semiconductor substrate 10, the covering layer 15 can also act as a sidewall. During the subsequent ion implantation process, the distance between the ion implantation and the channel region Q1 can be controlled through the first sidewall 152, reducing the influence of doping on the channel region.

[0077] As Figure 10 shown, in the above step S203, after forming the trench W and before epitaxially growing the second semiconductor material inside and outside the trench W, it further includes: removing the oxide layer on the inner wall of the trench W (when the semiconductor substrate 10 includes a silicon material, this oxide layer can be a silicon oxide layer). Specifically, an epitaxial in-situ cleaning process can be used to process the inner wall of the trench W. Exemplarily, hydrogen fluoride (HF) and ammonia (NH3) can be used to process the inner wall of the trench W. From Figure 10 it can be seen that during the process of removing the oxide layer on the inner wall of the trench W, the exposed part of the edge of the buffer layer 17 will also be lost. Since the covering portion 151 can cover the edge of the trench W above the semiconductor substrate 10, the semiconductor substrate 10 at the edge of the trench W will not be exposed.

[0078] As Figure 11As shown, in the above step S203, a second semiconductor material 19 is epitaxially grown inside and outside the trench W, and the lattice constant of the second semiconductor material 19 is greater than that of the first semiconductor material. In this way, the second semiconductor material 19 filled in the trench W can generate a lateral compressive stress to squeeze the channel region Q1, so that the lattice constant of the channel region Q1 becomes smaller, thereby improving the hole mobility. Exemplarily, the first semiconductor material may be silicon, and the second semiconductor material 19 may be an alloy semiconductor material. For example, the second semiconductor material may be a silicon-germanium (SiGe) material. Of course, the first semiconductor material and the second semiconductor material 19 may also be other semiconductor materials. For example, the second semiconductor material may also be silicon carbide (SiC), silicon phosphide (SiP), etc. In a possible implementation manner, the second semiconductor material 19 can fill the trench W and protrude from the surface of the semiconductor substrate 10. Since the covering layer 15 covers the surface of the semiconductor substrate 10 at the edge of the trench W, thus, during the epitaxial growth process of the second semiconductor material 19, the growth of the second semiconductor material 19 on the surface of the semiconductor substrate 10 can be avoided. Furthermore, a second semiconductor material 19 with a normal morphology can be obtained, thereby ensuring the normal reliability of the chip.

[0079] Referring to Figure 11 and Figure 12 , after the above step S203, it may further include: removing the hard mask 18, the buffer layer 17, and the protective layer 16, and forming a third sidewall 20 on the side of the gate 11. Exemplarily, the third sidewall 20 can be made of a silicon nitride material. During the subsequent process of heavily doping the source-drain electrode region Q2, the distance between the ion implantation and the channel region Q1 can be controlled by the third sidewall 20, reducing the influence of the doping on the channel region Q1. The first sidewall 152 is located between the third sidewall 20 and the second sidewall 13, and the distance between the ion implantation and the channel region Q1 can also be controlled by the first sidewall 152, reducing the influence of the doping on the channel region Q1.

[0080] Referring to Figure 3 , after forming the third sidewall 20, a first contact hole 21, a second contact hole 22, and an interlayer dielectric layer 23 may also be formed, wherein the first contact hole 21 is electrically connected to the second semiconductor material 19, and the second contact hole 22 is electrically connected to the gate 11.

[0081] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.

[0082] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications.

Claims

1. A chip, characterized in that, include: A semiconductor substrate having a channel region and a source-drain electrode region; The semiconductor substrate comprises a first semiconductor material; the semiconductor substrate is provided with a groove in the source-drain electrode region, the groove is filled with a second semiconductor material, and the lattice constant of the second semiconductor material is greater than the lattice constant of the first semiconductor material; A gate, the gate being located on the semiconductor substrate at a position corresponding to the channel region; A covering portion and a first side wall are connected to each other, wherein the covering portion covers the surface of the semiconductor substrate, the first side wall is located on the side of the covering portion away from the semiconductor substrate, and the covering portion is located between the edge of the trench and the gate; the covering portion includes: any insulating material other than the oxide of the first semiconductor material.

2. The chip according to claim 1, characterized in that, Also includes: Second side wall; The second sidewall spacer is located on the semiconductor substrate, and the second sidewall spacer is located between the first sidewall spacer and the gate; The covering portion is located between the edge of the groove and the second sidewall.

3. The chip according to claim 2, wherein, The first spacer includes any insulating material except an oxide of the first semiconductor material, and the material of the first spacer is different from that of the second spacer.

4. The chip according to any one of claims 1 to 3, characterized in that Also includes: The third side wall; The third spacer is located on the semiconductor substrate, and the first spacer is located between the third spacer and the gate; The third sidewall covers at least a portion of the covering portion.

5. The chip according to any one of claims 1 to 4, characterized in that, The groove has a first cross section, and the area of ​​the first cross section is larger than the opening area of ​​the groove; The first cross section is a cross section of the trench in a direction parallel to the surface of the semiconductor substrate, and the first cross section is located between the opening and the bottom surface of the trench.

6. The chip according to any one of claims 1 to 5, characterized in that The second semiconductor material fills the trench and protrudes from the surface of the semiconductor substrate.

7. An electronic device, characterized in that, include: The chip and circuit board according to any one of claims 1 to 6, wherein the chip is electrically connected to the circuit board.

8. A method for manufacturing a chip, characterized in that, include: A semiconductor substrate is provided; the semiconductor substrate has a channel region and a source-drain electrode region, a gate is provided on the semiconductor substrate at a position corresponding to the channel region, and the semiconductor substrate comprises a first semiconductor material; Using any insulating material except the oxide of the first semiconductor material to form a covering layer on the surface of the semiconductor substrate; The covering layer at least covers the area between the position for forming the trench and the gate, and the covering layer includes: a covering portion and a first sidewall connected to each other, wherein the first sidewall is located on a side of the covering portion away from the semiconductor substrate; A trench is formed in the source-drain electrode region of the semiconductor substrate, and a second semiconductor material is epitaxially grown in the trench; the lattice constant of the second semiconductor material is greater than the lattice constant of the first semiconductor material.

9. The manufacturing method according to claim 8, characterized in that, A protective layer is provided on the top surface of the gate; The forming of trenches in the source-drain electrode region of the semiconductor substrate comprises: forming a buffer layer and a hard mask in sequence on the film layer where the cover layer is located; Remove the buffer layer and the hard mask on the area where the trench is to be formed and the top surface of the gate, and use the hard mask and the protective layer as a mask to etch the semiconductor substrate to form the trench in the source-drain electrode region of the semiconductor substrate.

10. The manufacturing method according to claim 9, characterized in that, After removing the buffer layer and the hard mask on the area where the trench is to be formed and the top surface of the gate, and before etching the semiconductor substrate using the hard mask and the protective layer as a mask, it further includes: Etch the covering layer on the area where the trench is to be formed and the top surface of the gate to obtain the interconnected covering portion and the first sidewall.

11. The manufacturing method according to any one of claims 9 to 10, characterized in that, Before forming a covering layer on the surface of the semiconductor substrate using any insulating material other than the oxide of the first semiconductor material, it further includes: Wet-etch the native oxide layer on the surface of the semiconductor substrate using a hydrofluoric acid solution.

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