Semi-super junction field effect transistor based on silicon carbide material and manufacturing process thereof

Abstract

The invention discloses a semi-super junction field effect transistor based on a silicon carbide material and a manufacturing process thereof, and the semi-super junction field effect transistor based on the silicon carbide material comprises an N-type substrate; the barrier layer is arranged on the upper surface of the N-type substrate; the drift region is arranged on the upper surface of the barrier layer; the N column region is arranged on the upper surface of the drift region; the two P column regions are arranged on the upper surface of the drift region and located on the two sides of the N column region respectively; the channel part is arranged on the upper surface of the N column region; the two P-type regions are arranged on the upper surface of the P column region respectively, and the side walls of the two P-type regions are located on the two sides of the channel part respectively; the source region is arranged on the upper surface of the channel part; a source electrode on the upper surface of the source region; the gate electrode is arranged on the surface of the P-type region; and the drain electrode is arranged on the lower surface of the N-type substrate. According to the invention, the N column region and the P column region are introduced above the drift region, so that a semi-super junction structure is formed, and charge balance and electric field modulation are realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a semi-superjunction field effect transistor based on silicon carbide material and its manufacturing process. Background Art

[0002] Traditional 4H-SiC JFETs adopt standard manufacturing processes, including steps such as epitaxial growth, photolithography, ion implantation, and etching. Its structure mainly includes an N-type drift region, a P-type gate, and an N-type source-drain region. The electric field distribution of traditional 4H-SiC JFETs is not uniform enough, resulting in a low breakdown voltage. In addition, the on-resistance of traditional JFETs is relatively high, affecting the device efficiency, which limits the performance of traditional 4H-SiC JFETs in high power density and high efficiency applications. Summary of the Invention

[0003] In view of the above problems, the present invention overcomes at least one deficiency and proposes a semi-superjunction field effect transistor based on silicon carbide material and its manufacturing process.

[0004] The technical solution adopted by the present invention is as follows: A semi-superjunction field effect transistor based on silicon carbide material, comprising: An N-type substrate; A blocking layer on the upper surface of the N-type substrate; A drift region on the upper surface of the blocking layer; An N-column region on the upper surface of the drift region; Two P-column regions on the upper surface of the drift region and located on both sides of the N-column region respectively; A channel portion on the upper surface of the N-column region; Two P-type regions are respectively disposed on the upper surfaces of the P-column regions, and the side walls of the two P-type regions are respectively located on both sides of the channel portion; A source region on the upper surface of the channel portion; A source electrode on the upper surface of the source region; A gate electrode on the surface of the P-type region A drain electrode on the lower surface of the N-type substrate.

[0005] In the structure of the present application, an N-column region and a P-column region are introduced above the drift region to form a semi-superjunction structure. The semi-superjunction structure is a design between a traditional structure and a superjunction structure. By introducing a P-N column structure above the drift region, charge balance and electric field modulation are achieved. Compared with the traditional structure, the semi-superjunction structure can significantly improve the breakdown voltage and reduce the on-resistance of the device without increasing the manufacturing complexity.

[0006] In one embodiment of the present invention, the doping concentration of the P-column region is 2×10¹ 6 cm⁻³.

[0007] In one embodiment of the present invention, the doping concentration of the N pillar region is 8×10¹ 6 cm⁻³.

[0008] In one embodiment of the present invention, the width of the channel portion is 1.0 um.

[0009] In one embodiment of the present invention, the length of the channel portion is 1.4 um.

[0010] In the semi-superjunction field effect transistor based on silicon carbide material of this embodiment, in the reverse conduction state, most of the electric field lines emitted by the ionized positive charges in the N pillar region flow to the ionized negative charges in the adjacent P pillar region, which introduces a significant two-dimensional electric field effect in the voltage-resistant layer. The complex electric field modulation technology greatly reduces the peak electric field on the surface of the device and optimizes the electric field distribution in the device body, and the voltage-resistant ability of the device is improved. At the same time, in the forward conduction state, due to the relatively high doping concentration of the N pillar region, the on-resistance of the device is reduced, and the contradictory relationship between the breakdown voltage (BV) and the specific on-resistance (Ron,sp) is significantly weakened.

[0011] This application also discloses a manufacturing process of a semi-superjunction field effect transistor based on silicon carbide material, including the following steps: Step S1: Prepare a heavily doped N-type substrate, and sequentially deposit a blocking layer, a drift region, and a first N pillar layer on the upper surface of the N-type substrate. The thickness of the first N pillar layer is a; Step S2: Form a first P pillar layer at a specified position in the first N pillar layer by channel implantation. The depth of the first P pillar layer is a; Step S3: Form a second N pillar layer with a thickness of a on the upper surface of the first N pillar layer by chemical vapor deposition; Step S4: Use the same mask and ion implantation parameters (such as energy and dose) as in Step S2, and form a second P pillar layer at a specified position in the second N pillar layer by channel implantation. The second P pillar layer corresponds to the first P pillar layer to obtain a P pillar region with a depth of 2a, and the second N pillar layer corresponds to the first N pillar layer to obtain an N pillar region with a depth of 2a; Step S5: Form a channel region on the upper surface of the structure obtained in Step S4 by chemical vapor deposition; Step S6: Form a source region (P+ source region) on the upper surface of the channel region by vertical ion implantation; Step S7: Etch the channel region to obtain a gate groove, and the gate groove is on both sides of the source region; Step S8: Form a P-type region at the bottom and side walls of the gate groove by ion implantation. The part of the channel region between the two P-type regions is the channel portion; Step S9: Deposit a metal material on the P-type region to form a gate electrode, deposit a metal material on the lower surface of the N-type substrate to form a drain electrode, and deposit a metal material on the upper surface of the source region to form a source electrode.

[0012] In one embodiment of the present invention, it is characterized in that the doping concentration of the P-column region is 2×10¹ 6 cm⁻³.

[0013] In one embodiment of the present invention, it is characterized in that the doping concentration of the N-column region is 8×10¹ 6 cm⁻³.

[0014] In one embodiment of the present invention, it is characterized in that the width of the channel portion is 1.0 um.

[0015] In one embodiment of the present invention, it is characterized in that the length of the channel portion is 1.4 um.

[0016] The beneficial effect of the present invention is that: in the structure of this application, an N-column region and a P-column region are introduced above the drift region to form a semi-superjunction structure. The semi-superjunction structure is a design between a traditional structure and a superjunction structure. By introducing a P-N column structure above the drift region, charge balance and electric field modulation are achieved. Compared with the traditional structure, the semi-superjunction structure can significantly improve the breakdown voltage capability of the device and reduce the on-resistance without increasing the manufacturing complexity. Description of the Drawings

[0017] Figure 1 is a schematic diagram of a semi-superjunction field-effect transistor based on a silicon carbide material; Figure 2 is a schematic diagram of successively depositing a blocking layer, a drift region, and a first N-column layer on the upper surface of an N-type substrate; Figure 3 is a schematic diagram of forming a first P-column layer at a specified position on the first N-column layer; Figure 4 is a schematic diagram of forming a second N-column layer on the upper surface of the first N-column layer; Figure 5 is a schematic diagram of forming a second P-column layer on the second N-column layer; Figure 6 is Figure 5 a schematic diagram after depositing to form a channel region; Figure 7 is a schematic diagram of forming a source region on the upper surface of the channel region; Figure 8 is a schematic diagram of etching the channel region to obtain a gate groove; Figure 9 is a schematic diagram of forming a P-type region at the bottom and side walls of the gate groove; Figure 10 is a schematic diagram of depositing to form a gate electrode, a drain electrode, and a source electrode; Figure 11 is a diagram showing the influence of the doping concentration in the column region on the breakdown voltage and the specific on-resistance; Figure 12 is a diagram showing the influence of the doping concentration in the column region on the BFOM value; Figure 13 is a diagram showing the influence of the width of the channel portion on the breakdown voltage and the specific on-resistance; Figure 14 is a diagram showing the influence of the width of the channel portion on the BFOM value; Figure 15 is a diagram showing the influence of the length of the channel portion on the breakdown voltage and the specific on-resistance; Figure 16 is a diagram showing the influence of the length of the channel portion on the BFOM value; Figure 17 is the transfer characteristic curve of the device; Figure 18 is the output characteristic curve of the device; Figure 19 is the breakdown characteristic curve of the device; Figure 20 is a diagram of the simulation result of P-column ion implantation obtained by the random injection method; Figure 21 is a diagram of the simulation result of P-column ion implantation obtained by the channel injection method.

[0018] The reference numerals in the figure are as follows: 1. N-type substrate; 2. Barrier layer; 3. Drift region; 4. First N-column layer; 5. First P-column layer; 6. Second N-column layer; 7. P-column region; 8. N-column region; 9. Channel region; 10. Source region; 11. Gate trench; 12. P-type region; 13. Channel portion; 14. Gate electrode; 15. Drain electrode; 16. Source electrode. Detailed implementation manners

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0020] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "inner" and "outer" is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0021] In the description of the present application, it should also be noted that unless otherwise clearly specified and defined, the terms "arrangement" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0022] The present invention will be described in detail below with reference to the accompanying drawings.

[0023] As Figures 2 to 10 shown, this embodiment discloses a manufacturing process of a semi-superjunction field effect transistor based on silicon carbide material, including the following steps: Step S1: As Figure 2 shown, prepare a heavily doped N-type substrate 1, and sequentially deposit a blocking layer 2, a drift region 3, and a first N-column layer 4 on the upper surface of the N-type substrate 1. The thickness of the first N-column layer 4 is a, and a is 3.5 μm; Step S2: As Figure 3 shown, form a first P-column layer 5 at a specified position in the first N-column layer 4 by means of channel implantation. The depth of the first P-column layer 5 is a; Step S3: As Figure 4 shown, form a second N-column layer 6 with a thickness of a on the upper surface of the first N-column layer 4 by chemical vapor deposition; Step S4: As Figure 5 shown, use the same mask and ion implantation parameters (such as energy and dose) as in Step S2, and form a second P-column layer with a thickness of a at a specified position in the second N-column layer 6 by means of channel implantation. The second P-column layer corresponds to the first P-column layer, and a P-column region 7 with a depth of 2a is obtained. The second N-column layer 6 corresponds to the first N-column layer 4, and an N-column region 8 with a depth of 2a is obtained; Step S5: As Figure 6 shown, form a channel region 9 on the upper surface of the structure obtained in Step S4 by chemical vapor deposition; Step S6: As Figure 7As shown, a source region 10 (P+ source region 10) is formed on the upper surface of the channel region 9 by vertical ion implantation; Step S7: As Figure 8 shown, the channel region 9 is etched to obtain a gate trench 11, and the gate trench 11 is on both sides of the source region 10; Step S8: As Figure 9 shown, a P-type region 12 is formed at the bottom and side walls of the gate trench 11 by ion implantation. The part of the channel region 9 between the two P-type regions 12 is the channel portion 13; specifically, the P-type region 12 at the bottom of the gate trench 11 is formed by vertical ion implantation, and the P-type region 12 on the side walls of the gate trench 11 is formed by inclined ion implantation; Step S9: As Figure 10 shown, a gate electrode 14 is formed by depositing a metal material on the P-type region 12, a drain electrode 15 is formed by depositing a metal material on the lower surface of the N-type substrate 1, and a source electrode 16 is formed by depositing a metal material on the upper surface of the source region 10.

[0024] As Figure 1 and Figure 10 shown, a semi-superjunction field effect transistor based on a silicon carbide material prepared by the above manufacturing process includes: An N-type substrate 1; A blocking layer 2 on the upper surface of the N-type substrate 1; A drift region 3 on the upper surface of the blocking layer 2; An N-column region 8 on the upper surface of the drift region 3; Two P-column regions 7 on the upper surface of the drift region 3 and located on both sides of the N-column region 8 respectively; A channel portion 13 on the upper surface of the N-column region 8; Two P-type regions 12 are respectively arranged on the upper surface of the P-column region 7, and the side walls of the two P-type regions 12 are respectively located on both sides of the channel portion 13; A source region 10 on the upper surface of the channel portion 13; A source electrode 16 on the upper surface of the source region 10; A gate electrode 15 on the surface of the P-type region 12 A drain electrode 15 on the lower surface of the N-type substrate 1.

[0025] In the structure of the present application, an N-column region 8 and a P-column region 7 are introduced above the drift region 3 to form a semi-superjunction structure. The semi-superjunction structure is a design between a traditional structure and a superjunction structure. By introducing a P-N column structure above the drift region 3, charge balance and electric field modulation are achieved. Compared with the traditional structure, the semi-superjunction structure can significantly improve the breakdown voltage capability of the device and reduce the on-resistance without increasing the manufacturing complexity.

[0026] For the semi-superjunction field-effect transistor based on silicon carbide material in this embodiment, in the reverse conduction state, most of the electric field lines emitted by the ionized positive charges in the N-column region flow towards the ionized negative charges in the adjacent P-column region, which introduces a significant two-dimensional electric field effect in the breakdown voltage layer. The complex electric field modulation technology greatly reduces the peak electric field on the device surface and optimizes the electric field distribution inside the device, thereby improving the breakdown voltage capability of the device. At the same time, in the forward conduction state, due to the relatively high doping concentration in the N-column region, the on-resistance of the device is reduced, and the contradictory relationship between the breakdown voltage (BV) and the specific on-resistance (Ron,sp) is significantly weakened.

[0027] To obtain the optimized parameters, combined with Figure 1 , a simulation test is carried out on the semi-superjunction field-effect transistor. Table 1 below shows the unoptimized structural parameters of the semi-superjunction field-effect transistor (device cell structure).

[0028] Table 1

[0029] In the table, the device cell width is the N-type substrate (W cell ). During the device optimization process, the effects of the doping concentration in the column region (the doping concentration in the P-column region and the N-column region), the width of the channel part, and the length of the channel part on the transfer, output, and breakdown characteristics of the device are studied. For details, see Figures 11 to 16 , among which, Figure 11 is the influence diagram of the doping concentration in the column region on the breakdown voltage and the specific on-resistance; Figure 12 is the influence diagram of the doping concentration in the column region on the BFOM value; Figure 13 is the influence diagram of the width of the channel part on the breakdown voltage and the specific on-resistance; Figure 14 is the influence diagram of the width of the channel part on the BFOM value; Figure 15 is the influence diagram of the length of the channel part on the breakdown voltage and the specific on-resistance; Figure 16 is the influence diagram of the length of the channel part on the BFOM value. Figures 11 to 16 The BFOM values under different doping concentrations in the column region, widths of the channel part, and lengths of the channel part are respectively shown. BFOM is a key index for evaluating the performance of power semiconductor devices, which can comprehensively reflect the performance balance between the breakdown voltage and the specific on-resistance of the device. A higher BFOM value means that the device can maintain a lower specific on-resistance at a higher breakdown voltage, thereby reducing the conduction loss. It can be found that during the optimization process, the doping concentration in the P-column region and the N-column region corresponding to the highest BFOM value are 2×10¹ 6 cm⁻³ and 8×10¹ 6 cm⁻³ respectively, the width of the channel part is 1.0 um, and the length of the channel part is 1.4 um.

[0030] The electrical performance of the optimized device is simulated, and the results are asFigures 17 to 19 As shown. Figure 17 shows the transfer characteristic curve of the device, where the drain-source voltage is 2 V and the gate voltage is scanned from -20 V to 2 V. When the drain current reaches 1×10 -7 A, the gate voltage is the threshold voltage of the semi-superjunction SiC JFET, and the threshold voltage is -4.988 V. Figure 18 For the output characteristic curve of the device, when the gate-source voltage is 0 V, the drain voltage is increased to 30 V, and the specific on-resistance obtained by calculation is 3.31 mΩ·cm 2 . Figure 19 For the breakdown characteristic curve, with the source grounded and the gate voltage at -10 V, the drain voltage is gradually increased. When the current density reaches 1×10 -6 A, the device is considered to break down. At this time, the breakdown voltage is 1701.49 V, reaching a design margin of 40% of 1200 V.

[0031] As Figure 20 and Figure 21 shown, it shows the simulation result diagram of P-column ion implantation obtained by random implantation and channel implantation methods (the abscissa is the implantation depth, and the ordinate is the Al concentration). It can be seen from the figure that random implantation (i.e., the ion beam is implanted perpendicular to the wafer surface) requires 9 superimposed implantations to form a P-column with a uniform concentration distribution and a thickness of 3.5 um, while channel implantation (i.e., the ion beam is implanted along the <0001> crystal orientation of silicon carbide) can achieve a similar uniform doping effect with only two implantations. In this embodiment, the semi-superjunction SiC JFET cell adopts the channel implantation method, and the manufacturing cost of the ion implantation process is significantly reduced by reducing the number of implantations.

[0032] The above are only the preferred embodiments of the present invention, and thus do not limit the patent protection scope of the present invention. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention, directly or indirectly applied in other related technical fields, shall be included in the protection scope of the present invention by the same token.

Claims

1. A semi-superjunction field effect transistor based on a silicon carbide material, characterized in that Comprising: N-type substrate; Blocking layer, on the upper surface of the N-type substrate; Drift region, on the upper surface of the blocking layer; N pillar region, on the upper surface of the drift region; Two P pillar regions, on the upper surface of the drift region and located on both sides of the N pillar region respectively; Channel portion, on the upper surface of the N pillar region; Two P-type regions, respectively arranged on the upper surfaces of the P pillar regions, and the side walls of the two P-type regions are respectively located on both sides of the channel portion; Source region, on the upper surface of the channel portion; Source electrode, on the upper surface of the source region; Gate electrode, on the surface of the P-type region Drain electrode, on the lower surface of the N-type substrate.

2. The semi-superjunction field effect transistor based on silicon carbide material according to claim 1, wherein, The doping concentration of the P-column region is 2×10¹ 6 cm⁻³.

3. The semi-superjunction field effect transistor based on silicon carbide material according to claim 1, characterized in that, The doping concentration of the N-column region is 8×10¹ 6 cm⁻³.

4. The semi-superjunction field-effect transistor based on a silicon carbide material according to claim 1, wherein The width of the channel portion is 1.0 um.

5. The semi-superjunction field effect transistor based on a silicon carbide material according to claim 1, wherein The length of the channel portion is 1.4 um.

6. A manufacturing process for a semi-superjunction field effect transistor based on silicon carbide material, characterized in that, Including the following steps: Step S1: Prepare a heavily doped N-type substrate, and sequentially deposit a blocking layer, a drift region, and a first N pillar layer on the upper surface of the N-type substrate. The thickness of the first N pillar layer is a; Step S2: Form a first P pillar layer at a specified position in the first N pillar layer by means of channel implantation. The depth of the first P pillar layer is a; Step S3: Form a second N pillar layer with a thickness of a on the upper surface of the first N pillar layer by chemical vapor deposition; Step S4: Use the same mask and ion implantation parameters as in Step S2, and form a second P pillar layer at a specified position in the second N pillar layer by means of channel implantation. The second P pillar layer corresponds to the first P pillar layer to obtain a P pillar region with a depth of 2a, and the second N pillar layer corresponds to the first N pillar layer to obtain an N pillar region with a depth of 2a; Step S5: Form a channel region on the upper surface of the structure obtained in Step S4 by chemical vapor deposition; Step S6: Form a source region on the upper surface of the channel region by vertical ion implantation; Step S7: Etch the channel region to obtain a gate trench, and the gate trench is on both sides of the source region; Step S8: Form P-type regions at the bottom and side walls of the gate trench by ion implantation. The part of the channel region between the two P-type regions is the channel portion; Step S9: Deposit a metal material on the P-type region to form a gate electrode, deposit a metal material on the lower surface of the N-type substrate to form a drain electrode, and deposit a metal material on the upper surface of the source region to form a source electrode.

7. The manufacturing process of the semi-superjunction field-effect transistor based on silicon carbide material according to claim 6, characterized in that, The doping concentration of the P-column region is 2×10¹ 6 cm⁻³.

8. The manufacturing process of the semi-superjunction field effect transistor based on silicon carbide material as claimed in claim 6, characterized in that, The doping concentration of the N-column region is 8×10¹ 6 cm⁻³.

9. The manufacturing process of the semi-superjunction field effect transistor based on silicon carbide material as claimed in claim 6, wherein The width of the channel portion is 1.0 um.

10. The manufacturing process of the semi-superjunction field effect transistor based on silicon carbide material as claimed in claim 6, characterized in that, The length of the channel portion is 1.4 um.

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