Novel trench gate SiC MOSFET and preparation method thereof

Abstract

According to the novel trench gate SiC MOSFET and the preparation method, N + active regions and P + electric field shielding layers are periodically and alternately distributed in the trench gate arrangement direction (z-axis), part of gate oxide layers are protected through all-around wrapping of the P + electric field shielding layers, and the other part of gate oxide layers are protected through attraction of electric field lines by the P + electric field shielding layers on the two sides. Meanwhile, the p-well is grounded through the P + electric field shielding layer, and the problem that the dynamic on-resistance is increased due to the charge storage effect is solved. Compared with a half-package groove and an adjacent-package groove, smaller cell-pitch can be achieved, higher current density is achieved, meanwhile, low miller capacitance is considered, and low switching loss is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and particularly relates to a novel trench-gate SiC MOSFET and a preparation method thereof. Background Art

[0002] In aerospace and military equipment, power semiconductor devices are mainly applied to power supply and power distribution subsystems and belong to core components. Power semiconductor devices made of Si materials have gradually reached their theoretical limits, and it is difficult to further achieve high-frequency operation, high power density, and miniaturization of power converters at the current research level.

[0003] Silicon Carbide (SiC) materials, which have characteristics such as a large bandgap width, a high critical breakdown electric field, a high thermal conductivity, and a high electron saturation drift velocity, can better meet the higher working frequencies, higher working voltages, lower on-resistances, and high power density requirements for power semiconductor devices in the rapidly developing aerospace technology. At the same time, they have the ability to withstand special environments such as radiation resistance and extremely high temperatures.

[0004] When the SiC trench-gate MOSFET operates in the reverse direction, the N-drift region depletion is used to withstand a relatively high reverse bias voltage. Due to the high critical breakdown electric field of the SiC material, the drift region at the bottom of the trench gate will reach a very high electric field near breakdown. The dielectric constant of the oxide layer is less than that of the SiC material, so the electric field strength is approximately 2.8 times that of SiC. Coupled with the curvature effect, extremely high electric field strengths accumulate at the corners of the oxide layer. Working at a high electric field for a long time will cause degradation of the gate oxide layer and a decrease in reliability. To reduce the electric field strength of the oxide layer during the reverse operation of the device and improve the reliability of the oxide layer, a grounded P+ shielding layer is usually introduced at the bottom of the trench oxide layer to shield the influence of the high electric field strength. The grounded P+ shielding layer always operates at zero potential, shields part of the gate-drain capacitance, reduces the switching loss, and can better shield the electric field in the oxide layer. However, the JFET introduced by it will significantly increase the forward on-resistance. Summary of the Invention

[0005] A novel trench-gate SiC MOSFET is designed with a periodic structure of alternating N+ active regions and P-type electric field shielding layers. Part of the gate oxide layer is fully covered and protected by the P+ electric field shielding layer, while the other part of the gate oxide layer is effectively protected by the P+ electric field shielding layers on both sides attracting the electric field lines. In addition, the p-well is grounded through the P+ electric field shielding layer, fundamentally solving the problem of the increase in dynamic on-resistance caused by the charge storage effect. Compared with the half-packaged trench and adjacent-packaged trench structures, this solution can achieve a smaller cell-pitch, significantly improve the current density, and take into account the low Miller capacitance characteristic, thereby reducing the switching loss.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A novel trench-gate SiC MOSFET includes an N+ substrate region 6, an N- drift region 5 above the N+ substrate region 6, and a current spreading layer CSL4 above the interior of the N- drift region 5. In the middle above the interior of the current spreading layer CSL4, a P-type electric field shielding layer 1 and an N+ ohmic contact region 2 are alternately distributed along the z direction. Directly below the N+ ohmic contact region 2 is a P-type base region 3, and the P-type base region 3 serves as the channel of the trench-gate SiC MOSFET and is grounded through the P+ electric field shielding layer 1. A gate trench is provided in the middle between the alternately distributed P+ electric field shielding layer 1 and the N+ ohmic contact region 2, and its depth is greater than the sum of the depths of the P-type base region 3 and the N+ ohmic contact region 2. The gate trench is provided with a polysilicon gate 7 and a gate dielectric 8 filling the gate trench; the bottom of the gate trench alternately contacts the current spreading layer CSL4 or the P-type electric field shielding layer 1; above the N+ ohmic contact region 2 and the P-type electric field shielding layer 1 is a source metal 10, and above the gate trench is an interlayer dielectric 9; it is set that the x direction is the direction in which the cell repeating units are arranged, the y direction is the direction pointing from the N+ ohmic contact region 2 or the P-type electric field shielding layer 1 to the N+ substrate 6, and the z direction is the direction in which the gate trench 8 is arranged.

[0008] As a preferred embodiment, the gate dielectric 8 is SiO2.

[0009] As a preferred embodiment, the interlayer dielectric 9 is SiO2.

[0010] As a preferred embodiment, the P-type electric field shielding layer 1, the N+ ohmic contact region 2, and the P-type base region 3 are all formed by multiple ion implantations.

[0011] As a preferred embodiment, the materials of the P-type electric field shielding layer 1, the N+ ohmic contact region 2, the P-type base region 3, the current spreading layer CSL4, the N- drift region 5, and the N+ substrate region 6 are all silicon carbide.

[0012] To achieve the above object of the invention, the present invention also provides a preparation method for a novel trench-gate SiC MOSFET, including the following steps:

[0013] The first step: Cleaning the epitaxial wafer, and implanting nitrogen ions on the N- epitaxial wafer to form a CSL layer;

[0014] The second step: Using polysilicon as an implantation blocking layer to implant aluminum ions to form a P-type shielding layer;

[0015] The third step: Implanting aluminum ions to form a P-type base region;

[0016] The fourth step: Using polysilicon as an implantation blocking layer to implant nitrogen ions to form an N+ ohmic contact region and annealing to activate;

[0017] Step 5: Etch to form gate trenches;

[0018] Step 6: After the sacrificial oxidation process, grow a gate oxide layer by thermal oxidation, and then perform nitrogen passivation

[0019] Step 7: Deposit polysilicon in the gate trenches, pattern the polysilicon, and deposit the interlayer dielectric;

[0020] Step 8: Etch to form source contact holes, deposit metal to form a source ohmic contact on the front side and a drain ohmic contact on the back side;

[0021] Step 9: Deposit a passivation layer, and etch away the passivation dielectric in the gate and source contact areas through photolithography.

[0022] Through the periodic structure design of the alternating arrangement of N+ active regions and P-type electric field shielding layers in the present invention, part of the gate oxide layer is fully covered and protected by the P+ electric field shielding layer, while the other part of the gate oxide layer is effectively protected by the P+ electric field shielding layers on both sides attracting the electric field lines. In addition, the p-well is grounded through the P+ electric field shielding layer, fundamentally solving the problem of the increase in dynamic on-resistance caused by the charge storage effect. Compared with the half-packaged trench and adjacent-packaged trench structures, this solution can achieve a smaller cell-pitch, significantly improve the current density, and take into account the low Miller capacitance characteristics, thereby reducing the switching loss. Brief Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of a novel trench-gate SiC MOSFET according to Embodiment 1 of the present invention;

[0024] Figure 2 is a schematic cross-sectional diagram of a novel trench-gate SiC MOSFET according to Embodiment 1 of the present invention; where (a) is the overall view of the cell of the novel trench-gate SiC MOSFET, (b) is the A cross-sectional view, and (c) is the A' cross-sectional view;

[0025] The A' cross-section is a view showing the x-y cross-section perpendicular to the z-axis, from the N+ ohmic contact region 2 to the N+ substrate region 6, passing through the N+ ohmic contact region 2, the P-type base region 3, the current spreading layer 4, the N- drift region 5, and the N+ substrate 6;

[0026] The A cross-section is a view showing the x-y cross-section perpendicular to the z-axis, from the P-type electric field shielding layer 1 to the N+ substrate region 6, passing through the P-type electric field shielding layer 1, the current spreading layer 4, the N- drift region 5, and the N+ substrate 6.

[0027] Figure 3 is a schematic diagram of the cleaned epitaxial wafer in Embodiment 2 of the present invention, where nitrogen ions are implanted on the N-epitaxial wafer to form a CSL layer;

[0028] Figure 4 It is a schematic structural diagram of forming a P-type shielding layer by implanting aluminum ions with polysilicon as an implantation barrier layer in Embodiment 2 of the present invention;

[0029] Figure 5 It is a schematic structural diagram of implanting aluminum ions to form a P-type base region in Embodiment 2 of the present invention;

[0030] Figure 6 It is a schematic structural diagram of implanting nitrogen ions with polysilicon as an implantation barrier layer to form an N+ ohmic contact region and annealing for activation in Embodiment 2 of the present invention;

[0031] Figure 7 It is a schematic structural diagram of etching to form a gate trench in Embodiment 2 of the present invention;

[0032] Figure 8 It is a schematic structural diagram of, after the sacrificial oxidation process in Embodiment 2 of the present invention, generating a gate oxide layer by thermal oxidation, then performing nitrogen passivation, depositing polysilicon in the gate trench, patterning the polysilicon, and depositing an interlayer dielectric;

[0033] Figure 9 It is a schematic structural diagram of etching to form a source contact hole, depositing metal to form a source ohmic contact on the front side and a drain ohmic contact on the back side in Embodiment 2 of the present invention;

[0034] 1 - P-type electric field shielding layer, 2 - N+ ohmic contact region, 3 - P-type base region, 4 - current spreading layer CSL, 5 - N - drift region, 6 - N+ substrate, 7 - polysilicon gate, 8 - gate dielectric, 9 - interlayer dielectric, 10 - source metal. Specific embodiments

[0035] The following illustrates the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Embodiment 1

[0037] Such as Figure 2As shown in the figure, a novel trench-gate SiC MOSFET includes an N+ substrate region 6, an N- drift region 5 above the N+ substrate region 6, and a current spreading layer CSL4 above the interior of the N- drift region 5. In the middle above the interior of the current spreading layer CSL4, there are P-type electric field shielding layers 1 and N+ ohmic contact regions 2 alternately distributed along the z direction. Directly below the N+ ohmic contact region 2 is a P-type base region 3, and the P-type base region 3 is the channel of the trench-gate SiC MOSFET, which is grounded through the P+ electric field shielding layer 1. In the middle between the alternately distributed P+ electric field shielding layers 1 and N+ ohmic contact regions 2, there is a gate groove, whose depth is greater than the sum of the depths of the P-type base region 3 and the N+ ohmic contact region 2. Inside the gate groove, there are a polysilicon gate 7 and a gate dielectric 8 filling the gate groove. The bottom of the gate groove alternately contacts the current spreading layer CSL4 or the P-type electric field shielding layer 1. Above the N+ ohmic contact region 2 and the P-type electric field shielding layer 1 is a source metal 10, and above the gate groove is an interlayer dielectric 9. It is set that the x direction is the direction in which the cell repeating units are arranged, the y direction is the direction from the N+ ohmic contact region 2 or the P-type electric field shielding layer 1 to the N+ substrate 6, and the z direction is the direction in which the gate trench 8 is arranged.

[0038] As shown in Figure 2 (b), the gate groove is located within the P-type electric field shielding layer 1, and its bottom contacts the P-type electric field shielding layer 1.

[0039] As shown in Figure 2 (c), the gate groove is located within the N+ ohmic contact region 2, the P-type base region 3, and the current spreading layer CSL4, and its bottom contacts the current spreading layer CSL4.

[0040] As a preferred embodiment, the gate dielectric 8 is SiO2.

[0041] As a preferred embodiment, the interlayer dielectric 9 is SiO2.

[0042] As a preferred embodiment, the P-type electric field shielding layer 1, the N+ ohmic contact region 2, and the P-type base region 3 are all formed by multiple ion implantations.

[0043] As a preferred embodiment, the materials of the P-type electric field shielding layer 1, the N+ ohmic contact region 2, the P-type base region 3, the current spreading layer CSL4, the N- drift region 5, and the N+ substrate region 6 are all silicon carbide.

[0044] In this example, through the design of a periodic structure with alternating N+ active regions and P-type electric field shielding layers, part of the gate oxide layer is fully covered and protected by the P+ electric field shielding layer, while the other part of the gate oxide layer is effectively protected by the P+ electric field shielding layers on both sides attracting electric field lines. In addition, the p-well is grounded through the P+ electric field shielding layer, fundamentally solving the problem of increased dynamic on-resistance caused by the charge storage effect. Compared with the half-packaged trench and adjacent-packaged trench structures, this solution can achieve a smaller cell pitch, significantly improve the current density, and take into account the low Miller capacitance characteristics, thereby reducing the switching loss.

[0045] Example 2

[0046] As Figures 2-8 shown, this example provides a method for fabricating a novel trench-gate SiC MOSFET, including the following steps:

[0047] The first step: Clean the epitaxial wafer, and implant nitrogen ions on the N-epitaxial wafer to form a CSL layer; as shown in Figure (3);

[0048] The second step: Use polysilicon as an implantation blocking layer to implant aluminum ions to form a P-type shielding layer; as shown in Figure (4);

[0049] The third step: Implant aluminum ions to form a P-type base region; as shown in Figure (5);

[0050] The fourth step: Use polysilicon as an implantation blocking layer to implant nitrogen ions to form an N+ ohmic contact region and anneal to activate; as shown in Figure (6);

[0051] The fifth step: Etch to form a gate trench; as shown in Figure (7);

[0052] The sixth step: After the sacrificial oxidation process, generate a gate oxide layer by thermal oxidation, and then perform nitrogen passivation

[0053] The seventh step: Deposit polysilicon in the gate trench, pattern the polysilicon, and deposit an interlayer dielectric as shown in Figure (8);

[0054] The eighth step: Etch to form source contact holes, deposit metal to form a source ohmic contact on the front side and a drain ohmic contact on the back side. As shown in Figure (9).

[0055] The ninth step: Deposit a passivation layer, and etch away the passivation dielectric in the gate and source contact regions through photolithography.

[0056] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A novel trench-gate SiC MOSFET, characterized in that: It includes an N+ substrate region (6), an N- drift region (5) above the N+ substrate region (6), and a current spreading layer CSL (4) above the interior of the N- drift region (5). Inside the current spreading layer CSL (4) and in the middle above, there are P-type electric field shielding layers (1) and N+ ohmic contact regions (2) distributed alternately in the z direction. Right below the N+ ohmic contact region (2) is a P-type base region (3). The P-type base region (3) serves as the channel of the trench-type SiC MOSFET and is grounded through the P+ electric field shielding layer (1). In the middle between the alternately distributed P+ electric field shielding layers (1) and N+ ohmic contact regions (2), there is a gate trench, whose depth is greater than the sum of the depths of the P-type base region (3) and the N+ ohmic contact region (2). Inside the gate trench, there are a polysilicon gate (7) and a gate dielectric (8) filling the gate trench. The bottom of the gate trench alternately contacts the current spreading layer CSL (4) or the P-type electric field shielding layer (1). Above the N+ ohmic contact region (2) and the P-type electric field shielding layer (1) is a source metal (10), and above the gate trench is an interlayer dielectric (9). It is set that the x direction is the direction of the arrangement of the cell repeating unit, the y direction is the direction from the N+ ohmic contact region (2) or the P-type electric field shielding layer (1) pointing to the N+ substrate (6), and the z direction is the direction of the arrangement of the gate trench (8).

2. A novel trench-gate SiC MOSFET according to claim 1, characterized in that: The gate dielectric (8) is SiO2.

3. A novel trench-gate SiC MOSFET according to claim 1, characterized in that: The interlayer dielectric (9) is SiO2.

4. A novel trench-gate SiC MOSFET according to claim 1, characterized in that: The P-type electric field shielding layer (1), the N+ ohmic contact region (2), and the P-type base region (3) are formed by multiple ion implantations.

5. A novel trench-gate SiC MOSFET according to claim 1, wherein: The materials of the P-type electric field shielding layer (1), the N+ ohmic contact region (2), the P-type base region (3), the current spreading layer CSL (4), the N- drift region (5), and the N+ substrate region (6) are all silicon carbide.

6. A method for fabricating a novel trench-gate SiC MOSFET according to any one of claims 1 to 5, characterized in that, It includes the following steps: The first step: Clean the epitaxial wafer, and implant nitrogen ions on the N- epitaxial wafer to form a CSL layer. The second step: Use polysilicon as an implantation blocking layer to implant aluminum ions to form a P-type shielding layer. The third step: Implant aluminum ions to form a P-type base region. The fourth step: Use polysilicon as an implantation blocking layer to implant nitrogen ions to form an N+ ohmic contact region and anneal for activation. The fifth step: Etch to form a gate trench. The sixth step: After the sacrificial oxidation process, generate a gate oxide layer by thermal oxidation, and then perform nitrogen passivation. The seventh step: Deposit polysilicon in the gate trench, pattern the polysilicon, and deposit an interlayer dielectric. The eighth step: Etch to form a source contact hole, deposit metal to form a source ohmic contact on the front side and a drain ohmic contact on the back side. The ninth step: Deposit a passivation layer, and etch away the passivation dielectric of the gate and source contact regions through photolithography.

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