Fast switch shielding trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a fast switch shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a gate metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a P-type well region, an N-type source region, a P-type source region and a low-resistance region are formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing polycrystalline silicon, and forming a polycrystalline silicon region; depositing an insulating medium; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; and forming a barrier layer again, etching, depositing metal, forming a source metal layer, and removing the barrier layer to complete preparation. The gate-drain capacitance of the device is reduced, and the switching speed of the device is improved.

Description

Technical Field

[0001] The present invention relates to a fast-switching shielded trench-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for devices vary in different fields. In the range of 650 - 900V, there is an urgent need to provide a silicon carbide VDMOS device to reduce the on-resistance and improve the switching speed. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a fast-switching shielded trench-gate silicon carbide VDMOS and a preparation method thereof, which reduce the gate-drain capacitance of the device and improve the switching speed of the device.

[0004] In a first aspect, the present invention provides a preparation method of a fast-switching shielded trench-gate silicon carbide VDMOS, including the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a gate metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a barrier layer on the drift layer, etch the barrier layer to form a through hole, and perform ion implantation to form a P-type well region;

[0007] Step 3: Remove the original barrier layer, re-form a barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form an N-type source region;

[0008] Step 4: Remove the original barrier layer, re-form a barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form a P-type source region;

[0009] Step 5: Remove the original barrier layer, re-form a barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form a low-resistance region;

[0010] Step 6: Remove the original barrier layer, re-form a barrier layer, etch the barrier layer to form a through hole, etch the drift layer to form a groove, and deposit to form an insulating dielectric layer;

[0011] Step 7: Remove the original barrier layer, re-form a barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer, deposit polysilicon to form a polysilicon region; then deposit an insulating dielectric;

[0012] Step 8: Remove the original barrier layer, re-form a barrier layer, etch the barrier layer to form a through hole, etch the insulating dielectric layer to form a trench, and deposit metal to form a gate metal layer;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, and etch the low-resistance region, P-type well region, P-type source region, and N-type source region. Deposit metal to form a source metal layer, and remove the barrier layer to complete the preparation.

[0014] In a second aspect, the present invention provides a fast-switching shielded trench-gate silicon carbide VDMOS, which is prepared by using the preparation method of a fast-switching shielded trench-gate silicon carbide VDMOS described in the first aspect.

[0015] The advantages of the present invention are as follows:

[0016] 1. The gate structure of the present invention includes a gate metal layer, a first N-type polysilicon layer, a P-type polysilicon layer, and a second N-type polysilicon layer. When a positive voltage is applied to the gate metal layer, positive charges are generated in the first N-type polysilicon layer near the gate metal layer through the charge effect. The positive charges gradually conduct from top to bottom in the polysilicon region, and effectively suppress the gate-drain capacitance of the device.

[0017] 2. When a positive charge is applied to the gate of the present invention, a forward pn junction is formed at the upper part and a reverse pn junction is formed at the bottom in the first N-type polysilicon layer, P-type polysilicon layer, and second N-type polysilicon layer. Compared with the traditional single polysilicon, this structure constructs an NPN-type shield gate for the device on the basis of not affecting the inversion of the P-type well region of the device, and improves the shielding effect of the gate-drain capacitance of the device.

[0018] 3. The low-resistance region of the present invention can ensure the characteristics of the parasitic body Schottky diode of the device, realize the freewheeling of the low-resistance body diode of the device, and the P-type source region can improve the reverse breakdown voltage of the N-type source region and ensure the freewheeling ability of the body diode. Description of the Drawings

[0019] The present invention will be further described below with reference to the drawings in conjunction with embodiments.

[0020] Figure 1 It is a schematic diagram of a fast-switching shielded trench-gate silicon carbide VDMOS of the present invention.

[0021] Figure 2 It is a process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS of the present invention Figure 1 .

[0022] Figure 3 It is a process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS of the present invention Figure 2 .

[0023] Figure 4 It is a process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS of the present invention Figure 3 .

[0024] Figure 5 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 4 。

[0025] Figure 6 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 5 。

[0026] Figure 7 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 6 。

[0027] Figure 8 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 7 。

[0028] Figure 9 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 8 。

[0029] Figure 10 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 9 。

[0030] Figure 11 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 。

[0031] Figure 12 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 One.

[0032] Figure 13 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 Two.

[0033] Figure 14 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 Three.

[0034] Figure 15 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 Four.

[0035] Figure 16 Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 Five.

[0036] Figure 17Process cross-section of a fast-switching shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 VI. Specific embodiments

[0037] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of the present application herein are for the purpose of describing specific embodiments only and are not intended to limit the present application.

[0039] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, the first element, component, region, layer, doping type or portion discussed below may be denoted as the second element, component, region, layer or portion without departing from the teachings of the present invention.

[0040] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0041] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. Meanwhile, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0042] As Figures 1 to 17 shown, an embodiment of the present application provides a method for preparing a fast-switching shielded trench-gate silicon carbide VDMOS, including the following steps:

[0043] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0044] Step 2: Form a barrier layer 9 on the drift layer 2, etch the barrier layer 9 to form a through hole, and perform ion implantation to form a P-type well region 4;

[0045] Step 3: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, and perform ion implantation to form an N-type source region 41;

[0046] Step 4: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, and perform ion implantation to form a P-type source region 42;

[0047] Step 5: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, and perform ion implantation to form a low-resistance region 3;

[0048] Step 6: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the drift layer 2 to form a groove 21, and deposit to form an insulating dielectric layer 5;

[0049] Step 7: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the insulating dielectric layer 5, and deposit polysilicon to form a polysilicon region 51; then deposit an insulating dielectric;

[0050] Step 8: Remove the original barrier layer 9, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the insulating dielectric layer 5 to form a trench 52, and deposit metal to form a gate metal layer 6;

[0051] Step 9, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and etch the low resistance area 3, the P-type well area 4, the P-type source area 42 and the N-type source area 41, deposit metal to form a source metal layer 7, remove the barrier layer 9, and complete the preparation.

[0052] In this embodiment, preferably, the polysilicon region 51 includes a first N-type polysilicon layer 511, a P-type polysilicon layer 512 and a second N-type polysilicon layer 513, the lower side of the first N-type polysilicon layer 511 is connected to the upper side of the P-type polysilicon layer 512, and the lower side of the P-type polysilicon layer 512 is connected to the upper side of the second N-type polysilicon layer 513.

[0053] In this embodiment, preferably, the doping concentration of the first N-type polysilicon layer 511 is greater than the doping concentration of the P-type polysilicon layer 512 , and the doping concentration of the P-type polysilicon layer 512 is greater than the doping concentration of the second N-type polysilicon layer 513 .

[0054] In this embodiment, preferably, the doping concentration of the polysilicon region 51 is greater than or equal to 1e20 cm -3 .

[0055] In this embodiment, preferably, the silicon carbide substrate 1 , the drift layer 2 and the low resistance region 3 are all of N type.

[0056] In this embodiment, preferably, a thickness L1 of the insulating dielectric layer 5 on the side of the polysilicon region 51 is greater than a thickness L2 of the insulating dielectric layer 5 on the side of the gate metal layer 6 .

[0057] In this embodiment, preferably, the distance between the gate metal layer 6 and the upper side of the polysilicon region 51 is smaller than the distance between the lower side of the polysilicon region 51 and the bottom surface of the groove 21 .

[0058] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0059] Silicon carbide substrate 1;

[0060] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a groove 21 and a protrusion 22 are provided on the drift layer 2;

[0061] A low resistance region 3, wherein the lower side of the low resistance region 3 is connected to the upper side of the protrusion 22;

[0062] The P-type well region 4, the lower side of the P-type well region 4 is connected to the drift layer 2, and the outer side of the P-type well region 4 is connected to the inner side of the convex portion 22 and the inner side of the low-resistance region 3; an N-type source region 41 and a P-type source region 42 are provided on the P-type well region 4; the outer side of the P-type source region 42 is connected to the P-type well region 4, and the inner side of the P-type well region 4 is connected to the outer side of the N-type source region 41;

[0063] The insulating dielectric layer 5, the lower part of the insulating dielectric layer 5 is arranged in the groove 21, and the outer side of the insulating dielectric layer 5 is respectively connected to the inner side of the P-type well region 4 and the inner side of the N-type source region 41; a polysilicon region 51 and a trench 52 are arranged in the insulating dielectric layer 5, and the trench 52 is located directly above the polysilicon region;

[0064] The gate metal layer 6, the gate metal layer 6 is arranged in the trench 52;

[0065] The source metal layer 7, the source metal layer 7 is respectively connected to the low-resistance region 3, the P-type well region 4, the P-type source region 42 and the N-type source region 41;

[0066] And, the drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0067] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 5 - 9e17 cm -3 , the doping concentration of the N-type low-resistance region 3 is 6 - 9e17 cm -3 , the doping concentration of the P-type well region 4 is 1 - 5e16 cm -3 , the doping concentration of the P-type source region 42 is 1 - 5e19 cm -3 , the doping concentration of the N-type source region 41 is 2 - 8e18 cm -3, the material of the insulating dielectric layer 5 can be silicon dioxide; the doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device; the doping concentration of the P-type well region 4 is to achieve the breakdown voltage of the pn junction structure of the device when the drain of the device bears a high voltage. Reducing the doping concentration can reduce the gate switching charge, and increasing the concentration can improve the reverse breakdown voltage ability of the device. The set doping concentration is a compromise between the switching charge and the breakdown voltage; the doping concentration of the P-type source region 42 is for the ohmic contact with the source metal layer 7, so as to construct a low-resistance parasitic pn junction body diode of the source metal layer 7 - P-type source region 42 (ohmic contact) - P-type well region 4 - N-type drift layer 2 (pn junction) of the device; the doping concentration of the N-type low-resistance region 3 is to form a Schottky contact with the middle source metal layer 7 of the device, reduce the on-voltage drop of the body diode of the device, and ensure the reverse breakdown voltage; the structure of the first N-type polysilicon layer 511 - P-type polysilicon layer 512 - second N-type polysilicon layer 513, through the N-P-N type charge, improves the shielding effect of the shield gate on the gate-drain capacitance and reduces the switching charge of the device;

[0068] The thickness of the N-type silicon carbide substrate 1 of the device is 300 nm, which is to form a low-resistance ohmic contact with the drain metal layer 8 and reduce the on-resistance of the device; the thickness of the N-type drift layer 2 is 30 - 60 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device, and the breakdown voltage range of the device is 650 - 900 V; the total depth of the gate structure of the device is 1.8 μm, the thickness of the gate metal layer 6 is 0.9 μm, the thicknesses of the first N-type polysilicon layer 511, P-type polysilicon layer 512 and second N-type polysilicon layer 513 are all 200 nm, the thickness of the insulating dielectric between the first N-type polysilicon layer 511 and the gate metal layer 6 is 100 nm, the distance from the bottom of the second N-type polysilicon layer 513 to the bottom of the insulating dielectric layer 5 is 200 nm, and the widths of the insulating dielectrics on the left and right sides of the gate metal layer 6 are both 50 nm, which is to ensure a compromise between the gate control ability and the gate reliability of the device; the widths of the insulating dielectrics on the left and right sides of the polysilicon region 51 are both 100 nm, which is to ensure the reliability of the insulating dielectric layer 5 under deep trench conditions, the thickness of the source metal layer 7 is 200 nm, the thicknesses of the P-type source region 42 and N-type source region 41 are both 200 nm, the thickness of the N-type low-resistance region 3 is 200 nm, the thickness of the P-type well region 4 is 600 nm, the width of the N-type low-resistance region 3 is 100 - 500 nm, the width of the P-type well region 4 is 1 μm - 3 μm, the widths of the P-type source region 42 and N-type source region 41 are both 300 - 1000 nm, and the width of the insulating dielectric layer 5 is 1 μm - 1.5 μm, which is to ensure the width of the deepest etched part;

[0069] The gate structure of the device includes a gate metal layer 6, a first N-type polysilicon layer 511, a P-type polysilicon layer 512, and a second N-type polysilicon layer 513. When a positive voltage is applied to the gate metal layer 6, positive charges are generated in the first N-type polysilicon layer 511 near the gate metal layer 6 through the charge effect. The positive charges are gradually conducted from top to bottom in the polysilicon region 51. The first N-type polysilicon layer near the gate metal layer 6 is heavily doped, and the doping concentration is 1 - 5e21 cm -3 , which can quickly respond to the gate charges of the device; the doping concentration of the P-type polysilicon layer is 5 - 8e20 cm -3 , and the doping concentration of the second N-type polysilicon layer 513 is 1 - 5e20 cm -3 . The doping concentration of the polysilicon region 51 gradually decreases from top to bottom, which can effectively suppress the gate-drain capacitance of the device;

[0070] When a positive charge is applied to the gate, a forward pn junction is formed in the upper part and a reverse pn junction is formed in the bottom part of the first N-type polysilicon layer 511, the P-type polysilicon layer 512, and the second N-type polysilicon layer 513. Compared with the traditional single polysilicon, this structure constructs an NPN-type shield gate for the device without affecting the inversion of the P-type well region 4 of the device, and improves the shielding effect of the gate-drain capacitance of the device;

[0071] The N-type low-resistance region 3 can ensure the parasitic body Schottky diode characteristics of the device, realize the freewheeling of the low-resistance body diode of the device, and the P-type source region 42 can improve the reverse breakdown voltage of the N-type source region 41 and ensure the freewheeling ability of the body diode.

[0072] Although the specific implementation manners of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a fast-switching shielded trench-gate silicon carbide VDMOS, characterized in that: The method includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a gate metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer on the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region; Step 3: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 4: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source region; Step 5: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a low-resistance region; Step 6: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, etch the drift layer to form a groove, and deposit to form an insulating dielectric layer; Step 7: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, etch the insulating dielectric layer, deposit to respectively form a first N-type polysilicon layer, a P-type polysilicon layer, and a second N-type polysilicon layer; the polysilicon region includes the first N-type polysilicon layer, the P-type polysilicon layer, and the second N-type polysilicon layer, and then deposit an insulating dielectric; Step 8: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, etch the insulating dielectric layer to form a trench, and deposit metal to form a gate metal layer; Step 9: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the low-resistance region, the P-type well region, the P-type source region, and the N-type source region, deposit metal to form a source metal layer, and remove the blocking layer to complete the preparation.

2. The manufacturing method of a fast-switching shielded trench-gate silicon carbide VDMOS according to claim 1, characterized in that: Specifically, Step 7 is: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, etch the insulating dielectric layer, and deposit to respectively form a first N-type polysilicon layer, a P-type polysilicon layer, and a second N-type polysilicon layer; the polysilicon region includes the first N-type polysilicon layer, the P-type polysilicon layer, and the second N-type polysilicon layer, and then deposit an insulating dielectric.

3. The manufacturing method of a fast-switching shielded trench-gate silicon carbide VDMOS according to claim 2, wherein: The doping concentration of the first N-type polysilicon layer is greater than that of the P-type polysilicon layer, and the doping concentration of the P-type polysilicon layer is greater than that of the second N-type polysilicon layer.

4. The manufacturing method of a fast-switching shielded trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the polysilicon region is greater than or equal to 1e20 cm -3 .

5. The manufacturing method of a fast-switching shielded trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, the drift layer, and the low-resistance region are all N-type.

6. The manufacturing method of a fast-switching shielded trench-gate silicon carbide VDMOS as described in claim 1, wherein: The thickness of the insulating dielectric layer on the side of the polysilicon region is greater than the thickness of the insulating dielectric layer on the side of the gate metal layer.

7. The manufacturing method of a fast-switching shielded trench-gate silicon carbide VDMOS according to claim 1, wherein: The distance between the gate metal layer and the upper side of the polysilicon region is less than the distance between the lower side of the polysilicon region and the bottom surface of the groove.

8. A fast-switching shielded trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method according to any one of claims 1 to 7.

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