RC-IGBT and manufacturing method thereof

Abstract

The embodiment of the invention provides an RC-IGBT and a manufacturing method thereof, and the RC-IGBT comprises an epitaxial layer; the plurality of column regions are arranged in the middle of the epitaxial layer side by side; the gate region and the source region are formed at the upper part of the epitaxial layer; the first collector region and the second collector region are formed in the epitaxial layer and are positioned at the lower part of the epitaxial layer; the first collector region is located in the column region along the center line in the height direction; the second collector regions and the first collector regions are alternately arranged; the distance between the upper surface of the second collector region and the column region is smaller than that between the upper surface of the first collector region and the column region; and a buffer layer formed on the upper surfaces of the first collector region and the second collector region and the side surface of the second collector region. According to the RC-IGBT and the manufacturing method thereof provided by the embodiment of the invention, the problem that the current is too concentrated when the diode is conducted due to the fact that the occupied area of the N-type collector region is too small in the traditional scheme can be solved.

Description

Technical Field

[0001] This application relates to semiconductor technology, and particularly to an RC-IGBT and a manufacturing method thereof. Background Art

[0002] A reverse conducting insulated gate bipolar transistor (Resistor-Capacitor Insulated Gate Bipolar Transistor, hereinafter referred to as RC-IGBT) is based on a conventional insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, hereinafter referred to as IGBT). The back P-type collector region is replaced with an N-type collector region. While maintaining the original IGBT function, it can conduct reversely to act as a diode. In this way, the IGBT and the anti-parallel diode can be integrated on one chip, saving the terminal area, reducing the cost, and increasing the maximum current rating of the package.

[0003] The patent document with the publication number CN107464842A discloses a current RC-IGBT. When a collector trench structure is introduced in the bottom collector region and the new device conducts forwardly and has not entered the bipolar mode, the P-type bar will deplete the N-drift region at the bottom of the collector trench, thus squeezing the electron current path and reducing the effective electron concentration, thereby increasing the distributed resistance of the electron current near the collector region, enabling the new device to eliminate the device snapback effect at a smaller cell size.

[0004] However, in the RC-IGBT provided by this patent document, the N-type collector region is narrow and the P-type collector region is wide. The too small area of the N-type collector region in the cell will cause the current to be too concentrated when the diode conducts, resulting in thermal failure of the device under large current. Summary of the Invention

[0005] To solve one of the above technical defects, an RC-IGBT and a manufacturing method thereof are provided in the embodiments of this application.

[0006] According to the first aspect of the embodiments of this application, an RC-IGBT is provided, including:

[0007] An epitaxial layer, which is of a first conductivity type;

[0008] A column region formed in the epitaxial layer; a plurality of column regions are arranged side by side and spaced apart in the middle of the epitaxial layer, and the column region is of a second conductivity type;

[0009] A gate region formed in the epitaxial layer and located in the upper part of the epitaxial layer;

[0010] A source region formed in the epitaxial layer and located in the upper part of the epitaxial layer, and the source region is located on both sides of the gate region;

[0011] The first collector region is formed within the epitaxial layer and is located at the lower part of the epitaxial layer; the center line of the first collector region in the height direction is located within the column region; the first collector region is of the first conduction type;

[0012] The second collector region is formed within the epitaxial layer and is located at the lower part of the epitaxial layer; the second collector region is of the second conduction type; the second collector region and the first collector region are arranged alternately; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region;

[0013] The buffer layer is formed on the upper surfaces of the first collector region and the second collector region and on the side surface of the second collector region; the buffer layer is of the first conduction type.

[0014] According to the second aspect of the embodiments of the present application, a manufacturing method of an RC-IGBT is provided, including:

[0015] Forming column regions within the epitaxial layer; a plurality of column regions are arranged side by side and spaced apart in the middle of the epitaxial layer, and the column regions are of the second conduction type; the epitaxial layer is of the second conduction type;

[0016] Forming a gate region in the upper part within the epitaxial layer;

[0017] Forming source regions on both sides of the gate region;

[0018] Forming a buffer layer in the lower part within the epitaxial layer;

[0019] Forming the first collector region and the second collector region on the lower surface of the buffer layer, the center line of the first collector region in the height direction is located within the column region; the first collector region is of the first conduction type; the second collector region is of the second conduction type; the second collector region and the first collector region are arranged alternately; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region.

[0020] In the technical solution provided by the embodiment of the present application, a column region of a second conductivity type is formed in an epitaxial layer of a first conductivity type, and a plurality of column regions are arranged side by side and spaced apart in the middle of the epitaxial layer; a gate region is formed in the epitaxial layer and located in the upper part of the epitaxial layer; a source region is formed in the epitaxial layer and located in the upper part of the epitaxial layer, and the source region is located on both sides of the gate region; a first collector region is formed in the epitaxial layer and located in the lower part of the epitaxial layer; the center line of the first collector region is located between two adjacent column regions; the first collector region is of the first conductivity type; a second collector region is formed in the epitaxial layer and located in the lower part of the epitaxial layer; the second collector region is of the second conductivity type; the second collector region and the first collector region are alternately arranged; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region; a buffer layer is formed on the upper surfaces of the first collector region and the second collector region and on the side surface of the second collector region; the buffer layer is of the first conductivity type. When the device is turned on, the electron current can flow laterally from the buffer layer on the surface of the second collector region and flow into the first collector region, which can solve the problem that the current is too concentrated when the diode is turned on due to the too small area occupied by the N-type collector region in the traditional solution, thereby improving the problem of thermal failure of the device under large current. Description of the Drawings

[0021] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0022] Figure 1 is a schematic structural diagram of the RC-IGBT provided by the embodiment of the present application;

[0023] Figure 2 is a flowchart of the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0024] Figure 3 is a schematic structural diagram of forming a column region in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0025] Figure 4 is a schematic structural diagram of re-epitaxially growing silicon in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0026] Figure 5 is a schematic structural diagram of forming a polysilicon gate and a source region in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0027] Figure 6 is a schematic structural diagram of forming a collector region trench in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0028] Figure 7Schematic structural diagram of forming a buffer layer in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0029] Figure 8 Schematic structural diagram of forming a second collector region in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0030] Figure 9 Schematic structural diagram of forming a first collector region in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0031] Figure 10 Schematic structural diagram of forming a collector metal layer in the manufacturing method of the RC-IGBT provided by the embodiment of the present application;

[0032] Figure 11 Schematic structural diagram of filling silicon epitaxy to form a second collector region in the manufacturing method of the RC-IGBT provided by the embodiment of the present application.

[0033] Reference numerals:

[0034] 1 - Metal electrode; 2 - Source region; 3 - Polysilicon gate; 4 - Gate oxide layer; 5 - Contact hole injection region; 6 - Body region; 7 - Column region; 8 - Epitaxial layer; 9 - Buffer layer; 10 - Second collector region; 11 - First collector region; 12 - Collector metal layer; 13 - Collector region trench. Detailed implementation manners

[0035] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further describes the exemplary embodiments of the present application in detail with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0036] As Figure 1 shown, this embodiment provides an RC-IGBT, including: an epitaxial layer 8, and the epitaxial layer 8 is formed by epitaxial growth on a silicon wafer.

[0037] Column regions 7 are formed in the epitaxial layer 8, and a plurality of column regions 7 are arranged side by side and spaced apart in the middle of the epitaxial layer 8.

[0038] The gate region is formed in the epitaxial layer 8 and is located in the upper part of the epitaxial layer 8. The gate region specifically includes: a polysilicon gate 3 and a gate oxide layer 4 located outside the polysilicon gate 3.

[0039] The source regions 2 are formed within the epitaxial layer 8 and are located in the upper part of the epitaxial layer 8. The source regions 2 are located on both sides of the gate region, specifically on both sides of the gate oxide layer 4. Further, a contact hole injection region 5 is also formed between the two source regions 2. The contact hole injection region 5 injects metal to be electrically connected to the source regions 2. A metal electrode 1 is also provided on the upper surfaces of the source regions 2 and the contact hole injection region 5. Further, a body region 6 is also provided in the upper part of the epitaxial layer 8.

[0040] In this embodiment, the epitaxial layer 8 is of the first conduction type, and the pillar region 7 is of the second conduction type. One implementation is: the first conduction type is N-type, and the second conduction type is P-type. Then the epitaxial layer 8 is an N-type epitaxial layer and can be formed on a P-type silicon wafer. The pillar region 7 is a P-type pillar region 7, which can also be referred to as a P pillar or a P-type pillar. The epitaxial layer 8 between adjacent P pillars can also be referred to as an N pillar or an N-type pillar.

[0041] The first collector region 11 is formed within the epitaxial layer 8 and is located in the lower part of the epitaxial layer 8. The center line of the first collector region 11 in the height direction is located within the pillar region 7. The first collector region 11 is of the first conduction type. Based on the above scheme, the first collector region 11 is N-type.

[0042] The second collector region 10 is formed within the epitaxial layer 8 and is located in the lower part of the epitaxial layer 8. The second collector region 10 and the first collector region 11 are alternately arranged, that is: the second collector region 10 is located between two adjacent first collector regions 11. The distance between the upper surface of the second collector region 10 and the pillar region 7 is less than the distance between the upper surface of the first collector region 11 and the pillar region 7. That is to say, the top of the second collector region 10 is higher than the first collector region 11. The second collector region 10 is of the second conduction type. Based on the above scheme, the second collector region 10 is P-type.

[0043] The buffer layer 9 is formed on the upper surfaces of the first collector region 11 and the second collector region 10, and is formed on the side surfaces of the second collector region 10. The buffer layer 9 is of the first conduction type. Based on the above scheme, the buffer layer 9 is N-type.

[0044] An N-type collector region is provided below each P pillar. When the RC-IGBT device conducts single-stage conduction, the electron current can only pass through the drift region from the superjunction N pillar. At this time, electrons basically flow into the N-type first collector region 11 through the buffer layer 9 above the P-type second collector region 10 (as Figure 1 the red arrow), increasing the voltage drop between the P-type second collector region 10 and the N-type buffer layer 9, which is equivalent to broadening the flow area of electrons. And as the current increases, the P-type second collector region 10 and the N-type buffer layer 9 conduct, realizing bipolar conduction, solving the problem that the current is too concentrated when the diode conducts due to the too small area occupied by the N-type collector region in the traditional scheme, thereby improving the problem of thermal failure of the device under large current.

[0045] The technical solution provided in this embodiment forms a column region of a second conductivity type within an epitaxial layer of a first conductivity type. A plurality of column regions are arranged side by side and spaced apart in the middle of the epitaxial layer; a gate region is formed within the epitaxial layer and located in the upper part of the epitaxial layer; a source region is formed within the epitaxial layer and located in the upper part of the epitaxial layer, and the source region is located on both sides of the gate region; a first collector region is formed within the epitaxial layer and located in the lower part of the epitaxial layer; the center line of the first collector region is located between two adjacent column regions; the first collector region is of the first conductivity type; a second collector region is formed within the epitaxial layer and located in the lower part of the epitaxial layer; the second collector region is of the second conductivity type; the second collector region and the first collector region are arranged alternately; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region; a buffer layer is formed on the upper surfaces of the first collector region and the second collector region and on the side surface of the second collector region; the buffer layer is of the first conductivity type. When the device is turned on, the electron current can flow laterally from the buffer layer on the surface of the second collector region and flow into the first collector region, which can solve the problem that the current is too concentrated when the diode is turned on due to the too small area occupied by the N-type collector region in the traditional solution, thereby improving the problem of thermal failure of the device under large current.

[0046] Moreover, the distance between the upper surface of the second collector region 10 and the column region 7 is less than the distance between the upper surface of the first collector region 11 and the column region 7, that is to say, the second collector region 10 is closer to the column region 7. From the perspective of the device, the depth of the second collector region 10 is relatively large, and the path of the single-stage current flowing through the buffer layer 9 can be extended in the height direction (longitudinal direction) of the column region 7. Then, when the single-stage conduction current is small, the voltage drop across the two ends of the P-type second collector region 10 and the N-type buffer layer 9 on the back of the device can turn on the PN junction, thus solving the snapback effect. And the deeper the depth of the P-type second collector region 10, the stronger the suppression of the snapback effect.

[0047] Furthermore, the center line of the first collector region 11 in the height direction coincides with the center line of the column region 7 in the height direction. It is equivalent to that electrons move from the region between the two column regions 7 towards the central position of the second collector region 10 and move along the buffer layer 9 on the surface of the second collector region 10 to the second collector region 11, and the movement path is relatively long, which can further solve the problem of over-concentration of current.

[0048] Based on the above content, further make the lower surface of the first collector region 11 flush with the lower surface of the second collector region 10, which is equivalent to that the thickness of the second collector region 10 is greater than the thickness of the first collector region 11, so that the top of the second collector region 10 is higher than the top of the first collector region 11. Subsequently, the lower surfaces of the first collector region 11 and the second collector region 10 can be planarized, and then the collector metal layer 12 can be fabricated.

[0049] The above-mentioned buffer layer 9 is formed on the upper surfaces of the first collector region 11 and the second collector region 10 and on the side surfaces of the second collector region 10. For two adjacent second collector regions 10, the buffer layer 9 is formed on the right side of the left second collector region 10, and the buffer layer 9 is formed on the left side of the right second collector region 10. When the sum of the thicknesses of the buffer layers 9 on these two side surfaces is greater than or equal to the width of the first collector region 11, the buffer layer 9 fills the area above the first collector region 11. When the sum of the thicknesses of the buffer layers 9 on these two side surfaces is less than the width of the first collector region 11, there is a gap between the buffer layers 9 on these two side surfaces, and this part of the gap belongs to the epitaxial layer 8, that is, the buffer layers 9 on the sides of the second collector region 10 are separated by the epitaxial layer 8. Using the epitaxial layer 8 as a gap separator can form a hole injection channel on the side of the first collector region 11, thereby expanding the hole injection path and eliminating the influence of the introduction of the first collector region 11 on the amount of holes injected into the back surface of the IGBT.

[0050] One implementation is that the width of the first collector region 11 is less than the width of the column region 7, then the width of the second collector region 10 is greater than the width of the first collector region 11. It is equivalent that the center line of the second collector region 10 along the height direction coincides with the center line of the N column along the height direction, and the second collector region 10 extends to the left and right sides and extends to the lower sides of the left and right P columns respectively. Since the width of the second collector region 10 is larger, the area of the buffer layer 9 on the surface of the second collector region 11 is larger, so that the electron current has a longer conduction path.

[0051] One implementation is that the distance between the upper surface of the buffer layer 9 and the lower surface of the column region 7 is 3 μm - 5 μm. For example: the thickness of the first collector region 11 is 0.2 μm to 0.5 μm, and the width of the first collector region 11 is 2 μm to 4 μm; the thickness of the second collector region 10 is 5 μm to 10 μm, and the width of the second collector region 10 is 7 μm to 9 μm; the thickness of the buffer layer 9 located on the upper surface of the first collector region 11 or the second collector region 10 is 1.5 μm to 4 μm, and the thickness of the buffer layer 9 located on the side surface of the second collector region 10 is 0.5 μm to 1.5 μm.

[0052] Based on the above technical solution, this embodiment further provides a manufacturing method of an RC-IGBT for manufacturing the above-mentioned RC-IGBT. The following content will still be described with the first conduction type being N-type and the second conduction type being P-type. This method is fabricated on a wafer, and multiple devices can be fabricated on the wafer at one time. As Figure 2 shown, the manufacturing method provided in this embodiment includes:

[0053] Step 101, forming column regions in the epitaxial layer; a plurality of column regions are arranged side by side and spaced apart in the middle of the epitaxial layer, and the column regions are of the second conduction type; the epitaxial layer is of the second conduction type.

[0054] First, fabricate on the front side of the wafer: In this step, an N-type epitaxial layer 8 can be formed on a P-type substrate. Then, avoid using a mask to etch deep trenches on the epitaxial layer 8, and then grow a sacrificial oxide layer in the deep trenches. After that, remove the sacrificial oxide layer to remove the interface defects on the sidewalls and bottom of the deep trenches.

[0055] Next, fill the deep trenches with P-type doped silicon, and then etch back to the surface of the epitaxial layer 8 to make the P-type column region 7 flush with the surface of the epitaxial layer 8, as Figure 3 shown.

[0056] Next, epitaxially grow N-type silicon on the upper surfaces of the epitaxial layer 8 and the column region 7, as Figure 4 shown. The region formed by epitaxially growing N-type silicon is also part of the epitaxial layer 8, which is equivalent to the column region 7 being located in the middle region of the epitaxial layer 8.

[0057] Step 102: Form a gate region in the upper part of the epitaxial layer.

[0058] Step 103: Form source regions on both sides of the gate region.

[0059] The above steps 102 and 103 can be specifically implemented by using the existing technologies of IGBT devices. For example: First, use a terminal ring mask to shield the cell region, then implant into the terminal region to form a terminal ring and anneal. Then use a mask to shield the terminal region and form a gate region, source regions, etc. in the cell region.

[0060] Specifically, use a mask to etch a gate region trench in the epitaxial layer 8 of the cell region, grow a sacrificial oxide layer in the trench and then remove it, and then grow a gate oxide layer 4 on the bottom wall and sidewalls of the trench.

[0061] Then fill the trench with polysilicon and etch back to the surface of the epitaxial layer 8 to form a polysilicon gate 3.

[0062] Then use a mask to form a body region 6 and source regions 2 in the epitaxial layer 8 of the cell region successively, as Figure 5 shown.

[0063] Deposit an insulating isolation layer on the surface of the epitaxial layer 8 and perform high-temperature reflow.

[0064] Etch on the isolation layer and implant P-type highly doped impurity arsenic, and anneal to form contact holes.

[0065] After that, deposit metal in the contact holes and on the surface of the epitaxial layer, and then etch to form metal electrodes 1, as Figure 1 shown.

[0066] Deposit a passivation layer on the surface of the metal electrodes 1.

[0067] Next, turn the wafer over and perform a thinning process, for example, by mechanical grinding, to thin the bottom of the epitaxial layer 8.

[0068] Step 104: Form a buffer layer in the lower part within the epitaxial layer.

[0069] Specifically, this step is as follows: Use a mask to etch a collector region trench 13 on the back surface of the wafer, that is, etch upward from the lower surface of the epitaxial layer 8 to form the collector region trench 13. The position of the collector region trench 13 is used to form the second collector region 10, as Figure 6 shown.

[0070] Then, inject to form the buffer layer 9 on the lower surface of the epitaxial layer 8. The buffer layer 9 is distributed within the epitaxial layer 8 above the collector region trench 13 and within the epitaxial layer 8 between adjacent collector region trenches 13, as Figure 7 shown.

[0071] Step 105: Form a first collector region and a second collector region on the lower surface of the buffer layer. The center line of the first collector region in the height direction is located within the column region; the first collector region is of the first conductivity type; the second collector region is of the second conductivity type; the second collector regions and the first collector regions are arranged alternately; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region.

[0072] Fill the collector region trench 13 with P-type silicon to form the second collector region 10, as Figure 8 shown.

[0073] Use a mask to inject on the lower surface of the epitaxial layer 8 between adjacent collector region trenches 13 to form an N-type first collector region 11, as Figure 9 shown. After that, it is also possible to fill again below the previously formed second collector region 10 so that the lower surfaces of the second collector region 10 and the first collector region 11 are flush. The center line of the first collector region 11 in the height direction passes through the column region 7.

[0074] After that, use a backside metal process to form a collector metal layer 12 on the lower surfaces of the second collector region 10 and the first collector region 11, as Figure 10 shown. The material of the collector metal layer 12 can be Al, Ti, NiV, Ag.

[0075] In the above solution, the P-type second collector region 10 can be formed by metal filling deposition, as Figures 8 to 10 . Or it can also be formed by P-type silicon epitaxial filling, as Figure 11 shown.

[0076] In the above solution, the width of the first collector region 10 is less than the width of the column region 7; the width of the second collector region 11 is greater than the width of the first collector region 10. Since the width of the second collector region 11 is larger, the area of the buffer layer 9 on the surface of the second collector region 11 is larger, so that the electron current has a longer conduction path.

[0077] During the implementation of the above manufacturing method, the distance between the upper surface of the buffer layer 9 and the lower surface of the column region 7 is 3 μm - 5 μm. For example: the thickness of the first collector region 11 is 0.2 μm - 0.5 μm, and the width of the first collector region 11 is 2 μm - 4 μm; the thickness of the second collector region 10 is 5 μm - 10 μm, and the width of the second collector region 10 is 7 μm - 9 μm; the thickness of the buffer layer 9 on the upper surface of the first collector region 11 or the second collector region 10 is 1.5 μm - 4 μm, and the thickness of the buffer layer 9 on the side surface of the second collector region 10 is 0.5 μm - 1.5 μm.

[0078] In the above solution, due to the relative position of the P-type column region 7 and the N-type first collector region 11 being on a vertical line, when unipolar conduction occurs, the path of the electron current in the epitaxial layer 8 is restricted to the N-type epitaxial region 8. When reaching the buffer layer 9, it is mainly above the P-type second collector region 10, increasing the voltage drop across the PN junction formed by the second collector region 10 and the buffer layer 9, enabling it to conduct faster.

[0079] Moreover, the collector trench on the back surface of the device extends the length of the buffer zone 9 and the area of the back collector region longitudinally, jointly achieving the suppression of the snapback effect of the RC-IGBT. At the same time, in this solution, the N-type first collector region 11 is evenly distributed in the device and will not cause a current concentration effect during the conduction of the diode, resulting in thermal failure of the device.

[0080] The process provided in this embodiment is simpler. The back surface of the device is only a collector region, just like a normal IGBT structure, making it easier to implement, capable of simplifying the process complexity, and thus improving production efficiency.

[0081] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to this application.

[0082] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0083] In this application, unless otherwise clearly stipulated and defined, terms such as "installed", "connected", "linked", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or capable of communicating with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal connection of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0084] Although the preferred embodiments of this application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of this application.

[0085] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. An RC-IGBT, characterized in that, Comprising: An epitaxial layer of a first conductivity type. Column regions formed within the epitaxial layer; multiple column regions are arranged side by side and spaced apart in the middle of the epitaxial layer, and the column regions are of a second conductivity type. A gate region formed within the epitaxial layer and located at the upper part of the epitaxial layer. Source regions formed within the epitaxial layer and located at the upper part of the epitaxial layer, and the source regions are located on both sides of the gate region. A first collector region formed within the epitaxial layer and located at the lower part of the epitaxial layer; the center line of the first collector region in the height direction is located within the column region; the first collector region is of the first conductivity type. A second collector region formed within the epitaxial layer and located at the lower part of the epitaxial layer; the second collector region is of the second conductivity type; the second collector region and the first collector region are alternately arranged; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region. A buffer layer formed on the upper surfaces of the first collector region and the second collector region and on the side surfaces of the second collector region; the buffer layer is of the first conductivity type.

2. The RC-IGBT according to claim 1, wherein The buffer layers located on the side surfaces of the second collector region are separated by the epitaxial layer.

3. The RC-IGBT according to claim 1, characterized in that, The center line of the first collector region in the height direction coincides with the center line of the column region in the height direction.

4. The RC-IGBT according to claim 1, wherein The lower surface of the first collector region is flush with the lower surface of the second collector region.

5. The RC-IGBT according to claim 1, wherein The first conductivity type is N-type and the second conductivity type is P-type.

6. The RC-IGBT according to claim 1, characterized in that, The distance between the buffer layer and the column region is 3 μm - 5 μm.

7. A manufacturing method of an RC-IGBT, characterized in that, Comprising: Forming column regions within the epitaxial layer; multiple column regions are arranged side by side and spaced apart in the middle of the epitaxial layer, and the column regions are of the second conductivity type; the epitaxial layer is of the second conductivity type. Forming a gate region at the upper part within the epitaxial layer. Forming source regions on both sides of the gate region. Forming a buffer layer at the lower part within the epitaxial layer. Forming a first collector region and a second collector region on the lower surface of the buffer layer, the center line of the first collector region in the height direction is located within the column region; the first collector region is of the first conductivity type; the second collector region is of the second conductivity type; the second collector region and the first collector region are alternately arranged; the distance between the upper surface of the second collector region and the column region is less than the distance between the upper surface of the first collector region and the column region.

8. The manufacturing method according to claim 7, characterized in that Forming a buffer layer at the lower part within the epitaxial layer, including: Forming a plurality of collector trenches upward from the lower surface of the epitaxial layer. Injecting into the lower surface of the epitaxial layer to form a buffer layer, and the buffer layer is distributed in the epitaxial layer above the collector trenches and in the epitaxial layer between adjacent collector trenches. Forming a first collector region and a second collector region on the lower surface of the buffer layer, including: Filling the collector trenches to form the second collector region. Forming the first collector region on the lower surface of the epitaxial layer between adjacent collector trenches.

9. The manufacturing method according to claim 8, wherein, The lower surface of the first collector region is flush with the lower surface of the second collector region.

10. The manufacturing method according to claim 7, characterized in that, The center line of the first collector region in the height direction coincides with the center line of the column region in the height direction.

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