Manufacturing method of integrated passive device and integrated passive device
By integrating resistors and MIM capacitors on the same side of the substrate and forming connection holes through one etching, the problem of high process cost of integrated passive devices is solved, and more efficient resistance and capacitor integration is achieved, reducing process costs and improving accuracy.
Patent Information
- Application Number
- CN202311869438.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-08
AI Technical Summary
The existing integrated passive devices have high process costs, mainly due to the complex integration methods of resistors and capacitors, resulting in increased process steps.
Set the resistor and MIM capacitor on the same side of the substrate, and form the connection holes that expose the resistor and the connection holes that expose the MIM capacitor by etching one time, simplifying the process flow and reducing process steps.
It reduces process costs, improves the accuracy of resistance and the accuracy of resistance values, and simplifies the processing process flow.
Smart Images
Figure CN120282525A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to a manufacturing method and an integrated passive device for integrated passive devices. Background Art
[0002] Integrated passive devices (IPDs) are currently widely used in microwave radio frequency circuits and their products due to their superior characteristics of independent passive components. Among them, integrated passive devices mainly include resistors, inductors, capacitors, etc., and resistors play an extremely important role in adjusting the filtering signal of the filter and the quality factor (Q value) of the filter. Therefore, how to integrate resistors into the entire filtering circuit at low cost has gradually become a hot topic of concern.
[0003] However, the method of integrating resistors and capacitors in related technologies is relatively complex, resulting in a high process cost for integrated passive devices. Summary of the Invention
[0004] The problem solved by the present invention is the problem of high process cost of existing integrated passive devices.
[0005] To solve the above problems, the present invention provides a manufacturing method for an integrated passive device, and the manufacturing method includes:
[0006] Providing a substrate and a MIM capacitor, the MIM capacitor being located on one side of the substrate;
[0007] Setting a resistor on the substrate, the resistor and the MIM capacitor being located on the same side of the substrate;
[0008] Setting a first dielectric layer on the substrate, the first dielectric layer covering the resistor and the MIM capacitor;
[0009] Etching the first dielectric layer to form a first connection hole exposing the resistor and a second connection hole exposing the MIM capacitor.
[0010] By setting the resistor and the MIM (Metal-Insulator-Metal) capacitor on the same side of the substrate, and setting the first dielectric layer to cover the resistor and the MIM capacitor, and etching the first dielectric layer once to obtain both the first connection hole exposing the resistor and the second connection hole exposing the MIM capacitor at the same time, compared with the related technology where the resistor is designed before the capacitor process and a separate connection hole for the resistor needs to be etched, the present application reduces the process steps and lowers the process cost.
[0011] Optionally, the MIM capacitor includes: an upper electrode, an insulating dielectric layer, and a lower electrode stacked from top to bottom;
[0012] In the direction perpendicular to the substrate, the positive projection of the upper electrode is located within the positive projections of the insulating dielectric layer and the lower electrode;
[0013] The upper electrode includes a first metal layer and a second metal layer arranged in a stacked manner;
[0014] The lower electrode includes a third metal layer and a fourth metal layer arranged in a stacked manner.
[0015] Optionally, the upper surface of the resistor away from the substrate is substantially flush with the upper surface of the fourth metal layer away from the substrate.
[0016] By setting the upper surface of the resistor away from the substrate to be substantially flush with the upper surface of the fourth metal layer away from the substrate, it can be ensured that the resistor and the first metal layer are etched approximately simultaneously, and it can also be ensured that the resistor and the fourth metal layer are not etched through.
[0017] Optionally, a barrier layer is further provided on the MIM capacitor, and the thickness of the barrier layer is greater than or equal to the thickness of the third metal layer.
[0018] By providing a barrier layer with a thickness greater than or equal to the thickness of the third metal layer on the MIM capacitor, it can be ensured that the first metal layer and the fourth metal layer are exposed in the same etching, and it can also be ensured that the first metal layer is not over-etched.
[0019] Optionally, forming the second connection hole exposing the MIM capacitor includes:
[0020] Etching the first dielectric layer and the barrier layer to form a first sub-connection hole exposing the first metal layer;
[0021] Etching the first dielectric layer, the insulating dielectric layer, and the third metal layer to form a second sub-connection hole exposing the fourth metal layer.
[0022] By etching the first dielectric layer and the barrier layer, as well as the first dielectric layer, the insulating dielectric layer, and the third metal layer at one time, the first sub-connection hole and the second sub-connection hole can be obtained. Compared with the related art where the first dielectric layer and the MIM capacitor need to be etched separately to obtain the first sub-connection hole and the second sub-connection hole, the present application reduces the process steps and lowers the process cost.
[0023] Optionally, the depth of the first connection hole is substantially equal to the depth of the second sub-connection hole.
[0024] The depths of the first connection hole and the second sub-connection hole obtained by etching are equal, effectively avoiding the process window of the connection hole and greatly ensuring the high-precision resistor pattern and the accuracy of the resistor resistance value.
[0025] Optionally, the material of the first metal layer includes at least one of Au, Al, Cu, and Pt;
[0026] The material of the second metal layer includes at least one of TiN, TaN, and Ni;
[0027] The material of the third metal layer is the same as that of the second metal layer, and the material of the fourth metal layer is the same as that of the first metal layer;
[0028] The material of the insulating dielectric layer includes at least one of SiN, SiO2, and Ta2O5.
[0029] Optionally, the material of the barrier layer includes at least one of TiN, TaN, and Ni.
[0030] Optionally, providing a resistor on the substrate includes:
[0031] Providing a resistor material layer on the side of the substrate where the MIM capacitor is provided to cover the substrate and the MIM capacitor;
[0032] Patterning the resistor material layer by at least one of dry etching, wet etching, or Lift-off process to form a resistor.
[0033] This application also provides an integrated passive device, including:
[0034] A substrate;
[0035] A MIM capacitor located on one side of the substrate;
[0036] A resistor located on the same side of the substrate as the MIM capacitor;
[0037] A first dielectric layer provided on the side of the resistor and the MIM capacitor away from the substrate to cover the resistor and the MIM capacitor.
[0038] Optionally, the MIM capacitor includes a top electrode, an insulating dielectric layer, and a bottom electrode stacked from top to bottom;
[0039] In the direction perpendicular to the substrate, the orthographic projection of the top electrode is located within the orthographic projections of the insulating dielectric layer and the bottom electrode;
[0040] The top electrode includes a first metal layer and a second metal layer stacked;
[0041] The bottom electrode includes a third metal layer and a fourth metal layer stacked.
[0042] Optionally, the upper surface of the resistor away from the substrate is substantially flush with the upper surface of the fourth metal layer away from the substrate.
[0043] By setting the upper surface of the resistor away from the substrate to be substantially flush with the upper surface of the fourth metal layer away from the substrate, the resistor and the MIM capacitor can be etched approximately simultaneously to obtain connection holes on the resistor and the MIM capacitor, reducing the process difficulty of etching the connection holes and also reducing the process flow.
[0044] Optionally, it further includes:
[0045] A barrier layer, which is located on the MIM capacitor, and the thickness of the barrier layer is greater than or equal to the thickness of the third metal layer.
[0046] By setting the thickness of the barrier layer to be greater than or equal to the thickness of the third metal layer, over-etching of the first metal layer can be prevented.
[0047] Optionally, it further includes:
[0048] A first connection hole that penetrates the first dielectric layer to expose the surface of the resistor;
[0049] A second connection hole that penetrates the first dielectric layer and part of the MIM capacitor to expose the MIM capacitor.
[0050] Forming the first connection hole and the second connection hole in the same etching step reduces the process steps and the process cost.
[0051] Optionally, the second connection hole includes:
[0052] A first sub-connection hole that penetrates the first dielectric layer and the barrier layer to expose the surface of the first metal layer;
[0053] A second sub-connection hole that penetrates the first dielectric layer, the insulating dielectric layer, and the third metal layer to expose the surface of the fourth metal layer;
[0054] Wherein, the depth of the first connection hole is approximately equal to the depth of the second sub-connection hole.
[0055] By setting the depths of the first connection hole and the second sub-connection hole to be equal, the process window of the connection hole is effectively avoided, and a high accuracy of the resistor is greatly ensured.
[0056] Optionally, the material of the first metal layer includes at least one of Au, Al, Cu, and Pt;
[0057] The material of the second metal layer includes at least one of TiN, TaN, and Ni;
[0058] The third metal layer has the same material as the second metal layer, and the fourth metal layer has the same material as the first metal layer;
[0059] The material of the insulating dielectric layer includes at least one of SiN, SiO2, and Ta2O5.
[0060] Optionally, the material of the barrier layer includes at least one of TiN, TaN, and Ni.
[0061] The manufacturing method of the integrated passive device provided by this application sets the resistor and the MIM capacitor on the same side of the substrate, and sets the first dielectric layer to cover the resistor and the MIM capacitor. When etching the first dielectric layer, the first connection hole exposing the resistor and the second connection hole exposing the MIM capacitor are obtained simultaneously. Compared with the related technology where the resistor is designed before the capacitor process and the connection hole of the resistor needs to be etched separately, this application reduces the process steps and lowers the process cost. Description of the Drawings
[0062] Figure 1 It is a schematic structural diagram of the integrated passive device provided by the embodiment of this application;
[0063] Figure 2 is Figure 1 a schematic structural diagram of the MIM capacitor and the substrate in the shown integrated passive device.
[0064] Figure 3 It is a schematic flowchart of the manufacturing method of the integrated passive device provided by the embodiment of this application;
[0065] Figure 4 is Figure 3 a schematic flowchart of setting the resistor in the shown manufacturing method;
[0066] Figure 5 is Figure 3 a schematic flowchart of manufacturing the second connection hole in the shown manufacturing method;
[0067] Figure 6 is Figure 3 a process schematic diagram corresponding to the manufacturing method of the shown integrated passive device;
[0068] Description of the Reference Numerals:
[0069] 100 - Integrated passive device, 10 - MIM capacitor, 20 - Substrate, 30 - Resistor, 40 - First dielectric layer, 50 - Second dielectric layer, 60 - First connection hole, 70 - Second connection hole, 80 - Barrier layer;
[0070] 101 - Upper electrode, 102 - Insulating dielectric layer, 103 - Lower electrode;
[0071] 1011 - First metal layer, 1012 - Second metal layer;
[0072] 1031 - Third metal layer, 1032 - Fourth metal layer;
[0073] 701 - First sub - connection hole, 702 - Second sub - connection hole, 301 - Resistor material layer, 302 - Photoresist layer. Detailed Embodiments
[0074] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following will provide a detailed description of specific embodiments of the present invention.
[0075] As described in the background art, when integrating a resistor and a capacitor, to ensure the resistor pattern with high accuracy and the accuracy of the resistor value, in the related art, an etching process needs to be performed separately for the resistor, which results in more process steps for forming the resistor in the related art, thereby making the method of integrating the resistor and the capacitor complex and having a high process cost.
[0076] Therefore, the present application provides a manufacturing method and an integrated passive device for an integrated passive device to solve the above technical problems. Specifically, refer to the following.
[0077] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an integrated passive device provided by an embodiment of the present application. An embodiment of the present application provides an integrated passive device 100, which includes a substrate 20, a MIM capacitor 10, a resistor 30, and a first dielectric layer 40. Among them, the MIM capacitor 10 is located on one side of the substrate 20. The resistor 30 and the MIM capacitor 10 are located on the same side of the substrate 20. The first dielectric layer 40 is disposed on the side of the resistor 30 and the MIM capacitor 10 away from the substrate 20 to cover the resistor 30 and the MIM capacitor 10.
[0078] Among them, the upper surface of the first dielectric layer 40 away from the substrate 20 is a planarized surface, which is beneficial for subsequent etching of the first dielectric layer 40 to form connection holes, and can also avoid affecting the subsequent Photo process due to the rough upper surface and poor flatness of the first dielectric layer 40.
[0079] Please continue to refer to Figure 2 , Figure 2 which is a schematic structural diagram of the MIM capacitor and the substrate in the integrated passive device shown in Figure 1 . In some embodiments, the MIM capacitor 10 includes an upper electrode 101, an insulating dielectric layer 102, and a lower electrode 103 that are stacked from top to bottom. In the direction perpendicular to the substrate, the orthographic projection of the upper electrode 101 is located within the orthographic projections of the insulating dielectric layer 102 and the lower electrode 103. Among them, the upper electrode 101 includes a first metal layer 1011 and a second metal layer 1012 that are stacked, and the lower electrode 103 includes a third metal layer 1031 and a fourth metal layer 1032 that are stacked. The fourth metal layer 1032 is disposed on one side of the substrate 20, and the third metal layer 1031 is disposed on the side of the fourth metal layer 1032 away from the substrate 20.
[0080] Among them, the substrate uses a high-resistance Si substrate.
[0081] The material of the first metal layer 1011 includes at least one of Au, Al, Cu, and Pt. It can be understood that the first metal layer is used for external connection of wires, and the specific material of the first metal layer 1011 can be selected according to the actual situation, and a metal with a lower resistivity can be chosen, and no specific limitation is made here.
[0082] The thickness of the first metal layer only needs to ensure that it will not be over-etched during manufacturing, and no specific limitation is made here.
[0083] The material of the second metal layer 1012 includes at least one of TiN, TaN, and Ni. It can be understood that the specific material of the second metal layer 1012 can be selected according to the actual situation, and a metal with a resistivity higher than that of the first metal layer can be chosen, and no specific limitation is made here.
[0084] The material of the third metal layer 1031 includes at least one of TiN, TaN, and Ni. It can be understood that the specific material of the third metal layer 1031 can be selected according to the actual situation, and a metal with a resistivity higher than that of the first metal layer can be chosen, and no specific limitation is made here.
[0085] The material of the fourth metal layer 1032 includes at least one of Au, Al, Cu, and Pt. It can be understood that the fourth metal layer is used for external connection of wires, and the specific material of the fourth metal layer 1032 can be selected according to the actual situation, and a metal with a lower resistivity can be chosen, and no specific limitation is made here.
[0086] The thickness of the fourth metal layer only needs to ensure that it will not be over-etched during manufacturing, and no specific limitation is made here.
[0087] In some embodiments, the material of the third metal layer 1031 is the same as that of the second metal layer 1012, and the material of the fourth metal layer 1032 is the same as that of the first metal layer 1011.
[0088] The material of the insulating dielectric layer 102 includes at least one of High-K (high dielectric constant) materials such as SiN, SiO2, and Ta2O5. It can be understood that the specific material of the insulating dielectric layer 102 can be selected according to the actual situation, and no specific limitation is made here.
[0089] The resistance material includes TiN, TaN, AL, Cu, etc., and can be specifically selected according to the required resistance value, and no specific limitation is made here.
[0090] In some embodiments, the upper surface of the resistor 30 away from the substrate 20 is substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20, so that the resistor 30 and the MIM capacitor 10 can be etched approximately simultaneously to obtain the connection holes on the resistor 30 and the MIM capacitor 10, reducing the process difficulty of etching the connection holes and also reducing the process flow.
[0091] In some embodiments, the integrated passive device 100 further includes a barrier layer 80, which is located on the MIM capacitor. Exemplarily, the barrier layer 80 is disposed on the side of the first metal layer 1011 away from the second metal layer 1012. By providing the barrier layer 80 on the first metal layer 1011, the situation where the first metal layer 1011 is over-etched and causes the MIM capacitor 10 to fail can be prevented.
[0092] In some embodiments, the thickness of the barrier layer 80 is greater than or equal to the thickness of the third metal layer 1031. By setting the thickness of the barrier layer 80 to be greater than or equal to the thickness of the third metal layer 1031, the upper electrode 101 and the lower electrode 103 can be etched approximately simultaneously, without the need to etch the upper electrode 101 and the lower electrode 103 separately, reducing the processing process and improving the processing efficiency. Moreover, during the etching of the upper electrode 101 and the lower electrode 103, it is ensured that the first metal layer 1011 is not over-etched, thereby ensuring the functionality of the MIM capacitor 10.
[0093] Among them, the material of the barrier layer 80 includes at least one of TiN, TaN, and Ni. It can be understood that the specific material of the barrier layer 80 can be selected according to the actual situation, and no specific limitation is made here.
[0094] In some embodiments, the integrated passive device 100 further includes a first connection hole 60 and a second connection hole 70. The first connection hole 60 penetrates through the first dielectric layer 40 to expose the surface of the resistor 30, and the second connection hole 70 penetrates through the first dielectric layer 40 and a part of the MIM capacitor 10 to expose the MIM capacitor 10. In the integrated passive device 100 provided by the embodiments of the present application, after integrating the resistor 30 and the MIM capacitor 10, the first connection hole 60 and the second connection hole 70 are obtained through the same etching. Compared with the related art where the resistor 30 is designed before the capacitor process and the connection hole of the resistor 30 needs to be etched separately, the present application not only ensures the function of the integrated passive device 100, but also simplifies the processing process flow and saves costs.
[0095] Please refer to again Figure 1 , the second connection hole 70 includes a first sub-connection hole 701 and a second sub-connection hole 702. The first sub-connection hole 701 penetrates through the first dielectric layer 40 and the barrier layer 80 to expose the surface of the first metal layer 1011, and the second sub-connection hole 702 penetrates through the first dielectric layer 40, the insulating dielectric layer 102, and the third metal layer 1031 to expose the surface of the fourth metal layer 1032. Among them, the depth of the first connection hole 60 and the depth of the second sub-connection hole 702 are approximately equal, and the depth of the second sub-connection hole 702 is greater than the depth of the first sub-connection hole 701. By setting the depth of the first connection hole 60 and the depth of the second sub-connection hole 702 to be approximately equal, the process window of the connection hole is effectively avoided, and a high accuracy of the resistor 30 is greatly ensured.
[0096] It should be noted that the depth of the first connection hole 60 being approximately equal to the depth of the second sub-connection hole 702 can be understood as the difference between the depth of the first connection hole 60 and the depth of the second sub-connection hole 702 being less than or equal to a preset height difference. It should be noted that the specific numerical range of the preset height difference can be set according to the actual process flow and actual process accuracy, and no specific limitation is made here.
[0097] In some embodiments, the integrated passive device 100 further includes a second dielectric layer 50, and the second dielectric layer 50 is disposed between the substrate 20 and the resistor 30, so that the upper surface of the resistor 30 away from the substrate 20 is substantially flush with the upper surface of the first metal layer 1011 away from the substrate 20. By making the upper surface of the resistor 30 away from the substrate 20 substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20, the depth of the first connection hole 60 and the etching depth of the second sub-connection hole 702 are made approximately equal, and at the same time, it is ensured that the first metal layer 1011 and the fourth metal layer 1032 are not over-etched.
[0098] It should be noted that the upper surface of the resistor 30 away from the substrate 20 being substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20 can be understood as the distance difference between the distance from the upper surface of the resistor 30 away from the substrate 20 to the substrate 20 and the distance from the upper surface of the fourth metal layer 1032 away from the substrate 20 to the substrate 20 being less than or equal to a preset value. Wherein, the specific size of the preset value can be set according to the actual process and actual accuracy, and no specific limitation is made here, as long as the depth of the first connection hole 60 and the etching depth of the second sub-connection hole 702 are approximately equal.
[0099] Please refer to Figure 3 , Figure 3 which is a schematic flow chart of the manufacturing method of the integrated passive device provided by the embodiment of the present application. The embodiment of the present application also provides a manufacturing method of an integrated passive device 100, and this manufacturing method includes the following processes:
[0100] 110. Provide a substrate and a MIM capacitor, and the MIM capacitor is located on one side of the substrate.
[0101] In some embodiments, providing the substrate 20 and the MIM capacitor 10 can be that after the substrate 20 and the MIM capacitor 10 are separately manufactured, the MIM capacitor 10 is disposed on one side of the substrate 20. In some embodiments, providing the substrate 20 and the MIM capacitor 10 can be that a lower electrode 103, an insulating dielectric layer 102, and an upper electrode 101 are sequentially disposed on one side of the substrate 20 to form the MIM capacitor 10 on one side of the substrate 20. It can be understood that the specific acquisition of the substrate 20 and the MIM capacitor 10 can be set according to the actual situation, and no specific limitation is made here.
[0102] In some embodiments, a high-resistance Si substrate is adopted as the substrate to provide a process platform for forming integrated passive devices.
[0103] The MIM capacitor 10 includes a top electrode 101, an insulating dielectric layer 102, and a bottom electrode 103 that are stacked from top to bottom; in the direction perpendicular to the substrate 20, the orthographic projection of the top electrode 101 is located within the orthographic projections of the insulating dielectric layer 102 and the bottom electrode 103, and the top electrode 101 includes a first metal layer 1011 and a second metal layer 1012 that are stacked; the bottom electrode 103 includes a third metal layer 1031 and a fourth metal layer 1032 that are stacked.
[0104] The material of the first metal layer 1011 includes at least one of Au, Al, Cu, and Pt. The material of the second metal layer 1012 includes at least one of TiN, TaN, and Ni. The material of the third metal layer 1031 includes at least one of TiN, TaN, and Ni. The material of the fourth metal layer 1032 includes at least one of Au, Al, Cu, and Pt. Among them, the specific materials of the first metal layer 1011, the second metal layer 1012, the third metal layer 1031, and the fourth metal layer 1032 can be set according to actual situations and are not specifically limited herein.
[0105] In some embodiments, the manufacturing method further includes providing a barrier layer 80 on the MIM capacitor 10, and the thickness of the barrier layer 80 is greater than or equal to the thickness of the third metal layer 1031. In the present application, by providing a barrier layer 80 on the side of the first metal layer 1011 away from the second metal layer 1012, it not only ensures the process of forming multiple connection holes through one photomask in subsequent processes, but also avoids the situation that the first metal layer 1011 is etched through or damaged due to over-etching when setting multiple connection holes, thereby simplifying the process steps and reducing or avoiding the damage of the MIM capacitor 10.
[0106] In some embodiments, the material of the barrier layer 80 may include at least one of High-K materials such as SiN, SiO2, and Ta2O5. It can be understood that, due to the large difference in the etching selectivity ratio between the material of the barrier layer 80 and the material of the first metal layer 1011, it can effectively prevent the etching plasma from damaging the first metal layer 1011.
[0107] It can be understood that, since the distance from the upper surface of the first metal layer 1011 far from the second metal layer 1012 to the planarized surface of the first dielectric layer 40 is less than the distance from the upper surface of the fourth metal layer 1032 close to the third metal layer 1031 to the planarized surface of the first dielectric layer 40, when the upper electrode 101 and the lower electrode 103 are etched approximately simultaneously, the first metal layer 1011 in the upper electrode 101 may be damaged by etching. To avoid this situation, a barrier layer 80 is provided in the upper electrode 101 in the embodiments of the present application. Also, since the third metal layer 1031 is also etched when the lower electrode 103 is etched, and the etching rate of the barrier layer 80 is the same as that of the third metal layer 1031, and the etching rate of the first dielectric layer 40 is greater than the etching rate of the barrier layer 80, the embodiments of the present application ensure that the first metal layer 1011 is not over-etched during etching by setting the thickness of the barrier layer 80 to be greater than or equal to the thickness of the third metal layer 1031.
[0108] It can be understood that, since the material of the barrier layer 80 is different from that of the first dielectric layer 40, and the etching rate of the barrier layer 80 is slower than that of the first dielectric layer 40, to avoid the situation where the upper electrode 101 is not etched and exposed after the fourth metal layer 1032 is etched and exposed due to the too thick thickness of the barrier layer 80, the thickness difference between the thickness of the barrier layer 80 and the thickness of the third metal layer 1031 cannot be too large. Among them, the specific range of the thickness difference between the thickness of the barrier layer 80 and the thickness of the third metal layer 1031 can be set according to experimental data, historical data or simulation data, and no specific limitation is made here, as long as the first metal layer 1011 and the fourth metal layer 1032 can be exposed after the same etching, and the first metal layer 1011 and the fourth metal layer 1032 are not over-etched.
[0109] In some embodiments, the barrier layer 80 can be obtained simultaneously when the MIM capacitor 10 is obtained. Exemplarily, the upper electrode 101 and the barrier layer 80 can be formed first, and then the insulating dielectric layer 102 and the lower electrode 103 are formed.
[0110] For example, after the first photomask is etched and etched, the upper electrode 101 and the barrier layer 80 of the MIM capacitor 10 are formed. Among them, this step can complete the patterning of 3 metal thin films at one time on a metal etching machine tool, without performing multiple etching steps to obtain the upper electrode 101 and the barrier layer 80, thereby simplifying the process steps.
[0111] In addition, after the second photomask is etched and etched, the insulating dielectric layer 102 and the lower electrode 103 of the MIM capacitor 10 are formed. Exemplarily, in some embodiments, the first photomask first patterns the insulating dielectric layer 102 on a dielectric etcher, and then without performing the photoresist removal step, directly enters a metal etcher to pattern the lower electrode 103. It can be understood that, in some embodiments, the insulating dielectric layer 102 and the lower electrode 103 can also be patterned at one time on a metal etcher to simplify the processing process flow. Among them, the specific manner of patterning the insulating dielectric layer 102 and the lower electrode 103 can be selected according to the debugging of the etching process, and no specific limitation is made here. By etching the first photomask and the second photomask and then obtaining the MIM capacitor 10 and the barrier layer 80, compared with the related art of manufacturing the MIM capacitor 10, the manufacturing method of the MIM capacitor 10 provided in this application is simpler, reduces the process flow, and reduces the process cost. Moreover, the situation of damage to the MIM capacitor 10 is effectively prevented by providing the barrier layer 80 in the upper electrode 101.
[0112] 120. A resistor is disposed on the substrate, and the resistor and the MIM capacitor are on the same side of the substrate.
[0113] A resistor 30 is disposed on one side of the substrate 20, and the MIM capacitor 10 and the resistor 30 are on the same side of the substrate 20.
[0114] In some embodiments, for the specific steps of setting the resistor 30, reference can be made to Figure 4 , Figure 4 is Figure 3 the schematic flow chart of setting the resistor in the manufacturing method shown. The specific process is as follows:
[0115] 121. A resistor material layer is disposed on the side of the substrate where the MIM capacitor is disposed to cover the substrate and the MIM capacitor.
[0116] On the side of the substrate 20 where the MIM capacitor 10 is disposed, a resistor material is deposited by a sputtering process so that the resistor material layer 301 covers the substrate 20 and the MIM capacitor 10.
[0117] In some embodiments, the resistor material may include TiN, TaN, AL, Cu, etc., and can be specifically selected according to the required resistance value, and no specific limitation is made here.
[0118] In some embodiments, the upper surface of the resistor material layer 301 away from the substrate 20 is substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20, so as to reduce the process difficulty of forming the resistor.
[0119] It should be noted that the upper surface of the resistive material layer 301 away from the substrate 20 being substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20 can mean that the distance from the upper surface of the resistive material layer 301 away from the substrate 20 to the substrate 20 is approximately equal to the distance from the upper surface of the third metal layer 1031 in the MIM capacitor 10 away from the substrate 20 to the substrate 20. That is, in the case of process errors, the difference between the distance from the upper surface of the resistive material layer 301 away from the substrate 20 to the substrate 20 and the distance from the upper surface of the third metal layer 1031 in the MIM capacitor 10 away from the substrate 20 to the substrate 20 is within a range less than or equal to 0.5 micrometers. It should be noted that this numerical range is only an example to illustrate the case where the upper surface of the resistive material layer 301 away from the substrate 20 is not flush with the upper surface of the third metal layer 1031 in the MIM capacitor 10 in the case of process errors. The specific numerical range can also be set according to the actual process flow and actual process accuracy, and no specific limitation is made here, nor should it be understood as a specific limitation on the numerical range.
[0120] In some embodiments, the thickness range of the resistive material layer 301 is greater than or equal to 500 angstroms and less than or equal to 1500 angstroms.
[0121] 122. Pattern the resistive material layer by at least one of dry etching, wet etching, or Lift-off process to form a resistor.
[0122] In the embodiment of the present application, by forming a resistor 30 on one side of the substrate 20 where the MIM capacitor 10 is provided, the position and size of the resistor 30 can be adjusted according to the size and position of the MIM capacitor 10, so that the thickness of the resistor 30 can more quickly meet the relationship with the thickness of the third metal layer 1031 in the MIM capacitor 10, thereby facilitating the subsequent setting of via holes and improving the manufacturing efficiency.
[0123] In some embodiments, before setting the resistor 30 on one side of the substrate 20 where the MIM capacitor 10 is provided, the manufacturing method further includes:
[0124] Set a second dielectric layer 50 on one side of the substrate 20 where the MIM capacitor 10 is provided, and the second dielectric layer 50 covers the MIM capacitor 10 and the substrate 20, so that the upper surface of the resistor 30 away from the substrate 20 is substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20. By making the upper surface of the resistor 30 away from the substrate 20 substantially flush with the upper surface of the fourth metal layer 1032 away from the substrate 20, it can be ensured that the resistor 30 and the first metal layer 1011 are etched approximately simultaneously, and it can also be ensured that the resistor 30 and the fourth metal layer 1032 are not etched through.
[0125] Among them, it should be noted that the upper surface of the resistor 30 far from the substrate 20 being substantially flush with the upper surface of the fourth metal layer 1032 far from the substrate 20 can be understood as the distance difference between the distance from the upper surface of the resistor 30 far from the substrate 20 to the substrate 20 and the distance from the upper surface of the fourth metal layer 1032 far from the substrate 20 to the substrate 20 being less than or equal to a preset value. The specific size of the preset value can be set according to the actual process and actual precision, and no specific limitation is made here, as long as it can approximately etch the resistor 30 and the MIM capacitor 10 at the same time.
[0126] 130. A first dielectric layer is provided on the substrate, and the first dielectric layer covers the resistor and the MIM capacitor.
[0127] On one side of the MIM capacitor 10 far from the substrate 20 and one side of the resistor 30 far from the substrate 20, an oxide is deposited to form a first dielectric layer 40, and the first dielectric layer 40 covers the resistor 30 and the MIM capacitor 10.
[0128] In some embodiments, the surface of the first dielectric layer 40 far from the substrate 20 is planarized by using a CMP process. This is beneficial for subsequent etching of the first dielectric layer 40 to provide connection holes, and can also avoid affecting the subsequent Photo process due to the rough upper surface and poor flatness of the first dielectric layer 40.
[0129] It should be noted that in the related art, the resistor is first set, and then a dielectric layer is formed to prevent the resistor from being damaged in the subsequent process. After the first planarization process of the dielectric layer, the first etching is performed to form a connection hole on the resistor. Thereafter, the MIM capacitor is formed and a dielectric layer is formed on the MIM capacitor, and then the second planarization process and the second etching are respectively performed to form a connection hole on the MIM capacitor. However, in this application, only one first dielectric layer needs to be formed to integrate the resistor and the capacitor, and only the filled first dielectric layer needs to be planarized once, and only one etching is required to form the connection holes on the resistor and the MIM capacitor. There is no need to set the dielectric layer multiple times, nor to perform multiple planarization processes. This not only ensures the function of the integrated passive device, but also simplifies the processing process flow and saves costs.
[0130] 140. The first dielectric layer is etched to form a first connection hole exposing the resistor and a second connection hole exposing the MIM capacitor.
[0131] The first dielectric layer 40 is etched to form a first connection hole 60 exposing the resistor 30, and the first dielectric layer 40 and a part of the MIM capacitor 10 are etched to form a second connection hole 70 exposing the MIM capacitor 10. Among them, the first connection hole 60 and the second connection hole 70 are formed by the same etching. Compared with the related art where the connection hole on the exposed resistor and the connection hole on the exposed MIM capacitor need to be etched separately, in the embodiment of the present application, the first connection hole 60 and the second connection hole 70 can be formed by the same etching, reducing the process steps and the process cost.
[0132] Among them, for the specific steps of etching the first dielectric layer 40 and a part of the MIM capacitor 10 to form the second connection hole 70 exposing the MIM capacitor 10, please continue to refer to Figure 5 , Figure 5 which is Figure 3 a schematic flow diagram of manufacturing the second connection hole in the manufacturing method shown.
[0133] 141. The first dielectric layer and the barrier layer are etched to form a first sub-connection hole exposing the first metal layer.
[0134] 142. The first dielectric layer, the insulating dielectric layer, and the third metal layer are etched to form a second sub-connection hole exposing the fourth metal layer.
[0135] The upper electrode 101 of the MIM capacitor 10 and the lower electrode 103 of the MIM capacitor 10 are etched simultaneously. Since the upper electrode 101 is disposed on the side of the lower electrode 103 away from the substrate 20, therefore, etching in the direction from the first dielectric layer 40 to the substrate 20 can obtain that the depth of the second sub-connection hole 702 is greater than the depth of the first sub-connection hole 701.
[0136] Among them, the depth of the first connection hole 60 and the depth of the second sub-connection hole 702 are substantially equal. Since the upper surface of the resistor 30 away from the substrate 20 and the upper surface of the fourth metal layer 1032 away from the substrate 20 are substantially flush, therefore, the depth of the first connection hole 60 and the depth of the second sub-connection hole 702 obtained by etching are substantially equal, effectively avoiding the process window of the connection hole and greatly ensuring the high precision of the resistor 30.
[0137] Among them, the explanation for the fact that the depth of the first connection hole 60 and the depth of the second sub-connection hole 702 are substantially equal can be seen above and will not be elaborated here.
[0138] Please continue to refer to Figure 6 , Figure 6 which is Figure 3 a process schematic diagram corresponding to the manufacturing method of the integrated passive device shown. In some embodiments, the manufacturing method of the integrated passive device 100 is as Figure 6As shown, first, a substrate 20 having a MIM capacitor 10 is provided. The MIM capacitor 10 is disposed on one side of the substrate 20. The MIM capacitor 10 includes an upper electrode 101, an insulating dielectric layer 102, and a lower electrode 103. A barrier layer 80 is provided on the side of the upper electrode 101 of the MIM capacitor 10 away from the insulating dielectric layer 102. Then, a second dielectric layer 50 is provided to cover the MIM capacitor 10 and the substrate 20. Then, a resistive material layer 301 is provided on the side of the second dielectric layer 50 away from the substrate 20. Then, a patterned photoresist layer 302 is provided on the side of the resistive material layer 301 away from the substrate 20. Then, the resistive material layer 301 not covered by the photoresist layer 302 is removed, and the patterned photoresist layer 302 is removed to form a resistor 30. Then, a first dielectric layer 40 is provided to cover the resistor 30 and the MIM capacitor 10. Then, the first dielectric layer 40 is planarized. Finally, the first dielectric layer 40 is etched to form a first connection hole 60 and a second connection hole 70. Among them, the second connection hole 70 includes a first sub-connection hole 701 and a second sub-connection hole 702. It should be noted that Figure 6 The manufacturing method shown is only an example and should not be construed as a limitation on the specific steps of the manufacturing method. The specific process can be set according to the actual situation and is not specifically limited herein.
[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.
Claims
1. A manufacturing method of an integrated passive device, characterized in that, Comprising: Providing a substrate and a MIM capacitor, the MIM capacitor being located on one side of the substrate; Providing a resistor on the substrate, the resistor being on the same side of the substrate as the MIM capacitor; Providing a first dielectric layer on the substrate, the first dielectric layer covering the resistor and the MIM capacitor; Etching the first dielectric layer to form a first connection hole exposing the resistor and a second connection hole exposing the MIM capacitor.
2. The manufacturing method according to claim 1, characterized in that, The MIM capacitor comprises: an upper electrode, an insulating dielectric layer, and a lower electrode stacked from top to bottom; In a direction perpendicular to the substrate, the orthographic projection of the upper electrode is located within the orthographic projections of the insulating dielectric layer and the lower electrode; The upper electrode comprises a first metal layer and a second metal layer stacked; The lower electrode comprises a third metal layer and a fourth metal layer stacked.
3. The manufacturing method according to claim 2, characterized in that, The upper surface of the resistor away from the substrate is substantially flush with the upper surface of the fourth metal layer away from the substrate.
4. The manufacturing method according to claim 2, wherein Further comprising providing a barrier layer on the MIM capacitor, the thickness of the barrier layer being greater than or equal to the thickness of the third metal layer.
5. The manufacturing method according to claim 4, characterized in that, The forming of the second connection hole exposing the MIM capacitor comprises: Etching the first dielectric layer and the barrier layer to form a first sub-connection hole exposing the first metal layer; Etching the first dielectric layer, the insulating dielectric layer, and the third metal layer to form a second sub-connection hole exposing the fourth metal layer.
6. The manufacturing method according to claim 5, characterized in that, The depth of the first connection hole is substantially equal to the depth of the second sub-connection hole.
7. The manufacturing method according to any one of claims 2 to 6, characterized in that, The material of the first metal layer comprises at least one of Au, Al, Cu, and Pt; The material of the second metal layer comprises at least one of TiN, TaN, and Ni; The material of the third metal layer is the same as that of the second metal layer, and the material of the fourth metal layer is the same as that of the first metal layer; The material of the insulating dielectric layer comprises at least one of SiN, SiO2, and Ta2O5.
8. The manufacturing method according to any one of claims 4 to 6, characterized in that, The material of the barrier layer comprises at least one of TiN, TaN, and Ni.
9. The manufacturing method according to claim 1, characterized in that, Providing a resistor on the substrate comprises: Providing a resistor material layer on the side of the substrate where the MIM capacitor is provided to cover the substrate and the MIM capacitor; Patterning the resistor material layer by at least one of dry etching, wet etching, or Lift-off process to form the resistor.
10. An integrated passive device, characterized in that, Comprising: Substrate; MIM capacitor, the MIM capacitor being located on one side of the substrate; Resistor, the resistor being on the same side of the substrate as the MIM capacitor; First dielectric layer, the first dielectric layer being provided on the side of the resistor and the MIM capacitor away from the substrate to cover the resistor and the MIM capacitor.
11. The integrated passive device according to claim 10, characterized in that, The MIM capacitor comprises an upper electrode, an insulating dielectric layer, and a lower electrode stacked from top to bottom; In a direction perpendicular to the substrate, the orthographic projection of the upper electrode is located within the orthographic projections of the insulating dielectric layer and the lower electrode; The upper electrode comprises a first metal layer and a second metal layer stacked; The lower electrode comprises a third metal layer and a fourth metal layer stacked.
12. The integrated passive device according to claim 11, characterized in that, The upper surface of the resistor away from the substrate is substantially flush with the upper surface of the fourth metal layer away from the substrate.
13. The integrated passive device according to claim 12, wherein, Further included are: A barrier layer, which is located on the MIM capacitor, and the thickness of the barrier layer is greater than or equal to the thickness of the third metal layer.
14. The integrated passive device according to claim 13, wherein Also included is A first connection hole that penetrates the first dielectric layer to expose the surface of the resistor; A second connection hole that penetrates the first dielectric layer and part of the MIM capacitor to expose the MIM capacitor.
15. The integrated passive device according to claim 14, characterized in that, The second connection hole includes: A first sub-connection hole that penetrates the first dielectric layer and the barrier layer to expose the surface of the first metal layer; A second sub-connection hole that penetrates the first dielectric layer, the insulating dielectric layer, and the third metal layer to expose the surface of the fourth metal layer; Wherein, the depth of the first connection hole and the depth of the second sub-connection hole are substantially equal.
16. The integrated passive device according to any one of claims 11 to 15, characterized in that, The material of the first metal layer includes at least one of Au, Al, Cu, and Pt; The material of the second metal layer includes at least one of TiN, TaN, and Ni; The material of the third metal layer is the same as that of the second metal layer, and the material of the fourth metal layer is the same as that of the first metal layer; The material of the insulating dielectric layer includes at least one of SiN, SiO2, and Ta2O5.
17. The integrated passive device according to any one of claims 13 to 15, characterized in that The material of the barrier layer includes at least one of TiN, TaN, and Ni.