Semiconductor device
By adding gate-source capacitance structure to semiconductor devices, the crosstalk problem is solved, the ratio between Ciss and Crss is increased, the crosstalk risk is reduced, and the device reliability and outflow capability are maintained.
Patent Information
- Application Number
- CN202510221244.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-07-08
AI Technical Summary
Existing semiconductor devices are prone to crosstalk, and the ratio of Ciss to Crss is difficult to reach the requirement of 200 or 400.
An additional gate-source capacitance structure is added to the semiconductor device, and a capacitor plate layer is formed by modifying the gate pad position, so that the gate electrode layer, the gate bus layer and the capacitor plate layer are insulated from each other, thereby increasing Cgs, thereby increasing the ratio of Ciss to Crss.
It effectively reduces the risk of crosstalk of semiconductor devices, while not affecting the reliability and area of the device, improves the outflow capability and reduces the on-resistance.
Smart Images
Figure CN120282532A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device. Background Art
[0002] As a core component in power electronic systems, power semiconductor devices have always been important electronic components indispensable in modern life, and are widely used in consumer electronic devices, automotive electronic systems, smart grids, to various industrial devices, locomotives, aerospace, and ship systems. SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) devices have become the mainstream devices in the development of high-voltage and high-frequency fields due to their advantages such as high input impedance, good temperature stability, excellent high-frequency and high-voltage performance, and large safe operating area.
[0003] However, crosstalk phenomena are likely to occur in existing semiconductor devices. Summary of the Invention
[0004] The semiconductor device provided by this application aims to solve the problem that crosstalk is likely to occur in existing semiconductor devices.
[0005] To solve the above technical problems, the first technical solution adopted by this application is: to provide a semiconductor device, which includes a semiconductor epitaxial wafer, including an active region and an edge termination region surrounding the active region;
[0006] A plurality of first doping regions and a plurality of second doping regions, the plurality of first doping regions are arranged in the active region, and the first doping regions and the second doping regions have different conduction types;
[0007] A first conductive layer, including a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is arranged in the active region, and the gate bus layer is arranged in the edge termination region; the first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer;
[0008] An interlayer dielectric layer covers the first conductive layer; the interlayer dielectric layer has a first opening, so that a part of the capacitor plate layer is exposed to form a first exposed part;
[0009] A second conductive layer is arranged on the side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least arranged in the active region and is electrically connected to the first doping region; the gate pad is at least arranged in the edge termination region and is electrically connected to the gate bus layer;
[0010] A dielectric layer is arranged in the first opening and covers the first exposed part; the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer;
[0011] Wherein, the dielectric layer has an opening; the opening is spaced from the sidewall of the first opening of the interlayer dielectric layer along a first direction; a part of the source pad is in contact electrical connection with the first exposed portion through the first opening and the opening in sequence; a part of the gate pad is stacked on a side of the dielectric layer away from the capacitor plate layer.
[0012] In an embodiment of the present application, the opening is disposed at an edge of the dielectric layer close to the active region.
[0013] In an embodiment of the present application, the first opening has opposite first sidewall and second sidewall along the first direction; along the first direction, a first distance between the opening and the first sidewall is less than a second distance between the opening and the second sidewall.
[0014] In an embodiment of the present application, the first opening has opposite third sidewall and fourth sidewall along a second direction; along the second direction, the opening is spaced from the third sidewall, and the opening is spaced from the fourth sidewall.
[0015] In an embodiment of the present application, a length of the opening along the second direction is greater than a length of the opening along the first direction.
[0016] To solve the above technical problem, a second technical solution adopted by the present application is: providing a semiconductor device, the semiconductor device includes:
[0017] A semiconductor epitaxial wafer, including an active region and an edge termination region surrounding the active region;
[0018] A plurality of first doping regions, disposed in the active region;
[0019] A first conductive layer, including a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, the gate bus layer is disposed in the edge termination region; the first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer;
[0020] An interlayer dielectric layer, covering the first conductive layer; the interlayer dielectric layer has a first opening, such that a part of the capacitor plate layer is exposed to form a first exposed portion;
[0021] A second conductive layer, disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and is electrically connected to the first doping region; the gate pad is at least disposed in the edge termination region and is electrically connected to the gate bus layer;
[0022] A dielectric layer is disposed within the first opening and covers the first exposed portion; the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer;
[0023] Wherein, the dielectric layer includes a first portion and a second portion which are spaced apart, and an opening is formed between the first portion and the second portion; a portion of the source pad is in contact electrical connection with the first exposed portion through the first opening and the opening in sequence; a portion of the gate pad is stacked on a side of the dielectric layer away from the capacitor plate layer.
[0024] In an embodiment of the present application, the first portion is located on a side of the second portion close to the active region along a first direction.
[0025] In an embodiment of the present application, the width of the first portion along the first direction is less than the width of the second portion along the first direction.
[0026] In an embodiment of the present application, the dielectric layer further includes a third portion and a fourth portion which are spaced apart along a second direction; the first portion, the second portion, the third portion and the fourth portion jointly enclose to form the opening.
[0027] In an embodiment of the present application, the distance between the third portion and the fourth portion is greater than the distance between the first portion and the second portion.
[0028] Distinct from the prior art, the beneficial effects of the present application are as follows. The semiconductor device provided by the present application includes a semiconductor epitaxial wafer, a plurality of first doping regions, a plurality of second doping regions, a first conductive layer, an interlayer dielectric layer, and a second conductive layer. The semiconductor epitaxial wafer includes an active region and an edge termination region surrounding the active region; a plurality of first doping regions are disposed in the active region, and the first doping regions and the second doping regions have different conduction types; the first conductive layer includes a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge termination region; the first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer; the interlayer dielectric layer covers the first conductive layer; the interlayer dielectric layer has a first opening, such that a part of the capacitor plate layer is exposed to form a first exposed portion; the second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and is electrically connected to the first doping region; the gate pad is at least disposed in the edge termination region and is electrically connected to the gate bus layer. A dielectric layer is disposed in the first opening and covers the first exposed portion; the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer; wherein, the dielectric layer has an opening; the opening is spaced from the sidewall of the first opening of the interlayer dielectric layer along a first direction; a part of the source pad is sequentially in contact and electrically connected to the first exposed portion through the first opening and the opening; a part of the gate pad is stacked on a side of the dielectric layer away from the capacitor plate layer. Among them, the semiconductor device further includes a capacitor plate layer in the first conductive layer, and the gate electrode layer and the gate bus layer are insulated from the capacitor plate layer; the source pad is electrically connected to the capacitor plate layer; a part of the gate pad is stacked with a part of the capacitor plate layer and is isolated by the dielectric layer, so as to form an additional gate-source capacitance through the part of the gate pad covering the capacitor plate layer, the dielectric layer, and the part where the capacitor plate layer is stacked with the gate pad, thereby increasing the ratio of Ciss to Crss and reducing the risk of crosstalk of the semiconductor device. At the same time, this design only involves a small change in the position of the gate pad, which has little impact on the reliability of the active region and the semiconductor device. Description of the Drawings
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, where:
[0030] Figure 1 Is an equivalent circuit diagram of the semiconductor device;
[0031] Figure 2 Is a top view of some embodiments of the semiconductor device provided by the present application;
[0032] Figure 3 A cross-sectional view of a partial structure of the semiconductor device shown along the line A-A'; Figure 2 shown in FIG. 4 is a schematic diagram of the regional division of the semiconductor device;
[0033] Figure 4a A top view of the semiconductor device shown without the second conductive layer;
[0034] Figure 4b A magnified view of the pad area in FIG. 20; Figure 2 A cross-sectional view of a partial structure of the structure shown along the line A-A';
[0035] Figure 4c Another cross-sectional view of a partial structure of the semiconductor device shown along the line A-A'; Figure 4b A magnified view of the location M in FIG. 38;
[0036] Figure 5 A schematic diagram of the structure for forming the second conductive layer on the semiconductor device shown in FIG. 44; Figure 4b Another top view of the semiconductor device shown without the interlayer dielectric layer and the second conductive layer;
[0037] Figure 6a A cross-sectional view of a partial structure of the structure shown along the line B-B'; Figure 2 A schematic diagram of the structure for forming the passivation layer on the structure shown in FIG. 62;
[0038] Figure 6b A top view of some other embodiments of the semiconductor device provided by the present application; Figure 6a A cross-sectional view of a partial structure of the semiconductor device provided by one embodiment of the present application along the line C-C';
[0039] Figure 7 A cross-sectional view of a partial structure of the semiconductor device provided by another embodiment of the present application along the line C-C'; Figure 6a shown in FIG. 44;
[0040] Figure 8 A cross-sectional view of a partial structure of the structure shown along the line B-B'; Figure 2 Another top view of the semiconductor device shown without the interlayer dielectric layer and the second conductive layer;
[0041] Figure 9 A cross-sectional view of a partial structure of the structure shown along the line B-B'; Figure 8 shown in FIG. 56;
[0042] Figure 10 A schematic diagram of the structure for forming the passivation layer on the structure shown in FIG. 62; Figure 3 shown in FIG. 62;
[0043] Figure 11 A top view of some other embodiments of the semiconductor device provided by the present application;
[0044] Figure 12 A cross-sectional view of a partial structure of the semiconductor device provided by one embodiment of the present application along the line C-C'; Figure 11 shown in FIG. 72;
[0045] Figure 13 A cross-sectional view of a partial structure of the semiconductor device provided by another embodiment of the present application along the line C-C';
[0046] Figure 14 and Figure 15 are partial structural cross-sectional views of a semiconductor device provided for different embodiments of the present application along the C-C' line;
[0047] Figure 16 is a flowchart of a method for manufacturing a semiconductor device provided for an embodiment of the present application;
[0048] Figure 17 is a partial intermediate product structure schematic diagram of a semiconductor epitaxial wafer after being processed by step S2 in Figure 16 ;
[0049] Figure 18 is a partial intermediate product structure schematic diagram of a semiconductor epitaxial wafer after being processed by step S3 in Figure 16 ;
[0050] Figure 19 is Figure 18 a partial structural cross-sectional view of the semiconductor device shown along the C-C' line;
[0051] Figure 20 is a top view of a partial intermediate product structure of a semiconductor epitaxial wafer after step S5;
[0052] Figure 21 is Figure 20 a partial structural cross-sectional view of the structure shown along the C-C' line;
[0053] Figure 22 is a top view of a partial intermediate product structure of a semiconductor epitaxial wafer after being processed by step S6 in Figure 16 ;
[0054] Figure 23 is Figure 22 a partial structural cross-sectional view of the structure shown along the C-C' line.
[0055] Description of Reference Numerals
[0056] 1 - Semiconductor epitaxial wafer; A1 - Active region; A2 - Edge termination region; A3 - Ring trace region; A4 - Pad region; 11 - Terminal structure; 12 - Second doping region; 2 - Third doping region; 18 - Drain electrode; 13 - First doping region; 3 - First conductive layer; 31 - Gate electrode layer; 31a - Gate structure; 32 - Gate bus layer; 33 - Capacitor plate layer; 4 - Interlayer dielectric layer; 41 - First opening; b1 First sidewall; b2 Second sidewall; b3 Third sidewall; b4 Fourth sidewall; 42 - Second opening; 43 - Third opening; 44 - Fourth opening; 5 - Second conductive layer; 51 - Source pad; 52 - Gate pad; 6 - Dielectric layer; 61 - Opening; 7a - Gate insulating layer; 7b - Trace insulating layer; 7c - Passivation layer; 71 - Fifth opening; 72 - Sixth opening. Detailed implementation manners
[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.
[0058] The terms "first", "second", and "third" in the present application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", and "third" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.
[0059] Referring to "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.
[0060] In practical applications, there are a large number of converters, and a large part of them have an upper and lower transistor structure, such as half-bridge, three-phase full-bridge, three-level, etc. When the active transistor performs a switching action, its own drive voltage has no obvious oscillation or glitch, while the drive voltage of the synchronous rectifier transistor will have glitches. That is to say, in a bridge circuit, the active switching action of a device will affect the Vgs (maximum gate-source voltage) of its counterpart transistor, and this phenomenon is crosstalk.
[0061] See Figure 1 , Figure 1It is an equivalent circuit diagram of a semiconductor device. Among them, Cds (source-drain parasitic capacitance), Cgd (gate-drain parasitic capacitance), and Cgs (gate-source parasitic capacitance) are the junction capacitances of the disturbed transistor, Rg(int) is the internal resistance of the device gate bus layer, Rg(ext) is the external drive resistance, and the turn-off drive voltage is V DRV(off) .
[0062] Affected by the switching action of the opposite transistor, the terminal voltage Vds of the disturbed transistor rises at a speed of dV DS(on) / dt when the opposite transistor turns on, and drops at a speed of dV DS(off) / dt when the operating transistor turns off. The positive spike V CK-on(max) of the gate bus layer voltage in the turn-on crosstalk and the negative spike V CK-off(min) of the voltage in the gate bus layer of the turn-off crosstalk are respectively:
[0063]
[0064] It can be seen from the above formula that the larger Cgd is, the larger the displacement current is, resulting in serious crosstalk; the larger Cgs is, the slower the displacement current charges it, playing a role in alleviating crosstalk. Therefore, generally, module users require the ratio of Ciss to Crss to be greater than 200, or even greater than 400; however, most of the existing semiconductor devices cannot meet the requirement that the ratio of Ciss to Crss (i.e., Ciss / Crss) is greater than 400, resulting in crosstalk problems in semiconductor devices. Among them, Ciss is the input capacitance; Crss is the reverse capacitance.
[0065] Therefore, the embodiment of the present application provides a new semiconductor device, by adding an additional gate-source capacitance structure to increase Cgs, thereby increasing the ratio of Ciss to Crss, and further reducing the risk of crosstalk in the semiconductor device. At the same time, it will not affect the reliability of the semiconductor device.
[0066] The following will describe the present application in detail with reference to the drawings and embodiments.
[0067] Please refer to Figures 2 to 5 , Figure 2 which is a top view of some embodiments of the semiconductor device provided by the present application; Figure 3 is Figure 2 a partial structural cross-sectional view of the semiconductor device shown along the line A-A';
[0068] Figure 4b is a schematic diagram of the region division of the semiconductor device; Figure 4b is Figure 2 a top view of the semiconductor device shown without the second conductive layer; Figure 4c is Figure 4bEnlarged view of the middle pad area; Figure 5 is Figure 4b Partial structural cross-sectional view of the structure shown along line A-A'.
[0069] The present application provides a semiconductor device, which can be a SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) device. The semiconductor device includes a semiconductor epitaxial wafer 1, a plurality of first doping regions 13, a first conductive layer 3, an interlayer dielectric layer 4, and a second conductive layer 5.
[0070] Among them, as Figure 2 and Figure 3 shown, the semiconductor epitaxial wafer 1 includes an active region A1 and an edge termination region A2 surrounding the outside of the active region A1; a plurality of first doping regions 13 are disposed in the semiconductor epitaxial wafer 1 and are located in the active region A1, and each first doping region 13 extends from one side of the active region A1 to the opposite side of the active region A1. As Figure 3 shown, the edge termination region A2 is provided with a terminal structure 11 for protecting the device from damage such as overvoltage or overcurrent. Among them, the terminal structure 11 can be a field limiting ring structure or a junction termination extension region (JTE region). The functions and structures of the field limiting ring structure and the junction termination extension region are prior arts and will not be elaborated here.
[0071] As Figure 3 shown, the first conductive layer 3 includes a gate electrode layer 31 and a gate bus layer 32 that are electrically connected to each other. The gate electrode layer 31 is disposed on the semiconductor epitaxial wafer 1 and is located in the active region A1, and the gate electrode layer 31 includes a plurality of gate structures 31a spaced apart along the first direction Y. The orthographic projection of each gate structure 31a on the semiconductor epitaxial wafer 1 is located between two first doping regions 13. In some embodiments, the first conductive layer 3 is a doped polysilicon layer or a conductive metal, which is not limited herein as long as it has a conductive function.
[0072] In some embodiments, the semiconductor device further includes a plurality of second doping regions 12 and a plurality of third doping regions 2. The plurality of second doping regions 12 and the plurality of third doping regions 2 are disposed in the semiconductor epitaxial wafer 1. The plurality of second doping regions 12, the plurality of third doping regions 2, and the plurality of first doping regions 13 are correspondingly disposed; among them, the first doping region 13 and the third doping region 2 are located in the corresponding second doping region 12, and a part of the third doping region 2 is located in the first doping region 13. Among them, the second doping region 12, the third doping region 2, and the first doping region 13 all extend from one side of the active region A1 to the opposite side of the active region A1 along the surface of the semiconductor epitaxial wafer 1 within the semiconductor epitaxial wafer 1.
[0073] Among them, the semiconductor epitaxial wafer 1 and the first doped region 13 have a first conduction type, and the ion doping concentration of the first doped region 13 is greater than that of the semiconductor epitaxial wafer 1; the second doped region 12 and the third doped region 2 have a second conduction type, and the ion doping concentration of the third doped region 2 is greater than that of the second doped region 12. In some embodiments, the first doped region 13 can be the source region, the second doped region 12 can be the well region, and the third doped region 2 can be the well contact region.
[0074] Among them, the first conduction type can be one of N-type or P-type, and the second conduction type can be the other of N-type or P-type. In this application, the first conduction type is N-type and the second conduction type is P-type as an example.
[0075] Combined with Figure 2 and Figure 3 , the gate bus layer 32 is disposed in the edge terminal region A2; and the gate bus layer 32 surrounds the active region A1 and is connected to the end of each gate structure 31a. Combined with Figure 4b , specifically, the gate bus layer 32 is connected to the end of each gate structure 31a along the second direction X. The multiple gate structures 31a are spaced apart in the first direction Y, and the gate bus layer 32 is disposed around the periphery of all the gate structures 31a.
[0076] Specifically, in the embodiment of the present application, by disposing the gate bus layer 32 on the edge terminal region A2, compared with the prior art in which the gate bus layer 32 is disposed in the active region A1, the area of the active region A1 can be saved, so that basically all of the semiconductor device except the edge terminal region A2 is the active region A1, thereby improving the current output ability of the device and reducing the on-resistance. And the gate bus layer 32 is connected to the end of each gate structure 31a extending to the edge of the active region A1, and the gate bus layer 32 can drive each gate structure 31a, thus not affecting the reliability of the device.
[0077] Combined with Figure 3 , the interlayer dielectric layer 4 covers the first conductive layer 3. The second conductive layer 5 is disposed on the side of the interlayer dielectric layer 4 away from the semiconductor epitaxial wafer 1. The second conductive layer 5 includes a source pad 51 and a gate pad 52; the source pad 51 and the gate pad 52 are used for electrically connecting the device to an external device. Among them, the source pad 51 is disposed at least in the active region A1 and is electrically connected to the first doped region 13. The gate pad 52 is disposed at least in the edge terminal region A2 and is electrically connected to the gate bus layer 32.
[0078] Specifically, the gate pad 52 can be entirely disposed in the edge terminal region A2 and disposed around the active region A1. Alternatively, at least a portion of the gate pad 52 extends into the active region A1 and is insulated from the source pad 51, which can be designed according to specific needs. The materials of the source pad 51 and the gate pad 52 include, but are not limited to, any one or a combination of aluminum, copper, tungsten, silver, or nickel.
[0079] Among them, the interlayer dielectric layer 4 specifically coats each gate structure 31a to isolate each gate structure 31a; and Figure 5 in the active region A1, the interlayer dielectric layer 4 has a third opening 43 corresponding to each first doping region 13, so that at least a portion of each first doping region 13 is exposed through its corresponding third opening 43. A portion of the source pad 51 extends into the third opening 43 and is in electrical contact with the first doping region 13.
[0080] In a specific embodiment, the semiconductor device further includes a plurality of ohmic contact metals (not shown in the figure). The plurality of ohmic contact metals are respectively disposed in each third opening 43 and are in electrical contact with the corresponding first doping region 13. The source pad 51 specifically forms an ohmic contact metal contact with each first doping region 13 to be in electrical contact with the first doping region 13 through the ohmic contact metal. The materials of the ohmic contact metals include, but are not limited to, any one or a combination of Ti, Ni, Al, Au, Ta, or W.
[0081] Furthermore, combining Figure 3 and Figure 5 the interlayer dielectric layer 4 also coats the gate bus layer 32 to isolate the gate bus layer 32. In the edge terminal region A2, the interlayer dielectric layer 4 has a fourth opening 44 corresponding to the gate bus layer 32, so that at least a portion of the gate bus layer 32 is exposed through the fourth opening 44. A portion of the gate pad 52 extends into the fourth opening 44 and is in electrical contact with the gate bus layer 32.
[0082] In some embodiments, the material of the interlayer dielectric layer 4 can be silicon oxide or silicon nitride, etc. The thickness of the interlayer dielectric layer 4 is 800 nm - 1000 nm. For example, the thickness of the interlayer dielectric layer 4 can be 800 nm, 850 nm, 900 nm, 950 nm, or 1000 nm, etc., which is not limited herein. It is specifically designed according to the actual device size.
[0083] In one embodiment, referring to Figure 3, the first conductive layer 3 further includes a capacitor plate layer 33, and the gate electrode layer 31 and the gate bus layer 32 are both insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a part of the gate pad 52 and a part of the capacitor plate layer 33 are stacked and isolated by the dielectric layer 6; wherein, the thickness of the dielectric layer 6 is less than the thickness of the interlayer dielectric layer 4. Specifically, the gate bus layer 32 can be disposed around the periphery of the capacitor plate layer 33 and spaced from the capacitor plate layer 33. In this way, during the process of forming the semiconductor device, a part can be segmented from the original gate bus layer 32 to serve as the capacitor plate layer 33; thus, the capacitor plate layer 33 can be formed without increasing the area of the semiconductor device.
[0084] In some embodiments, the thickness of the dielectric layer 6 can be 50 - 200 nanometers; for example, the thickness of the dielectric layer 6 can be 50nm, 80nm, 110nm, 140nm, 170nm, or 200nm, etc., which is not limited herein. The dielectric layer 6 is a thermally oxidized silicon oxide layer.
[0085] Among them, the magnitude of the gate-source capacitance value (C gs ) can be adjusted by adjusting the thickness of the dielectric layer 6, so as to increase Cgs as much as possible, thereby making the range of Ciss / Crss adjustable.
[0086] In the above solution, by making the first conductive layer 3 further include a capacitor plate layer 33, and making the gate electrode layer 31 and the gate bus layer 32 both insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a part of the gate pad 52 and a part of the capacitor plate layer 33 are stacked and isolated by the dielectric layer 6, so as to form an additional gate-source capacitance by covering a part of the capacitor plate layer 33, the dielectric layer 6, and the part where the capacitor plate layer 33 and the gate pad 52 are stacked by the gate pad 52, thereby increasing the ratio of Ciss / Crss to reduce the risk of crosstalk in the semiconductor device.
[0087] At the same time, it is easy to understand that the core of the above solution is to segment a part from the original first conductive layer 3 to serve as the capacitor plate layer 33; for example, if the capacitor plate layer 33 is located in the edge termination region A2, it is equivalent to segmenting a part from the original gate bus layer 32 to serve as the capacitor plate layer 33, and then forming an additional gate-source capacitance, so as to achieve the purpose of increasing Ciss / Crss. This design only involves the change of the position of the gate pad 52, and since the capacitor plate layer 33 will not affect the connection between the gate pad 52 and the source pad 51 and other structures in the active region A1, the change is small and will not affect the reliability of the original semiconductor device, greatly improving the anti-crosstalk ability of the semiconductor device. At the same time, the area of the semiconductor device will not be increased.
[0088] In some embodiments, the capacitor plate layer 33 is disposed on the same layer as the gate electrode layer 31 and the gate bus layer 32 and has the same material. In this way, in the process of manufacturing the semiconductor device, the capacitor plate layer 33, the gate electrode layer 31, and the gate bus layer 32 can be formed synchronously by the same process step. Thus, the process steps are not increased and the cost is saved.
[0089] In some embodiments, in combination with Figure 5 , the capacitor plate layer 33 is located in the edge termination region A2; the interlayer dielectric layer 4 has a first opening 41, such that a part of the capacitor plate layer 33 is exposed to form a first exposed portion; the dielectric layer 6 is disposed in the first opening 41 and covers the first exposed portion. Wherein, a part of the gate pad 52 extends into the first opening 41 and is located on the surface of the dielectric layer 6 away from the first exposed portion.
[0090] By disposing the capacitor plate layer 33 in the edge termination region A2 as described above, an additional gate-source capacitance structure can be formed; and compared with disposing the capacitor plate layer 33 in the active region A1, the area of the active region A1 can be saved, such that basically the entire semiconductor device except for the edge termination region A2 is the active region A1, thereby improving the current output capacity of the device; and there is no need to consider the limitation of the occupied area too much.
[0091] The following are two ways for the source pad 51 to be electrically connected to the capacitor plate layer 33.
[0092] In one embodiment, in combination with Figures 3 to 5 , the dielectric layer 6 has an opening 61; the opening 61 is spaced from the sidewall of the first opening 41 of the interlayer dielectric layer 4 along the first direction Y. A part of the source pad 51 sequentially contacts the first exposed portion through the first opening 41 and the opening 61 to be electrically connected to the capacitor plate layer 33. It can be understood that a part of the source pad 51 extends into the first opening 41 and further extends into the opening 61 to contact the first exposed portion. Wherein, the part of the source pad 51 extending into the first opening 61 and the part of the gate pad 52 extending into the first opening 41 can be spaced apart to achieve insulation between the two.
[0093] In order to ensure that the area of the part of the gate pad 52 extending into the first opening 41 is large enough to meet the requirements of subsequent packaging and wire bonding, the opening 61 needs to be close to the edge of the dielectric layer 6 and the width cannot be too large. In some embodiments, in combination with Figure 4c , the opening 61 is disposed at the edge of the dielectric layer 6 close to the active region A1. Wherein, the first opening 41 has opposite first sidewall b1 and second sidewall b2 along the first direction Y; along the first direction Y, the first distance L1 between the opening 61 and the first sidewall b1 is less than the second distance L2 between the opening 61 and the second sidewall b2.
[0094] Further, to ensure effective contact between the source pad 51 and the capacitor plate layer 33 and facilitate the formation of the opening 61. In some embodiments, the first opening 41 has opposite third sidewall b3 and fourth sidewall b4 along the second direction X; along the second direction X, the opening 61 is spaced from the third sidewall b3, and the opening 61 is spaced from the fourth sidewall b4. Wherein, the length L3 of the opening 61 along the second direction X is greater than the length L4 of the opening 61 along the first direction Y.
[0095] In other words, the dielectric layer 6 includes a first part and a second part which are spaced apart, and an opening 61 is formed between the first part and the second part. Wherein, to ensure that the area of the part of the gate pad 52 extending into the first opening 41 is large enough to meet the requirements of subsequent packaging and wire bonding, the opening 61 needs to be close to the edge of the dielectric layer 6 and the width cannot be too large. In some embodiments, the first part is located on the side of the second part close to the active region A1 along the first direction Y. Wherein, the width L1 of the first part along the first direction Y is less than the width L2 of the second part along the first direction Y.
[0096] Further, to ensure effective contact between the source pad 51 and the capacitor plate layer 33 and facilitate the formation of the opening 61. In some embodiments, the dielectric layer 6 further includes a third part and a fourth part which are spaced apart along the second direction X; the first part, the second part, the third part and the fourth part together enclose to form the opening 61. Wherein, the distance L3 between the third part and the fourth part is greater than the distance L4 between the first part and the second part.
[0097] In another embodiment, referring to Figures 6a to 7 , Figure 6a is Figure 2 another cross-sectional view of a partial structure of the semiconductor device shown along the A-A' line; Figure 6b is Figure 6a the enlarged view of M in Figure 7 is the schematic structural diagram of forming a second conductive layer on the semiconductor device shown in Figure 6a . The interlayer dielectric layer 4 has a second opening 42 spaced from the first opening 41, so that a part of the capacitor plate layer 33 is exposed to form a second exposed part; that is, the part of the capacitor plate layer 33 exposed through the second opening 42 forms the second exposed part. A part of the source pad 51 extends into the second opening 42 and contacts the second exposed part to realize the electrical connection between the source pad 51 and the capacitor plate layer 33.
[0098] Combined with Figure 3 and Figure 7 it is easy to understand that this solution compared with Figure 3For the corresponding embodiment, more area of the gate pad 52 can extend into the first opening 41 to be stacked with the capacitor plate layer 33; thereby effectively increasing the relative area between the gate pad 52 and the capacitor plate layer 33, increasing the Cgs value, and further reducing the risk of crosstalk in the semiconductor device.
[0099] The following is an introduction to the specific setting positions of the capacitor plate layer 33 in the edge terminal region A2 provided by different embodiments of the present application.
[0100] In one embodiment, in combination with Figure 4a and Figure 4b , the edge terminal region A2 includes an annular trace region A3 and a pad region A4. The annular trace region A3 surrounds the periphery of the active region A1 for one week. The pad region A4 is connected to the annular trace region A3 and is located on one side of the active region A1. Among them, the cross-sectional area of the pad region A4 is larger than the cross-sectional area of the annular trace region A3 on each side of the active region A1; the capacitor plate layer 33 is specifically located in the pad region A4. In this way, a larger area of the capacitor plate layer 33 can be set in the edge terminal region A2, so that a larger area of the gate pad 52 can be disposed opposite to the capacitor plate layer 33 to further increase the gate-source capacitance value.
[0101] In some embodiments, the pad region A4 is located inside the annular trace region A3; that is, it is located on the side of the annular trace region A3 close to the active region A1.
[0102] In a specific embodiment, the edge terminal region A2 includes an annular trace region A3 surrounding the active region A1 for one week and a pad region A4 connected to the annular trace region A3; the annular trace region A3 includes a first edge region and a second edge region oppositely disposed along the first direction Y, and a third edge region and a fourth edge region oppositely disposed along the second direction X; the first edge region to the fourth edge region enclose a closed-loop structure, and the active region A1 is located within this closed-loop structure. The above-mentioned pad region A4 is specifically connected to the first edge region, is located on the side of the first edge region facing the second edge region, and is located between the active region A1 and the first edge region. Part of the first doping region 13 specifically extends from the third edge region to the fourth edge region.
[0103] In one embodiment, the pad region A4 extends along the first direction Y, and the active region A1 extends to the opposite sides of the pad region A4 along the second direction X; that is, part of the active region A1 is located on both sides of the pad region A4 along the second direction X. In this way, the area of the active region A1 can be increased as much as possible within a limited area. The first direction Y is perpendicular to the second direction X.
[0104] In another embodiment, refer to Figures 8 to 9 , Figure 8 is Figure 2Another top view of the semiconductor device shown, excluding the interlayer dielectric layer 4 and the second conductive layer 5; Figure 9 is Figure 8 A partial cross-sectional view of the structure shown along line B-B'; Different from the embodiment corresponding to the above Figure 4b is that: the gate bus layer 32 includes a ring trace layer located in the ring trace area A3 and a pad layer located in the pad area A4; the capacitor plate layer 33 is located in the second edge area and inside the ring trace layer. In this way, it is beneficial to elongate the capacitor plate layer 33 along the first direction Y. Specifically, the part of the ring trace layer located in the second edge area surrounds the entire capacitor plate layer 33 and is spaced from the capacitor plate layer 33.
[0105] Of course, in other embodiments, the capacitor plate layer 33 can also be disposed in the third edge area and the fourth edge area, as long as it is insulated from the various layer structures and the ring trace layer disposed in the active area A1.
[0106] In some embodiments, referring to Figure 10 , Figure 10 is Figure 3 A schematic structural diagram of forming a passivation layer on the structure shown; The semiconductor device further includes a plurality of second doped regions 12, a plurality of third doped regions 2, a gate insulating layer 7a, a trace insulating layer 7b, a passivation layer 7c, and a drain electrode 18.
[0107] A plurality of second doped regions 12 and a plurality of third doped regions 2 are provided in the semiconductor epitaxial wafer 1. A plurality of second doped regions 12, a plurality of third doped regions 2, and a plurality of first doped regions 13 are correspondingly provided. Among them, the second doped regions 12, the third doped regions 2, and the first doped regions 13 all extend in the semiconductor epitaxial wafer 1 along the surface of the semiconductor epitaxial wafer 1.
[0108] The gate insulating layer 7a is at least provided in the active area A1; the gate electrode layer 31 is provided on the side of the gate insulating layer 7a away from the semiconductor epitaxial wafer 1 to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the second doped region 12, the third doped region 2, and / or the first doped region 13 through the gate insulating layer 7a. In one embodiment, a part of the gate insulating layer 7a further extends to the edge terminal area A2 to be connected to the trace insulating layer 7b.
[0109] The trace insulating layer 7b is provided on the semiconductor epitaxial wafer 1 and located in the edge terminal area A2; the gate bus layer 32 is provided on the surface of the trace insulating layer 7b away from the semiconductor epitaxial wafer 1. The trace insulating layer 7b isolates the gate bus layer 32 from the semiconductor epitaxial wafer 1 and the terminal structure 11.
[0110] Among them, the materials of the gate insulating layer 7a and the wiring insulating layer 7b can be silicon oxide, silicon nitride, etc., which are not limited here, as long as the first conductive layer 3 and the semiconductor epitaxial wafer 1 can be dielectrically isolated.
[0111] In some embodiments, the thickness of the wiring insulating layer 7b is greater than the thickness of the gate insulating layer 7a. Herein, the thickness refers to the dimension along the direction in which the semiconductor epitaxial wafer 1 faces the gate insulating layer 7a.
[0112] Among them, the semiconductor device can be a planar gate semiconductor device or a trench gate semiconductor device. When the semiconductor device is a planar gate semiconductor device, refer to Figure 10 , the gate insulating layer 7a is disposed on the surface of the semiconductor epitaxial wafer 1, and the gate electrode layer 31 is disposed on the surface of the gate insulating layer 7a facing away from the semiconductor epitaxial wafer 1. The gate insulating layer 7a is used to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, and when the gate insulating layer 7a and the gate electrode layer 31 also extend on the second doped region 12 and at least a part of the third doped region 2, the gate insulating layer 7a is also used to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the second doped region 12, and the third doped region 2. When the semiconductor device is a trench gate semiconductor device, not shown in the figure, the gate structure 31a extends along the surface of the semiconductor epitaxial wafer 1 and extends into the semiconductor epitaxial wafer 1, and the gate insulating layer 7a wraps the gate electrode layer 31 to isolate the gate electrode layer 31 from the semiconductor epitaxial wafer 1, the second doped region 12, the third doped region 2, and the first doped region 13.
[0113] The passivation layer 7c covers the second conductive layer 5. Specifically, the passivation layer 7c wraps the source pad 51 to isolate the source pad 51, and the region of the passivation layer 7c corresponding to the source pad 51 has a fifth opening 71 so that a part of the source pad 51 is exposed through the fifth opening 71. Further, the passivation layer 7c also wraps the gate pad 52 to isolate the gate pad 52, and the region of the passivation layer 7c corresponding to the gate pad 52 has a sixth opening 72 so that a part of the gate pad 52 is exposed through the sixth opening 72.
[0114] The drain electrode 18 is disposed on the surface of the semiconductor epitaxial wafer 1 facing away from the first doped region 13. The material of the drain electrode 18 can be the same as or similar to the material of the gate pad 52 and / or the source pad 51.
[0115] The semiconductor device provided in this embodiment enables the first conductive layer 3 to further include a capacitor plate layer 33, and insulates both the gate electrode layer 31 and the gate bus layer 32 from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a part of the gate pad 52 is stacked with a part of the capacitor plate layer 33 and is isolated by the dielectric layer 6, so as to form an additional gate-source capacitance by covering the part of the capacitor plate layer 33, the dielectric layer 6, and the part where the capacitor plate layer 33 and the gate pad 52 are stacked by the gate pad 52, thereby increasing Ciss / Crss, having a large adjustment range, and improving the crosstalk resistance ability of the semiconductor device. At the same time, it does not affect the active region A1 and the reliability of the semiconductor device.
[0116] In one embodiment, refer to Figures 11 to 12 , Figure 11 is a top view of some other embodiments of the semiconductor device provided in this application; Figure 12 is provided by one embodiment of this application Figure 11 a partial structural cross-sectional view of the semiconductor device shown along the C-C' line; a second semiconductor device is provided. Different from the semiconductor device provided in the first embodiment above: the first conductive layer 3 does not include the capacitor plate layer 33; a part of the gate bus layer 32 is stacked with a part of the source pad 51 and is isolated by the dielectric layer 6.
[0117] In this embodiment, the first opening 41 exposes a part of the gate bus layer 32. The dielectric layer 6 is disposed in the first opening 41 and covers the part of the gate bus layer 32 exposed through the first opening 41. A part of the source pad 51 extends into the first opening 41 and is located on the surface of the dielectric layer 6 away from the first exposed portion. It can be understood that in this embodiment, the part of the gate bus layer 32 covered by the dielectric layer 6, the dielectric layer 6, and the part of the source pad 51 covering the dielectric layer 6 together form an additional gate-source capacitance (Cgs), thereby increasing Ciss / Crss to reduce the risk of crosstalk in the semiconductor device.
[0118] In the above solution, compared with the first semiconductor device, the first conductive layer 3 does not need to separate the capacitor plate layer 33, and the area of a part of the gate bus layer 32 can be directly sacrificed for preparing Cgs. However, this solution may not be compatible with the original design of the semiconductor device, and at the same time, it will also limit the use margin of the package wire bonding.
[0119] In one embodiment, refer to Figure 13 , Figure 13 is a partial structural cross-sectional view of the semiconductor device provided in another embodiment of this application along the C-C' line; a third semiconductor device is provided. Different from the semiconductor device provided in the first embodiment above: the first conductive layer 3 does not include the capacitor plate layer 33; a part of the gate electrode layer 31 is stacked with a part of the source pad 51 and is isolated by the dielectric layer 6.
[0120] Specifically, a seventh opening is further formed in the interlayer dielectric layer 4, and the seventh opening exposes a portion of the gate electrode layer 31 facing away from the semiconductor epitaxial wafer 1 to form a third exposed portion; a dielectric layer 6 is disposed in the seventh opening and covers the third exposed portion. A portion of the source pad 51 extends into the seventh opening and is located on a surface of the dielectric layer 6 away from the first exposed portion; so that the third exposed portion, the dielectric layer 6, and a portion of the source pad 51 covering the dielectric layer 6 together form an additional gate-source capacitance (C gs ), thereby increasing Ciss / Crss to reduce the risk of crosstalk in the semiconductor device.
[0121] Among them, the dielectric layer 6 can be obtained by oxidizing the surface of the gate electrode layer 31.
[0122] In this solution, compared with the first semiconductor device, the first conductive layer 3 also does not need to separate the capacitor plate layer 33, and a part of the area of the gate electrode layer 31 can be directly sacrificed for preparing Cgs. However, in this case, since there is a large current in the active region A1, it is easy to generate heat, the structure is complex and the stress is high, and gate-source short circuit is more likely to occur.
[0123] In one embodiment, referring to Figure 14 and Figure 15 , a partial structural cross-sectional view of the semiconductor device provided by different embodiments of the present application along the C-C' line; different from the semiconductor device provided by the first embodiment: the first conductive layer 3 does not include a capacitor plate layer 33; a part of the source pad 51 and a part of the gate pad 52 are stacked and isolated by the dielectric layer 6, thereby forming a capacitor Cgs. That is, the stacked part of the source pad 51 and the gate pad 52 cooperates with the dielectric layer 6 to form a capacitor Cgs.
[0124] In one embodiment, as Figure 14 shown, the dielectric layer 6 is located in the edge termination region A2 and on a surface of the gate pad 52 away from the semiconductor epitaxial wafer 1; a part of the source pad 51 extends to a surface of the dielectric layer 6 away from the semiconductor epitaxial wafer 1 to be stacked with a part of the gate pad 52.
[0125] In another embodiment, as Figure 15 shown, the dielectric layer 6 is located in the active region A1 and on a surface of the source pad 51 away from the semiconductor epitaxial wafer 1; a part of the gate pad 52 extends to a surface of the dielectric layer 6 away from the semiconductor epitaxial wafer 1 to be stacked with a part of the gate pad 52.
[0126] In one embodiment, referring to Figure 16 , Figure 16Flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application; a method for manufacturing a semiconductor device is also provided. This method can be used to manufacture a first semiconductor device, and the manufacturing methods of other semiconductor devices are similar to this method. The method includes:
[0127] Step S1: Provide a semiconductor epitaxial wafer 1, where the semiconductor epitaxial wafer 1 includes an active region A1 and an edge termination region A2.
[0128] In some embodiments, the semiconductor epitaxial wafer 1 includes a substrate (not shown) and a semiconductor epitaxial layer (not shown) stacked. In some embodiments, the substrate is a SiC substrate with a crystal form of 4H SiC, and a SiC epitaxial layer is grown on the SiC substrate using a chemical vapor deposition process.
[0129] Step S2: Form a plurality of second doping regions 12, a plurality of third doping regions 2, and a plurality of first doping regions 13 in the active region A1.
[0130] Specifically, please refer to Figure 17 , Figure 17 which is a schematic diagram of a partial intermediate product structure of the semiconductor epitaxial wafer after being processed by step S2 in Figure 16 . A plurality of second doping regions 12, a plurality of third doping regions 2, and a plurality of first doping regions 13 can be formed in the active region A1 of the semiconductor epitaxial wafer 1 by ion implantation. Among them, the plurality of second doping regions 12, the plurality of third doping regions 2, and the plurality of first doping regions 13 all extend along the surface of the semiconductor epitaxial wafer 1 into the semiconductor epitaxial wafer 1; and the plurality of second doping regions 12, the plurality of third doping regions 2, and the plurality of first doping regions 13 extend from the active region A1 to the edge of the active region A1. The plurality of second doping regions 12 are arranged at intervals, and each second doping region 12 is provided with an adjacent third doping region 2 and a first doping region 13.
[0131] Please continue to refer to Figure 17 . In step S2, a terminal structure 11 is also formed synchronously in the edge termination region A2 to protect the device from damage such as overvoltage or overcurrent.
[0132] Step S3: Activate the semiconductor epitaxial wafer 1 at a high temperature, and form a wiring insulating layer 7b in the region of the first surface of the semiconductor epitaxial wafer 1 located in the edge termination region A2.
[0133] Specifically, a dielectric material layer can be grown by a thermal oxidation method, and then the oxidation and annealing temperature range is 1200°C - 1450°C, the oxidation time is 10 min - 30 min, the annealing time is 30 min - 300 min, and finally a wiring insulating layer 7b located in the edge termination region A2 is formed by patterning.
[0134] Refer to Figures 18 to 19 , Figure 18is a schematic diagram of a partial intermediate product structure after the semiconductor epitaxial wafer is processed through step S3 in Figure 16 ; Figure 19 is Figure 18 a partial structural cross-sectional view of the semiconductor device shown along the C-C' line. The routing insulating layer 7b surrounds the active region A1.
[0135] Step S4: Form a first conductive layer 3 on the first surface of the semiconductor epitaxial wafer 1; the first conductive layer 3 includes a capacitor plate layer 33, and a gate electrode layer 31 and a gate bus layer 32 that are electrically connected to each other; the gate electrode layer 31 is disposed in the active region A1, and the gate bus layer 32 is disposed in the edge termination region A2; both the gate electrode layer 31 and the gate bus layer 32 are insulated from the capacitor plate layer 33.
[0136] Combined with Figure 9 , in a specific implementation process, before step S4, a gate insulating layer 7a is further formed on the surface of the semiconductor device. Among them, the gate insulating layer 7a can be formed by the same process as the routing insulating layer 7b; however, due to their different thicknesses, the routing insulating layer 7b and the gate insulating layer 7a are not formed in the same step, and there is no order between them.
[0137] Among them, the gate electrode layer 31 is specifically formed on the surface of the gate insulating layer 7a facing away from the semiconductor epitaxial wafer 1; the gate bus layer 32 and the capacitor plate layer 33 are specifically formed on the surface of the routing insulating layer 7b facing away from the semiconductor epitaxial wafer 1.
[0138] In a specific implementation process, the gate electrode layer 31, the gate bus layer 32, and the capacitor plate layer 33 can be formed in the same step by magnetron sputtering or chemical vapor deposition. Specifically, a gate material can be formed on the entire surface of the semiconductor epitaxial wafer 1 on which the routing insulating layer 7b and the gate insulating layer 7a are formed. Among them, the gate material can be polysilicon or a conductive metal material, and then the gate material is patterned to form a plurality of layers disposed on the gate electrode layer 31, the gate bus layer 32, and the capacitor plate layer 33.
[0139] Step S5: Form an interlayer dielectric layer 4 on the first conductive layer 3, and expose at least a part of the capacitor plate layer 33.
[0140] Combined with Figures 20 to 21 , Figure 20 is a top view of a partial intermediate product structure after the semiconductor epitaxial wafer goes through step S5; Figure 21 is Figure 20 a partial structural cross-sectional view of the structure shown along the C-C' line. In some embodiments, the interlayer dielectric layer 4 is formed by magnetron sputtering or chemical vapor deposition, and the material of the interlayer dielectric layer 4 can be silicon oxide or silicon nitride, etc.
[0141] The interlayer dielectric layer 4 has a first opening 41, and the first opening 41 exposes a part of the capacitor electrode layer 33 and forms a part to be converted.
[0142] Step S6: Oxidize the part of the capacitor electrode layer 33 that exposes the interlayer dielectric layer 4 to form a dielectric layer 6.
[0143] See Figures 22 to 23 , Figure 22 is a top view of a partial intermediate product structure of the semiconductor epitaxial wafer after being processed by step S6 in Figure 16 ; Figure 23 is Figure 22 a partial structural cross-sectional view of the structure shown along the C-C' line. Specifically, a high-quality thermally oxidized silicon dioxide dielectric layer 6 can be obtained using a mature silicon oxidation process. In the specific implementation process, the part to be converted is specifically oxidized, so that the part of the part to be converted that is away from the semiconductor epitaxial wafer 1 is oxidized to form the dielectric layer 6, and the unoxidized part of the part to be converted forms a first exposed part.
[0144] Step S7: Pattern the interlayer dielectric layer 4 to expose at least part of the first doping region 13 and at least part of the gate bus layer 32; and pattern the dielectric layer 6 or the interlayer dielectric layer 4 to expose a part of the first exposed part.
[0145] Among them, in combination with Figure 5 , the interlayer dielectric layer 4 has a third opening 43 and a fourth opening 44; the third opening 43 is located in the active region A1 to expose at least part of the first doping region 13; the fourth opening 44 is located in the edge terminal region A2 to expose at least part of the gate bus layer 32.
[0146] In some implementation processes, as shown in Figure 5 , an opening 61 can be further formed on the dielectric layer 6 to expose a part of the first exposed part, and the subsequently formed source pad 51 can be electrically connected to the electrode plate layer through the opening 61. Of course, as shown in Figure 6a , a second opening 42 can be formed on the interlayer dielectric layer 4 to expose a part of the first exposed part, that is, the second exposed part above, so that the source pad 51 contacts the second exposed part through the second opening 42.
[0147] In some specific implementation processes, ohmic contact metal can also be formed in each third opening 43. Among them, the ohmic contact metal can be formed in the third opening 43 by evaporation, magnetron sputtering, and patterning. The annealing process temperature range is 800°C - 1100°C, and the time range is 60s - 300s.
[0148] Step S8: Form a second conductive layer 5 on the interlayer dielectric layer 4; the second conductive layer 5 includes a source pad 51 and a gate pad 52; the source pad 51 is disposed at least in the active region A1 and is electrically connected to the first doped region 13; the gate pad 52 is disposed at least in the edge termination region A2 and is electrically connected to the gate bus layer 32.
[0149] Combined with Figure 2 and Figure 3 , in some embodiments, a metal layer is formed over the entire surface of the interlayer dielectric layer 4 by evaporation or magnetron sputtering, and then patterned to form the source pad 51 and the gate pad 52 at least partially located in the edge termination region A2.
[0150] The source pad 51 is disposed on the interlayer dielectric layer 4 and extends into each third opening 43 and is metallically connected to the ohmic contact within each third opening 43, and thus connected to each first doped region 13, and the gate pad 52 is disposed on the interlayer dielectric layer 4 and extends into the fourth opening 44 and is connected to the gate bus layer 32.
[0151] Step S9: Form a passivation layer 7c covering the source pad 51 and the gate pad 52; wherein, the region of the passivation layer 7c corresponding to the source pad 51 has an eighth opening, and the region of the passivation layer 7c corresponding to the gate pad 52 has a ninth opening.
[0152] Wherein, the formation process of the passivation layer 7c can be the same as that of the interlayer dielectric layer 4, which will not be elaborated here.
[0153] Combined with Figure 10 , specifically, the passivation layer 7c is used to isolate the source pad 51 and to isolate the gate pad 52.
[0154] Step S10: Form a drain pad on the side of the semiconductor epitaxial wafer 1 facing away from the source pad 51 and the gate pad 52.
[0155] In some embodiments, the surface of the substrate on the side facing away from the source pad 51 and the gate pad 52 can be thinned first; then the drain pad is formed. Specifically, an ohmic contact can be formed on the back surface of the semiconductor epitaxial wafer 1 first, and then a metal layer covering the entire surface is formed on the back surface of the semiconductor epitaxial wafer 1 by evaporation or magnetron sputtering as the drain pad.
[0156] Specifically, in the manufacturing method of the semiconductor device provided by the embodiments of the present application, a capacitor plate layer 33 is formed on the same layer as the gate electrode layer 31 and the gate bus layer 32, and both the gate electrode layer 31 and the gate bus layer 32 are insulated from the capacitor plate layer 33; the source pad 51 is electrically connected to the capacitor plate layer 33; a part of the gate pad 52 is stacked with a part of the capacitor plate layer 33 and is isolated by the dielectric layer 6, so as to form an additional gate-source capacitance by covering the part of the capacitor plate layer 33, the dielectric layer 6, and the stacked part of the capacitor plate layer 33 and the gate pad 52 with the gate pad 52, thereby increasing the ratio of Ciss to Crss to reduce the risk of crosstalk in the semiconductor device. At the same time, this design only involves the modification of the position of the gate pad 52 and does not affect the reliability of the active region A1 and the semiconductor device. In addition, by disposing the gate bus layer 32 on the edge terminal region A2, compared with the prior art in which the gate bus layer 32 is disposed in the active region A1, the area of the active region A1 can be saved, so that the semiconductor device is basically the active region A1 except for the edge terminal region A2, thereby improving the current output ability of the device and reducing the on-resistance. Moreover, the gate bus layer 32 is connected to the end of each gate structure 31a extending to the edge of the active region A1, and the gate bus layer 32 can drive each gate structure 31a, thus not affecting the reliability of the device.
[0157] The above are only the embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.
Claims
1. A semiconductor device, characterized in that, Comprising: A semiconductor epitaxial wafer, including an active region and an edge termination region surrounding the active region; A plurality of first doping regions and a plurality of second doping regions, the plurality of first doping regions being disposed in the active region, and the first doping regions and the second doping regions having different conduction types; A first conductive layer, including a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge termination region; the first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are both insulated from the capacitor plate layer; An interlayer dielectric layer covering the first conductive layer; The interlayer dielectric layer has a first opening, such that a part of the capacitor plate layer is exposed to form a first exposed portion; A second conductive layer disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is at least disposed in the active region and is electrically connected to the first doping region; the gate pad is at least disposed in the edge termination region and is electrically connected to the gate bus layer; A dielectric layer disposed in the first opening and covering the first exposed portion; the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer; Wherein, the dielectric layer has an opening; The opening is spaced from a side wall of the first opening of the interlayer dielectric layer along a first direction; a part of the source pad is sequentially in contact and electrically connected to the first exposed portion through the first opening and the opening; a part of the gate pad is stacked on a side of the dielectric layer away from the capacitor plate layer.
2. The semiconductor device according to claim 1, wherein The opening is disposed at an edge of the dielectric layer close to the active region.
3. The semiconductor device according to claim 1, wherein The first opening has opposite first side walls and second side walls along a first direction; along the first direction, a first distance between the opening and the first side wall is less than a second distance between the opening and the second side wall.
4. The semiconductor device according to claim 3, wherein The first opening has opposite third side walls and fourth side walls along a second direction; along the second direction, the opening is spaced from the third side wall, and the opening is spaced from the fourth side wall.
5. The semiconductor device according to claim 4, wherein A length of the opening along the second direction is greater than a length of the opening along the first direction.
6. A semiconductor device, characterized in that, Comprising: A semiconductor epitaxial wafer, including an active region and an edge termination region surrounding the active region; A plurality of first doping regions disposed in the active region; A first conductive layer, including a gate electrode layer and a gate bus layer that are electrically connected to each other; the gate electrode layer is disposed in the active region, and the gate bus layer is disposed in the edge termination region; the first conductive layer further includes a capacitor plate layer, and the gate electrode layer and the gate bus layer are both insulated from the capacitor plate layer; An interlayer dielectric layer covering the first conductive layer; The interlayer dielectric layer has a first opening, such that a part of the capacitor plate layer is exposed to form a first exposed portion; A second conductive layer is disposed on a side of the interlayer dielectric layer away from the semiconductor epitaxial wafer; the second conductive layer includes a source pad and a gate pad; the source pad is disposed at least in the active region and is electrically connected to the first doped region; the gate pad is disposed at least in the edge termination region and is electrically connected to the gate bus layer; A dielectric layer is disposed in the first opening and covers the first exposed portion; the thickness of the dielectric layer is less than the thickness of the interlayer dielectric layer; Wherein, the dielectric layer includes a first part and a second part arranged at intervals, and an opening is formed between the first part and the second part; a part of the source pad is in contact electrical connection with the first exposed portion through the first opening and the opening in sequence; a part of the gate pad is stacked on a side of the dielectric layer away from the capacitor plate layer.
7. The semiconductor device according to claim 6, wherein, The first part is located on a side of the second part close to the active region along a first direction.
8. The semiconductor device according to claim 7, wherein, The width of the first part along the first direction is less than the width of the second part along the first direction.
9. The semiconductor device according to claim 7, wherein, The dielectric layer further includes a third part and a fourth part arranged at intervals along a second direction; the first part, the second part, the third part and the fourth part jointly enclose to form the opening.
10. The semiconductor device according to claim 9, wherein, The distance between the third part and the fourth part is greater than the distance between the first part and the second part.