Pixel cell for image sensor with vertical transfer gate

Abstract

The invention relates to a pixel cell for an image sensor having a vertical transfer gate. A pixel unit for an image sensor is described. The pixel cell includes a photodiode disposed within a semiconductor substrate and a transfer gate coupled to the photodiode. The photodiode includes a shallow doped region and a deep doped region having the same conductivity type. The shallow doped region is disposed between the first side of the semiconductor substrate and the deep doped region. The transfer gate includes a vertical portion that is adjacent to the lightly doped region and extends into the semiconductor substrate from the first side toward the deeply doped region of the photodiode. When the pixel unit is viewed from a plan view, the lightly doped region includes a base segment and a protrusion extending from the base segment. The protrusion is separated from the vertical portion by a first lateral separation distance, and the base segment is separated from the vertical portion by a second lateral separation distance different from the first lateral separation distance.

Description

Technical Field

[0001] The present disclosure generally relates to image sensors, and more particularly but not exclusively, to complementary metal oxide semiconductor image sensors. Background Art

[0002] Image sensors are a type of semiconductor device that have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, etc. (e.g., resolution, power consumption, dynamic range, size, etc.) of the image sensors in as many ways as possible through both device architecture design and image acquisition processing.

[0003] Typical image sensors operate in response to image light reflected from an external scene incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges immediately after absorbing the image light. The image charges generated by the pixels can be measured as an analog output image signal that varies with the incident image light on the column bit lines. In other words, the amount of the generated image charges is proportional to the intensity of the image light, which is read out as an analog image signal from the column bit lines and converted into a digital value to generate a digital image (i.e., image data) representing the external scene. Summary of the Invention

[0004] Embodiments of the present disclosure provide a pixel unit for an image sensor, which includes: a photodiode disposed in a semiconductor substrate, the semiconductor substrate including a first side and a second side opposite to the first side, wherein the photodiode includes a lightly doped region and a heavily doped region each having the same conductivity type, and wherein the lightly doped region is disposed between the first side of the semiconductor substrate and the heavily doped region; a transfer gate coupled to the photodiode, the transfer gate including a vertical portion adjacent to the lightly doped region and extending from the first side into the semiconductor substrate toward the heavily doped region of the photodiode, wherein, when viewing the pixel unit from a plan view, the lightly doped region includes a base segment and a protrusion extending from the base segment, wherein the protrusion is separated from the vertical portion by a first lateral separation distance, and the base segment is separated from the vertical portion by a second lateral separation distance different from the first lateral separation distance.

[0005] Another embodiment of the present disclosure provides an image sensor, which includes: a plurality of pixel units arranged to form a pixel unit array, and each pixel unit included in the plurality of pixel units includes: a floating diffusion region disposed within a semiconductor substrate, the semiconductor substrate including a first side and a second side opposite to the first side; a plurality of photodiodes disposed within the semiconductor substrate and arranged to laterally surround the floating diffusion region, wherein each photodiode included in the plurality of photodiodes includes: a lightly doped region including a base segment and a protrusion extending from the base segment; and a heavily doped region, wherein the lightly doped region is disposed between the first side of the semiconductor substrate and the heavily doped region, and wherein the lightly doped region and the heavily doped region have the same conductivity type; and a plurality of transfer gates, each corresponding transfer gate included in the plurality of transfer gates being adapted to electrically couple the corresponding photodiode included in the plurality of photodiodes to the floating diffusion region, wherein the corresponding transfer gate includes a vertical portion extending into the semiconductor substrate from the first side close to the lightly doped region of the corresponding photodiode, and wherein the plurality of photodiodes and the plurality of transfer gates are arranged to surround the floating diffusion region such that when viewing the pixel unit from a plan view, there is mirror symmetry about two vertical axes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like components throughout the various views unless otherwise specified. Not all instances of an element need to be labeled so as not to clutter the drawings in inappropriate cases. The drawings are not necessarily to scale, and emphasis is instead placed on illustrating the described principles.

[0007] Figure 1 A cross-sectional view illustrating a photodiode included in a pixel unit of an image sensor having a vertical transfer gate according to an embodiment of the present disclosure.

[0008] Figure 2A A plan view illustrating a photodiode having at least two protrusions included in a pixel unit of an image sensor having a vertical transfer gate according to an embodiment of the present disclosure.

[0009] Figure 2B An illustration according to an embodiment of the present disclosure Figure 2A An expanded plan view of the pixel unit illustrated in

[0010] Figure 2C A plan view illustrating an alternative pixel unit included in an image sensor having a vertical transfer gate according to an embodiment of the present disclosure.

[0011] Figure 2DThe graphical illustration shows a simulation of current density, which shows the main transfer path of a pixel unit included in an image sensor having a vertical transfer gate according to an embodiment of the present disclosure.

[0012] Figure 3A The graphical illustration shows a plan view of a photodiode having at least one protrusion included in a pixel unit of an image sensor having a vertical transfer gate according to an embodiment of the present disclosure.

[0013] Figure 3B The graphical illustration shows according to an embodiment of the present disclosure Figure 3A an extended plan view of the pixel unit illustrated therein.

[0014] Figure 4 The graphical illustration shows a stacked image sensor including a plurality of pixel units (each pixel unit including a vertical transfer gate) according to an embodiment of the present disclosure.

[0015] Figure 5 is a functional block diagram of an imaging system including a plurality of pixel units (each pixel unit including a vertical transfer gate) according to an embodiment of the present disclosure.

[0016] Throughout several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to assist in improving the understanding of the various embodiments of the present invention, the dimensions of some of the elements in the figures may be enlarged relative to other elements. Additionally, commonly known elements that are useful or necessary in a commercially viable embodiment are typically not depicted to facilitate an unobstructed view of the various embodiments of the present invention. Detailed Description

[0017] Embodiments of devices, systems, and / or methods related to pixel units for an image sensor having a vertical transfer gate are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0018] An image sensor may be characterized based on transfer or image lag, which is related to the time it takes to transfer photo-generated image charge from a given photodiode included in a pixel cell of the image sensor to a floating diffusion region coupled to the given photodiode via a transfer gate. Image lag can occur when an image of an external scene captured by the image sensor contains information from a previously captured image (e.g., when multiple images are captured successively). Another metric used to characterize an image sensor is referred to as white pixels, which are associated with dark current. When the dark current increases, the image sensor can produce an inaccurate representation of a dark scene, which can be expressed as "white pixels" in the image produced by the image sensor. Embodiments disclosed herein utilize a transfer gate that includes a vertical portion extending into a semiconductor substrate in which a given photodiode is formed. The given photodiode of embodiments of the present disclosure includes a lightly doped region and a heavily doped region, where the lightly doped region has a peak doping concentration higher than the peak doping concentration of the heavily doped region. It has been found that the spacing between the given photodiode and the vertical portion of the transfer gate and the lateral separation distance between the lightly doped region of the given photodiode and the vertical portion of the transfer gate are highly correlated. Thus, when attempting to reduce image lag, there is typically a trade-off because it generally results in an increase in dark current.

[0019] However, the pixel cells of embodiments of the present disclosure are configured to improve both image lag and dark current. Specifically, the lightly doped region and the transfer gate are non-uniformly separated. This is achieved at least in part by structuring the lightly doped region of the given photodiode to include a base segment and a protrusion extending from the base segment. In one embodiment, the lateral separation distance between the vertical portion of the transfer gate and the protrusion is different from the lateral separation distance between the vertical portion of the transfer gate and the base segment. The non-uniform separation distance facilitates reducing both image lag and dark current. In the same or another embodiment, the given photodiode is implanted or otherwise configured such that the distance between the vertical portion of the transfer gate and the region of the given photodiode close to the main transfer path is close to the shortest lateral separation distance to reduce image lag. In the same or another embodiment, the lightly doped region of the given photodiode, the vertical portion of the transfer gate, and the floating diffusion region are jointly configured such that an axis in a plane parallel to the substrate surface plane extending through both the lightly doped region and the floating diffusion region is tangent to the vertical portion of the transfer gate. More generally, the lightly doped region is structured to facilitate reducing both image lag and dark current, which will be discussed throughout the present disclosure.

[0020] Figure 1 FIG. illustrates a cross-sectional view of a photodiode 115 included in a pixel cell 105 of an image sensor having a vertical transfer gate (i.e., transfer gate 140) according to an embodiment of the present disclosure. It should be noted that Figure 1The cross-sectional view provided corresponds to a side view or profile view of the image sensor along the Y-Z plane according to coordinate system 199. Thus, the x-direction of coordinate system 199 extends into and out of the plane of the paper illustrated. In the illustrated embodiment, pixel unit 105 includes: a semiconductor substrate 102; a first side 104 of semiconductor substrate 102; a second side 106 of semiconductor substrate 102, which is opposite the first side 104; a color filter 108; a microlens 110; a metal grid 112; a photodiode 115, which includes a lightly doped region 116, a heavily doped region 124, and a pinned region 126; a gate dielectric 130, which includes a planar gate dielectric 130-P and a vertical gate dielectric 130-V; a transfer gate 140, which includes a planar portion 141 and a vertical portion 142; and a floating diffusion region 148. Figure 1 The semiconductor substrate 102 may correspond to a part or all of a semiconductor wafer (e.g., a silicon wafer). In some embodiments, semiconductor substrate 102 comprises or is otherwise formed from: silicon, silicon-germanium alloy, germanium, silicon carbide alloy, indium gallium arsenide alloy, any other alloy formed from III-V compounds, combinations thereof, one or more epitaxial layers of the foregoing materials, or a bulk substrate thereof. More specifically, semiconductor substrate 102 may correspond to any semiconductor material or combination of materials that can be doped or otherwise configured to facilitate the formation of a photosensitive region of photodiode 115 in pixel unit 105. For example, in some embodiments, semiconductor substrate 102 may correspond to one or more epitaxial layers (e.g., P- or N-doped silicon) formed on a carrier wafer. In this embodiment, during fabrication, photodiode 115 may be formed in one or more epitaxial layers corresponding to semiconductor substrate 102, and the carrier wafer may be removed or otherwise thinned. In one embodiment, semiconductor substrate 102 is formed of pure or impure silicon having regions that are sufficiently doped to form photodiode 115. For example, lightly doped region 116, heavily doped region 124, and pinned region 126 of photodiode 115 may each correspond to regions of semiconductor substrate 102 doped with appropriate impurities to form a photosensitive region capable of generating image charge in response to incident light 189.

[0021]

[0022] ​It should be understood that in the illustrated embodiment, the photodiode 115 is a pinned photodiode, where the pinned region 126 has a conductivity type opposite to that of the lightly doped region 116 and the heavily doped region 124. In other words, the lightly doped region 116 and the heavily doped region 124 have the same conductivity type, which is opposite to the conductivity type of the pinned region 126 and may also be opposite to the conductivity type of the semiconductor substrate 102. For example, in some embodiments, the pinned region 126 has P-type conductivity and is doped with acceptor impurities (e.g., boron, aluminum, gallium, or indium), while the lightly doped region 116 and the heavily doped region 124 have N-type conductivity and are doped with donor impurities (e.g., phosphorus, arsenic, antimony, or bismuth). In another embodiment, the pinned region 126 has N-type conductivity, while the lightly doped region 116 and the heavily doped region 124 have P-type conductivity. Additionally, it should be understood that in some embodiments, the region of the semiconductor substrate 102 that is close to or otherwise directly abuts the lightly doped region 116 and the heavily doped region 124 has a conductivity type opposite to that of the lightly doped region 116 and the heavily doped region 124 to form a PN junction to facilitate the generation of optically generated image charges in response to incident light 189. Thus, in some embodiments, the semiconductor substrate 102 has a conductivity type opposite to that of the lightly doped region 116 and the heavily doped region 124 (e.g., when the lightly doped region 116 and the heavily doped region 124 have N-type conductivity, the semiconductor substrate 102 has P-type conductivity). In the same or other embodiments, the lightly doped region 116 and the heavily doped region 124 may be formed within a well (not illustrated) formed in the semiconductor substrate 102 that has a conductivity type opposite to that of the lightly doped region 116 and the heavily doped region 124 (e.g., when the lightly doped region 116 and the heavily doped region 124 have N-type conductivity, the well formed in the semiconductor substrate 102 that directly abuts the lightly doped region 116 and / or the heavily doped region 124 has P-type conductivity). It should be understood that the lightly doped region 116 and the heavily doped region 124 may have different doping concentrations. For example, in one embodiment, the heavily doped region 124 may have a lower doping concentration relative to the lightly doped region 116 (e.g., a lower peak doping concentration or a lower average doping concentration).

[0023] As Figure 1As illustrated, the lightly doped region 116, the heavily doped region 124, and the pinned region 126 are each formed within the semiconductor substrate 102 and are thus each disposed between the first side 104 and the second side 106 of the semiconductor substrate 102. Additionally, the lightly doped region 116 is disposed between the heavily doped region 124 and the pinned region 126. Further, the lightly doped region 116 is disposed between the first side 104 of the semiconductor substrate 102 and the heavily doped region 124. Similarly, the heavily doped region 124 is disposed between the lightly doped region 116 and the second side 106 of the semiconductor substrate 102. In the illustrated embodiment, the lightly doped region 116 is at least partially defined by a dimension 117 (e.g., a length or width associated with the lightly doped region 116 along the Y direction of the coordinate system 199), and the heavily doped region 124 is at least partially defined by a dimension 125 (e.g., a length or width associated with the heavily doped region 124 along the Y direction of the coordinate system 199). The dimension 117 and the dimension 125 are parallel to each other, as Figure 1 illustrated. In an embodiment of the present disclosure, the dimension 125 of the heavily doped region 124 may be greater than the dimension 117. More generally, the lateral area (e.g., along the x-y plane of the coordinate system 199) of the heavily doped region 124 of the photodiode 115 is greater than the lateral area (e.g., along the x-y plane of the coordinate system 199) of the lightly doped region 116 (see, e.g., Figures 2A to 3B ).

[0024] In the illustrated embodiment, the microlens 110 and the color filter 108 are each optically aligned with the lightly doped region 116 and the heavily doped region 124. The microlens 110 (e.g., molded plastic or polymeric material) is structured to form an optical structure to focus or otherwise direct incident light 189 through the corresponding color filter 108 and beyond the second side 106 of the semiconductor substrate 102 to be incident on the lightly doped region 116 and / or the heavily doped region 124. Thus, in some embodiments, the second side 106 of the semiconductor substrate 102 may be referred to as a light receiving surface. The color filter 108 corresponds to a red color filter, a green color filter, a blue color filter, an infrared color filter, a clear, transparent or white color filter, a cyan color filter, a magenta color filter, a yellow color filter, a black color filter, or any other type of color filter that selectively transmits a specific wavelength range contained in the incident light 189 such that the image charge generated photoelectrically by the photodiode 115 in response to the incident light 189 represents the specific wavelength range.

[0025] The pixel unit 105 also includes a transfer gate 140 (e.g., polysilicon), which is coupled to the photodiode 115 to facilitate the transfer (e.g., in response to a transfer signal applied to the transfer gate 140) of the photo-generated image charge from the photodiode 115 to the floating diffusion region 148. The transfer gate 140 may be referred to as a vertical transfer gate within the present disclosure because the transfer gate 140 includes both a planar portion 141 and a vertical portion 142. As illustrated, the planar portion 141 of the transfer gate 140 is disposed close to the first side 104 of the semiconductor substrate, and the vertical portion 142 of the transfer gate extends from the planar portion 141 into the semiconductor substrate 102 (e.g., through the first side 104) toward the second side 106 of the semiconductor substrate. In other words, the planar portion 141 of the transfer gate 140 is coupled to the vertical portion 142 to form an individual gate electrode to form a transfer transistor to facilitate the transfer of the image charge photo-generated by the photodiode 115 to the floating diffusion region 148. In the illustrated embodiment, the planar portion 141 of the transfer gate 140 is at least partially defined by a dimension 149 (e.g., the length or width of the planar portion 141), and the vertical portion 142 of the transfer gate 140 is at least partially defined by a dimension 143 (e.g., length or width). In some embodiments, the dimension 143 and the dimension 149 are parallel to each other, as Figure 1 illustrated. In an embodiment of the present disclosure, the dimension 149 of the planar portion 141 is greater than the dimension 143 of the vertical portion. In other words, the lateral dimension (e.g., along the x-axis or y-axis of the coordinate system 199) of the planar portion 141 of the transfer gate 140 is greater than the corresponding lateral dimension of the vertical portion 142 of the transfer gate 140. More generally, the lateral area (e.g., along the x-y plane of the coordinate system 199) of the planar portion 141 is greater than the lateral area (e.g., along the x-y plane of the coordinate system 199, parallel to the lateral area of the planar portion 141) of the vertical portion 142. It should be understood that the geometric center of the vertical portion 142 may not be positioned to align with or otherwise overlap the corresponding geometric center of the planar portion 141 (see, for example, Figures 2A to 4 ). In other words, the geometric centers of the vertical portion 142 and the planar portion 141 do not overlap or are otherwise offset from each other.

[0026] The transfer transistor further includes a gate dielectric 130 (e.g., silicon dioxide, hafnium dioxide, other insulating materials, or combinations thereof), which may be segmented (for illustrative purposes) into a planar gate dielectric 130-P and a vertical gate dielectric 130-V. The planar gate dielectric and the vertical gate dielectric together isolate (physically and electrically) the transfer gate 140 from at least the lightly doped region 116, the heavily doped region 124, and the floating diffusion region 148 that form the source / drain regions of the transfer transistor. The planar gate dielectric 130-P extends proximate to the first side 104 of the semiconductor substrate and is disposed between the planar portion 141 of the transfer gate and the lightly doped region 116 of the photodiode 115. The vertical gate dielectric 130-V surrounds the vertical portion 142 of the transfer gate 140 such that the vertical gate dielectric 130-V is disposed between the lightly doped region 116 and the vertical portion 142 of the transfer gate 140, the vertical gate dielectric 130-V is disposed between the floating diffusion region 148 and the vertical portion 142 of the transfer gate 140, and the vertical gate dielectric 130-V is disposed between the heavily doped region 124 and the vertical portion 142 of the transfer gate 140. In some embodiments, the semiconductor substrate 102 may be doped to form a passivation region 135 disposed proximate to the vertical gate dielectric 130-V. The passivation region 135 extends around the vertical gate dielectric 130-V, which may provide functionality similar to that of the pinned region 126 and enhance the performance of the transfer transistor. Thus, the passivation region 135 has a conductivity type opposite to that of the lightly doped region 116 and the heavily doped region 124 (e.g., when the conductivity types of the lightly doped region 116 and the heavily doped region 124 are N-type, the conductivity of the passivation region 135 is P-type). In some embodiments, the passivation region 135 may have an asymmetric thickness to reduce the transfer lag of image charge from the photodiode 115 to the floating diffusion region 148. The asymmetric thickness results in the thickness of the passivation region 135 disposed between the lightly doped region 116 and the vertical portion 142 of the transfer gate 140 being less than the thickness of the passivation region 135 disposed between the floating diffusion region 148 and the vertical portion 142 of the transfer gate 140. However, it should be understood that in other embodiments, the thickness of the passivation region 135 may be substantially uniform (e.g., as illustrated), or according to embodiments of the present disclosure, the passivation region 135 may be omitted.

[0027] As Figure 1As illustrated, the vertical portion 142 of the transfer gate 140 extending into the semiconductor substrate 102 is disposed adjacent to the lightly doped region 116. The lightly doped region 116 and the vertical portion 142 of the transfer gate 140 may be arranged to vertically overlap the heavily doped region 124 (e.g., disposed on or above the heavily doped region). In some embodiments, the vertical portion 142 extends deeper into the semiconductor substrate 102 than the lightly doped region 116 (e.g., from the first side 104 to the second side 106). In the illustrated embodiment, a first lateral separation distance 151 is disposed between the vertical portion 142 of the transfer gate 140 and the lightly doped region 116. The first lateral separation distance 151 is positioned to be proximate to or otherwise overlap the main transfer path extending between the photodiode 115 and the floating diffusion region 148 (see, e.g., Figures 2A to 2D ). In some embodiments, the first lateral separation distance 151 is less than any other lateral separation distance between the vertical portion 142 of the transfer gate 140 and the lightly doped region 116 (see, e.g., Figures 2A to 2D ). The main transfer path may be defined as the transfer channel path formed by the transfer gate 140 immediately after biasing between the photodiode 115 and the floating diffusion region 148, in which most of the photo-generated charges (e.g., electrons are emitted from the photodiode 115 via the lightly doped region 116) are collected and transferred to the floating diffusion region 148. As previously discussed, it has been found that the image lag of an image sensor including the pixel unit 105 can be improved by reducing the first lateral separation distance 151. However, it has been found that the trench etching utilized during the formation of the vertical portion 142 can cause surface and / or interface defects, and the negative consequences (e.g., an increase in white pixels and / or dark current of the image sensor) can be exacerbated when the vertical portion 142 of the transfer gate 140 and the lightly doped region 116 are uniformly separated and / or when the first lateral separation distance 151 decreases as the size of the pixel unit 105 decreases. To mitigate the white pixel and / or dark current problems, the lateral region of at least the lightly doped region 116 of the photodiode 115 is configured to be non-uniformly separated from the vertical portion 142 (see, e.g., Figures 2A to 3B ). In other words, the layout of the lightly doped region 116 is adjusted such that the shortest distance between the lightly doped region 116 and the vertical portion 142 (e.g., close to the main transfer path) can be reduced to minimize image lag, while the area between the lightly doped region 116 and the vertical portion 142 is increased to mitigate white pixels and / or dark current. This is achieved at least in part by configuring the lightly doped region 116 to include a base segment and one or more protrusions extending from the base segment such that when viewing the photodiode 115 from a plan view (e.g., as illustrated in the embodiment detailed in Figures 2A to 4 ), the vertical portion 142 of the transfer gate 140 and the lightly doped region 116 are non-uniformly separated, and embodiments thereof will be discussed in more detail below.

[0028] Figure 2A The figure illustrates a plan view of a photodiode 215 having at least two protrusions (e.g., a first protrusion 220 and a second protrusion 222) included in a pixel unit 205-1 of an image sensor having a vertical transfer gate 240 according to an embodiment of the present disclosure. The pixel unit 205-1 includes a photodiode 215, a transfer gate 240, and a floating diffusion region 248, each formed in or on a semiconductor substrate 202. The pixel unit 205-1 is a possible implementation of the pixel unit 105 and includes many similarly labeled elements. For example, Figure 2A the photodiode 215 including a lightly doped region 216 and a heavily doped region 224, the transfer gate 240 including a planar portion 241 and a vertical portion 242, and the floating diffusion region 248 may respectively correspond to Figure 1 the photodiode 115 including a lightly doped region 116 and a heavily doped region 124, the transfer gate 140 including a planar portion 141 and a vertical portion 142, and the floating diffusion region 148. In some embodiments, the vertical portion 242 may be surrounded by a region of the semiconductor substrate 202 doped with one or more dopants having a conductivity opposite to that of the lightly doped region 216 to reduce dark current. That is, a doped region having a conductivity opposite to that of the lightly doped region 216 (e.g., Figure 1 the passivation region 135 illustrated in Figure 2A is disposed between the lightly doped region 216 and the vertical portion 242. The doped region further surrounds the vertical portion 242 to provide surface passivation to reduce or minimize defects and to produce an improved dark current. It should be understood that not all elements of the pixel unit 205-1 must be included in Figure 1The pixel unit 105 illustrated in the figure, the photodiode 215 is adapted to generate an image charge in response to incident light, and the transfer gate 240 is adapted to transfer the image charge along the main transfer path (e.g., along the axis 261 extending between the protrusion 220 and the vertical portion 242) from the photodiode 215 to the floating diffusion region 248. In some embodiments, the axis 261 may be tangent to the vertical portion 242 of the transfer gate 240. In the illustrated embodiment, the main transfer path provided by the transfer gate 240 immediately after biasing may be formed as a lateral separation distance 251 between the protrusion 220 extending through the lightly doped region 216 and the vertical portion 242 of the transfer gate 240. The main transfer path is a transfer channel path formed by the transfer gate 240 immediately after biasing between the photodiode 215 (the lightly doped region 216 of the photodiode 215) and the floating diffusion region 248, in which most of the generated image charges (e.g., electrons emitted from the lightly doped region 216) are collected and transferred to the floating diffusion region 248.

[0029] Referring back Figure 2A , the lightly doped region 216 and the heavily doped region 224 are formed in the semiconductor substrate 202. When viewing the pixel unit 205-1 from a plan view, the lightly doped region 216 includes a base segment 218 and protrusions 220 (e.g., a first protrusion) and 222 (e.g., a second protrusion) extending from the base segment 218. It should be understood that there are no intermediate elements disposed between the base segment 218 and the protrusions 220 and 222, as the protrusions 220 and 222 are directly connected to the base segment 218. In some embodiments, the lightly doped region 216 of the photodiode 215 consists of the base segment 218 and the protrusions 220 and 222. In other embodiments, the protrusion 222 may be omitted, such that the lightly doped region 216 of the photodiode 215 consists of the base segment 218 and the protrusion 220. In other embodiments, the photodiode 215 may include additional protrusions (e.g., in addition to the protrusions 220 and 222) extending from the base segment 218, such that the lightly doped region 216 includes more than two protrusions. In some embodiments, the lightly doped region 216 has a "J" or "C" shape to at least partially surround the vertical portion 242 of the transfer gate 240 (e.g., extending around at least its two sides). In other words, the protrusion 222 (e.g., the second protrusion) extends from the base segment 218 opposite to the protrusion 220 (e.g., the first protrusion), such that the lightly doped region 216 at least partially surrounds the vertical portion 242 of the transfer gate 240. More specifically, the protrusions 220 and 222 extend to opposite ends of the base segment 218 (e.g., opposite in the y direction with respect to the coordinate system 299), and further extend toward the vertical portion 242 of the transfer gate 240, such that the protrusions 220 and 222 each face the vertical portion 242.

[0030] As illustrated, the lightly doped region 216 is separated from the vertical portion 242 of the transfer gate by a lateral separation distance 251 (e.g., a first lateral separation distance), a lateral separation distance 233 (e.g., a second lateral separation distance), and a lateral separation distance 235 (e.g., a third lateral separation distance). It should be understood that the lateral separation distance 251 is different from the lateral separation distances 233 and 235. Thus, the lightly doped region 216 is non-uniformly separated from the vertical portion 242 of the transfer gate 240 to facilitate image lag and dark current reduction. The protrusion 220 is separated from the vertical portion 242 by the lateral separation distance 251. The substrate segment 218 is separated from the vertical portion 242 by the lateral separation distance 233. The protrusion 222 is separated from the vertical portion 242 by the lateral separation distance 235. It should be understood that the lateral separation distance 253 may correspond to the minimum separation distance between the vertical portion 242 and the protrusion 220, the lateral separation distance 233 may correspond to the minimum separation distance between the vertical portion 242 and the substrate segment 218, and the lateral separation distance 235 may correspond to the minimum separation distance between the vertical portion 242 and the protrusion 222. In some embodiments, the lateral separation distances 253, 233, and 235 are different. To configure the non-uniform separation between the lightly doped region 216 and the vertical portion 242, the protrusion 220 is positioned closer to the vertical portion 242 than either of the substrate segment 218 and the protrusion 222. Thus, the lateral separation distance 251 is less than any other lateral separation distance between the lightly doped region 216 and the vertical portion 242 of the transfer gate 240, including the lateral separation distances 233 and 235.

[0031] When viewed from as Figure 2AWhen viewing the planar pixel unit 205-1 illustrated in the figure, the first edge 253 of the vertical portion 242 extends adjacent to the first boundary 255 of the protrusion 220. In some embodiments, the first edge 253 of the vertical portion 242 extends parallel to the first boundary 255 of the protrusion 220 (e.g., along the y direction of the coordinate system 299). Additionally, the first edge 253 of the vertical portion 242 extends adjacent to the second boundary 257 of the substrate segment 218. In some embodiments, the first edge 253 of the vertical portion 242 extends parallel to the second boundary 257 of the substrate segment 218. In the illustrated embodiment, the first boundary 225 and the second boundary 257 of the protrusion 220 each directly face the first edge 253 of the vertical portion 242 (e.g., no intervening portion of the lightly doped region 216 is disposed therebetween). The vertical portion 242 of the transfer gate 240 further includes a second edge 254 perpendicular to the first edge 253. The protrusion 222 includes a third boundary 259 facing the second edge 254 such that the second edge 254 of the vertical portion 242 extends adjacent to the third boundary 259 of the protrusion 222. In some embodiments, the second edge 254 of the vertical portion 242 extends parallel to the third boundary 259 of the protrusion 222. In the illustrated embodiment, the third boundary 259 of the protrusion 222 directly faces the second edge 254 of the vertical portion 242 (e.g., no intervening portion of the lightly doped region 216 is disposed therebetween).

[0032] In an embodiment, the lightly doped region 216 is configured (e.g., via doping and implantation depth) as a connection portion of the photodiode 215 for connecting the deeply doped region 224 to the transfer channel provided by the transfer gate 240, and the deeply doped region 224 may be formed to configure a full well capacity for the photodiode 215 to accumulate image charges generated optically in response to incident light. As illustrated, the deeply doped region 224 of the photodiode 215 may have a larger lateral area than the combined lateral area of the lightly doped region 216 and the vertical portion 242 of the transfer gate 240 to increase the full well capacity of the photodiode 215. The transfer gate 240 further includes a planar portion 241 coupled to the vertical portion 242. It should be understood that the first side of the semiconductor substrate 202 (e.g., corresponding to Figure 1 the first side 104 of the semiconductor substrate 102 illustrated in the figure) is disposed between the planar portion 241 and the protrusion 220 of the lightly doped region 216. In other words, the planar portion 241 may be arranged to overlap the protrusion 220 in the depth direction (e.g., the z direction of the coordinate system 299). In Figure 2AIn the illustrated embodiment, the planar portion 241 completely covers the protrusion 220 and does not cover the protrusion 222 or otherwise overlap with the protrusion 222. In some embodiments, the doping concentration of the lightly doped region 216 is greater than that of the heavily doped region 224. In some embodiments, the doping profile of the photodiode 215 is a graded doping profile in the depth direction. In some embodiments, the doping concentration of the lightly doped region 216 near the axis 261 extending between the protrusion 220 and the vertical portion 242 is greater than that of other regions of the lightly doped region 216. In other words, the doping of the lightly doped region 216 can be maximum near the minimum lateral separation distance (e.g., the lateral separation distance 251) between the vertical portion 242 and the lightly doped region 216 to facilitate charge transfer (e.g., by increasing the electric field of the region of the lightly doped region 216 of the photodiode 215 near the main transfer path between the photodiode 215 and the floating diffusion region 248). In some embodiments, the first doping concentration of the protrusion 220 included in the lightly doped region 216 near the vertical portion 242 of the transfer gate 240 is greater than the second doping concentration of the substrate segment 218 to facilitate charge transfer while reducing dark current and white pixels. In some embodiments, the first doping concentration is at least 10%, 15%, 20% greater than the second doping concentration and up to about 25%.

[0033] In the illustrated embodiment, the substrate segment 218 is defined by dimensions 217 and 219 (e.g., length or width respectively or vice versa), the protrusion 220 is defined by dimensions 221 and 223 (e.g., length or width respectively or vice versa), and the protrusion 222 is defined by dimensions 227 and 229 (e.g., length or width respectively or vice versa). The dimensions 217, 223, and 229 are parallel. The dimensions 219, 221, and 227 are parallel. In the illustrated embodiment, the dimension 221 is less than the dimensions 219 and 227, and the dimension 219 is greater than the dimension 227. Similarly, the dimension 223 is less than the dimensions 217 and 229, and the dimension 217 is greater than the dimension 229. In other words, the substrate segment 218 is longer and / or wider than the protrusions 220 and 222. The vertical portion 242 is defined by dimensions 243 and 245 (e.g., length or width respectively or vice versa) that may be equal or different. In one embodiment, the vertical portion 242 is columnar.

[0034] Figure 2B Illustrating embodiments in accordance with the present disclosure Figure 2AExpanded plan view of pixel unit 205-1 illustrated in the figure. Pixel unit 205-1 includes a plurality of photodiodes, the plurality of photodiodes including photodiodes 215-1, 215-2, 215-3, and 215-4, which are arranged in a 2×2 photodiode array laterally surrounding floating diffusion region 248 and each electrically coupled to floating diffusion region 248 via a respective transfer gate (e.g., the transfer gate of photodiode 215-1 includes planar portion 241-1 and vertical portion 242-1, the transfer gate associated with photodiode 215-2 includes planar portion 241-2 and vertical portion 242-2, the transfer gate associated with photodiode 215-3 includes planar portion 241-3 and vertical portion 242-3, the transfer gate associated with photodiode 215-4 includes planar portion 241-4 and vertical portion 242-4). Each of the plurality of photodiodes (e.g., 215-1, 215-2, 215-3, and 215-4) corresponds to Figure 2A an example of photodiode 215 illustrated in the figure and includes elements with corresponding similar markings. For example, Figure 2B photodiode 215-1 of can correspond to Figure 2A photodiode 215 illustrated in the figure, while Figure 2B photodiodes 215-2, 215-3, and 215-4 of correspond to Figure 2A additional examples of photodiode 215 illustrated in the figure. It should be understood that Figure 2B the suffix of the elements in indicates association with a given one of photodiodes 215-1, 215-2, 215-3, or 215-3. For example, photodiode 215-1 includes a lightly doped region 216-1 having a substrate segment 218-1, a first protrusion 220-1, and a second protrusion 222-1, a heavily doped region 224-1, and a transfer gate including planar portion 241-1 and vertical portion 242-1, which respectively correspond to Figure 2AA shallow doping region 216 including a substrate segment 218, a protrusion 220, and a protrusion 222, a deep doping region 224, and a transfer gate 240 including a planar portion 241 and a vertical portion 242. Relative to the front side 104 of the semiconductor substrate 102, the deep doping region 224 is located at a greater depth than the shallow doping region 216. Accordingly, the respective shallow doping regions (e.g., 216-2, 216-3, and 216-4) of three additional photodiodes (e.g., 215-2, 215-3, and 215-4) each include a respective substrate segment (e.g., 218-2, 218-3, and 218-4), a first protrusion (e.g., 220-2, 220-3, and 220-4), and a second protrusion (e.g., 222-2, 222-3, and 222-4). Similarly, each of the three additional photodiodes (e.g., 215-2, 215-3, and 215-4) includes a deep doping region (e.g., 224-2, 224-3, and 224-4). The transfer gate associated with the photodiode 215-1 includes a planar portion 241-1 and a vertical portion 242-2 corresponding respectively to the transfer gate 240 illustrated in Figure 2A The planar portion 241-1 and the vertical portion 242-2 of the transfer gate illustrated therein. The pixel unit 205-1 further includes three additional transfer gates, each of which includes a respective vertical portion (e.g., 242-2, 242-3, and 242-4) extending into the semiconductor substrate 202 and a respective planar portion (e.g., 241-2, 241-3, and 241-4) disposed adjacent to the first side of the semiconductor substrate 202. The three additional transfer gates couple the three additional photodiodes (e.g., 215-2, 215-3, and 215-4) to the floating diffusion region 248 respectively.

[0035] In some embodiments, the pixel unit 205-1 is configured to have mirror symmetry with respect to one or more axes (e.g., axis 265 and / or axis 267). In the illustrated embodiment, the pixel unit 205-1 is configured to have mirror symmetry about two axes. For example, the pixel unit 205-1 is mirror symmetric about the axes 265 and 267 that are perpendicular to each other. In some embodiments, a plurality of photodiodes (e.g., 215-1, 215-2, 215-3, and 215-4) and a plurality of transfer gates (e.g., the vertical portions 242-1, 242-2, 242-3, and 242-4 and / or the planar portions 241-1, 241-2, 241-3, and 241-4) are arranged around the floating diffusion region 248 such that when viewing the pixel unit 205-1 from a plan view, there is mirror symmetry about two perpendicular axes (e.g., axes 265 and 267) (e.g., as Figure 2Bas illustrated. Accordingly, the mirror symmetry of pixel unit 205-1 includes at least a photodiode (e.g., 215-1), three additional photodiodes (e.g., 215-2, 215-3, and 215-4), a transfer gate (e.g., planar portion 241-1 and / or vertical portion 242-1), and three additional transfer gates (e.g., planar portions 241-2, 241-3, and 241-4 and / or vertical portions 242-2, 242-3, and 242-4). More specifically, in some embodiments, the mirror symmetry includes lightly doped regions 216-1, 216-2, 216-3, and 216-4 including corresponding substrate segments (e.g., 218-1, 218-2, 218-3, and 218-4) and protrusions (e.g., first protrusions 220-1, 220-2, 220-3, and 220-4 and / or second protrusions 222-1, 222-2, 222-3, and 222-4). In the same or other embodiments, the mirror symmetry further includes heavily doped regions 224-1, 224-2, 224-3, and 224-4.

[0036] As Figure 2BAs illustrated, the lightly doped regions (e.g., 216-1, 216-2, 216-3, or 216-4) of at least one of the photodiodes (e.g., 215-1, 215-2, 215-3, or 215-4), the vertical portions of the transfer gates (e.g., 242-1, 242-2, 242-3, or 242-4), and / or the floating diffusion region 248 are configured such that an axis (e.g., axis 261 and / or axis 263) extending through the centers of both the lightly doped region (e.g., 271-1, 271-2, 271-3, and 271-4) and the floating diffusion region 273 is tangent to the vertical portion of the corresponding transfer gate (e.g., 242-1, 242-2, 242-3, or 242-4) to facilitate the transfer of photo-generated image charges from the plurality of photodiodes (e.g., 215-1, 215-2, 215-3, and 215-4) to the floating diffusion region 248, which increases the transfer efficiency by reducing transfer lag. In this configuration, the main transfer path from each of the plurality of photodiodes 214-1, 214-2, 314-3, 214-4 to the floating diffusion region 248 extends through the shortest lateral separation distance between the edge boundary of the lightly doped region (e.g., 216-1, 216-2, 216-3, and 216-4) and the vertical portion of the transfer gate (e.g., 242-1, 242-2, 242-3, or 242-4) (relative to the lateral separation distances between other portions of the lightly doped region (e.g., 216-1, 216-2, 216-3, and 216-4) of each of the photodiodes (e.g., 215-1, 215-2, 215-3, and 215-4) and the vertical portion (e.g., 242-1, 242-2, 242-3, or 242-4)), which increases the electrical coupling between the main transfer path and the lightly doped regions of the photodiodes (e.g., 215-1, 215-2, 215-3, and 215-4) while minimizing the coupling or mediation of other portions of the lightly doped region at the distal end (e.g., away from the main transfer path) of the main transfer path. It should be understood that the foregoing features in combination with passivation doping (e.g., doping of opposite conductivity with respect to the lightly doped region disposed around the vertical portion (e.g., 242-1, 242-2, 242-3, or 242-4)) result in reduced image lag and dark current.

[0037] The pixel unit 205-1 further includes an isolation structure 236 (e.g., a shallow trench isolation structure and / or a deep trench isolation structure) to provide electrical and (optionally) optical isolation between the pixel unit 205-1 and adjacent pixel units included in the pixel unit array. In other words, the pixel unit 205-1 corresponds to an individual pixel unit included in a plurality of pixel units arranged to form a pixel unit array. In some embodiments, each of the pixel units included in the pixel unit array may correspond to an instance of the pixel unit 205-1 having the same or different color filters (e.g., four instances of the pixel unit 205-1 may be arranged in a 2×2 array to form a full-color image pixel including one red pixel unit, one blue pixel unit, and two green pixel units).

[0038] Figure 2C The figure illustrates a plan view of an alternative pixel unit 205-2 included in an image sensor having a vertical transfer gate according to an embodiment of the present disclosure. Figure 2C The alternative pixel unit 205-2 is similar to Figure 2B the pixel unit 205-1 illustrated in Figure 2B in many aspects, and thus includes many features that are the same or similar, either identically marked or otherwise. For the sake of brevity, the same elements included in both the pixel unit 205-1 of Figure 2B and the alternative pixel unit 205-2 are not necessarily marked or illustrated. Figure 1 One difference between the pixel unit 205-1 of Figure 2CThe extended plan view also illustrates a circuit system 275 (e.g., pixel control circuitry such as source follower transistors, reset transistors, row select transistors, etc., other circuit system elements such as memory elements, or combinations thereof) to facilitate the operation of the alternative pixel unit 205-2. The circuit system 275 can include source / drain regions (e.g., doped regions of the semiconductor substrate 202), gate electrodes (e.g., polysilicon), gate dielectrics (e.g., silicon dioxide, hafnium dioxide, other insulating materials, or combinations thereof). It should be further understood that Figure 2B the pixel unit 205-1 of Figure 2C can also include

[0039] Figure 2D The illustration shows a simulation of current density, which shows the main transfer paths (e.g., 262-1, 262-2, 262-3, and 262-4) of pixel units (e.g., Figures 2A to 2C the pixel units 205-1 and / or 205-2 illustrated in Figure 2D contained in an image sensor having vertical transfer gates according to embodiments of the present disclosure. The simulation illustrated in Figures 2A to 2C represents the pixel unit 205-1 and the alternative pixel unit 205-2, and thus includes

[0040] shallower doped regions 216-1, 216-2, 216-3, and 216-4 with similar markings in Figures 2A to 2D transfer gates including planar portions 241-1, 241-2, 241-3, and 241-4 and vertical portions 242-1, 242-2, 242-3, and 242-4, and a floating diffusion region 248. The simulation shows that the configurations disclosed in embodiments of the present disclosure produce main transfer paths 262-1, 262-2, 262-3, and 262-4 that extend through the shortest lateral separation distances between the shallower doped regions and the vertical portions of the transfer gates, and further shows that the current density increases near the shortest separation distances, which results in reduced image lag and dark current.

[0040] It should be understood that Figures 2A to 2D the views presented in Figures 2A to 2D may omit certain features of embodiments of the image sensor including the pixel unit 205-1 and / or 205-2 to avoid obscuring the details of the present disclosure. In other words, not all elements of the pixel unit 205-1 and / or 205-2 may be labeled, illustrated, or otherwise shown in Figures 2A to 2D or throughout other figures of the present disclosure. It should be further understood that in some embodiments, the pixel unit 205-1 and / or 205-2 may not necessarily include all of the elements shown. For example, Figure 2BThe pixel unit 205-1 illustrated therein shows a 2×2 array of photodiodes (e.g., 215-1, 215-2, 215-3, and 215-4), but in other embodiments, configurations with additional or fewer photodiodes may be utilized. For example, there may be 1, 2, 4, 8, 16, or any other number of photodiodes included in the pixel unit 205-1.

[0041] Figure 3A A plan view (e.g., along the x-y plane of the coordinate system 399) of a photodiode 315 having at least one protrusion 320 included in a pixel unit 305 of an image sensor having a vertical transfer gate (e.g., transfer gate 340) according to an embodiment of the present disclosure. The pixel unit 305 is similar in many aspects to Figures 2A to 2C the pixel units 205-1 and 205-2 illustrated therein, and includes similar features, many of which are labeled. The pixel unit 305 is also Figure 1 a possible implementation of the pixel unit 105 illustrated therein and includes many similarly labeled elements. The pixel unit 305 includes a photodiode 315, a transfer gate 340, and a floating diffusion region 348 each formed in or on a semiconductor substrate 302. Figure 3A The photodiode 315 including the lightly doped region 316 and the heavily doped region 324, the transfer gate 340 including the planar portion 341 and the vertical portion 342, and the floating diffusion region 348 may respectively correspond to Figure 1 the photodiode 115 including the lightly doped region 116 and the heavily doped region 124, the transfer gate 140 including the planar portion 141 and the vertical portion 142, and the floating diffusion region 148. It should be understood that not all elements of the pixel unit 305 must be included in the Figure 3A illustrated embodiment therein (e.g., features such as gate dielectrics, pinned regions, color filters, microlenses, etc. may be omitted to avoid obscuring certain features of the present disclosure). Similar to Figure 1 the pixel unit 105 illustrated therein, Figure 3A the photodiode 315 illustrated therein is adapted to photogenerate image charges in response to incident light, and the transfer gate 340 is adapted to transfer the image charges along a main transfer path (e.g., along an axis 361 extending between the protrusion 320 and the vertical portion 342) from the photodiode 315 to the floating diffusion region 348. In the illustrated embodiment, the main transfer path extends through a lateral separation distance 351 between the protrusion 320 of the lightly doped region 316 and the vertical portion 342 of the transfer gate 340.

[0042] In the illustrated plan view, the lightly doped region 316 includes a substrate segment 318 and a protrusion 320 extending from the substrate segment 318. The protrusion 320 is separated from the vertical portion 342 by a lateral separation distance 351 (e.g., a first lateral separation distance), and the substrate segment 318 is separated from the vertical portion 342 by a lateral separation distance 333 (e.g., a second lateral separation distance) different from the lateral separation distance 351, such that there is a non-uniform separation distance between the lightly doped region 316 and the vertical portion 342. In the illustrated embodiment, the lateral separation distance 351 is less than any other lateral separation distance, including the lateral separation distance 333, between the vertical portion 342 of the transfer gate 340 and the lightly doped region 316. In some embodiments, the lightly doped region 316 consists of the substrate segment 318 and the protrusion 320.

[0043] As Figure 3A illustrated in the plan view of, a first edge 353 of the vertical portion 342 of the transfer gate 340 extends adjacent to a first boundary 355 of the protrusion 320, and a second edge 354 of the vertical portion 342 of the transfer gate 340 extends adjacent to a second boundary 357 of the substrate segment 318 of the lightly doped region 316. In other words, the first edge 353 and the second edge 354 of the vertical portion 342 face the first boundary 355 of the protrusion 320 and the second boundary 357 of the substrate segment 318, respectively, with no intervening portion of the lightly doped region 316 disposed therebetween. In the illustrated embodiment, the first edge 353 is perpendicular to the second edge 354, such that the lightly doped region 316 forms an "L" shape extending around the vertical portion 342 of the transfer gate 340. To increase the full well capacity of the photodiode 315, the deep doped region 324 of the photodiode 315 has a lateral area larger than the combined lateral area of the lightly doped region 316 and the vertical portion 342 of the transfer gate 340.

[0044] Figure 3B Illustrating an expanded plan view of the pixel unit 305 according to an embodiment of the present disclosure Figure 3A as illustrated in. The pixel unit 305 includes a plurality of photodiodes (e.g., 315-1, 315-2, 315-3, and 315-4) corresponding to respective instances of the photodiode 315 Figure 3A as illustrated in. For example, Figure 3B the photodiode 315-1 of Figure 3A may correspond to the photodiode 315 of Figure 3BThe photodiodes 315-2, 315-3, and 315-4 may correspond to three additional photodiodes (e.g., additional instances) of the photodiode 315, which are collectively arranged to laterally surround the floating diffusion region 348 and are each electrically coupled to the floating diffusion region 348. Accordingly, the lightly doped regions 316-1, 316-2, 316-3, and 316-4 of the photodiodes 315-1, 315-2, 315-3, and 315-4 each include corresponding substrate segments 318-1, 318-2, 318-3, and 318-4 and corresponding protrusions 320-1, 320-2, 320-3, and 320-4 extending from the corresponding substrate segments 318-1, 318-2, 318-3, and 318-4. The pixel unit 305 further includes transfer gates that couple the photodiodes 315-1, 315-2, 315-3, and 315-4 to the floating diffusion region 348, respectively, to facilitate the transfer of image charge from the photodiodes 315-1, 315-2, 315-3, and 315-4 to the floating diffusion region 348. The transfer gates each include corresponding planar portions 341-1, 341-2, 341-3, and 341-4 disposed close to the first side (e.g., Figure 1 the first side 104 illustrated in

[0045] as Figure 3BAs illustrated, pixel unit 305 is configured to facilitate transfer of image charge along respective main transfer paths extending between protrusions 320-1, 320-2, 320-3, and 320-4 and vertical portions 342-1, 342-2, 342-3, and 342-3 of the transfer gate from photodiodes 315-1, 315-2, 315-3, and 315-4 to floating diffusion region 348. Pixel unit 305 is further configured to facilitate transfer of image charge based on the positioning, sizing, and arrangement of elements of photodiodes 315-1, 315-2, 315-3, and 315-4. For example, the lightly doped region 316-1 of photodiode 315-1, the vertical portion 342-1 of the transfer gate, and floating diffusion region 348 are jointly configured such that axis 361 extending through both the center 371-1 of the lightly doped region 316-1 and the center 373 of floating diffusion region 348 is tangent to the vertical portion 342-1 of the transfer gate. In the illustrated embodiment, the components of photodiodes 315-2, 315-3, and 315-4 are arranged in a similar manner. Additionally, multiple photodiodes (e.g., 315-1, 315-2, 315-3, and 315-4) and multiple transfer gates (e.g., unlabeled planar portions and / or vertical portions 342-1, 342-2, 342-3, and 342-4) are arranged around floating diffusion region 348 such that when viewing pixel unit 305 from a plan view, there is mirror symmetry about two vertical axes (e.g., axis 365 and axis 367). Pixel unit 305 also includes circuitry 375 (e.g., pixel control circuitry such as source follower transistors, reset transistors, row select transistors, etc., other circuit system elements such as memory elements, or combinations thereof) to facilitate operation of pixel unit 305 disposed adjacent to photodiodes 315-3 and 315-4. Circuitry 375 may include source / drain regions (e.g., doped regions of semiconductor substrate 302), gate electrodes (e.g., polysilicon), gate dielectrics (e.g., silicon dioxide, hafnium dioxide, other insulating materials, or combinations thereof). It should be understood that Figure 3B The views provided may represent units of an image sensor that are repeated in the x and y directions of coordinate system 399 to form an array of pixel units of the image sensor.

[0046] It should be understood that Figures 3A to 3B The views presented may omit certain features of an embodiment of the image sensor including pixel unit 305 to avoid obscuring details of the present disclosure. In other words, not all elements of pixel unit 305 may be labeled, illustrated, or otherwise shown in Figures 3A to 3B or throughout other figures of the present disclosure. It should be further understood that in some embodiments, pixel unit 305 may not necessarily include all of the elements shown. For example, Figure 3BThe pixel unit 305 illustrated therein shows a 2×2 array of photodiodes (e.g., 315-1, 315-2, 315-3, and 315-4), but in other embodiments, configurations with additional or fewer photodiodes may be utilized. For example, there may be 1, 2, 4, 8, 16, or any other number of photodiodes included in the pixel unit 305.

[0047] It should be further understood that when viewed from a plan view (e.g., as illustrated in Figures 2A to 3B ), the elements are located at different z-positions of a given coordinate system (e.g., coordinate systems 299 and 399, which may represent different views of the coordinate system 199 illustrated in Figure 1 ), but are otherwise optically aligned. For example, the protrusion 220 of the lightly doped region 216, the heavily doped region 224, and the planar portion 241 of the transfer gate 240 are each located in a different plane (e.g., different z-positions of the coordinate system 299). Figure 2A The foregoing elements are shown as being optically aligned or otherwise disposed one above the other, although there may be a vertical separation distance between the foregoing elements. For example, Figure 2A the planar portion 242 of the transfer gate 240 illustrated in Figure 1 does not directly contact the lightly doped region 216 and the heavily doped region 224 (e.g., as shown in

[0048] Figure 4 Illustrated is a stacked image sensor 400 according to an embodiment of the present disclosure that includes a plurality of pixel units 405 (each pixel unit including a vertical transfer gate). The stacked image sensor 400 includes a semiconductor substrate 402 and a second semiconductor substrate 481, each of which may correspond to a part or all of a semiconductor wafer according to an embodiment of the present disclosure. The semiconductor substrate 402 includes a plurality of pixel units 405 arranged in a plurality of rows (e.g., R1, R2, R3, etc.) and a plurality of columns (e.g., C1, C2, C3, etc.). Each pixel unit included in the plurality of pixel units 405 may represent the pixel units discussed in various embodiments of the present disclosure (e.g., pixel units 105, 205-1, 205-2, 305, or a combination thereof). The semiconductor substrate 402 includes peripheral circuitry 403, which may include, but is not limited to, row and column decoders and drivers, an analog signal processing chain, a digital imaging processing block, a memory, timing and control circuitry, an input / output interface, a vertical scanner, sample and hold circuitry, an amplifier, analog-to-digital converter circuitry, and any other embodiments of logic and / or circuitry suitable for the function of the image sensor 400.

[0049] In Figure 4 the illustrated embodiment, the stacked image sensor 400 is a stacked complementary metal oxide semiconductor (CMOS) device formed at least in part by a semiconductor substrate 401 (e.g., a first die) and a second semiconductor substrate 451 (e.g., a second die), the semiconductor substrate and the second semiconductor substrate being stacked and coupled together (e.g., electrically and / or physically) in a stacked chip arrangement implemented via bonding (e.g., oxide bonding, metal bonding, hybrid bonding), silicon connection (e.g., through-silicon vias), other suitable circuit coupling techniques, or combinations thereof. Additionally, it should be understood that Figure 4 the views presented in Figure 4 may omit certain components of the stacked image sensor 400 to avoid obscuring the details of the present disclosure. In other words, not all elements of the stacked image sensor 400 may be labeled, illustrated, or otherwise shown in

[0050] Figure 4 the stacked chip arrangement of the stacked image sensor 400 illustrated in

[0051] Figure 5 is a functional block diagram of an imaging system 500 including a plurality of pixel units 505 (each pixel unit including a vertical transfer gate). More specifically, in accordance with an embodiment of the present disclosure, each pixel unit included in the plurality of pixel units 505 may correspond to or otherwise include the same or similar features as: Figure 1 the pixel unit 105 illustrated in Figures 2A to 2B the pixel unit 205-1 illustrated in Figure 2C the pixel unit 205-2 illustrated in Figures 3A to 3BThe pixel unit 305 illustrated therein, or a combination thereof. The imaging system 500 includes: a plurality of pixel units 505 that are configured to generate an electrical signal or an image signal in response to incident light 596; an objective lens 597 having an adjustable optical power to focus on one or more points of interest within an external scene 595; and a controller 572 that is configured to control the operation of, in particular, the plurality of pixel units 505 and the objective lens 597. The plurality of pixel units 505 is a simplified schematic diagram that shows a semiconductor substrate 502 (wherein a plurality of photodiodes 515 are disposed within respective portions of the semiconductor substrate 502), a plurality of color filters 508, and a plurality of microlenses 510. The controller 572 includes one or more processors 574, a memory 576, control circuitry 578, readout circuitry 580, and functional logic 582.

[0052] The controller 572 includes logic and / or circuitry to control the operation of the various components of the imaging system 500 (e.g., during, before, after, and in-situ phases of image and / or video acquisition). The controller 572 can be implemented as hardware logic (e.g., an application specific integrated circuit, a field programmable gate array, a system-on-a-chip, etc.), software / firmware logic executed on a general-purpose microcontroller or microprocessor, or a combination of both hardware and software / firmware logic. In one embodiment, the controller 572 includes a processor 574 coupled to the memory 576, which stores instructions for execution by the controller 572 and / or one or more other components of the imaging system 500. When executed, the instructions can cause the imaging system 500 to perform operations associated with various functional modules, logic blocks, or circuitry of the imaging system 500 including any one or combination of the following: control circuitry 578, readout circuitry 580, functional logic 582, the plurality of pixel units 505, the objective lens 597, and any other element of the imaging system 500 (illustrated or otherwise). The memory is a non-transitory computer-readable medium that can include, but is not limited to, volatile (e.g., RAM) or non-volatile (e.g., ROM) storage systems readable by the controller 572. It should be further understood that the imaging system 500 can be a monolithic integrated circuit, one or more discrete interconnected electrical components, or a combination thereof that can be formed on one or more substrates (e.g., as Figure 4 illustrated therein) coupled together. Additionally, in some embodiments, one or more electrical components can be coupled together to collectively act as the controller 572 to orchestrate the operation of the imaging system 500.

[0053] The control circuit system 578 can control the operating characteristics of an array formed by a plurality of photodiodes 515 (e.g., exposure duration, when to capture a digital image or video, etc.). The readout circuit system 580 reads or otherwise samples the analog signals from individual photodiodes (e.g., reads the electrical signals generated by each of the plurality of photodiodes 515 in response to incident light to generate an image signal for capturing an image frame, etc.), and can include an amplifier circuit system, an analog-to-digital converter (ADC) circuit system, an image buffer, or others. In the illustrated embodiment, the readout circuit system 580 is included in the controller 572, but in other embodiments, the readout circuit system 580 can be separate from the controller 572. The functional logic 582 is coupled to the readout circuit system 580 to receive image data for demosaicking the image data and generating one or more image frames.

[0054] at least Figures 1 to 5 The embodiments of the present disclosure illustrated herein can utilize conventional semiconductor device processing and microfabrication techniques known to those of ordinary skill in the art, which can include, but are not limited to, lithography, ion implantation, chemical vapor deposition, physical vapor deposition, thermal evaporation, sputter deposition, reactive ion etching, plasma etching, wafer bonding, chemical mechanical planarization, and the like. It should be understood that the described techniques are illustrative only and not exhaustive, and other techniques can be utilized to fabricate one or more components of the various embodiments of the present disclosure.

[0055] References to "one embodiment" or "an embodiment" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout the specification are not necessarily all referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0056] Spatial relative terms, such as "beneath", "below", "above", "under", "over", "upper", "top", "bottom", "left", "right", "center", "middle", etc., may be used for ease of description to describe the relationship of one element or feature relative to another (other) element or feature, as illustrated in the figures. It should be understood that the spatial relative terms are intended to cover different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is rotated or flipped, an element described as "beneath" or "under" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "beneath" and "below" can cover both an above and a below orientation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein should be interpreted accordingly. Additionally, it should also be understood that when an element is referred to as being "between" two other elements, the element may be the only element between the two other elements or there may also be one or more intervening elements.

[0057] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they pertain, unless specifically defined herein otherwise or the context in which they are used clearly implies otherwise. It should be noted that in this document, element names and symbols may be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0058] The above description of the illustrated examples of the invention, which includes what is described in the abstract of the invention, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention have been described herein for illustrative purposes, as will be recognized by those skilled in the relevant art, various modifications can be made within the scope of the invention.

[0059] These modifications can be made in view of the above detailed description. The terms used in the appended claims should not be construed as limiting the invention to the specific examples disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which are to be interpreted in accordance with the established principles of claim interpretation.

Claims

1. A pixel unit for an image sensor, comprising: A photodiode disposed within a semiconductor substrate, the semiconductor substrate including a first side and a second side opposite the first side, wherein the photodiode includes a lightly doped region and a heavily doped region each having the same conductivity type, and wherein the lightly doped region is disposed between the first side of the semiconductor substrate and the heavily doped region; A transfer gate coupled to the photodiode, the transfer gate including a vertical portion adjacent to the lightly doped region and extending into the semiconductor substrate from the first side toward the heavily doped region of the photodiode; Wherein, when viewing the pixel unit from a plan view, the lightly doped region includes a base segment and a protrusion extending from the base segment, wherein the protrusion is separated from the vertical portion by a first lateral separation distance, and the base segment is separated from the vertical portion by a second lateral separation distance different from the first lateral separation distance.

2. The pixel unit according to claim 1, further comprising a floating diffusion region disposed within the semiconductor substrate, wherein the photodiode is adapted to generate image charges in response to incident light, wherein the transfer gate is adapted to transfer the image charges along a main transfer path from the photodiode to the floating diffusion region, and wherein the main transfer path extends through the first lateral separation distance between the protrusion of the lightly doped region and the vertical portion of the transfer gate.

3. The pixel unit according to claim 2, wherein the lightly doped region of the photodiode, the vertical portion of the transfer gate, and the floating diffusion region are jointly configured such that an axis extending through the centers of both the lightly doped region and the floating diffusion region is tangent to the vertical portion of the transfer gate.

4. The pixel unit according to claim 1, wherein the first lateral separation distance is less than any other lateral separation distance between the vertical portion of the transfer gate and the lightly doped region, including the second lateral separation distance.

5. The pixel unit according to claim 1, wherein when viewing the pixel unit from the plan view, a first edge of the vertical portion extends adjacent to a first boundary of the protrusion.

6. The pixel unit according to claim 5, wherein when viewing the pixel unit from the plan view, the first edge of the vertical portion extends adjacent to a second boundary of the base segment, and wherein the first boundary and the second boundary each face the first edge of the vertical portion.

7. The pixel unit according to claim 6, wherein the lightly doped region includes a second protrusion extending from the base segment opposite the protrusion, such that the lightly doped region at least partially surrounds the vertical portion of the transfer gate.

8. The pixel unit according to claim 7, wherein the vertical portion of the transfer gate includes a second edge perpendicular to the first edge, wherein the second protrusion includes a third boundary facing the second edge, and wherein the second edge of the vertical portion extends adjacent to the third boundary of the second protrusion.

9. The pixel unit according to claim 5, wherein when viewing the pixel unit from the plan view, the second edge of the vertical portion extends adjacent to the second boundary of the substrate segment, wherein the first side faces the first edge and the second side faces the second edge, and wherein the first edge is perpendicular to the second edge.

10. The pixel unit according to claim 1, wherein the laterally doped region of the photodiode has a larger lateral area than the combined lateral area of the lightly doped region and the vertical portion of the transfer gate.

11. The pixel unit according to claim 1, wherein the transfer gate further includes a planar portion coupled to the vertical portion, wherein the first side of the semiconductor substrate is disposed between the planar portion and the protrusion of the lightly doped region.

12. The pixel unit according to claim 1, wherein a first doping concentration of the protrusion included in the lightly doped region close to the vertical portion of the transfer gate is greater than a second doping concentration of the substrate segment.

13. The pixel unit according to claim 1, wherein when viewed from the plan view, the lightly doped region and the vertical portion of the transfer gate are non-uniformly separated, and wherein the lightly doped region of the photodiode consists of the substrate segment and the protrusion.

14. The pixel unit according to claim 1, further comprising: a floating diffusion region disposed within the semiconductor substrate close to the photodiode; and three additional photodiodes, each having a corresponding substrate segment included in a corresponding lightly doped region and a corresponding protrusion extending from the corresponding substrate segment, wherein the three additional photodiodes and the photodiode are included in a plurality of photodiodes that laterally surround the floating diffusion region and are each electrically coupled to the floating diffusion region.

15. The pixel unit according to claim 14, wherein the lightly doped regions of the photodiode and the three additional photodiodes are arranged to surround the floating diffusion region such that when viewing the pixel unit from the plan view, there is mirror symmetry about two vertical axes.

16. The pixel unit according to claim 15, further comprising three additional transfer gates each including a corresponding vertical portion extending into the semiconductor substrate, wherein the three additional transfer gates respectively couple the three additional photodiodes to the floating diffusion region, and wherein the mirror symmetry of the pixel unit includes at least the photodiode, the three additional photodiodes, the transfer gate, and the three additional transfer gates.

17. An image sensor, comprising: A plurality of pixel units arranged to form an array of pixel units, each pixel unit included in the plurality of pixel units comprising: A floating diffusion region disposed within a semiconductor substrate, the semiconductor substrate including a first side and a second side opposite the first side; A plurality of photodiodes disposed within the semiconductor substrate and arranged to laterally surround the floating diffusion region, wherein each photodiode included in the plurality of photodiodes comprises: A lightly doped region including a base segment and a protrusion extending from the base segment; And A heavily doped region, wherein the lightly doped region is disposed between the first side of the semiconductor substrate and the heavily doped region, and wherein the lightly doped region and the heavily doped region have the same conductivity type; And A plurality of transfer gates, each respective transfer gate included in the plurality of transfer gates adapted to electrically couple a corresponding one of the plurality of photodiodes to the floating diffusion region, wherein the respective transfer gate includes a vertical portion extending into the semiconductor substrate from the first side proximate to the lightly doped region of the corresponding photodiode, and Wherein the plurality of photodiodes and the plurality of transfer gates are arranged to surround the floating diffusion region such that when viewing the pixel unit from a plan view, there is mirror symmetry about two perpendicular axes.

18. The image sensor according to claim 17, wherein when viewed from the plan view, the lightly doped region of the corresponding photodiode and the vertical portion of the transfer gate are non-uniformly separated.

19. The image sensor according to claim 17, wherein the corresponding photodiode is adapted to generate image charge in response to incident light, wherein the transfer gate is adapted to transfer the image charge along a main transfer path from the corresponding photodiode to the floating diffusion region, and wherein the main transfer path extends through a first lateral separation distance between the protrusion of the lightly doped region of the corresponding photodiode and the vertical portion of the transfer gate.

20. The image sensor according to claim 17, wherein the protrusion of the corresponding photodiode is separated from the vertical portion of the transfer gate by a first lateral separation distance, and wherein the first lateral separation distance is less than any other lateral separation distance between the vertical portion of the transfer gate and the lightly doped region of the corresponding photodiode.

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