Storage device, electronic apparatus, and storage device control method

Abstract

A memory device according to one embodiment of the present disclosure includes: a magnetoresistive element whose resistance state is changed by an applied voltage; a selection element connected to the magnetoresistive element; a control line connected to a side of the magnetoresistive element opposite to the selection element side; a voltage applying unit connected to the control line and outputting a voltage to the magnetoresistive element; and a reading unit connected to the control line and reading a resistance state of the magnetoresistive element, in which the reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage applying unit outputs the voltage, and the voltage applying unit controls the operation according to the resistance state of the magnetoresistive element read by the reading unit.

Description

Technical Field

[0001] The present disclosure relates to a storage device, an electronic device, and a storage device control method. Background Art

[0002] A magnetoresistive random access memory (MRAM) using a magnetoresistive element as a storage element is a non-volatile memory that retains recorded data even when the power is turned off because it stores states according to the magnetization states of ferromagnetic materials. The basic structure of the magnetoresistive element is a sandwich structure in which a nonmagnetic insulating film is sandwiched between two magnetic layers formed of thin magnetic materials. This structure is called a magnetic tunnel junction (MTJ). Since the thickness of the nonmagnetic thin film is extremely thin, on the order of several nanometers, a tunnel current flows when a voltage is applied across the element. The distinguishing feature of this structure is that the magnitude of the tunnel current depends on the relative magnetization angle between the two magnetic layers. This phenomenon is called the tunnel magnetoresistance (TMR) effect.

[0003] In MRAM, the magnetization of one of the two magnetic layers (magnetization fixed layer) is fixed, while the magnetization of the other magnetic layer (storage layer) is controlled by an external field. The state in which the magnetizations of the magnetization fixed layer and the storage layer are parallel to each other is defined as state 0, and the state in which they are antiparallel is defined as state 1. In this way, states ("0" or "1") are stored in a non-volatile manner by rewriting the parallel and antiparallel states of the magnetization. External fields for controlling the magnetization direction include a current magnetic field generated by passing a current through an external wiring, a method of passing a current directly through the MTJ and using the spin transfer torque (STT) effect, and a method of using voltage-controlled magnetic anisotropy (VCMA). The state is read using the TMR effect.

[0004] The current mainstream MRAM is STT-MRAM, which allows for greater miniaturization and lower power consumption compared to using a current-induced magnetic field. On the other hand, voltage-controlled (VC) MRAM using VCMA has attracted attention due to its high-speed writing ability and even lower operating power consumption. The voltage writing method using VCMA disclosed in Patent Document 1 achieves bidirectional writing by applying an ultrafast pulse voltage having a unipolarity (applying a voltage only in one direction).

[0005] In a conventional voltage writing method, a bipolar writing operation is performed using a unipolar voltage. When no voltage is applied to the MTJ, due to the perpendicular magnetic anisotropy of the storage layer (the property that magnetization tends to be oriented perpendicular to the film plane), the magnetization of the storage layer is oriented in a direction perpendicular to the film plane (z-direction). Similarly, due to the perpendicular magnetic anisotropy of the fixed layer, the magnetization orientation of the fixed layer is also oriented in the z-direction. Now, assume that the magnetizations of both the storage layer and the fixed layer are in the +z direction, i.e., in a parallel state, and state 0 is written. Additionally, assume that an external magnetic field is applied in the +x direction in the in-plane direction (x-direction and y-direction) of the film. In this case, if a voltage is applied to the MTJ, the electric field generated near the interface between the non-magnetic layer and the storage layer causes the perpendicular magnetic anisotropy of the storage layer to disappear, which results in the loss of the property that magnetization tends to be oriented perpendicular to the film plane. Therefore, the magnetization of the storage layer starts to move toward the x-direction, where the magnetic energy is minimized due to the external magnetic field, but it does not simply change from the +z direction to the +x direction in a straight line; instead, a so-called precessional motion starts, and the magnetization gradually moves toward the +x direction while rotating in the yz plane. During the precessional motion in the yz plane, the magnetization of the storage layer initially oriented in the +z direction has a moment that is oriented approximately in the -z direction. In this case, setting the voltage applied to the MTJ to zero causes the perpendicular magnetic anisotropy of the storage layer to return to its initial state, which makes it easier for the magnetization to be oriented perpendicular to the film plane, resulting in the magnetization of the storage layer being fixed in the -z direction. In other words, by applying a pulsed voltage, the magnetizations of the storage layer and the fixed layer are written from the state 0 where the magnetizations are parallel to the state 1 where the magnetizations are antiparallel. A similar process occurs in state 1, where the magnetization of the storage layer is initially oriented in the -z direction, and thus, bipolar writing can be achieved by applying a unipolar pulsed voltage.

[0006] However, in the above writing method, for example, when writing from state 0 to state 1, when the magnetization of the storage layer is oriented approximately in the -z direction during its precessional motion in the yz plane, it is necessary to set the voltage applied to the MTJ to zero. In other words, it is necessary to control the pulse width of the pulsed writing voltage with high precision. Therefore, the adaptive writing method disclosed in Non-Patent Document 1 includes: monitoring the voltage applied to the MTJ during the writing operation and automatically setting the voltage to zero once the desired state is written, i.e., performing a so-called adaptive writing operation. This eliminates the need to control the pulse width of the pulsed writing voltage with high precision.

[0007] Citation List

[0008] Patent Document

[0009] Patent Document 1: JP 2018-092696 A

[0010] Non-Patent Document

[0011] Non-Patent Document 1: M. Long et al, "Self-Adaptive Write Circuit for Magnetic Tunneling Junction Memory With Voltage-Controlled Magnetic Anisotropy Effect", IEEE Transactions on Nanotechnology, vol. 17, no. 3, pp. 492-499, 2018 SUMMARY OF THE INVENTION

[0012] TECHNICAL PROBLEM

[0013] In the above-described self-adaptive writing method, the wiring connected between the MTJ and the cell selection transistor is used to monitor the voltage applied to the MTJ during the writing operation. However, this memory cell structure requires separate wiring to monitor each memory cell, which results in an increase in the memory cell area. For example, Non-Patent Document 1 discloses that the memory cell area of the self-adaptive writing method disclosed in Non-Patent Document 1 is approximately 20 times larger than that of a normal memory cell.

[0014] In addition, another problem with the above-described self-adaptive writing method is that, depending on whether the initial state before writing is state 0 or state 1, due to the influence of the wiring for monitoring (e.g., the influence of the monitoring circuit), the voltage applied to the MTJ at the start of writing is different from the desired voltage in either state or both states. In the voltage writing method using VCMA, it is desired that the voltage applied to the MTJ at the start of writing is equal to the voltage that cancels the perpendicular magnetic anisotropy of the storage layer. In this case, the precessional motion achieves an ideal form. In Non-Patent Document 1, the fact that the voltage applied to the MTJ at the start of writing is different from the desired voltage depending on whether the initial state before writing is state 0 or state 1 means that the voltage applied to the MTJ at the start of writing is different from the voltage that cancels the perpendicular magnetic anisotropy of the storage layer in either state or both states. This makes the precessional motion non-ideal, resulting in instability of the writing operation. A possible undesirable result may be a failure of the writing operation.

[0015] Accordingly, the present disclosure provides a storage device, an electronic device, and a method of controlling a storage device that can implement a self-adaptive writing method while minimizing the memory cell area and improving the stability of the writing operation.

[0016] SOLUTION TO THE PROBLEM

[0017] A memory device according to an embodiment of the present disclosure includes: a magnetoresistive element having a resistance state that changes when a voltage is applied; a selection element connected to the magnetoresistive element; a control line connected to a side of the magnetoresistive element opposite to the side connected to the selection element; a voltage application unit connected to the control line to output a voltage to the magnetoresistive element; and a reading unit connected to the control line to read the resistance state of the magnetoresistive element, wherein the reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs a voltage to the magnetoresistive element, and the voltage application unit controls the operation based on the resistance state of the magnetoresistive element read by the reading unit.

[0018] An electronic device according to an embodiment of the present disclosure includes: a storage device configured to store data, wherein the storage device includes: a magnetoresistive element having a resistance state that changes when a voltage is applied; a selection element connected to the magnetoresistive element; a control line connected to a side of the magnetoresistive element opposite to the side connected to the selection element; a voltage application unit connected to the control line to output a voltage to the magnetoresistive element; and a reading unit connected to the control line to read the resistance state of the magnetoresistive element, the reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs a voltage to the magnetoresistive element, and the voltage application unit controls the operation based on the resistance state of the magnetoresistive element read by the reading unit.

[0019] A method of controlling a storage device according to an embodiment of the present disclosure, the method includes: in a memory cell including a magnetoresistive element whose resistance state changes when a voltage is applied and a selection element connected to the magnetoresistive element, outputting a voltage to the magnetoresistive element by a voltage application unit connected to a control line, the control line being connected to a side of the magnetoresistive element opposite to the side connected to the selection element; and reading the resistance state of the magnetoresistive element by a reading unit connected to the control line, wherein the reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs a voltage to the magnetoresistive element, and the voltage application unit controls the operation based on the resistance state of the magnetoresistive element read by the reading unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a diagram showing a first configuration example of a memory system according to an embodiment of the present disclosure.

[0021] Figure 2 is a diagram showing a second configuration example of a memory system according to an embodiment of the present disclosure.

[0022] Figure 3 is a diagram showing a first configuration example of a memory cell according to an embodiment of the present disclosure.

[0023] Figure 4It is a diagram showing a second configuration example of a memory cell according to an embodiment of the present disclosure.

[0024] Figure 5 It is a diagram showing a first configuration example of a magnetoresistive element according to an embodiment of the present disclosure.

[0025] Figure 6 It is a diagram showing a second configuration example of a magnetoresistive element according to an embodiment of the present disclosure.

[0026] Figure 7 It is a diagram schematically showing a write unit according to an embodiment of the present disclosure.

[0027] Figure 8 It is a circuit diagram showing a first configuration example of a write unit according to an embodiment of the present disclosure.

[0028] Figure 9 It is a circuit diagram showing a first configuration example of a read unit according to an embodiment of the present disclosure.

[0029] Figure 10 It is a circuit diagram showing a second configuration example of a read unit according to an embodiment of the present disclosure.

[0030] Figure 11 It is a circuit diagram showing a first configuration example of a reference voltage generation unit according to an embodiment of the present disclosure.

[0031] Figure 12 It is a circuit diagram showing a second configuration example of a reference voltage generation unit according to an embodiment of the present disclosure.

[0032] Figure 13 It is a circuit diagram showing a configuration example of a reference resistor according to an embodiment of the present disclosure.

[0033] Figure 14 It is a circuit diagram showing a configuration example of a voltage application unit and a memory cell according to an embodiment of the present disclosure.

[0034] Figure 15 It is a diagram showing a first example of describing simulation results according to an embodiment of the present disclosure.

[0035] Figure 16 It is a diagram showing a second configuration example of describing simulation results according to an embodiment of the present disclosure.

[0036] Figure 17 It is a circuit diagram showing a second configuration example of a write unit according to an embodiment of the present disclosure.

[0037] Figure 18is a circuit diagram showing a third configuration example of a writing unit according to an embodiment of the present disclosure.

[0038] Figure 19 is a circuit diagram showing configuration examples of a write voltage generation unit, a voltage application unit, and a memory unit according to an embodiment of the present disclosure.

[0039] Figure 20 is a diagram showing a third example for describing simulation results according to an embodiment of the present disclosure.

[0040] Figure 21 is a diagram showing a third example description of a load resistor based on simulation results according to an embodiment of the present disclosure.

[0041] Figure 22 is a diagram showing a fourth example for describing simulation results according to an embodiment of the present disclosure.

[0042] Figure 23 is a diagram showing an example of a schematic configuration of an imaging device.

[0043] Figure 24 is a diagram showing an example of a general configuration of a distance measurement device.

[0044] Figure 25 is a diagram showing an appearance embodiment of a game device.

[0045] Figure 26 is a diagram showing an example of a general configuration of a game device. Detailed Description of Specific Embodiments

[0046] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments include examples and modifications. In addition, the embodiments do not limit the devices, apparatuses, methods, etc. of the present disclosure. Further, in the following embodiments, the same parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0047] One or more of the following embodiments can be implemented independently. On the other hand, at least a part of the following multiple embodiments can be appropriately combined with at least a part of other embodiments to be implemented. These multiple embodiments can include novel features different from each other. Therefore, each embodiment can contribute to solving different objectives or problems and can produce different effects. In addition, the effects of each embodiment are merely illustrative and are not to be construed as restrictive, and other effects are also possible.

[0048] In addition, the accompanying drawings referred to in the following description are provided to describe the embodiments of the present disclosure and facilitate understanding. For ease of understanding, the shapes, sizes, ratios, etc. shown in the drawings may be different from the actual ones. In addition, the elements shown in the drawings and the like may be appropriately modified in design by considering the following description and well-known techniques. In addition, in the following description, the up-down direction and the like of the stacked structure of the elements correspond to the relative direction when the surface of the substrate on which the elements are provided is regarded as upward, and this direction may be different from the up-down direction according to the actual acceleration of gravity.

[0049] In addition, when describing the magnetization direction (magnetic moment) and magnetic anisotropy, for convenience, terms such as "vertical direction" (the direction perpendicular to the film surface or the stacking direction of the stacked structure) and "in-plane direction" (the direction parallel to the film surface or the direction perpendicular to the stacking direction of the stacked structure) may be used. However, these terms do not necessarily indicate the exact direction of magnetization. For example, expressions such as "the magnetization direction is vertical" and "has perpendicular magnetic anisotropy" mean that the magnetization in the vertical direction is dominant compared to the magnetization in the in-plane direction. Similarly, for example, expressions such as "the magnetization direction is in-plane" and "has in-plane magnetic anisotropy" mean that the magnetization in the in-plane direction is dominant compared to the perpendicular magnetization.

[0050] In this context, the present inventors have developed a compact model in Verilog-A language for MTJs having the VCMA effect, which can be incorporated into a simulation program with an integrated circuit emphasis (SPICE) simulator, and as a result of the research on SPICE simulation using the MTJ model, they have invented a non-triggered writing method. In the non-triggered writing method disclosed herein, for example, in a memory cell in which a cell transistor and an MTJ are connected in series, different magnitudes of voltage are applied to the memory cell in the case of writing state 1 and writing state 0. In this case, the voltage applied to the memory cell is divided between the cell transistor and the MTJ, but the voltage applied to the MTJ changes depending on the state already written in the MTJ. As a result, in the case where state 1 has been written and state 1 needs to be written, and in the case where state 0 has been written and state 0 needs to be written, an incorrect write can be prevented from occurring. Therefore, the prior art triggered writing method requires reading the initial state before writing, while the non-triggered writing method of the present disclosure eliminates the need to read the initial state before writing. Therefore, the read time and power consumption required for the initial read can be reduced. The non-triggered writing method of the present disclosure will be described in detail later.

[0051] Now, the present disclosure will be described in the order of the items shown below.

[0052] 1. Embodiments

[0053] 1-1. Configuration Example of Memory System

[0054] 1-2. Configuration Example of Memory Cell

[0055] 1-3. Configuration Example of Magnetoresistive Element

[0056] 1-4. First Configuration Example of Write Unit

[0057] 1-5. Simulation Results

[0058] 1-6. Second Configuration Example of Write Unit

[0059] 1-7. Simulation Results

[0060] 1-8. Operations and Effects

[0061] 2. Other Embodiments

[0062] 3. Configuration Example of Electronic Device

[0063] 3-1. Imaging Device

[0064] 3-2. Distance Measuring Device

[0065] 3-3. Game Device

[0066] 4. Supplementary Explanation

[0067] <1. Embodiment>

[0068] <1-1. Configuration Example of Memory System>

[0069] Now refer to Figure 1 and Figure 2 to describe a configuration example of the memory system 1 according to this embodiment.

[0070] Figure 1 is a diagram showing a configuration example of the memory system 1 according to this embodiment. The memory system 1 is an example of a storage device that holds information based on the magnetization direction of a magnetic material.

[0071] As Figure 1 shown, the memory system 1 according to this embodiment includes an interface unit 2, a memory control unit 3, and a memory array 4.

[0072] The interface unit 2 uses the memory system 1 to perform signal exchange (e.g., transmission and reception) with a host system (not shown) and the like.

[0073] The memory control unit 3 communicates with a host system or the like via the interface unit 2 and controls the memory array 4. The memory control unit 3 receives commands from the host system and controls data writing and reading based on the received commands. For example, the memory control unit 3 outputs write and read commands or addresses to the memory array 4. In the case of a write command, write target data is also output simultaneously. In addition, the memory control unit 3 outputs a read command and then receives read data from the memory array 4.

[0074] The memory array 4 is used to store data. The memory array 4 includes a memory cell array 10, a bit line address decoder 20, a word line address decoder 30, a write control unit 40, a write unit 50, and a sense amplifier 60.

[0075] The memory cell array 10 is configured with memory cells 100 that store data and are arranged in a two-dimensional matrix. The memory cell 100 includes a selection element 110 and a magnetoresistive element 120. For the magnetoresistive element 120, a magnetoresistive element such as an MTJ can be used. The selection element 110 is an element that is connected to one end of the magnetoresistive element 120 and controls the application of voltage to the magnetoresistive element 120. For example, for the selection element 110, an n-channel MOS transistor can be used.

[0076] The memory cell 100 is connected to a word line 11 (WL) and a bit line 12 (BL) that transmit control signals. In addition, in the memory cell 100, a source line 13 (SL) that sends signals from the magnetoresistive element 120 is also configured. In the memory cell array 10, a plurality of word lines 11 are wired to extend in the row direction, and a plurality of bit lines 12 and a plurality of source lines 13 are wired to extend in the column direction. Each word line 11, bit line 12, and source line 13 serves as a control line.

[0077] In addition, in the memory cell array 10, the source line 13 is shared by two adjacent memory cells 100 in the row direction. By doing so, the area of the memory cell array 10 can be reduced. However, two adjacent memory cells 100 in the row direction may not share the source line 13 but be connected to separate source lines 13.

[0078] The bit line address decoder 20 selects a write selection line 14 (SE) connected to the write unit 50 based on a control signal from the memory control unit 3 and outputs the control signal to the selected write selection line 14.

[0079] The word line address decoder 30 selects a word line 11 of the memory cell array 10 based on a control signal from the memory control unit 3 and outputs the control signal to the selected word line 11.

[0080] The write control unit 40 outputs a control signal to the write unit 50 based on a control signal from the memory control unit 3.

[0081] The write unit 50 outputs a control signal to the bit line 12 based on a control signal from the write control unit 40 and a control signal from the bit line address decoder 20. The write unit 50 performs writing to the magnetoresistive element 120 of the memory cell 100 at the intersection of the selected word line 11 and the bit line 12 via the selection element 110 of the memory cell 100.

[0082] The sense amplifier 60 detects the current flowing through the memory cell 100 during a read operation for reading data. The sense amplifier 60 reads the magnetoresistive element 120 of the memory cell 100 at the intersection of the selected word line 11 and the bit line 12 via the selection element 110 of the memory cell 100.

[0083] Reading from the memory cell 100 can be performed by applying a predetermined read voltage to the magnetoresistive element 120 of the memory cell 100 and detecting the current flowing through the memory cell 100. The read voltage preferably has a polarity different from that of the write voltage. In addition, details regarding writing to the memory cell 100 will be described later.

[0084] Now refer to Figure 2 Another configuration example of the memory system 1 according to an embodiment will be described. Figure 2 FIG. is a diagram showing another configuration example of the memory system 1 according to an embodiment of the present disclosure. The memory system 1 is also an example of a storage device that stores information based on the magnetization direction of a magnetic material.

[0085] As Figure 2 shown, different from Figure 1 , column switches 70 are arranged between the memory cell array 10 and the write unit 50. In the Figure 2 example, one column switch 70 is arranged for each of the four bit lines 12 of the memory cell array 10, but the number of bit lines 12 of the memory cell array 10 connected to one column switch 70 can be set to any value. If n is an integer equal to or greater than 1, it is preferable to connect the power supplies of n bit lines 12 of the memory cell array 10 to one column switch 70. Then, different from Figure 1 , the memory control unit 3 outputs a part of the bit line address received from the interface unit 2 to the column switch 70, and outputs the remaining bit line address to the bit line address decoder 20.

[0086] The column switch 70 connects the bit line 12 of the write unit 50 to one of the bit lines 12 of the memory cell array 10 connected to the column switch 70 based on a control signal from the memory control unit 3. In Figure 1In [description of a certain situation], the write unit 50 is connected to all the bit lines 12 of the memory cell array 10, but in Figure 2 In [another situation], the write unit 50 is connected to all the column switches 70. In this way, in Figure 2 the configuration example of [a certain situation], the number of write units 50 can be reduced. Other functions are similar to those of the memory system 1 shown in Figure 1 [a certain situation].

[0087] <1-2. Configuration Example of Memory Cell>

[0088] Now refer to Figure 3 and Figure 4 to describe a configuration example of the memory cell 100 according to the present embodiment. Figure 3 and Figure 4 are diagrams showing respective configuration examples of the memory cell 100 according to the present embodiment. Each figure is a schematic diagram showing a configuration example of the memory cell 100. In addition, as described above, the memory cell 100 includes a selection element 110 and a magnetoresistive element 120. In Figure 3 and Figure 4 the example, the selection element 110 and the magnetoresistive element 120 are connected in series, and the selection element 110 has a drain (drain terminal), a source (source terminal), and a gate (gate terminal).

[0089] As Figure 3 shown, the magnetoresistive element 120 of the memory cell 100 is connected to the wiring 101 via the contact layer 103 and is connected to the selection element 110 via the contact layer 104. The drain of the selection element 110 is connected to the contact layer 104, and the source is connected to the source line 13 (SL). In addition, the gate of the selection element 110 is connected to the word line 11 (WL). In addition, the contact layer 103 is connected to the wiring 101 that constitutes the bit line 12 (BL). By applying a conduction voltage to the word line 11 (WL), the selection element 110 becomes conductive, enabling a voltage to be applied to the magnetoresistive element 120.

[0090] As Figure 4 shown, the magnetoresistive element 120 of the memory cell 100 is connected to the wiring 102 via the contact layer 104 and is connected to the selection element 110 via the contact layer 103. The drain of the selection element 110 is connected to the bit line 12 (BL), and the source is connected to the contact layer 103. In addition, the gate of the selection element 110 is connected to the word line 11 (WL). In addition, the contact layer 104 is connected to the wiring 102 that constitutes the source line 13 (SL). By applying a conduction voltage to the word line 11 (WL), the selection element 110 becomes conductive, enabling a voltage to be applied to the magnetoresistive element 120.

[0091] As described above, the word line 11 (WL) is connected to the word line address decoder 30 (see Figure 1 orFigure 2 )。The bit line 12 (BL) is connected to the write unit 50 (see Figure 1 ) or the column switch 70 (see Figure 2 )。The source line 13 (SL) is connected to the sense amplifier 60 (see Figure 1 or Figure 2 ). By applying a voltage between the bit line 12 (BL) and the source line 13 (SL), and also applying a conductive voltage to the word line 11 (WL) to turn on the selection element 110, a voltage for writing or reading can be applied to the magnetoresistive element 120.

[0092] <1-3. Structural example of magnetoresistive element>

[0093] Next, Figure 5 and Figure 6 are used to illustrate a structural example of the magnetoresistive element 120 of the present embodiment. Figure 5 and Figure 6 are diagrams showing respective structural examples of the magnetoresistive element 120 of the present embodiment. Each figure is a cross-sectional view showing a structural example of the magnetoresistive element 120.

[0094] As Figure 5 and Figure 6 show, the magnetoresistive element 120 includes a base layer 121, a magnetization fixed layer 122, a tunnel barrier layer 123, a storage layer 124, and a capping layer 125. Figure 5 The magnetoresistive element 120 shown in Figure 6 is configured by stacking the base layer 121, the magnetization fixed layer 122, the tunnel barrier layer 123, the storage layer 124, and the capping layer 125 in this order. On the other hand,

[0095] The base layer 121 may be, for example, a layer formed of a noble metal or a transition metal element such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, and Rh, or a stacked structure thereof. In addition, the base layer 121 may also be formed of a conductive nitride such as TiN. For example, the base layer 121 is formed by a film for controlling the crystal orientation of the magnetization fixed layer 122 and for improving the adhesion strength to the lower electrode.

[0096] The magnetization fixed layer 122 has magnetic anisotropy and is a layer with an unchanging magnetization direction. The magnetization fixed layer 122 can be formed of, for example, CoFeB, CoFeC alloy, NiFeB alloy, NiFeC alloy, etc. In addition, the magnetization fixed layer 122 can also have a stacked ferromagnetic fixed structure in which a plurality of ferromagnetic layers are stacked and non-magnetic layers are interposed therebetween. As for the ferromagnetic layers of the magnetization fixed layer constituting the stacked ferromagnetic fixed structure, materials such as Co, CoFe, CoFeB, etc. can be used. In addition, for the non-magnetic layers, materials such as Ru, Re, Ir, Os, etc. can be used.

[0097] In addition, the magnetization fixed layer 122 can also be configured such that its magnetization direction is fixed by utilizing the antiferromagnetic coupling between the antiferromagnetic layer and the ferromagnetic layer. Examples of materials for the antiferromagnetic layer include magnetic materials such as FeMn alloy, PtMn alloy, PtCrMn alloy, NiMn alloy, IrMn alloy, NiO, Fe2O3, etc. In addition, non-magnetic elements such as Ag, Cu, Au, Al, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Hf, Ir, W, Mo, Nb, etc. can also be added to these magnetic materials.

[0098] The tunnel barrier layer 123 is arranged adjacent to the storage layer 124, which will be described later, and is used to apply an electric field to the storage layer 124 to impart a voltage-controlled magnetic anisotropy effect. The tunnel barrier layer 123 can be formed of an oxide of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba or a nitride of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. In addition, it can also be formed of an insulator, a dielectric material, or a semiconductor such as MgF2, CaF, SrTiO2, AlLaO3, AlNO, etc. It can also have a structure in which these layers are stacked. In addition, the thickness of the tunnel barrier layer 123 is preferably 0.6 nm or more.

[0099] The storage layer 124 has magnetic anisotropy and is a layer with a variable magnetization direction. In addition, the storage layer 124 is also a layer having the VCMA effect. The state in which the magnetization direction of the storage layer 124 is the same as the magnetization direction of the magnetization fixed layer 122 and the state in which the magnetization direction of the storage layer 124 is different from the magnetization direction of the magnetization fixed layer 122 are respectively referred to as the parallel state and the antiparallel state. The magnetoresistive element 120 is in a low-resistance state in the parallel state and in a high-resistance state in the antiparallel state. As described above, applying a voltage to the magnetoresistive element 120 enables the magnetization direction of the storage layer 124 to be changed. For example, the low-resistance state is defined as state 0, and the high-resistance state is defined as state 1.

[0100] The storage layer 124 can also be formed of materials such as cobalt iron (CoFe), cobalt iron boron (CoFeB), Fe, iron boride (FeB), etc. In addition, configurations including transition metals (Hf, Ta, W, Re, Ir, Pt, Au, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Ti, V, Cr, Mn, Ni, Cu), etc. can also be adopted. In addition, it can also contain nitrides or oxides. Additionally, materials such as iridium (Ir) or osmium (Os) can be used to induce proximity magnetic moments in magnetic materials. Furthermore, adding heavy metals to the storage layer 124 can enhance the voltage-controlled magnetic anisotropy effect. Preferably, the thickness of the storage layer 124 is 3.0 nm or less.

[0101] In addition, the storage layer 124 can also have a stacked structure in which a plurality of ferromagnetic layers are stacked and non-magnetic layers are interposed therebetween. In this case, two adjacent ferromagnetic layers can be exchange-coupled to each other via the non-magnetic layer. The non-magnetic layer can be formed of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, Ba, W, Re, Ir, Pt, Au, Nb, Mo, Ru, Rh, Pd, Ag, V, Mn, Ni, Cu, etc.

[0102] The capping layer 125 is a layer that prevents the diffusion of metals from the wiring components. The capping layer 125 can be formed of metals such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, Rh, etc. In addition, the capping layer 125 can also be formed of alloys containing these metals and layers composed of transition metal elements. In addition, the capping layer 125 can also be formed by stacking these layers. In addition, the capping layer 125 can also be formed of conductive nitrides such as TiN.

[0103] The foregoing various layers can be manufactured, for example, using physical vapor deposition (PVD) techniques such as sputtering, ion beam deposition, or vacuum evaporation, or chemical vapor deposition (CVD) techniques such as atomic layer deposition (ALD). In addition, these layers can be patterned using reactive ion etching (RIE) or ion milling techniques. Preferably, these different layers are continuously formed in a vacuum apparatus and then patterned.

[0104] <1-4. First configuration example of the write unit>

[0105] Now refer to Figures 7 to 13 Describe the first configuration example of the write unit 50 according to the present embodiment.

[0106] Figure 7 is a schematic diagram of the write unit 50. As Figure 7As shown, the writing unit 50 includes a writing voltage generation unit 51, a voltage application unit 52, a reading unit 53, a comparison unit 54, a feedback unit 55, and a writing selection unit 56.

[0107] The writing voltage generation unit 51 has a state-0 writing voltage line 15 (WR0), a state-1 writing voltage line 16 (WR1), a writing data line 17 (WD), and a writing signal line 19 (WE2) as input terminals. The state-0 writing voltage line 15, the state-1 writing voltage line 16, and the writing data line 17 are connected to the writing control unit 40. The writing signal line 19 is connected to the writing selection unit 56.

[0108] Under the control of the writing control unit 40, a voltage for writing state 0 is applied to the state-0 writing voltage line 15, and a voltage for writing state 1 is applied to the state-1 writing voltage line 16. These voltages (voltage values) are respectively represented as V WR0 and V WR1 . The voltage V WR0 and V WR1 have different values. In addition, under the control of the writing control unit 40, in the case of writing state 0, a cut-off voltage is applied to the writing data line 17, and in the case of writing state 1, a conduction voltage is applied to the writing data line 17.

[0109] The cut-off voltage is the voltage that makes the drain terminal and the source terminal of an n-channel MOS transistor non-conductive when applied to the gate voltage of the n-channel MOS transistor, and can be, for example, a ground voltage. In addition, the conduction voltage is the voltage that makes the drain terminal and the source terminal of an n-channel MOS transistor conductive when applied to the gate voltage of the n-channel MOS transistor, and can be, for example, a power supply voltage. The voltage of the writing data line 17 is represented as V WD .

[0110] The writing voltage generation unit 51 outputs the voltage V WD of the state-0 writing voltage line 15 or the voltage V WR0 of the state-1 writing voltage line 16 to the voltage application unit 52 according to the voltage V WR1 . Specifically, the writing voltage generation unit 51 outputs the voltage V WD when the voltage V WR0 is a cut-off voltage, and outputs the voltage V WD when the voltage V WR1 is a conduction voltage. However, if the voltage of the writing signal line 19 (the writing selection voltage indicating whether a writing operation is performed) is a cut-off voltage (the voltage indicating that writing is not performed), then the writing voltage generation unit 51 is independent of the voltage V WDThe value outputs the disconnection voltage or the conduction voltage to the voltage application unit 52. The voltage of the write signal line 19 is represented as V WE2 .

[0111] The voltage application unit 52 outputs to the bit line 12 a voltage depending on the voltage output from the write voltage generation unit 51. The voltage output from the write voltage generation unit 51 is represented as V WR , and the voltage of the bit line 12 is represented as V BL . The voltage application unit 52 outputs the voltage V BL to the reading unit 53. In addition, the memory cell 100 is connected to the bit line 12 (see Figure 1 ).

[0112] The reading unit 53 refers to the voltage V BL output from the voltage application unit 52, and reads the state (e.g., state 0 or state 1) of the magnetoresistive element 120 of the memory cell 100 to be written. The reading unit 53 has the write data line 17 as another input terminal. To read the state of the magnetoresistive element 120, the reading unit 53 can use the voltage V WD . The reading unit 53 outputs the read data (i.e., the read voltage corresponding to the read data) to the comparison unit 54. This voltage is represented as V RD . The voltage V RD is the disconnection voltage when the state of the magnetoresistive element 120 is state 0, and is the conduction voltage when the state is state 1.

[0113] The comparison unit 54 refers to the voltage V RD output from the reading unit 53, and compares the read data (e.g., the read state of the magnetoresistive element 120) with the write data (e.g., the target state of the magnetoresistive element 120). The comparison unit 54 has the write data line 17 as another input terminal. To perform the comparison, the comparison unit 54 can use the voltage V WD . The comparison unit 54 outputs the comparison voltage corresponding to the comparison result to the feedback unit 55. This voltage is represented as V CMP . The voltage V CMP is the conduction voltage when the read data and the write data are equal, and is the disconnection voltage when they are different. Alternatively, the voltage V CMP can be the cut-off voltage when the read data and the write data are equal, and can be the conduction voltage when the read data and the write data are equal.

[0114] Reading data indicates that the magnetoresistive element 120 is in state 0 or state 1, and writing data indicates that the magnetoresistive element 120 is in state 0 or state 1. When the reading data is the same as the writing data, it indicates that the state of the magnetoresistive element 120 is the same, and when the reading data is different from the writing data, it indicates that the state of the magnetoresistive element 120 is different.

[0115] The feedback unit 55 refers to the voltage V output from the comparison unit 54 CMP to determine whether to continue or stop writing. The feedback unit 55 has a write start signal line 18 (EN) as another input terminal. To determine whether to continue or stop writing, the feedback unit 55 can use the voltage on the write start signal line 18. This voltage is represented as V EN . The voltage V EN is the conduction voltage at the start of writing and is the cut-off voltage at other times. The feedback unit 55 refers to the voltage V CMP and the voltage V EN , and outputs a write continue signal to the write selection unit 56. This voltage is represented as V WE . The voltage V WE is the conduction voltage in the case of continuing writing and is the cut-off voltage in the case of stopping writing.

[0116] The write selection unit 56 refers to the voltage V output from the feedback unit 55 WE to select whether to continue or stop writing. The write selection unit 56 has a write selection line 14 (SE) as another input terminal. To select whether to continue or stop writing, the write selection unit 56 can use the voltage on the write selection line 14. This voltage is represented as V SE . The voltage V SE is the conduction voltage when writing is performed and is the disconnection voltage when writing is not performed. If the voltage V SE is the conduction voltage, the write selection unit 56 outputs the voltage V WE without making any changes to the write voltage generation unit 51, and if the voltage V SE is the disconnection voltage, outputs the disconnection voltage to the write voltage generation unit 51. As mentioned above, this voltage is represented as V WE2 .

[0117] Figure 8 Shows Figure 7 a more detailed circuit diagram of the write unit 50 shown. However, Figure 8 is only an example of the form of the write unit 50, and the write unit 50 is not limited to this form. Moreover, by comparing Figure 8 the operation of the circuit diagram shown with the description of Figure 7 mentioned previously, it can be easily understood Figure 8The operation of the circuit diagram shown, but with some additional descriptions provided.

[0118] The write voltage generation unit 51 has two multiplexers MUX0 and MUX1. The voltage application unit 52 has a p-channel MOS transistor P0. The comparison unit 54 has an inverter INV3 and an XOR gate XOR0. The feedback unit 55 has a p-channel MOS transistor P1, two n-channel MOS transistors N0 and N1, and an inverter INV4. The write selection unit 56 has an AND gate AND0.

[0119] The feedback unit 55 operates such that when the voltage V on the write start signal line 18 EN becomes the conduction voltage, the p-channel MOS transistor P1 becomes conductive and the n-channel MOS transistor N1 becomes insulating, causing the output voltage V of the feedback unit 55 WE to be charged to the conduction voltage. Additionally, the voltage V EN is the trigger signal for starting the write, so once the voltage V WE is charged to the conduction voltage, the voltage V EN is set to the off voltage. The duration for which the voltage V EN remains at the conduction voltage is preferably about 0.1 ns to 1 ns, but is not limited to this range. When the voltage V on the write selection line 14 SE is the off voltage, no write operation occurs, so this discussion focuses only on the case where the voltage V SE is the conduction voltage. The voltages V WE and V WE2 become the conduction voltage, and the write operation starts. Subsequently, the voltage signal propagates sequentially from the write selection unit 56, the write voltage generation unit 51, the voltage application unit 52, the read unit 53, and the comparison unit 54.

[0120] The output voltage V of the comparison unit 54 CMP is the conduction voltage when the read data and the write data are equal, and is the off voltage when they are different. Optionally, the output voltage V of the comparison unit 54 CMP can be the off voltage when the read data and the write data are equal, and can be the conduction voltage when the read data and the write data are equal, and can be the conduction voltage when they are different. In the case of the circuit diagram shown in Figure 8 the output voltage V of the comparison unit 54 CMP is the conduction voltage when the read data is equal to the write data, and is the off voltage when they are different. Then, when the read data and the write data are different, i.e., when continued writing is required, the n-channel MOS transistor N0 is insulated. Thus, the output voltage V of the feedback unit 55 WERemain charged to the conduction voltage, and writing continues. On the contrary, when the read data and the write data are equal, that is, when writing needs to be stopped, the n-channel MOS transistor N0 is turned on. In addition, as described above, the voltage V EN is the turn-off voltage of the n-channel MOS transistor N1, so this also becomes conductive. Then, the charge stored in the output terminal of the feedback unit 55 is discharged through the n-channel MOS transistor N0 and the n-channel MOS transistor N1. Therefore, the output voltage V WE of the feedback unit 55 becomes the turn-off voltage, and writing stops.

[0121] As described above, by using the writing unit 50 according to the present embodiment, an adaptive writing operation can be achieved, in which the writing operation continues when the read data and the write data are different, and the writing stops when they become the same. For example, it is not necessary to control the pulse width of the writing voltage, that is, the writing pulse width, which can reduce the writing error rate and improve the stability of the writing operation. Generally, the optimal writing pulse width of each magnetoresistive element 120 is different, but since an appropriate writing pulse width is automatically set for each magnetoresistive element 120, the writing error rate can be reduced.

[0122] In addition, Figure 8 The shown reading unit 53 can be configured in any manner as long as it can read the state of the selected magnetoresistive element 120. In addition, the write data line 17 (WD) can be used to perform the reading operation. In other words, it can use the bit line 12 (BL) and the write data line 17 (WD) as input terminals, and the read data line RD as the output terminal. The bit line 12 may be referred to as the bit line BL hereinafter, and the write data line 17 may be appropriately referred to as the write data line WD aligned with the read data line RD.

[0123] Figure 9 An example of the configuration of the reading unit 53 is shown. The reading unit 53 shown in Figure 9 has three inverters INV0, INV1, and INV2 and one multiplexer MUX2. The bit line BL is connected to the input terminal of each of the two inverters INV0 and INV1 having different threshold voltages. The individual output terminals of the inverters INV0 and INV1 are connected to the corresponding input terminals of the multiplexer MUX2, and the output terminal of the multiplexer MUX2 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the read data line RD.

[0124] The multiplexer MUX2 has a write data line WD as another input terminal. The multiplexer MUX2 connects one of the output terminals of the two inverters INV0 and INV1 to the input terminal of the inverter INV2 according to the voltage of the write data line WD. A method for setting the respective threshold voltages of the two inverters INV0 and INV1 will be described later.

[0125] Figure 10 Another example of the configuration of the read unit 53 is shown. Figure 10 The read unit 53 shown in has a comparator CMP0. The comparator CMP0 has a bit line BL and a reference line RL as the output terminal of the reference voltage generation unit 57 as input terminals. The voltage of the reference line RL is denoted as V RL . Figure 10 The read unit 53 shown in compares the voltages V BL and V RL in magnitude, and if the voltage V BL is greater than the voltage V RL , then an on voltage is output to the read data line RD, and if the voltage V BL is less than the voltage V RL , then an off voltage is output to the read data line RD.

[0126] Figure 11 An example of the configuration of the reference voltage generation unit 57 is shown. Figure 11 The reference voltage generation unit 57 shown in has two p-channel MOS transistors P0 ( Figure 8 the voltage application unit 52 shown in), two reference resistors REF, two n-channel MOS transistors N2, and a multiplexer MUX3. In the example of Figure 11 , the p-channel MOS transistor P0, the reference resistor REF, and the n-channel MOS transistor N2 are connected in parallel. The multiplexer MUX3 has a reference line RL0 corresponding to the write state 0, a reference line RL1 corresponding to the write state 1, and a write data line WD as input terminals.

[0127] The reference resistor REF has a resistance value different from that of the magnetoresistive element 120 of the memory cell 100. Specifically, the reference resistor REF is preferably an intermediate resistance between the resistance value of the magnetoresistive element 120 in the state 0 and the resistance value of the magnetoresistive element 120 in the state 1. In this way, if the selected magnetoresistive element 120 is in the state 0 in the write state 0, the voltage V RL0 of the reference line RL0 corresponding to the write state 0 is greater than the bit line voltage V BL , and if the selected magnetoresistive element 120 is in the state 1 in the write state 0, the voltage V of the reference line RL0 corresponding to the write state 0RL0 less than the bit line voltage V BL Similarly, if the selected magnetoresistive element 120 is in state 0 in write state 1, the voltage V of the reference line RL1 corresponding to write state 1 RL1 is greater than the bit line voltage V BL and if the selected magnetoresistive element 120 is in state 1 in write state 1, the voltage V of the reference line RL1 corresponding to write state 1 RL1 is less than the bit line voltage V BL . Then, one of the two reference lines RL0 and RL1 is selected according to the write data line WD and output to the reference line RL. In this way, if the selected magnetoresistive element 120 is in state 0, the read data line RD of the read unit 53 shown in Figure 10 becomes the off voltage, and if the selected magnetoresistive element 120 is in state 1, the read data line RD of the read unit 53 shown in Figure 10 becomes the on voltage.

[0128] Figure 12 is another example of the configuration of the reference voltage generation unit 57. Figure 12 The reference voltage generation unit 57 shown has a p-channel MOS transistor P0 ( Figure 8 the voltage application unit 52 shown), a reference resistor REF, an n-channel MOS transistor N2, and a multiplexer MUX4. The multiplexer MUX4 has a state-0 write voltage line WR0, a state-1 write voltage line WR1, and a write data line WD as input terminals. The multiplexer MUX4 selects the voltage of the state-0 write voltage line WR0 or the voltage of the state-1 write voltage line WR1 according to the write data line WD, and outputs the selected voltage as the voltage of the write voltage line WR, so that an output equivalent to the output of the reference voltage generation unit 57 shown in Figure 11 can be obtained.

[0129] Figure 13 is a circuit diagram showing an example of the configuration of the reference resistor REF shown in Figure 11 and Figure 12 . Figure 13The reference resistor REF shown in the figure has magnetoresistive elements M1 to M4 having the same structure as the magnetoresistive element 120 of the memory cell 100 as four resistors. For example, by setting the magnetoresistive elements M1 and M3 to state 0 and setting the magnetoresistive elements M2 and M4 to state 1, the resistance value of the reference resistor REF can be set to an intermediate value between the resistance value when the magnetoresistive element 120 is in state 0 and the resistance value when the magnetoresistive element 120 is in state 1. That is, by using a plurality of magnetoresistive elements M1 to M4, an intermediate value between the resistance value when the magnetoresistive element 120 is in state 0 and the resistance value when the magnetoresistive element 120 is in state 1 can be generated. The configuration of the reference resistor REF is not limited to Figure 13 the configuration shown, and can have any configuration.

[0130] <1-5. Simulation results>

[0131] Now, referring to Figure 14 and Figure 15 , the simulation results of the adaptive writing in the present embodiment will be described. Figure 14 is a circuit diagram of the voltage application unit 52 and the memory cell 100 configured for simulation. Figure 15 is a first example of the simulation results according to the present embodiment.

[0132] In Figure 14 the example, the magnetoresistive element 120 is an MTJ (MTJ element), the selection element 110 is an n-channel MOS transistor, and the voltage application unit 52 is a p-channel MOS transistor. The source line SL is grounded, and the power supply voltage VDD and the word line voltage of the word line WL are set to 1.5V. In addition, the bit line voltage of the bit line BL is set to V BL , the voltage of the write voltage line WR is set to V WR , and the voltage applied to the magnetoresistive element 120 is set to V MTJ .

[0133] In order to perform writing using the VCMA effect, a voltage (write voltage) needs to be applied to the magnetoresistive element 120 to reduce the magnetic anisotropy of the storage layer 124 to zero. The voltage V MTJ at which the magnetic anisotropy of the storage layer 124 becomes zero is set to V c0 . Since the voltage V MTJ depends on the voltage V WR of the write voltage line, it is necessary to adjust this voltage so that the voltage V MTJ is V c0 . At this time, the voltage V MTJ is V c0 of the voltage V WR is different between the case where the magnetoresistive element is in state 0 and the case where it is in state 1. The voltage V when the magnetoresistive element 120 is in state 1MTJ becomes equal to V c0 voltage V WR is set to V WR0 , when the magnetoresistive element 120 is in state 0, voltage V MTJ becomes equal to V c0 voltage V WR is set to V WR1 .

[0134] Figure 15 is a diagram showing a first example for describing the simulation results according to the present embodiment. Figure 15 The lower graph in MTJ plots the relationship between voltage V WR and voltage V MTJ is equal to V c0 voltage V WR is the voltage V used when writing state 1 into the magnetoresistive element 120 WR1 . Similarly, in curve C2, voltage V MTJ is equal to V c0 voltage V WR is the voltage V used when writing state 0 into the magnetoresistive element 120 WR0 .

[0135] Figure 15 The upper graph in BL plots the relationship between voltage V WR and voltage V WR is V WR0 voltage V BL is set to V th0 . This voltage can be used as the threshold voltage of the inverter INV0 constituting the Figure 9 shown in the reading unit 53. In curve C5, voltage V WR is V WR1 voltage V BL is set to V th1 . This voltage can be used as the threshold voltage of the inverter INV1 constituting the Figure 9 in the reading unit 53.

[0136] Figure 16 is a second example of the simulation results according to the embodiment of the present disclosure. InFigure 8 In, the reading unit 53 shown in Figure 9 Figure 9 is used as the reading unit 53.

[0137] In Figure 16 In, the voltage V EN becomes a conduction voltage having a pulse width of 0.3 ns starting at 1 ns, 6 ns, 11 ns, and 16 ns, and the write operation starts. At 1 ns, state 0 is written to the magnetoresistive element 120 that was initially in state 1. At 6 ns, state 0 is written to the magnetoresistive element 120 in state 0. At 11 ns, state 1 is written to the magnetoresistive element 120 in state 0. At 16 ns, state 1 is written to the magnetoresistive element 120 in state 1. In other words, writing is necessary at 1 ns and 11 ns, and writing is not required at 6 ns and 16 ns.

[0138] The voltage V MTJ is equal to V indicated by the horizontal line at 1 ns (A) and 11 ns (C) c0 , where writing is necessary. In other words, ideal precession motion occurs. On the other hand, at 6 ns (B) and 16 ns (D) where writing is not required, the voltage V EN becomes an off voltage, and the voltage V MTJ simultaneously becomes an off voltage, so that the write operation is interrupted. In the case where writing is required, even if the voltage V EN becomes a cut-off voltage, the voltage V WE remains at the conduction voltage, so that the write operation continues. Then, when the magnetization of the storage layer 124 is reversed (refer to the graph of the vertical component of the magnetization mz) and the writing is completed, the voltage V WE becomes a disconnection voltage, and the write operation is interrupted. As described above, it can be seen that an adaptive write mechanism is realized, which controls the continuation or interruption of the write operation while monitoring the current state.

[0139] <1-6. Second Configuration Example of Write Unit>

[0140] Now refer to Figure 7 , Figure 17 and Figure 18 to describe a second configuration example of the write unit 50 according to the present embodiment.

[0141] As Figure 7 shown, similar to the write unit 50 according to the first configuration example, the write unit 50 according to the second configuration example includes a write voltage generation unit 51, a voltage application unit 52, a reading unit 53, a comparison unit 54, a feedback unit 55, and a write selection unit 56. However, the write voltage generation unit 51 of the write unit 50 according to the second configuration example does not have Figure 7Rather than having the state-0 write voltage line 15 (WR0) and the state-1 write voltage line 16 (WR1) as input terminals, it has the write data line 17 (WD) and the write signal line 19 (WE2) as input terminals. Further details will be described later.

[0142] The write data line 17 is connected to the write control unit 40. The write signal line 19 is connected to the write selection unit 56. Under the control of the write control unit 40, in the case of writing state 0, a cut-off voltage is applied to the write data line 17, and in the case of writing state 1, a conduction voltage is applied. Further, the cut-off voltage is a voltage that makes the drain terminal and the source terminal of the n-channel MOS transistor non-conductive when applied to the gate voltage of the n-channel MOS transistor, and can be, for example, a ground voltage. Further, the conduction voltage is a voltage that makes the drain terminal and the source terminal of the n-channel MOS transistor conductive when applied to the gate voltage of the n-channel MOS transistor, and can be, for example, a power supply voltage. The voltage of the write data line 17 is denoted as V WD .

[0143] Now refer to Figure 17 Describe the write voltage generation unit 51 of the write unit 50 according to the second configuration example. However, the operations of the read unit 53, the comparison unit 54, the feedback unit 55, and the write selection unit 56 are similar to those of the first configuration example of the write unit of the present invention, so redundant descriptions will be omitted.

[0144] Figure 17 is a more detailed circuit diagram of the write unit 50 according to the second configuration example. However, Figure 17 is only an example of the configuration of the write unit 50, and the write unit 50 is not limited to this configuration. Moreover, by comparing with the description of Figure 7 mentioned previously, the operation of the circuit diagram shown in Figure 17 can be easily understood. However, some supplementary descriptions will be provided. Further, descriptions of overlapping parts with Figure 8 will be omitted. In the example of Figure 17 , the read unit 53 has the same configuration as the read unit 53 shown in Figure 9 .

[0145] In Figure 17 the write voltage generation unit 51 shown has an inverter INV5, two NAND gates NAND0 and NAND1, and two p-channel MOS transistors P3 and P4. In the example of Figure 17 , the p-channel MOS transistor P3 connected in parallel to the load resistor R0 and the p-channel MOS transistor P4 connected to the load resistor R1.

[0146] The write voltage generation unit 51 applies voltages to the load resistors R0 and R1 provided in the voltage application unit 52 based on the voltages of the write data line 17 (WD) and the write signal line 19 (WE2). For the load resistors R0 and R1, any resistive element can be used, but they can be resistive elements having a film structure equivalent to the film structure of the magnetoresistive element 120 constituting the memory cell 100. Further, in Figure 17 both of the load resistors R0 and R1 are single resistive elements, but one or both of the load resistors R0 and R1 may be configured to have a plurality of resistive elements connected in any desired configuration. In the write voltage generation unit 51, the voltages V WD and V WE2 (their corresponding voltage values) are the ground voltage or the power supply voltage, and thus V WR0 and V WR1 are also the ground voltage or the power supply voltage. In this way, compared with the first configuration example of the write unit 50 according to the present embodiment, there is no need to input an intermediate potential from an external source.

[0147] As described above, in order to perform an ideal precession motion, it is necessary that the voltage V MTJ is equal to V c0 . In order to apply a specific voltage to the magnetoresistive element 120 in this way, the load resistors R0 and R1 are used. The load resistor R0 is used when performing state-0 writing, and the load resistor R1 is used when performing state-1 writing. The setting of the resistance values of the load resistors R0 and R1 is described in the simulation mentioned later.

[0148] Figure 18 is a more detailed circuit diagram of the write unit 50 according to the third configuration example. However, Figure 18 is only an example of the form of the write unit 50, and the write unit 50 is not limited to this form. Further, the description of the overlapping part with Figure 17 will be omitted.

[0149] Figure 18 The read unit 53 shown is different from the read unit 53 shown in Figure 17 in that it has two p-channel MOS transistors P6 and P7, two load resistors R2 and R3, a reference resistor REF, one n-channel MOS transistor N2, and a comparator CMP0. In the example of Figure 18 , the connection of the p-channel MOS transistor P6 to the load resistor R2 and the connection of the p-channel MOS transistor P7 to the load resistor R3 are arranged in parallel. Using these load resistors R2 and R3, a reference voltage V RL can be generated.

[0150] The connection of the p-channel MOS transistor P6 to the load resistor R2 and the connection of the p-channel MOS transistor P7 to the load resistor R3 are also arranged in parallel with the connection of the p-channel MOS transistor P3 in the write voltage generation unit 51 to the load resistor R0 in the voltage application unit 52 and the connection of the p-channel MOS transistor P4 in the write voltage generation unit 51 to the load resistor R1 in the voltage application unit 52.

[0151] In addition, it is desirable that the load resistors R2 and R3 have the same configuration as the load resistors R0 and R1, but they are not limited to this configuration. In addition, the reference resistor REF provided in the read unit 53 may have a configuration similar to the configuration shown in Figure 13 Other operations are similar to those of the first configuration example of the write unit 50 according to the present embodiment, and thus further description will be omitted.

[0152] <1-7. Simulation Results>

[0153] Now refer to Figures 19 to 22 to describe the results of simulating the adaptive write in the present embodiment.

[0154] Figure 19 is a circuit diagram showing a configuration example of the write voltage generation unit 51, the voltage application unit 52, and the memory cell 100 configured for simulation. In the example of Figure 19 , the magnetoresistive element 120 is an MTJ (MTJ element), the selection element 110 is an n-channel MOS transistor, and the voltage application unit 52 has two load resistors R0 and R1. The source line SL is grounded (GND), and the power supply voltage VDD is set to 1.5V. In the case of state-0 write, the gate voltage of the p-channel MOS transistor P3 is set to GND to be in the on state, and the gate voltage of the p-channel MOS transistor P4 is set to VDD to be in the off state. Conversely, in the case of state-1 write, the gate voltage of the p-channel MOS transistor P4 is set to GND to be in the on state, and the gate voltage of the p-channel MOS transistor P3 is set to VDD to be in the off state. In either case, the gate voltage of the n-channel MOS transistor of the selection element 110 is set to VDD to be in the on state.

[0155] Figure 20 is a diagram showing a third example of describing the simulation results according to the present embodiment. The resistance value of the magnetoresistive element 120 is 30k in the 0 state and 90k in the 1 state. The horizontal axis represents the voltage of the magnetoresistive element 120 (MTJ voltage = V MTJ), the vertical axis represents the current flowing through the magnetoresistive element 120. Curve C6 is the voltage-current characteristic when the magnetoresistive element 120 is in state 0, and curve C7 is the voltage-current characteristic when the magnetoresistive element 120 is in state 1. In addition, curve C8 is the load curve of the load resistor R0 used in the case of writing in state -0. The horizontal axis is V MTJ , so when V MTJ is equal to VDD (1.5 V), the current value is 0. Similarly, curve C9 is the load curve of the load resistor R1 used in the case of writing in state -1. If the resistance values of the load resistors R0 and R1 change, then curves C8 and C9 will move up and down on the graph accordingly. Then, it should be understood that the resistance values of the load resistors R0 and R1 can be set such that the voltages at the operation points A and C for performing the write are exactly V c0 .

[0156] Figure 21 is a diagram showing a third example based on simulation results according to the present embodiment, depicting the load resistors R0 and R1. As Figure 21 shown, the simulation results show that the resistance value of the magnetoresistive element 120 in state 0 is normalized to 1, and the resistance value of the magnetoresistive element 120 in state 1 is normalized to 3. The value of the load resistor R0 is 1.64, and the value of the load resistor R1 is 0.87.

[0157] In addition, as described above, the load resistor R0 and the load resistor R1 can be constructed using magnetoresistive elements. In this case, the load resistor R0 and the load resistor R1 can be formed using the same magnetic film as the magnetoresistive element 120 of the memory cell 100. In this case, the desired resistance value can be obtained by setting the reciprocal of the resistance ratio of the load resistor R0 and the load resistor R1 as the area ratio. Additionally, from the perspective of process technology, in the case where it is difficult to form a load resistor with an area smaller than that of the magnetoresistive element 120, for example, by connecting large-area load resistors in series, as described above, the values can be set such that the voltages at the operation points A and C are exactly V c0 .

[0158] Figure 22 is a diagram showing a fourth example for describing the simulation results according to the present embodiment. Figure 18 The write unit 50 shown in is used for this simulation. The initial state of the magnetoresistive element is set to state 1 (m z = -1). In the first half of the simulation, the voltage V WD (write data WD) is set to 0, and state -0 write is performed. In the second half, the voltage V WD is set to 1, and state -1 write is performed.

[0159] The voltage VEN (The signal EN for starting writing) is set to an on voltage (on state) having a pulse width of 0.3 ns at 1 ns, 6 ns, 11 ns, and 16 ns. The voltage V EN The transition to the on voltage causes the voltage V WE (The write enable signal WE) transitions to the on voltage (on state), and writing starts. First, at 1 ns, the write data WD is 0, and the initial state of the magnetoresistive element 120 is state 1, so writing needs to be performed. Therefore, even after the voltage V EN becomes the cutoff voltage, the voltage V WE remains in the on state, and the writing operation continues. The magnetoresistive element 120 undergoes a state change of approximately 2 ns due to the precessional motion. Then, this state change is detected by the reading unit 53, causing the voltage V WE to become the off voltage. In this way, the magnetoresistive element 120 has undergone a state change, the application of the write voltage to the magnetoresistive element 120 is stopped, and unnecessary magnetization dynamics are suppressed. The magnetoresistive element 120 stabilizes to state 0 (mz = 1) in about 3 ns.

[0160] Next, at 6 ns, the voltage V WD is 0, and the magnetoresistive element 120 is in state 0, so writing is not required. Therefore, while the voltage V EN becomes the off state, the voltage V WE also becomes the off state, and the writing operation is interrupted. In this way, in the case where writing is not required, erroneous writing can be suppressed by quickly stopping the application of the write voltage.

[0161] In addition, except that the voltage V WD is set to 1, the writing operation after 11 ns follows the same process as described previously.

[0162] Next, note the voltage applied to the magnetoresistive element 120 at the start of writing. In the fifth graph at the top of Figure 22 , V MTJ = V c0 is represented by a horizontal line. In the case where writing is required, the resistance value of the load resistor (for example, each of the load resistors R0, R1, R2, and R3) is adjusted so that V MTJ = V c0 . In fact, as Figure 22 shows, at 1 ns (A) and 11 ns (C), at the start of writing, V MTJ = V c0 , and ideal precessional motion starts. On the other hand, at 6 ns (B) where a state 0 write is performed in state 0, the resistance value of the magnetoresistive element 120 is low, so V MTJ < Vc0 and there is no precession. Additionally, at 16 ns (D) when the state-1 write is performed in state 1, the resistance value of the magnetoresistive element 120 is high, so V MTJ >V c0 and in-plane precession occurs. Of course, due to self-adaptation, these voltages are no longer applied rapidly, but if only the magnitude of the voltage applied to the magnetoresistive element 120 is focused on, it reveals an operation similar to non-triggered writing. In other words, the writing method in this case can be said to be both self-adaptive type and non-triggered type.

[0163] In this way, independent of the initial state, non-triggered writing is performed by applying different voltages for state-0 writing and state-1 writing. In other words, non-triggered writing is possible, which eliminates the need to perform a read in the initial state before writing. As a result, the time and power consumption required for the initial state read can be reduced, enabling higher-speed and lower-power writing.

[0164] Furthermore, the write operation can be an operation that performs a write only once (single write operation) or an operation that repeatedly writes continuously multiple times (continuous write operation). By performing the write multiple times, the write error rate can be reduced. However, although the optimal write pulse width can vary among the magnetoresistive elements 120 in the memory cell array 10, by using the write unit 50, as described above, for each magnetoresistive element 120, the write pulse width becomes an appropriate pulse width, thereby reducing the write error rate. Thus, in the case where the write error is caused by variations in the optimal pulse width of each magnetoresistive element 120, a continuous write operation is not required. Additionally, the optimal write voltage (amplitude of the pulse voltage) can vary among the magnetoresistive elements 120 in the memory cell array 10, so the write error rate can be reduced by performing the write operation multiple times using different voltages.

[0165] Furthermore, the continuous write operation can be a continuous write process with a verification function. In the verification function, data is read from the target memory cell 100, and it is determined whether the read data matches the written data. If the read data matches the written data, the process ends, and if the read data does not match the written data, the write is repeated. Additionally, the continuous write operation can be a continuous write process with a verification function accompanied by an initial read. In the initial read, data is read from the target memory cell 100 to determine whether writing should start, and it is determined whether the read data matches the written data. If the read data matches the written data, the process ends, and if the read data does not match the written data, the writing starts.

[0166] <1-8. Effects>

[0167] As described above, according to the present embodiment, a memory system 1 as an example of a storage device includes: a magnetoresistive element 120 whose resistance state changes when a voltage is applied, a selection element 110 connected to the magnetoresistive element 120, a control line (e.g., bit line 12) connected to the side of the magnetoresistive element 120 opposite to the selection element 110, a voltage application unit 52 connected to the control line to output a voltage to the magnetoresistive element 120; and a reading unit 53 connected to the control line to read the resistance state of the magnetoresistive element 120. The reading unit 53 reads the resistance state of the magnetoresistive element 120 during a write operation in which the voltage application unit 52 outputs a voltage to the magnetoresistive element 120, and the voltage application unit 52 controls the write operation based on the resistance state of the magnetoresistive element 120 read by the reading unit 53. This configuration enables the voltage application unit 52 and the reading unit 53 to be connected to the bit line 12 (an example of a control line), thereby eliminating the need for separate monitoring wires for each memory cell and allowing adaptive writing without increasing the memory cell area. In addition, regardless of the initial state before writing, the voltage applied to the magnetoresistive element 120 at the start of writing can be made equal to the voltage that eliminates the perpendicular magnetic anisotropy of the storage layer 124, thereby improving write stability.

[0168] In addition, the voltage application unit 52 continues the write operation when the resistance state of the magnetoresistive element 120 read by the reading unit 53 is different from the target resistance state of the magnetoresistive element 120 (e.g., when writing data), and stops the write operation when the resistance state of the magnetoresistive element 120 read by the reading unit 53 is the same as the target resistance state of the magnetoresistive element 120. This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0169] In addition, when the resistance state of the magnetoresistive element 120 read by the reading unit 53 is the same as the target resistance state of the magnetoresistive element 120, the voltage application unit 52 can output a voltage (e.g., a power supply voltage or a ground voltage) to the magnetoresistive element 120 to stop the write operation. This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0170] In addition, the memory system 1 may further include a write voltage generation unit 51 that outputs a voltage that helps the voltage output by the voltage application unit 52 to the voltage application unit 52 according to the target resistance state of the magnetoresistive element 120 (see Figure 7 ). This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0171] In addition, the write voltage generation unit 51 can output a disconnection voltage or a conduction voltage to the voltage application unit 52 according to a write selection voltage indicating whether a write operation is to be performed. This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0172] In addition, in a case where the write selection voltage is a voltage indicating that no write operation is to be performed, the write voltage generation unit 51 can output a disconnection voltage or a conduction voltage to the voltage application unit 52 regardless of the target resistance state of the magnetoresistive element 120. This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0173] In addition, the memory system 1 may further include a comparison unit 54 that compares whether the resistance state of the magnetoresistive element 120 read by the read unit 53 is the same as or different from the target resistance state of the magnetoresistive element 120 (refer to Figure 7 ). This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0174] In addition, the memory system 1 may further include a feedback unit 55 that determines whether to continue or stop the write operation based on the comparison result from the comparison unit 54 (refer to Figure 7 ). This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0175] In addition, the memory system 1 may further include a write selection unit 56 that selects whether to continue or stop the write operation based on the determination result from the feedback unit 55, and the voltage application unit 52 can continue or stop the write operation based on the selection result from the write selection unit 56. This enables reliable implementation of adaptive writing and improved stability of the write operation.

[0176] In addition, the read unit 53 may also have two inverters INV0 and INV1 with different threshold voltages (refer to Figure 9 ). This enables the read unit 53 to be implemented with a simple configuration.

[0177] In addition, the memory system 1 may further include a reference voltage generation unit 57 that supplies a reference voltage to the read unit 53 (refer to Figure 10 ). This enables the read unit 53 to be implemented with a simple configuration.

[0178] In addition, the reference voltage generation unit 57 may also have a plurality of reference resistors REF or a single reference resistor REF (refer to Figure 11 and Figure 12 ). This enables the reference voltage generation unit 57 to be implemented with a simple configuration.

[0179] In addition, at least one of the plurality of reference resistors or the single reference resistor REF may include a plurality of magnetoresistive elements (refer to Figure 13 ). This enables the reference resistor REF to be implemented with a simple configuration.

[0180] In addition, the voltage application unit 52 may further include a plurality of magnetoresistive elements, each of which serves as a load resistor (e.g., load resistor R0 or load resistor R1). Thereby, the voltage application unit 52 can be implemented with a simple structure.

[0181] In addition, at least two of the magnetoresistive elements of the voltage application unit 52 may be elements having different areas. Thereby, two magnetoresistive elements having different resistance values can be implemented with a simple structure.

[0182] In addition, the reading unit 53 may have a plurality of magnetoresistive elements each serving as a load resistor (e.g., load resistor R2 or load resistor R3) (refer to Figure 18 ). This enables the reading unit 53 to be implemented with a simple configuration.

[0183] In addition, at least two magnetoresistive elements of the reading unit 53 may be elements having different regions. Thereby, two magnetoresistive elements having different resistance values can be implemented with a simple structure.

[0184] In addition, the selection element 110 may have a drain terminal, a source terminal, and a gate terminal. One of the two terminals of the magnetoresistive element 120 may be connected to the bit line 12, which is a control line, and the other terminal may be connected to the drain terminal. The source terminal may be connected to the source line 13, and the gate terminal may be connected to the word line 11 (refer to Figure 3 ). Such a configuration also enables reliable implementation of adaptive writing and improved stability of the writing operation.

[0185] In addition, the selection element 110 may have a drain terminal, a source terminal, and a gate terminal. One of the two terminals of the magnetoresistive element 120 may be connected to the source line 13, and the other terminal may be connected to the source terminal. The drain terminal may be connected to the bit line 12, which is a control line, and the gate terminal may be connected to the word line 11 (see Figure 4 ). Such a configuration also enables reliable implementation of adaptive writing and improved stability of the writing operation.

[0186] <2. Other Embodiments>

[0187] In addition to the above embodiments, the configurations and processes according to the above embodiments (examples and variations) can be implemented in various different forms. For example, these configurations and processes are not limited to the examples given above and can take different forms. In addition, unless otherwise specifically stated, the processing procedures, specific names, and information including various data and parameters described and shown herein, as well as the drawings, can be modified as needed.

[0188] In addition, the configurations and processes according to the above-described embodiments (examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific forms of the distribution and integration of the components of each device are not limited to the forms shown in the drawings, and depending on various factors such as load or usage conditions, all or part of them may be functionally or physically distributed and integrated into any unit.

[0189] For example, each MTJ according to the above-described embodiments and their modifications can be used as a magnetoresistive element 120 to configure a storage device such as a hard disk drive (HDD) or other types of storage devices.

[0190] <3. Configuration Example of Electronic Device>

[0191] As an electronic device applying the memory system 1 according to the above-described embodiments (including modifications), the imaging device 300, the distance measurement device 400, and the game device 900 will be described with reference to Figures 23 to 26 For example, each of the imaging device 300, the distance measurement device 400, and the game device 900 uses the memory system 1 according to each of the above-described embodiments as a memory. Examples of the memory include flash memory and the like.

[0192] <3-1. Imaging Device>

[0193] The imaging device 300 applying the memory system 1 according to the above-described embodiments will be described with reference to Figure 23 FIG. is a diagram showing an example of the schematic configuration of the imaging device 300. The imaging device 300 is an example of an electronic device applying the memory system 1 according to the present embodiment. Examples of the imaging device 300 include electronic devices such as digital cameras, video cameras, smartphones, and mobile phones having an imaging function. Figure 23 As shown in

[0194] As Figure 23 shown, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element 303, a control circuit (driving circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture still images and moving images.

[0195] The optical system 301 includes one or more lenses. The optical system 301 guides light (incident light) from a subject to the imaging element 303 and forms an image on the light-receiving surface of the imaging element 303.

[0196] The shutter device 302 is provided between the optical system 301 and the imaging element 303. The shutter device 302 controls the light irradiation period and the light shielding period for the imaging element 303 according to the control of the control circuit 304.

[0197] The imaging element 303 accumulates signal charges for a certain period of time in accordance with the light formed on the light-receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the imaging element 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304.

[0198] The control circuit 304 outputs drive signals for controlling the transfer operation of the imaging element 303 and the shutter operation of the shutter device 302 to drive the imaging element 303 and the shutter device 302.

[0199] The signal processing circuit 305 performs various types of signal processing on the signal charges output from the imaging element 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to the monitor 306 and is also supplied to the memory 307.

[0200] The monitor 306 displays a moving image or a still image captured by the imaging element 303 based on the image data supplied from the signal processing circuit 305. The monitor 306 uses, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel.

[0201] The memory 307 stores the image data supplied from the signal processing circuit 305, that is, the image data of the moving image or the still image captured by the imaging element 303. The memory 307 corresponds to the storage device 1 according to the above-described embodiment.

[0202] Also in the imaging device 300 configured in this way, by using the above-described memory system 1 as the memory 307, adaptive writing and improved writing stability can be reliably achieved.

[0203] <3-2. Distance measuring device>

[0204] Reference will be Figure 24 made to a distance measuring device 400 that applies the memory system 1 according to the above-described embodiment. Figure 24 FIG. is a diagram showing an example of a schematic configuration of the distance measuring device 400. The distance measuring device 400 is an example of an electronic device that applies the memory system 1 according to the present embodiment.

[0205] As Figure 24 shown, the distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, a solid-state imaging device (imaging element) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The distance measuring device 400 can obtain a distance image according to the distance to an object by projecting light from the light source unit 401 onto the object and receiving the light (modulated light or pulsed light) reflected from the surface of the object.

[0206] The light source unit 401 projects light onto the subject. As the light source unit 401, for example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source or a laser diode array in which laser diodes are arranged in a line is used. It should be noted that the laser diode array is supported by a predetermined driving unit (not shown) and is scanned in a direction perpendicular to the array direction of the laser diodes.

[0207] The optical system 402 includes one or more lenses. The optical system 402 guides the light (incident light) from the object to the solid-state imaging device 403 to form an image on the light receiving surface (sensor unit) of the solid-state imaging device 403.

[0208] The solid-state imaging device 403 stores signal charges according to the light of the image formed on the light receiving surface via the optical system 402. A distance signal representing the distance obtained from the light receiving signal (APD output) output from the solid-state imaging device 403 is provided to the signal processing circuit 405. As the solid-state imaging device 403, for example, a solid-state imaging element such as an image sensor is used.

[0209] The control circuit 404 outputs drive signals (control signals) for controlling the operations of the light source unit 401, the solid-state imaging device 403, etc., to drive the light source unit 401, the solid-state imaging device 403, etc.

[0210] The signal processing circuit 405 performs various types of signal processing on the distance signal provided from the solid-state imaging device 403. For example, the signal processing circuit 405 performs image processing for constructing a distance image (e.g., histogram processing, peak detection processing, etc.) based on the distance signal. The image (image data) obtained by the signal processing by the signal processing circuit 405 is provided to the monitor 406 and is also provided to the memory 407.

[0211] The monitor 406 displays the distance image captured by the solid-state imaging device 403 based on the image data provided from the signal processing circuit 405. As the monitor 406, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel is used.

[0212] The memory 407 stores the image data provided from the signal processing circuit 405, that is, the image data of the distance image captured by the solid-state imaging device 403. The memory 407 corresponds to the memory system 1 according to the above-described embodiment.

[0213] Also in the distance measurement device 400 configured in this way, by using the above-described memory system 1 as the memory 407, adaptive writing and improved writing stability can be reliably achieved.

[0214] <3-3. Game device>

[0215] Reference will be made to Figure 25 and Figure 26 describe a game device 900 that applies the memory system 1 according to the above-described embodiment. Figure 25 is a perspective view (external perspective view) showing an example of a schematic configuration of the game device 900. Figure 26 is a block diagram showing an example of a schematic configuration of the game device 900. The game device 900 is an example of an electronic device to which the memory system 1 according to the present embodiment is applicable.

[0216] As Figure 25 shown, for example, the game device 900 has an appearance in which each component is arranged inside and outside a housing 901 formed in a horizontally long flat shape.

[0217] On the front surface of the housing 901, a display panel 902 is provided at the center in its longitudinal direction. In addition, operation keys 903 and 904 are provided on the left and right sides of the display panel 902, respectively, spaced apart from each other in the circumferential direction. An operation key 905 is provided at the lower end of the front surface of the housing 901. The operation keys 903, 904, and 905 are used as direction keys, determination keys, etc., and are used to select menu items, game progress, etc. displayed on the display panel 902.

[0218] On the upper surface of the housing 901, connection terminals 906 for connecting external devices, power terminals 907, a light receiving window 908 for performing infrared communication with external devices, etc. are provided.

[0219] As Figure 26 shown, the game device 900 includes a computing processing unit 910 including a central processing unit (CPU), a storage unit 920 that stores various types of information, and a controller 930 that controls each configuration of the game device 900. Power is supplied to the computing processing unit 910 and the controller 930 from, for example, a battery (not shown) or the like.

[0220] The computing processing unit 910 generates a menu screen for allowing a user to set various types of information or select an application. In addition, the computing processing unit 910 executes the application selected by the user.

[0221] The storage unit 920 stores various types of information set by the user. The storage unit 920 corresponds to the memory system 1 according to the above-described embodiment.

[0222] The controller 930 includes an input receiving unit 931, a communication processing unit 933, and a power control unit 935. The input receiving unit 931 detects the states of, for example, the operation keys 903, 904, and 905. In addition, the communication processing unit 933 performs communication processing with an external device. The power control unit 935 controls the power supplied to each unit of the game device 900.

[0223] Also in the game device 900 configured in this way, by using the above-described memory system 1 as the storage unit 920, adaptive writing and improved writing stability can be reliably achieved.

[0224] It should be noted that the memory system 1 according to each of the above-described embodiments can be mounted on the same semiconductor chip together with a semiconductor circuit forming an arithmetic device or the like to form a semiconductor device (system on a chip: SoC).

[0225] In addition, the memory system 1 according to the above-described embodiments can be mounted on various electronic devices on which a memory (storage unit) can be mounted, as described above. For example, in addition to the imaging device 300 and the game device 900, the memory system 1 can be mounted on various electronic devices such as a notebook personal computer (PC), a mobile device (e.g., a smart phone, a tablet PC, etc.), a personal digital assistant (PDA), a wearable device, and a music device. For example, the memory system 1 serves as various memories such as a memory.

[0226] <4. Supplementary Explanation>

[0227] In addition, the present technology may also have the following configurations. (1)

[0229] A storage device, comprising:

[0230] A magnetoresistive element whose resistance state changes when a voltage is applied;

[0231] A selection element connected to the magnetoresistive element;

[0232] A control line that is connected to a side of the magnetoresistive element opposite to the side connected to the selection element;

[0233] A voltage application unit that is connected to the control line and outputs a voltage to the magnetoresistive element; and

[0234] A reading unit that is connected to the control line to read the resistance state of the magnetoresistive element, wherein

[0235] The reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs a voltage to the magnetoresistive element, and

[0236] The voltage application unit controls its operation based on the resistance state of the magnetoresistive element read by the reading unit. (2)

[0238] The storage device according to (1), wherein

[0239] a voltage application unit that continues the operation when the resistance state of the magnetoresistive element read by the reading unit is different from the target resistance state of the magnetoresistive element, and stops the operation when the resistance state of the magnetoresistive element read by the reading unit is the same as the target resistance state of the magnetoresistive element. (3)

[0241] The storage device according to (2), wherein

[0242] the voltage application unit outputs a voltage for stopping the operation to the magnetoresistive element when the resistance state of the magnetoresistive element read by the reading unit is the same as the target resistance state of the magnetoresistive element. (4)

[0244] The storage device according to (2) or (3) further includes:

[0245] a write voltage generation unit that outputs a voltage that helps the voltage application unit output according to the target resistance state of the magnetoresistive element to the voltage application unit. (5)

[0247] The storage device according to (4), wherein

[0248] the write voltage generation unit outputs a disconnection voltage or a conduction voltage to the voltage application unit according to a write selection voltage indicating whether an operation is to be performed. (6)

[0250] The storage device according to (5), wherein

[0251] the write voltage generation unit outputs a disconnection voltage or a conduction voltage to the voltage application unit regardless of the target resistance state of the magnetoresistive element when the write selection voltage is a voltage indicating that no operation is to be performed. (7)

[0253] The storage device according to any one of (2) to (6) further includes:

[0254] and a comparison unit that makes a comparison to determine whether the resistance state of the magnetoresistive element read by the reading unit is the same as or different from the target resistance state of the magnetoresistive element. (8)

[0256] The storage device according to (7) further includes:

[0257] a feedback unit configured to determine whether to continue or stop the operation according to the comparison result obtained by the comparison unit. (9)

[0259] The storage device according to (8) further includes:

[0260] A write selection unit configured to select to continue or stop an operation according to a determination result obtained by a feedback unit, wherein

[0261] A voltage application unit continues or stops an operation according to a selection result obtained by the write selection unit. (10)

[0263] The storage device according to any one of (1) to (9), wherein

[0264] The read unit includes two inverters having different threshold voltages. (11)

[0266] The storage device according to any one of (1) to (10) further includes:

[0267] A reference voltage generation unit configured to provide a reference voltage to the read unit. (12)

[0269] The storage device according to (11), wherein

[0270] The reference voltage generation unit includes a plurality of reference resistors or a single reference resistor. (13)

[0272] The storage device according to (12), wherein

[0273] At least one of the plurality of reference resistors or the single reference resistor includes a plurality of magnetoresistive elements. (14)

[0275] The storage device according to any one of (1) to (13), wherein

[0276] The voltage application unit includes a plurality of magnetoresistive elements, and each magnetoresistive element serves as a load resistor. (15)

[0278] The storage device according to (14), wherein

[0279] At least two of the plurality of magnetoresistive elements are elements having different areas from each other. (16)

[0281] The storage device according to any one of (1) to (15), wherein

[0282] The read unit includes a plurality of magnetoresistive elements, and each magnetoresistive element serves as a load resistor. (17)

[0284] The memory device according to (16), wherein

[0285] at least two of the plurality of magnetoresistive elements are elements having different areas from each other. (18)

[0287] The memory device according to any one of (1) to (17), wherein

[0288] the selection element includes a drain terminal, a source terminal, and a gate terminal,

[0289] one of the two terminals of the magnetoresistive element is connected to a bit line serving as a control line, and the other terminal is connected to the drain terminal,

[0290] the source terminal is connected to a source line, and

[0291] the gate terminal is connected to a word line. (19)

[0293] An electronic device, comprising:

[0294] a memory device configured to store data, wherein

[0295] the memory device includes:

[0296] a magnetoresistive element whose resistance state changes when a voltage is applied;

[0297] a selection element connected to the magnetoresistive element;

[0298] a control line that is connected to a side of the magnetoresistive element opposite to the side connected to the selection element;

[0299] a voltage application unit connected to the control line and outputting a voltage to the magnetoresistive element; and

[0300] a reading unit connected to the control line to read the resistance state of the magnetoresistive element,

[0301] the reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs a voltage to the magnetoresistive element, and

[0302] the voltage application unit controls its operation according to the resistance state of the magnetoresistive element read by the reading unit. (20)

[0304] A method of controlling a memory device, the method including:

[0305] In a voltage application unit connected to a control line, a voltage is output to a magnetoresistive element. The memory cell includes a magnetoresistive element whose resistance state changes when a voltage is applied and a selection element connected to the magnetoresistive element. The control line is connected to a side of the magnetoresistive element opposite to the side connected to the selection element; and

[0306] The resistance state of the magnetoresistive element is read by a reading unit connected to the control line,

[0307] The reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs a voltage to the magnetoresistive element, and

[0308] The voltage application unit controls its operation based on the resistance state of the magnetoresistive element read by the reading unit. (21)

[0310] A storage device includes:

[0311] A memory cell having a magnetoresistive element capable of changing between a first state and a second state when a voltage is applied and a selection element connected to the magnetoresistive element;

[0312] A voltage application unit connected to a bit line connected to the memory cell and configured to output a first voltage that sets the magnetoresistive element to the first state or a second voltage that sets the magnetoresistive element to the second state to the magnetoresistive element according to write data specifying that the magnetoresistive element is in the first state or the second state; and

[0313] A reading unit connected to the bit line and configured to read whether the magnetoresistive element is in the first state or the second state and output the result as read data, where

[0314] The reading unit reads whether the magnetoresistive element is in the first state or the second state at least during a write operation in which the voltage application unit outputs the first voltage or the second voltage, and outputs the result as read data, and

[0315] If the write data and the read data are different during the write operation, the voltage application unit continues the write operation, and if the write data and the read data are the same, the write operation is stopped. (22)

[0317] The storage device according to (21), wherein,

[0318] The voltage application unit outputs a third voltage different from the first voltage and the second voltage to the magnetoresistive element to stop the write operation when the write data and the read data are the same. (23)

[0320] The storage device according to (21) or (22) further includes:

[0321] A write voltage generation unit outputs a voltage that contributes to a first voltage or a second voltage to a voltage application unit according to write data. (24)

[0323] The storage device according to (23), wherein

[0324] The write voltage generation unit outputs a disconnection voltage or a conduction voltage to the voltage application unit according to a write selection voltage indicating whether a write operation is to be performed. (25)

[0326] The storage device according to (24), wherein

[0327] When the write selection voltage is a voltage indicating that a write operation is not to be performed, the write voltage generation unit outputs a disconnection voltage or a conduction voltage to the voltage application unit independently of the write data. (26)

[0329] The storage device according to any one of (21) to (25) further includes:

[0330] A comparison unit that performs a comparison to determine whether the write data and the read data are the same or different. (27)

[0332] The storage device according to (26) further includes:

[0333] A feedback unit that determines whether to continue or stop the write operation according to the comparison result obtained by the comparison unit. (28)

[0335] The storage device according to (27) further includes:

[0336] A write selection unit that selects whether to continue or stop the write operation according to the determination result obtained by the feedback unit, wherein

[0337] The voltage application unit continues or stops the write operation according to the selection result of the write selection unit. (29)

[0339] The storage device according to any one of (1) to (28), wherein

[0340] The read unit has two inverters with different threshold voltages. (30)

[0342] The storage device according to any one of (21) to (29) further includes:

[0343] A reference voltage generation unit that supplies a reference voltage to the read unit. (31)

[0345] The storage device according to (30), wherein,

[0346] The reference voltage generation unit has a plurality of reference resistors or a single reference resistor. (32)

[0348] The storage device according to (31), wherein,

[0349] At least one of the plurality of reference resistors or the single reference resistor includes a plurality of magnetoresistive elements. (33)

[0351] The storage device according to any one of (21) to (32), wherein,

[0352] The voltage application unit has a plurality of magnetoresistive elements that each function as a load resistor. (34)

[0354] The storage device according to (33), wherein,

[0355] At least two of the plurality of magnetoresistive elements are elements having different areas from each other. (35)

[0357] The storage device according to any one of (21) to (34), wherein,

[0358] The reading unit has a plurality of magnetoresistive elements that each serve as a load resistor. (36)

[0360] The storage device according to (35), wherein,

[0361] At least two of the plurality of magnetoresistive elements are elements having different areas from each other. (37)

[0363] The storage device according to any one of (21) to (36), wherein,

[0364] The selection element has a drain terminal, a source terminal, and a gate terminal,

[0365] One of the two terminals of the magnetoresistive element is connected to the bit line, and the other is connected to the drain terminal,

[0366] The source terminal is connected to the source line, and

[0367] The gate terminal is connected to the word line. (38)

[0369] The storage device according to any one of (21) to (36), wherein,

[0370] The selection element has a drain terminal, a source terminal, and a gate terminal.

[0371] One of the two terminals of the magnetoresistive element is connected to the source line, the other is connected to the source terminal, the drain terminal is connected to the bit line, and

[0372] the gate terminal is connected to the word line. (39)

[0374] An electronic device includes:

[0375] a storage device that stores data,

[0376] The storage device includes:

[0377] memory cells having a magnetoresistive element capable of changing between a first state and a second state when a voltage is applied and a selection element connected to the magnetoresistive element;

[0378] a voltage application unit connected to the bit line connected to the memory cell and configured to output a first voltage that sets the magnetoresistive element to the first state or a second voltage that sets the magnetoresistive element to the second state to the magnetoresistive element according to write data specifying that the magnetoresistive element is in the first state or the second state; and

[0379] a reading unit connected to the bit line and configured to read whether the magnetoresistive element is in the first state or the second state and output the result as read data, wherein

[0380] the reading unit reads whether the magnetoresistive element is in the first state or the second state at least during a write operation in which the voltage application unit outputs the first voltage or the second voltage, and outputs the result as read data, and

[0381] if the write data and the read data are different during the write operation, the voltage application unit continues the write operation, and if the write data and the read data are the same, the write operation is stopped. (40)

[0383] A method of controlling a storage device includes:

[0384] a voltage application unit connected to the bit line, the bit line being connected to the memory cell, the memory cell having a magnetoresistive element capable of changing between a first state and a second state when a voltage is applied and a selection element connected to the magnetoresistive element, and outputting a first voltage that sets the magnetoresistive element to the first state or a second voltage that sets the magnetoresistive element to the second state to the magnetoresistive element according to write data specifying that the magnetoresistive element is in the first state or the second state; and

[0385] A read unit connected to a bit line reads whether the magnetoresistive element is in a first state or a second state, and outputs the result as read data, where

[0386] the read unit reads whether the magnetoresistive element is in a first state or a second state at least during a write operation in which the voltage application unit outputs a first voltage or a second voltage, and outputs the result as read data, and

[0387] if the written data and the read data are different during the write operation, the voltage application unit continues the write operation, and if the written data and the read data are the same, the write operation is stopped. (41)

[0389] An electronic device includes a storage device according to any one of (1) to (18) or (21) to (38). (42)

[0391] A method of controlling a storage device, where the storage device is according to any one of (1) to (18) or (21) to (38).

[0392] List of reference numerals

[0393] 1 Memory system

[0394] 2 Interface unit

[0395] 3 Memory control unit

[0396] 4 Memory array

[0397] 10 Memory cell array

[0398] 11 Word line

[0399] 12 Bit line

[0400] 13 Source line

[0401] 14 Write selection line

[0402] 15 State-0 write voltage line

[0403] 16 State-1 write voltage line

[0404] 17 Write data line

[0405] 18 Write start signal line

[0406] 19 Write signal line

[0407] 20 Bit line address decoder

[0408] 30 Word line address decoder

[0409] 40 Write Control Unit

[0410] 50 Write Unit

[0411] 51 Write Voltage Generation Unit

[0412] 52 Voltage Application Unit

[0413] 53 Read Unit

[0414] 54 Comparison Unit

[0415] 55 Feedback Unit

[0416] 56 Write Selection Unit

[0417] 60 Sense Amplifier

[0418] 70 Column Switch

[0419] 100 Memory Cell

[0420] 101 Wiring

[0421] 102 Wiring

[0422] 103 Contact Layer

[0423] 104 Contact Layer

[0424] 110 Selection Element

[0425] 120 Magnetoresistive Element

[0426] 121 Base Layer

[0427] 122 Magnetization Fixed Layer

[0428] 123 Tunnel Barrier Layer

[0429] 124 Storage Layer

[0430] 125 Capping Layer

[0431] 300 Imaging Device

[0432] 307 Memory

[0433] 400 Distance Measurement Device

[0434] 407 Memory

[0435] 900 Game Device

[0436] 920 Memory Cell

Claims

1. A storage device, comprising: A magnetoresistive element whose resistance state changes when a voltage is applied; A selection element connected to the magnetoresistive element; A control line connected to a side of the magnetoresistive element opposite to the side connected to the selection element; A voltage application unit connected to the control line and outputting a voltage to the magnetoresistive element; And A reading unit connected to the control line and reading the resistance state of the magnetoresistive element, wherein, The reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs the voltage to the magnetoresistive element, and The voltage application unit controls the operation according to the resistance state of the magnetoresistive element read by the reading unit.

2. The storage device according to claim 1, wherein, The voltage application unit continues the operation when the resistance state of the magnetoresistive element read by the reading unit is different from the target resistance state of the magnetoresistive element; And stops the operation when the resistance state of the magnetoresistive element read by the reading unit is the same as the target resistance state of the magnetoresistive element.

3. The storage device according to claim 2, wherein, The voltage application unit outputs a voltage for stopping the operation to the magnetoresistive element when the resistance state of the magnetoresistive element read by the reading unit is the same as the target resistance state of the magnetoresistive element.

4. The storage device according to claim 2, further comprising: A write voltage generation unit configured to output a voltage that helps the voltage output by the voltage application unit according to the target resistance state of the magnetoresistive element to the voltage application unit.

5. The storage device according to claim 4, wherein, The write voltage generation unit outputs a disconnection voltage or a conduction voltage to the voltage application unit according to a write selection voltage indicating whether to perform the operation.

6. The storage device according to claim 5, wherein, The write voltage generation unit outputs the disconnection voltage or the conduction voltage to the voltage application unit independently of the target resistance state of the magnetoresistive element when the write selection voltage is a voltage indicating not to perform the operation.

7. The storage device according to claim 2, further comprising: A comparison unit configured to perform a comparison to determine whether the resistance state of the magnetoresistive element read by the reading unit is the same as or different from the target resistance state of the magnetoresistive element.

8. The storage device according to claim 7, further comprising: A feedback unit configured to determine whether to continue or stop the operation according to a comparison result obtained by the comparison unit.

9. The storage device according to claim 8, further comprising: A write selection unit configured to select whether to continue or stop the operation according to a determination result obtained by the feedback unit, wherein, The voltage application unit continues or stops the operation according to a selection result obtained by the write selection unit.

10. The storage device according to claim 1, wherein, The reading unit includes two inverters having different threshold voltages.

11. The storage device according to claim 1 further comprises: A reference voltage generation unit configured to supply a reference voltage to the reading unit.

12. The storage device according to claim 11, wherein The reference voltage generation unit includes a plurality of reference resistors or a single reference resistor.

13. The storage device according to claim 12, wherein At least one of the plurality of reference resistors or the single reference resistor includes a plurality of magnetoresistive elements.

14. The storage device according to claim 1, wherein The voltage application unit includes a plurality of magnetoresistive elements, and each of the magnetoresistive elements serves as a load resistor.

15. The storage device according to claim 14, wherein At least two of the plurality of magnetoresistive elements are elements having different areas from each other.

16. The storage device according to claim 1, wherein The reading unit includes a plurality of magnetoresistive elements, and each of the magnetoresistive elements serves as a load resistor.

17. The storage device according to claim 16, wherein At least two of the plurality of magnetoresistive elements are elements having different areas from each other.

18. The storage device according to claim 1, wherein The selection element includes a drain terminal, a source terminal, and a gate terminal, One of the two terminals of the magnetoresistive element is connected to a bit line as the control line, and the other terminal is connected to the drain terminal, The source terminal is connected to a source line, and The gate terminal is connected to a word line.

19. An electronic device comprising: A storage device configured to store data, wherein The storage device includes: A magnetoresistive element whose resistance state changes when a voltage is applied; A selection element connected to the magnetoresistive element; A control line connected to a side of the magnetoresistive element opposite to the side connected to the selection element; A voltage application unit connected to the control line and outputting a voltage to the magnetoresistive element; and A reading unit connected to the control line and reading the resistance state of the magnetoresistive element, The reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs the voltage to the magnetoresistive element, and The voltage application unit controls the operation according to the resistance state of the magnetoresistive element read by the reading unit.

20. A method for controlling a storage device, the method comprising: In a memory cell, outputting a voltage to a magnetoresistive element through a voltage application unit connected to a control line, the memory cell including a magnetoresistive element whose resistance state changes when a voltage is applied and a selection element connected to the magnetoresistive element, the control line being connected to a side of the magnetoresistive element opposite to the side connected to the selection element; And Reading the resistance state of the magnetoresistive element by a reading unit connected to the control line, wherein The reading unit reads the resistance state of the magnetoresistive element during an operation in which the voltage application unit outputs the voltage to the magnetoresistive element, and The voltage application unit controls the operation according to the resistance state of the magnetoresistive element read by the reading unit.

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