Memory device and operating method thereof, memory system and operating method thereof

Abstract

The embodiment of the invention discloses a memory device, an operation method of the memory device, a memory system and an operation method of the memory system. The peripheral circuit is coupled with the storage unit array and is configured to obtain a first result corresponding to a specified position in the storage unit array under the initial target reading voltage; the first result comprises the number of bits representing that the reading result of the specified position under the target reading voltage is overturned compared with actually stored specified data, and the specified data is stored at the specified position; adjusting the initial target reading voltage for multiple times, and respectively acquiring a first result corresponding to the target reading voltage at the specified position after each adjustment; determining a valley voltage according to the plurality of obtained first results; the valley voltage is used as a read voltage when a read operation is executed on the memory cell array.

Description

Memory device and operating method thereof, memory system and operating method thereof Technical Field

[0001] The present application relates to, but is not limited to, a memory device and an operating method thereof, a memory system and an operating method thereof. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells changes with age, repeated read operations, and temperature fluctuations, affecting the accuracy of data read from the cells.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory device, comprising: a memory cell array; a peripheral circuit coupled to the memory cell array and configured to: obtain a first result corresponding to an initial target read voltage at a specified position in the memory cell array; the first result includes a number of bits representing the number of bits that are flipped in the read result at the target read voltage at the specified position compared to the actually stored specified data, the specified data being stored at the specified position; adjusting the initial target read voltage multiple times, and obtaining the first result corresponding to the target read voltage at the specified position after each adjustment; determining a valley voltage based on the multiple first results obtained; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: one or more memory devices as described in any one of the first aspects; and a memory controller coupled to and controlling the memory device.

[0006] In a third aspect, an embodiment of the present application provides a memory system, comprising: at least one memory device; a memory controller coupled to the at least one memory device and configured to: obtain a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device; the first result includes a number of bits representing the number of bits that are flipped in the read result at the target read voltage at the specified position compared to the actually stored specified data, the specified data being stored at the specified position; adjusting the initial target read voltage multiple times, and obtaining the first result corresponding to the target read voltage at the specified position after each adjustment; determining a valley voltage based on the multiple first results obtained; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, comprising: obtaining a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device; the first result includes a representation of the number of bits at which the read result at the specified position at the target read voltage is flipped compared to the actually stored specified data, and the specified data is stored at the specified position; adjusting the initial target read voltage multiple times, and obtaining the first result corresponding to the target read voltage at the specified position after each adjustment; determining a valley voltage based on the multiple first results obtained; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: before performing a read operation on data stored in a memory device of the memory system, sending a first instruction, wherein the first instruction indicates obtaining a valley voltage; the valley voltage is obtained according to the operating method described in any one of the fourth aspects; performing a read operation on the data stored in the memory device according to the valley voltage; and performing an error correction code (ECC) decoding operation on the read result of the read operation.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: obtaining a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device; the first result includes a characterization of the number of bits at which the read result at the specified position at the target read voltage is flipped compared to the actually stored specified data, and the specified data is stored at the specified position; adjusting the initial target read voltage multiple times, and obtaining the first result corresponding to the target read voltage at the specified position after each adjustment; determining a valley voltage based on the multiple first results obtained; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0010] In a seventh aspect, the present application provides a memory device, comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit coupled to the memory cell array, comprising control logic and a page buffer; the control logic being configured to: store specified data in a first latch of the page buffer; read the specified data stored in the first latch at a target read voltage to obtain a second result, and store the second result in a second latch of the page buffer; perform a logical operation on the stored specified data and the second result to obtain a third result, and store the third result in a third latch of the page buffer; when the first result includes the number of bits representing that a read result at a specified position at the target read voltage is flipped compared to the actual stored specified data, counting the number of bits in the third result representing that the second result is flipped compared to the specified data and using the counted result as the first result; when the first result includes the relationship between the number of bits representing that a read result at a specified position at the target read voltage is flipped compared to the actual stored specified data and a first preset value, comparing the number of bits in the third result representing that the second result is flipped compared to the specified data with the first preset value, and using the comparison result as the first result.

[0011] In an eighth aspect, the present application provides an operating method for a memory device, wherein the memory device includes a memory cell array and a page buffer; the method includes: storing specified data in a first latch of the page buffer; reading the specified data stored at a specified position at a target read voltage to obtain a second result, and storing the second result in a second latch of the page buffer; performing a logical operation on the stored specified data and the second result to obtain a third result, and storing the third result in a third latch of the page buffer; when the first result includes the number of bits representing that the read result at the specified position at the target read voltage is flipped compared with the actual stored specified data, counting the number of bits in the third result representing that the second result is flipped compared with the specified data and using the statistical result as the first result; when the first result includes the relationship between the number of bits representing that the read result at the specified position at the target read voltage is flipped compared with the actual stored specified data and a first preset value, comparing the number of bits in the third result representing that the second result is flipped compared with the specified data with the first preset value, and using the comparison result as the first result. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0013] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0014] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0015] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0016] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present application;

[0017] FIG3 b is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0018] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0019] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0020] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0021] FIG7 is a schematic diagram of an implementation flow of an operating method of a memory device provided in one embodiment of the present application;

[0022] FIG8 is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0023] FIG9 is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0024] FIG10 is a schematic diagram of a method for confirming the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG8 according to an embodiment of the present application;

[0025] FIG11 is a flowchart of an operating method of a memory device according to an embodiment of the present application;

[0026] FIG12 is a flowchart of an operating method of a memory device according to another embodiment of the present application;

[0027] FIG13 is a block diagram of a memory system provided by an embodiment of the present application;

[0028] FIG14 is a block diagram of a memory system provided by another embodiment of the present application;

[0029] FIG15 is a timing diagram of performing a reread operation according to an embodiment of the present application;

[0030] FIG16 is a timing diagram of determining a valley voltage and performing a read operation in an embodiment of the present application;

[0031] FIG17 is a block diagram of a computer-readable storage medium provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0032] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0033] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0034] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0035] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0038] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0039] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0040] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0041] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0042] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0043] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0044] In one example as shown in FIG2 a , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ).

[0045] In another example, as shown in FIG2 b , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0046] Figure 3a illustrates a schematic structural diagram of a memory cell array of a three-dimensional NAND memory. As shown in Figure 3a, the memory cell array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cell rows parallel to gate isolation structures. Every two rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure, and each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas. An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this.

[0047] In some embodiments, each memory block may be coupled to multiple word lines, and multiple memory cells coupled to each independently controlled word line constitute a physical page. For example, all memory cells in each memory slice in FIG3 a are coupled to constitute a physical page.

[0048] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory device described herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0049] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0050] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0051] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0052] As shown in FIG3 b , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and a top select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0053] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, referring to FIG. 3 a , multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, with each memory cell row being parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page based on the storage mode of the corresponding memory cell 306 (e.g., SLC or MLC as described above). The logical page can constitute the basic data unit for programming and reading operations.

[0054] 3a and 3b, each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, top selection transistor (TSG) 312).

[0055] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0056] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0057] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0058] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0059] 3 b , peripheral circuitry 302 may be coupled to memory cell array 301 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, where the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG5 may also be included.

[0060] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0061] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0062] The control logic 512 can be coupled to each of the other parts of the peripheral circuit described above and is configured to control the operation of each of the other parts of the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface (I / F) 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0063] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient ECC (Error Correction Code) algorithm is typically used during data reading.

[0064] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error exceeds the ECC's error correction capability, data read failures can occur.

[0065] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0066] In some embodiments, a reread operation can typically be performed by querying a retry table provided by the manufacturer. The reread operation is essentially an error correction mechanism. The retry table can provide a reference voltage for reading data. By querying the retry table, each storage cell is read again using a read voltage that deviates from the normal threshold voltage and correcting errors with the ECC error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the retry table query is stopped. If the read error data cannot be corrected, the retry table query is continued until the entire retry table is traversed.

[0067] The aforementioned rereading method requires querying the trial-and-error table entry by entry, which inevitably increases the number of trial-and-error cycles and is time-consuming. Furthermore, the trial-and-error tables provided by manufacturers are only reference values ​​for specific environments. Real-world usage scenarios vary greatly, so the provided tables may not cover many scenarios. Consequently, even after traversing the table data, corrections may not be possible, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the trial-and-error table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0068] In view of one or more of the above problems, an embodiment of the present application provides an operating method for a memory device.

[0069] FIG7 is a schematic diagram of an implementation flow of a method for operating a memory device according to an embodiment of the present application. As shown in FIG7 , the method for operating a memory device specifically includes the following steps:

[0070] Step S10: Obtaining a first result corresponding to an initial target read voltage at a designated location in a memory cell array of the memory device; the first result includes a number of bits representing a flip in the read result at the designated location at the target read voltage compared to the actual stored designated data, and the designated data is stored at the designated location;

[0071] Step S20: adjusting the initial target reading voltage multiple times, and obtaining first results corresponding to the target reading voltage after each adjustment at the designated position;

[0072] Step S30: determining a valley voltage according to the obtained plurality of first results; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0073] Here, the structure of the memory device is referred to in FIG. 3 b , which will not be described in detail here.

[0074] In some embodiments, the memory cell array includes a plurality of memory blocks, each memory block includes a plurality of memory rows, each memory row includes a plurality of memory cells; a preset number of memory cells form a code word (CW).

[0075] Here, the storage row can be understood with reference to the structure and description of the physical page 320 in FIG. 3 b , and the structure of the memory cell array can be understood with reference to the aforementioned FIG. 3 a and FIG. 3 b , which will not be described in detail here.

[0076] Here, a preset number of storage units forms a codeword.

[0077] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a physical page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a physical page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, a code word may include 2 4 , 2 8 or 2 12 storage units.

[0078] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements.

[0079] Memory cells in different types of memory devices (eg, MLC, TLC, or QLC) can store different numbers of bits. Therefore, for codewords of the same size, the number of memory cells included may also be different.

[0080] For example, in a specific embodiment, the size of the codeword is 4KB. Taking the memory cells in the memory cell array as MLC as an example, each memory cell stores 2 bits, so the number of memory cells included in the codeword is 2. 11 .

[0081] For example, in other embodiments, the size of the codeword is 4KB. Taking the memory cells in the memory cell array as QLC as an example, each memory cell stores 4 bits, so the number of memory cells included in the codeword is 2. 10 .

[0082] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0083] It is understandable that a codeword may include multiple storage units, and the number of storage units included in a codeword may be adjusted according to actual conditions.

[0084] It should be noted that in some embodiments, during the process of reading the memory device, a read operation reads the data of a physical page. When the number of storage cells contained in a codeword may be less than the number of storage cells coupled to a physical page, the codeword is the unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the target read voltage can be obtained here. For example, a page can include 4 codewords, and the page buffer hardware operation can count the fail bit count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a physical page. The subsequent calculation uses the added value. It can be understood that the first result here is based on the data of a physical page and can include multiple codewords.

[0085] In some embodiments, before obtaining a first result corresponding to an initial target read voltage at a specified location, the read mode of the memory device is set to a single-level read mode (Single Level Read, SLR); the single-level read mode includes reading at least one bit of storage data stored in a memory cell through a first-level read voltage.

[0086] In some embodiments, the memory cell array includes M bits of memory cells, the memory device includes M pages, and the M-bit memory cells read their M-bit stored data through N-level read voltages; M and N are both integers greater than 1, and N=2 M -1; the method further comprises:

[0087] For each level of the multi-level read voltage corresponding to each type of page, a valley voltage of each level is determined according to a plurality of first results corresponding to the plurality of read voltages of each level.

[0088] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG8 , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7. The binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three types of pages: lower page (LP), middle page (MP), and upper page (UP).

[0089] Taking the memory cell shown in FIG8 as an example, the three-bit memory cell reads its three-bit eight-state storage data through seven levels of read voltages (first-level read voltage L1, second-level read voltage L2, third-level read voltage L3, fourth-level read voltage L4, fifth-level read voltage L5, sixth-level read voltage L6, and seventh-level read voltage L7 shown in FIG8).

[0090] In some embodiments, the memory device operating method further includes: determining a valley voltage of each level of the multiple levels of read voltages corresponding to each type of page according to multiple first results corresponding to the multiple read voltages of each level.

[0091] Exemplarily, each type of page corresponds to multiple levels of read voltages. As shown in FIG8 , the bottom page corresponds to the first-level read voltage L1 and the fifth-level read voltage L5. The middle page corresponds to the second-level read voltage L2, the fourth-level read voltage L4, and the sixth-level read voltage L6. The top page corresponds to the third-level read voltage L3 and the seventh-level read voltage L7. For the first-level read voltage L1 and the fifth-level read voltage L5 corresponding to the bottom page, the valley voltage of the first-level read voltage L1 can be determined based on multiple first results corresponding to the multiple read voltages of the first-level read voltage L1. Then, the valley voltage of the fifth-level read voltage L5 can be determined based on multiple first results corresponding to the multiple read voltages of the fifth-level read voltage L5. In this way, the valley voltage of each level of the multi-level read voltage corresponding to the bottom page can be obtained. The process for determining the valley voltage of each level of the multi-level read voltage corresponding to the middle and top pages is similar to that for the bottom page and will not be further described here.

[0092] The lower page is usually closest to the source / drain, so the valley voltage of each level of the multi-level read voltage corresponding to the lower page is determined first, which has the fastest access speed and the shortest response time, and can ensure balanced performance and durability during data access.

[0093] It should be noted that the method of preferentially determining the valley voltage of each level of the multi-level read voltage corresponding to the lower page is only an example and is not used to limit the order of determining the valley voltage of each level of the multi-level read voltage corresponding to each type of page in the embodiment of the present application.

[0094] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG9 , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four types of pages, namely, a lower page, a middle page, an upper page, and an extra page (Extra Page, XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0095] Taking the memory cell shown in Figure 9 as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in Figure 9).

[0096] Exemplarily, each type of page corresponds to multiple levels of read voltages. As shown in FIG9 , the lower page corresponds to the second level read voltage L2, the eighth level read voltage L8, and the fourteenth level read voltage L14. The middle page corresponds to the third level read voltage L3, the seventh level read voltage L7, the ninth level read voltage L9, and the thirteenth level read voltage L13. The upper page corresponds to the fifth level read voltage L5, the tenth level read voltage L10, the twelfth level read voltage L12, and the fifteenth level read voltage L15. The additional page corresponds to the first level read voltage L1, the fourth level read voltage L4, the sixth level read voltage L6, and the eleventh level read voltage L11.

[0097] For the second-level read voltage L2, the eighth-level read voltage L8, and the fourteenth-level read voltage L14 corresponding to the lower page, the valley voltage of the second-level read voltage L2 can be determined based on the multiple first results corresponding to the multiple read voltages of the second-level read voltage L2. Then, the valley voltage of the eighth-level read voltage L8 can be determined based on the multiple first results corresponding to the multiple read voltages of the eighth-level read voltage L8. Finally, the valley voltage of the fourteenth-level read voltage L14 can be determined based on the multiple first results corresponding to the multiple read voltages of the fourteenth-level read voltage L14. In this way, the valley voltage of each level of the multi-level read voltage corresponding to the lower page can be obtained. The process for determining the valley voltage of each level of the multi-level read voltage corresponding to the middle and upper pages is similar to that for the lower page and will not be repeated here.

[0098] Figure 10 is a schematic diagram of a method for determining the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in Figure 8, according to one embodiment of the present application. Figure 11 is a flow chart of a method for operating a memory device according to one embodiment of the present application. The process of determining the valley voltage will be described in detail below in conjunction with Figures 8, 10, and 11.

[0099] In step S301, a first preset value and a third preset value are obtained; the first preset value may be obtained based on historical data; in some embodiments, the first preset value is less than or equal to an upper limit of a fail bit count (FBC) supported by the memory device.

[0100] In step S302 , designated data is stored in a first latch of a memory device.

[0101] Before step S302 , in the process of performing a write operation on the memory cell array, designated data is written at a designated location in the memory cell array.

[0102] The designated location includes at least one of each storage block, each storage row, and each codeword.

[0103] Here, the designated data serves as functional data for verifying the difference between read data and actual stored data, used to determine valley voltages and verify the reliability and data integrity of memory cells. The designated data can be generated by the memory device itself according to a specified algorithm or provided by a memory controller. In short, the correct designated data (the designated data initially stored with user data) is known to the memory device. To facilitate subsequent comparison and verification operations, the designated data is stored in the first latch of the memory device in step S302 to detect whether the read data at the target read voltage contains read errors or data corruption compared to the actually stored designated data.

[0104] It should be noted that in the embodiments of the present application, the threshold voltage change of the storage cell where the specified data is located is used to reflect the threshold voltage change of the storage cell where the user data stored together with the specified data is located. It can be understood that the manufacturing process and the environment experienced by these storage cells are the same. Therefore, the threshold voltage change of the storage cell where the specified data is located can be used to reflect the threshold voltage change of the storage cell where the user data stored together with the specified data is located.

[0105] The designated location here actually limits the jurisdiction of the designated data. When the designated location includes each storage block, it means that there will be a designated data in each storage block, and the threshold voltage change of the storage cell where the designated data is located is used to reflect the threshold voltage change of the storage cell of the corresponding storage block; when the designated location includes each storage row, it means that there will be a designated data in each storage row, and the threshold voltage change of the storage cell where the designated data is located is used to reflect the threshold voltage change of the storage cell in the corresponding storage row. It can be understood that when the storage capacity corresponding to the designated location is larger, the threshold voltage change of the storage cell where the designated data is located is used to reflect the number of storage cells, and a large number of storage cells can share the threshold change of the storage cell at the designated location, and the time to find the valley voltage is shortened; when the storage capacity corresponding to the designated location is smaller, the threshold voltage change of the storage cell where the designated data is located is used to reflect the number of storage cells, and the corresponding valley voltage is more accurate.

[0106] Exemplarily, the designated data is 110110110…110. It can be understood that after the write operation is performed on the memory cell array, the data stored in each memory cell in the codeword is "110", that is, after the write operation is performed, each memory cell in the codeword is in the first state P1 shown in Figure 8.

[0107] In some embodiments, the first latch includes M sub-latches, and the M sub-latches are respectively used to store data of M types of pages.

[0108] For example, taking the memory cell shown in FIG8 as an example, the first latch includes three sub-latches (Latch1-1, Latch1-2, Latch1-3), and the specified data 110110110…110 is stored in the three sub-latches of the first latch. Among them, Latch1-1 is used to store the upper page data, Latch1-2 is used to store the middle page data, and Latch1-3 is used to store the lower page data, that is, Latch1-1 is used to store 111…1, Latch1-2 is used to store 111…1, and Latch1-3 is used to store 000…0.

[0109] In step S303 , designated data stored at a designated location is read at an initial target read voltage to obtain a second result; and the second result is stored in a second latch of the memory device.

[0110] It should be noted that what is stored in the first latch is the correct data of the designated data, and what is stored in the second latch is the read data of the designated data after a period of time.

[0111] For example, using the initial target read voltage V1 as an example, as shown in FIG10 , the specified data stored in the codeword is read at the initial target read voltage V1 to obtain a second result. Specifically, the data stored in the lower page of the memory cells in the codeword is read at the initial target read voltage V1. Memory cells with threshold voltages less than the initial target read voltage V1 are marked as bit 1, and memory cells with threshold voltages greater than the initial target read voltage V1 are marked as bit 0, thereby obtaining the second result, which is then stored in the second latch of the memory device.

[0112] It should be noted that the initial target read voltage V1 used for the first time here may refer to a preset read voltage that can distinguish two adjacent storage states of a memory cell of the memory device in a previous reading process, wherein the preset read voltage may be an empirical value; or it may be a default value configured when the memory device leaves the factory, which is obtained through a large number of simulation experiments before the memory device leaves the factory.

[0113] In step S304, a logic operation is performed on the stored designated data and the second result to obtain a third result; and the third result is stored in a third latch of the memory device.

[0114] Exemplarily, an exclusive OR (XOR) operation is performed on the data stored in the sub-latches Latch1-3 of the first latch and the second result to obtain a third result; and the third result is stored in the third latch of the memory device.

[0115] It should be noted that the XOR operation is one of the basic logical operations. In binary, if two binary numbers in the same position are the same, the result is "0", and if two binary numbers in the same position are different, the result is "1" (that is, the same is 0, and different is 1).

[0116] The portion of bits that are 1 in the third result represents the number of bits in the second result that are flipped compared to the specified data, that is, the number of bits that are flipped between the specified data stored in the storage cell of the codeword read at the initial target read voltage V1 and the specified data in the storage cell of the codeword written.

[0117] It should be noted that the specified data stored in the first latch can be understood as the data actually stored at the specified location, and the third result is used to determine whether the read data at the specified location obtained by performing a read operation under a certain read voltage is flipped compared to the data actually stored at the specified location. In other words, the third result represents the difference between the read data and the actually stored data.

[0118] For example, each codeword includes 2 3 TLC storage cells, the specified data of the written codeword is 110110110110110110110110, that is, the specified data stored in the first latch is 110110110110110110110110, the data stored in the sub-latch Latch1-1 of the first latch is 11111111, the data stored in the sub-latch Latch1-2 of the first latch is 11111111, and the data stored in the sub-latch Latch1-3 of the first latch is 00000000. The next page data of the specified data stored in the storage cell of the codeword read at the initial target read voltage V1 is 01010101, then the third result is 01010101, and the part of the third result with bits being 1 is the number of bits that are flipped in the read data at the specified position compared with the write data at the same specified position.

[0119] In step S305, the number of bits in the third result representing that the second result is flipped compared to the specified data is compared with the first preset value to determine whether the number of bits in the third result representing that the second result is flipped compared to the specified data is greater than the first preset value, and the comparison result is used as the first result.

[0120] In some embodiments, the first preset value is less than or equal to the upper limit of the failure bit count supported by the memory device. The upper limit of the failure bit count supported by the memory device means that the failure bits within the upper limit can be detected and corrected by the built-in error correction mechanism, while the failure bits exceeding the upper limit cannot be corrected. The size of the first preset value is related to the type of memory device, storage density, etc. The first preset value can be an empirical value; it can also be a default value configured when the memory device leaves the factory, and the default value is obtained through a large number of simulation experiments before the memory device leaves the factory. Exemplarily, the range of the first preset value is set to 70 to 120. More specifically, the first preset value can be 70, 80, 90, 100, 110, 120.

[0121] When the number of bits in the third result indicating that the second result is flipped compared to the specified data is greater than a first preset value, step S306 is executed to determine that the first result is in a failure state, which means that the difference between the read result obtained by performing a read operation with the read voltage corresponding to the first result and the actual stored data is too large, and the read result may contain uncorrectable errors, threatening the integrity and reliability of the data.

[0122] When the number of bits in the third result indicating that the second result is flipped compared to the specified data is less than or equal to a first preset value, step S307 is executed to determine that the first result is in a pass state, which means that the difference between the read result obtained by performing a read operation with the read voltage corresponding to the first result and the actual stored data is small, and the error rate of the read result is low and the reliability is high.

[0123] After executing step S306 or step S307, the process proceeds to step S308. In step S308, a first adjustment is performed on the target read voltage; the step length of the first adjustment is a fixed value.

[0124] Illustratively, Table 1 is an example of multiple first results obtained through multiple iterations.

[0125] Table 1

[0126] Here, the first adjustment can be understood as a large-scale adjustment. In some specific embodiments, the large-scale adjustment here, that is, the step range of the first adjustment, is set to 50mV to 80mV. For example, the step size of the first adjustment can be 50mV, 60mV, 70mV, or 80mV.

[0127] In conjunction with Table 1 and FIG10 , the first result corresponding to the initial target read voltage V1 obtained in the first iteration is a failure state. Step S308 is executed, and taking the initial target read voltage V1 as an example, a first adjustment is performed on the initial target read voltage V1 to obtain a target adjusted voltage (V2 shown in FIG10 ), which is recorded as the first adjusted target read voltage V2. A first voltage difference ΔV1 exists between the initial target read voltage V1 and the first adjusted target read voltage V2. The magnitude of this first voltage difference is the first adjustment step size.

[0128] After executing step S308 , the process returns to step S303 . It should be noted that the target read voltage at this time is the target read voltage V2 after the first adjustment.

[0129] Returning to step S303 , the first data stored at the designated location is read at the target read voltage V2 adjusted for the first time to obtain a second result; and the second result is stored in a second latch of the memory device.

[0130] Step S304 is executed to perform a logic operation on the stored designated data and the second result to obtain a third result; and the third result is stored in a third latch of the memory device.

[0131] Step S305 is executed to compare the number of bits in the third result indicating that the second result is flipped compared to the specified data with a first preset value to determine whether the number of bits in the third result indicating that the second result is flipped compared to the specified data is greater than the first preset value.

[0132] When the number of bits in the third result indicating that the second result is flipped compared to the designated data is greater than the first preset value, step S306 is executed to determine that the first result corresponding to the designated position being at the first adjusted target read voltage V2 is a failure state.

[0133] When the number of bits in the third result indicating that the second result is flipped compared to the designated data is less than or equal to the first preset value, step S307 is executed to determine that the first result corresponding to the designated position being at the first adjusted target read voltage V2 is a pass state.

[0134] As shown in Table 1 and FIG10 , a first adjustment is performed on the initial target read voltage V1 to obtain a target adjustment voltage (V2 shown in FIG10 is the target read voltage V2 after the first adjustment). A second iteration is performed to obtain the first result corresponding to the target read voltage V2 after the first adjustment, which is a failure state.

[0135] It is understood that the direction of the first adjustment of the initial target read voltage V1 can be random, as long as the absolute value of the voltage difference between the first adjusted target read voltage V2 obtained after the first adjustment of the initial target read voltage V1 and the initial target read voltage V1 is equal to the first adjustment step size. The first adjusted target read voltage V2 can be greater than or less than the initial target read voltage V1.

[0136] It is understood that multiple adjustments to the initial target read voltage are performed, and the first result corresponding to each adjusted target read voltage at the designated position is obtained. It is necessary to loop through steps 303 to S308. It should be noted that in actual use, the number of loops through steps 303 to S308 may vary based on actual needs, and this should not unduly limit the scope of protection of this application.

[0137] In some embodiments, step S309 is executed after executing step S303 to step S308 three times in a loop.

[0138] In some embodiments, step S308 is performed again after obtaining the first result corresponding to the first adjusted target read voltage V2 at the specified position. As shown in FIG10 , the first adjustment is performed on the first adjusted target read voltage V2 to obtain the second adjusted target read voltage V3. The first adjusted target read voltage V2 and the second adjusted target read voltage V3 have a voltage difference ΔV1.

[0139] After executing step S308, the process returns to step S303. It should be noted that the target read voltage at this time is the second adjusted target read voltage V3. Steps S303 to S07 are executed, and the third iteration obtains the first result corresponding to the second adjusted target read voltage V3, which is a pass state.

[0140] In this way, three first results corresponding to three different read voltages are obtained. In some embodiments, as shown in Table 1 and FIG10 , in the first iteration, the first result corresponding to the initial target read voltage V1 at the designated position is a failure state. In the second iteration, the first result corresponding to the first adjusted target read voltage V2 at the designated position is a failure state. In the third iteration, the first result corresponding to the second adjusted target read voltage V3 at the designated position is a failure state.

[0141] After obtaining a preset number of first results, the process proceeds to step S309 . In step S309 , it is determined whether the first results corresponding to the target read voltages adjusted multiple times are all in a failure state.

[0142] If one or more pass states appear in the multiple first results corresponding to the target read voltages after multiple adjustments, step S310 is executed. For example, the three first results corresponding to the three different read voltages shown in Table 1 are, in order, a fail state, a fail state, and a pass state. Therefore, if one pass state appears in the multiple first results, step S310 is continued.

[0143] In step S310 , it is determined whether a first pass state after one or more failure states appears in a plurality of first results corresponding to the target read voltages adjusted multiple times.

[0144] If the first pass state after one or more fail states appear in the multiple first results corresponding to the target read voltages after multiple adjustments, step S311 is executed. For example, the three first results corresponding to the three different read voltages shown in FIG10 are a fail state, a fail state, and a pass state, respectively, i.e., the first pass state after multiple fail states appear in the multiple first results.

[0145] If the first pass state after the fail state does not appear in the multiple first results corresponding to the target read voltage after multiple adjustments, then the process returns to step S308. For example, if the three first results corresponding to the three different read voltages are a pass state, a fail state, and a fail state, then the process returns to step S308, performs a first adjustment on the read voltage after the previous adjustment, and obtains the first result at the adjusted read voltage. The first result corresponding to the adjusted read voltage can be obtained by executing steps S303 to S307.

[0146] In step S311, after the first pass state after one or more failure states appear in multiple first results corresponding to the target read voltage after multiple adjustments, a second adjustment is performed on the target read voltage after the previous adjustment; the step size of the second adjustment is smaller than the step size of the first adjustment.

[0147] For example, as shown in Table 1 and Figure 10, a second adjustment is performed on the second-adjusted target read voltage V3 to obtain a third-adjusted target read voltage V4. The fourth iteration results in a first result corresponding to the third-adjusted target read voltage V4 being a pass. A second voltage difference ΔV2 exists between the second-adjusted target read voltage V3 and the third-adjusted target read voltage V4. The magnitude of this second voltage difference ΔV2 is the second adjustment step size. The second adjustment step size is smaller than the first adjustment step size, i.e., the second voltage difference ΔV2 is smaller than the first voltage difference ΔV1. The second adjustment step size is relatively small, and the second adjustment can be understood as a smaller adjustment.

[0148] Exemplarily, the step size range of the second adjustment is set to 10 mV to 40 mV. More specifically, the step size of the second adjustment can be 10 mV, 15 mV, 25 mV, 35 mV, or 40 mV.

[0149] It should be noted that after executing step S311 , the fourth iteration is performed by executing steps S303 to S307 to obtain the first result corresponding to the third adjusted target reading voltage V4 .

[0150] In other embodiments, after the first pass state occurs after one or more fail states appear in multiple first results corresponding to the target read voltage after multiple adjustments, a third adjustment is made to the read voltage after the previous adjustment based on the statistical number of third results corresponding to the first pass state; the step size of the third adjustment changes according to the number of bits in the third result that represent the flipping of the second result compared to the specified data.

[0151] As shown in Table 1 and Figure 10, the first result corresponding to the target read voltage V4 after the third adjustment obtained in the 4th iteration is the first pass state after one or more failure states appear in multiple first results corresponding to the target read voltages after multiple adjustments. According to the statistical number of third results corresponding to the target read voltage V4 after the third adjustment, the target read voltage V4 after the third adjustment is adjusted for the third time.

[0152] Specifically, the number of bits in the third result corresponding to the third adjusted target read voltage V4 that indicate flipped bits in the second result compared to the specified data is counted. If the statistical result is less than 0.5 times the first preset value, it can be considered that the number of flipped bits is small, indicating that the error rate of the read result obtained by performing the read operation with the third adjusted target read voltage V4 is very low. In this case, the step size of the third adjustment can be adjusted to be larger than the step size of the first adjustment. Increasing the step size can enable faster exploration of possible states, thereby improving efficiency.

[0153] If the statistical result is greater than or equal to 0.5 times the first preset value, then it can be considered that although the number of flipped bits is within the upper limit of the failed bit count supported by the memory device, the number of flipped bits is large, which means that the error rate of the read result obtained by performing the read operation with the target read voltage V4 after the third adjustment is high.

[0154] In this case, the step size of the third adjustment can be adjusted to be smaller than the step size of the second adjustment. Reducing the step size can obtain more first results of the pass state near the target read voltage V4 after the third adjustment of the first pass state, thereby increasing the judgment basis for determining the valley bottom voltage.

[0155] The above approach flexibly and dynamically adjusts the third adjustment step size according to the statistical number of the third results corresponding to the first-pass state, thereby improving system performance and accuracy.

[0156] After step S311 , step S312 is executed. If the multiple first results corresponding to the target read voltage after multiple adjustments reflect a change from a fail state to at least one pass state and then to a fail state, step S313 is executed to stop adjusting the read voltage and end the operation.

[0157] If the multiple first results corresponding to the target read voltages after multiple adjustments do not reflect a change from a fail state to at least one pass state and then to a fail state, return to step S311, perform a second adjustment on the target read voltage V4 after the third adjustment to obtain a fourth adjusted target read voltage V5, perform a fifth iteration, and obtain the first result corresponding to the fourth adjusted target read voltage V5 as a pass state.

[0158] Step S312 is executed again. At this time, the multiple first results corresponding to the target read voltage after multiple adjustments still do not reflect the change from the failure state to the pass state at least once and then to the failure state. Return to step S311 to perform a second adjustment on the target read voltage V5 after the fourth adjustment to obtain the target read voltage V6 after the fifth adjustment. Perform the sixth iteration to obtain the first result corresponding to the target read voltage V6 after the fifth adjustment, which is the failure state.

[0159] It should be noted that after executing step S311, the method in steps S303 through S307 is executed to obtain the first result corresponding to each adjusted read voltage at the specified position. If the multiple first results corresponding to the target read voltage after multiple adjustments reflect a change from a fail state to at least one pass state and then to a fail state, step S313 is executed to stop adjusting the read voltage, thus terminating the operation.

[0160] In some embodiments, when the adjusted read voltage corresponds to multiple first results reflecting multiple pass states between the fail states at both ends, the adjusted read voltage corresponding to a pass state in the middle of the multiple pass states is used as the valley voltage.

[0161] For example, as shown in Table 1 and FIG10 , the first result obtained at the initial target read voltage V1 in the first iteration is a fail state. The first result obtained at the target read voltage V2 after the first adjustment in the second iteration is a fail state. The first result obtained at the target read voltage V3 after the second adjustment in the third iteration is a pass state. The first result obtained at the target read voltage V4 after the third adjustment in the fourth iteration is a pass state. The first result obtained at the target read voltage V5 after the fourth adjustment in the fifth iteration is a pass state. The first result obtained at the target read voltage V6 after the fifth adjustment in the sixth iteration is a fail state.

[0162] The multiple first results corresponding to the adjusted read voltages shown in Table 1 reflect three pass states that are located between the fail states at both ends. The adjusted read voltage corresponding to the pass state at the middle position among the three pass states is used as the valley voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is used as the valley voltage.

[0163] It can be understood that the read voltage corresponding to the first result obtained in the fourth iteration is the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG. 8 .

[0164] It should be noted that, in actual use, the number of iterations (i.e., the number of times the second adjustment is made to the read voltage) may vary according to actual needs. The implementation method of obtaining 6 first results after 6 iterations for determining the valley voltage is only an example, and the scope of protection of this application should not be excessively limited here.

[0165] In some embodiments, when the multiple first results corresponding to the adjusted read voltage reflect an even number of pass states between the fail states at both ends, the adjusted read voltage corresponding to a pass state in the middle of the multiple pass states is used as the valley voltage.

[0166] For example, Table 2 is an example of a plurality of first results obtained through multiple iterations. In the plurality of first results shown in Table 2, the average value of the read voltages corresponding to the first results obtained in the fourth and fifth iterations is used as the valley voltage.

[0167] Table 2

[0168] In some embodiments, when the plurality of first results corresponding to the adjusted read voltages represent a pass state between the fail states at both ends, the adjusted read voltage corresponding to the pass state is used as the valley voltage.

[0169] For example, Table 3 is an example of a plurality of first results obtained through multiple iterations. Among the plurality of first results shown in Table 3, the read voltage corresponding to the first result obtained through the third iteration is used as the valley voltage.

[0170] Table 3

[0171] If the judgment result of step S309 in Figure 11 is yes, that is, the multiple first results corresponding to the target read voltage after multiple adjustments are all failure states, indicating that no pass state appears in the multiple first results, then step S314 is executed to increase the step size corresponding to the first adjustment.

[0172] If no pass state appears in the multiple first results corresponding to the target read voltage after multiple adjustments, it means that the step size corresponding to the current first adjustment is too small, resulting in a small voltage adjustment range. Therefore, by increasing the step size corresponding to the first adjustment, the voltage adjustment range can be increased to speed up the search for the first pass state.

[0173] After step S314 , step S315 is executed to compare the increased first adjustment step length with the third preset value to determine whether the increased first adjustment step length is greater than the third preset value.

[0174] In some embodiments, the third preset value serves as a limit or constraint, controlling the step size of the first adjustment to balance speed and accuracy. The size of the third preset value is related to the type and storage density of the memory device. The third preset value can be an empirical value or a factory-configured default value for the memory device, derived from extensive simulation experiments. For example, the third preset value is set in the range of 80mV to 100mV.

[0175] When the increased first adjustment step size is less than or equal to the third preset value, it means that when adjusting the voltage with this step size, the speed of searching for the first pass state is accelerated without reducing the accuracy. In this case, step S308 is executed again with the increased first adjustment step size.

[0176] If the increased first adjustment step size is greater than the third preset value, this indicates that adjusting the voltage with this step size speeds up the search for the first pass state, but the larger adjustment amplitude may result in missing some states, thereby reducing the accuracy of using the read state as a basis for determining the valley voltage. In this case, step S316 is executed to reduce the amount of data stored at the specified location, and then step S303 is executed again.

[0177] It can be understood that when the increased first adjustment step size is greater than the third preset value, a balance between speed and accuracy can be achieved by reducing the amount of data read from the designated data stored at the designated location. Specifically, the amount of designated data stored in the first latch remains unchanged, and the amount of data read from the designated data stored at the designated location is reduced. Because the designated data serves as functional data for verifying the difference between the read data and the actual stored data and is representative, even if the amount of data read from the designated location is reduced, necessary information is not lost. The threshold voltage changes of the storage cells containing the user data stored together with the designated data can still be reflected through the threshold voltage changes of the storage cells containing some of the designated data.

[0178] Then, when obtaining the first result corresponding to the specified position at the corresponding voltage, the total amount of data included in the second result can be reduced. This also reduces the total amount of data included in the third result obtained by performing a logical operation on the corresponding portion of the specified data stored in the first latch and the second result. This reduction in the total amount can, to a certain extent, reduce the number of bits counted from the total amount. Specifically, the number of bits in the third result indicating that the second result has been flipped compared to the specified data will also be reduced, making the number of bits in the third result indicating that the second result has been flipped compared to the specified data more likely to fall within the range of the first preset value. This makes it easier to find the first pass state after one or more failure states have occurred in multiple first results corresponding to the target read voltages after multiple adjustments.

[0179] It should be noted that the process of confirming the valley voltages of other levels of read voltages corresponding to the lower page, and the process of confirming the valley voltages of multi-level read voltages corresponding to the middle page and the upper page are similar to the methods disclosed in the above embodiments and will not be repeated here.

[0180] For example, taking the case where the designated position includes a codeword and the memory cell included in the codeword is a TLC memory cell, 7 levels of read voltage are required to read its three-bit eight-state storage data. Therefore, the operation method for determining the valley voltage disclosed in the above embodiment will be executed 7 times to obtain 7 valley voltages corresponding to the 7 levels of read voltage respectively.

[0181] It should be noted that the target read voltage in the embodiments of the present application is a general concept. The initial target read voltage and all subsequent adjusted read voltages (the target read voltage V2 after the first adjustment, the target read voltage V3 after the second adjustment, the target read voltage V4 after the third adjustment, the target read voltage V5 after the fourth adjustment, and the target read voltage V6 after the fifth adjustment) can all be referred to as target read voltages.

[0182] FIG12 is a flowchart of an operating method of a memory device according to another embodiment of the present invention. The process of determining the valley voltage will be described in detail below with reference to FIG8 , FIG10 and FIG12 .

[0183] Here, the operation method of step S301 to step S304 has been described before and will not be repeated here.

[0184] It should be noted that step S301 also includes a process of obtaining a second preset value.

[0185] In step S317, the number of bits in the third result indicating that the second result is flipped compared to the specified data is counted, and the result of the count is used as the first result. It is determined whether the number of bits in the third result indicating that the second result is flipped compared to the specified data is greater than a first preset value, that is, whether the first result is greater than the first preset value.

[0186] If the first result is less than or equal to the first preset value, step S318 is executed.

[0187] As shown in FIG12 , using the initial target read voltage as an example, when the first result corresponding to the initial target read voltage is less than or equal to the first preset value, step S318 is executed. In step S318, the initial target read voltage is first adjusted based on the first result to obtain a target adjusted read voltage; and the first result corresponding to the target adjusted read voltage at the specified position is obtained.

[0188] For example, as shown in FIG10 , the initial target read voltage V1 is first adjusted based on the first result to obtain an adjusted target voltage (V2 shown in FIG10 ), which is recorded as the target read voltage V2 after the first adjustment. A first voltage difference ΔV1 exists between the initial target read voltage V1 and the target read voltage V2 after the first adjustment. The magnitude of the first voltage difference is the first adjustment step size. The magnitude of the first adjustment step size is determined based on the first result.

[0189] Specifically, if the first result corresponding to the initial target read voltage V1 is less than 0.5 times the first preset value, it can be considered that the number of flipped bits is small, meaning that the error rate of the read result obtained by performing the read operation at the initial target read voltage V1 is very low. In this case, the first adjustment can be set to a large adjustment, that is, the first adjustment step size is relatively large, to more quickly explore possible first results, thereby improving efficiency.

[0190] If the first result corresponding to the initial target read voltage V1 is greater than or equal to 0.5 times the first preset value, then it can be considered that although the number of flipped bits is within the upper limit of the failed bit count supported by the memory device, the number of flipped bits is large, indicating that the error rate of the read result obtained by performing the read operation at the initial target read voltage V1 is high. In this case, the first adjustment can be set to a small adjustment, that is, the first adjustment step size is relatively small. Reducing the step size can obtain more first results within the first preset value range near the initial target read voltage V1, thereby increasing the basis for determining the valley voltage.

[0191] It is understood that the direction of the first adjustment of the initial target read voltage V1 can be random, and it is sufficient to ensure that the absolute value of the voltage difference between the first adjusted target read voltage V2 obtained after the first adjustment of the initial target read voltage V1 and the initial target read voltage V1 is equal to the first adjustment step size. It is understood that the first adjusted target read voltage V2 can be greater than or less than the initial target read voltage V1.

[0192] In step S319 , the first result corresponding to the target adjusted read voltage at the designated position is compared with a second preset value to determine whether the first result is less than or equal to the second preset value.

[0193] In some embodiments, the second preset value is used as a judgment threshold for determining the valley voltage. That is, when the first result is less than or equal to the second preset value, it indicates that the read voltage corresponding to the first result is used as the valley voltage, and the error rate of the read result is low and the reliability is high.

[0194] The size of the second preset value depends on the type and storage density of the memory device. The second preset value can be an empirical value or a default value configured at the factory for the memory device, which is derived from extensive simulation experiments before the memory device leaves the factory. For example, the second preset value ranges from 5 to 30. More specifically, the second preset value can be 5, 10, 15, 20, 25, or 30.

[0195] In some embodiments, when step S319 is executed after step S318, if the first result corresponding to the target adjusted read voltage (i.e., the first adjusted target read voltage V2) at the designated position is less than or equal to the second predetermined value, step S320 is executed, and the operation ends. It is understood that the first adjusted target read voltage V2 can now serve as the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG8 .

[0196] In other embodiments, when step S319 is executed after step S318, if the first result corresponding to the target adjustment read voltage (i.e., the target read voltage V2 after the first adjustment) at the specified position is greater than the second preset value, return to step S317, compare the first result greater than the second preset value with the first preset value, and determine whether the first result is less than or equal to the first preset value.

[0197] If the first result corresponding to the target adjusted read voltage (i.e., the target read voltage V2 after the first adjustment) at the designated position is less than or equal to the first preset value and greater than the second preset value, step S318 is continued to be executed. At this time, the target read voltage referred to in step S318 is the target read voltage V2 after the first adjustment. Based on the first result corresponding to the target read voltage V2 after the first adjustment at the designated position, a first adjustment is performed on the target read voltage V2 after the first adjustment to obtain the adjusted read voltage and the first result corresponding to the target read voltage after the first adjustment at the designated position.

[0198] In some embodiments, based on the first result corresponding to the first adjusted target read voltage V2 at the specified position, the step size of the first adjustment of the first adjusted target read voltage V2 is varied based on the value of the first result. The specific method for varying the step size of the first adjustment based on the value of the first result can be found in the description of step S318 and is not further described here.

[0199] In some embodiments, based on the first result corresponding to the target read voltage V2 after the first adjustment at the specified position, the direction of the second adjustment of the target read voltage V2 after the first adjustment is related to the size relationship between the first result corresponding to the initial target read voltage V1 and the first result corresponding to the target read voltage V2 after the first adjustment.

[0200] For example, after the first adjustment of the initial target read voltage V1, the target read voltage V2 after the first adjustment is greater than the initial target read voltage V1, and the first result corresponding to the target read voltage V2 after the first adjustment is smaller than the first result corresponding to the initial target read voltage V1, indicating that adjusting the initial target read voltage V1 to the right (in the direction of increasing voltage) can reduce the number of bits in the read result under the target read voltage that are flipped compared to the actually stored specified data.

[0201] Therefore, when the first adjusted target read voltage V2 is further adjusted to the right, the first adjusted target read voltage V2 is preferentially adjusted to obtain the adjusted read voltage and the first result corresponding to the specified position under the adjusted read voltage.

[0202] It is understandable that the direction of the first adjustment of a target read voltage is selected based on the change trend of the first result before and after the previous first adjustment to further reduce the number of bits of the read result under the adjusted read voltage that are flipped compared to the actually stored specified data.

[0203] After obtaining the adjusted read voltage and the first result corresponding to the specified position being at the adjusted read voltage, step S319 is continued.

[0204] If it is determined that the first result corresponding to the adjusted read voltage is less than or equal to the second preset value, step S320 is executed to end the operation.

[0205] In some embodiments, determining the valley voltage based on the obtained multiple first results includes: when the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value, taking the read voltage corresponding to the smallest first result among the multiple first results as the valley voltage.

[0206] For example, Table 4 shows an example of multiple first results obtained through multiple iterations. As shown in Table 4, the first result obtained in the first iteration is 120. The first result obtained in the second iteration is 100. The first result obtained in the third iteration is 70. The first result obtained in the fourth iteration is 5.

[0207] In some implementations, the first preset value is set to 120, and the second preset value is set to 10.

[0208] In some embodiments, during the execution of the operating method of the memory device shown in FIG. 12 , when the first result obtained in the fourth iteration is less than or equal to the second preset value, a preset number of iterations may be continued to obtain additional first results.

[0209] In this way, the accuracy of determining the valley voltage based on multiple first results can be further enhanced. The first results obtained from the 5th to 7th iterations are shown in Table 4. The first result obtained from the 5th iteration is 40. The first result obtained from the 6th iteration is 90. The first result obtained from the 7th iteration is 110.

[0210] The read voltage corresponding to the smallest first result among the multiple first results in Table 4 is used as the valley bottom voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is used as the valley bottom voltage.

[0211] It can be understood that the read voltage corresponding to the first result obtained in the fourth iteration is the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG. 8 .

[0212] Table 4

[0213] If the judgment result of step S317 in FIG. 12 is that the first result is greater than the first preset value, step S321 is executed to adjust the target read voltage multiple times and obtain multiple first results corresponding to the specified position under the target read voltage after the multiple adjustments.

[0214] After obtaining multiple first results, execute step S3222.

[0215] In step S322, the plurality of first results are compared with the first preset value to determine whether the plurality of first results are all greater than the first preset value. If the plurality of first results are all greater than the first preset value, step S314 is executed to increase the step size corresponding to the first adjustment.

[0216] After step S314 , step S315 is executed to compare the increased first adjustment step length with the third preset value to determine whether the increased first adjustment step length is greater than the third preset value.

[0217] If the increased first adjustment step size is less than or equal to the third preset value, this indicates that adjusting the voltage with this step size accelerates the search for the first result less than the first preset value without reducing accuracy. Step S3321 is then executed again with the increased first adjustment step size.

[0218] If the increased first adjustment step size is greater than the third preset value, this indicates that adjusting the voltage with this step size speeds up the search for first results less than the first preset value. However, the larger adjustment amplitude may result in missing some first results, thereby reducing the accuracy of using the first results as a basis for determining the valley voltage. In this case, step S316 is executed to reduce the amount of designated data stored at the designated location, and then step S303 is executed again.

[0219] In step S322 , if there is a first result less than or equal to the first preset value among the plurality of first results, step S318 is executed.

[0220] It should be noted that the process of confirming the valley voltages of other levels of read voltages corresponding to the lower page, and the process of confirming the valley voltages of multi-level read voltages corresponding to the middle page and the upper page are similar to the methods disclosed in the above embodiments and will not be repeated here.

[0221] The operating method of the memory device provided in the embodiments of the present application uses the number of bits flipped compared to the actual stored specified data in the read result at a target read voltage at a specified location in the memory cell array as a first result, adjusts the initial target read voltage multiple times, and obtains the first results corresponding to the read voltage at the specified location after each adjustment. Based on the obtained multiple first results, a valley voltage is determined as the read voltage when performing a read operation on the memory cell array. This effectively avoids the time-consuming and incomplete scenario coverage problems associated with using a trial-and-error table, saves space occupied by the trial-and-error table, finds the valley voltage more quickly and accurately, effectively reduces the delay in determining the valley voltage, and improves product reliability and user experience.

[0222] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0223] An embodiment of the present application provides a memory device, as shown in FIG3 b . The memory device 300 includes: a memory cell array 301; and a peripheral circuit 302 coupled to the memory cell array 301 and configured to perform the following steps shown in FIG7 :

[0224] Step S10: Obtaining a first result corresponding to an initial target read voltage at a designated location in a memory cell array of the memory device; the first result includes a number of bits representing a flip in the read result at the designated location at the target read voltage compared to the actual stored designated data, and the designated data is stored at the designated location;

[0225] Step S20: adjusting the initial target read voltage multiple times, and obtaining first results corresponding to the read voltage at each adjusted position;

[0226] Step S30: determining a valley voltage according to the obtained plurality of first results; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0227] Here, the structure of the memory device refers to the aforementioned FIG. 3 b , and the structure of the peripheral circuit refers to the aforementioned FIG. 5 , which will not be described in detail here.

[0228] In some embodiments, the peripheral circuit is configured to: before obtaining a first result corresponding to an initial target read voltage at a specified location, set the read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in the memory cell through a first-level read voltage.

[0229] In some embodiments, a memory cell array includes M bits, a memory device includes M pages, and an M-bit memory cell reads its M-bit stored data using an N-level read voltage; M and N are both integers greater than 1, and N=2 M -1; the peripheral circuit is configured as:

[0230] For each level of the multiple levels of read voltages corresponding to each type of page, a valley voltage of each level is determined according to a plurality of first results corresponding to the plurality of read voltages of each level.

[0231] Exemplarily, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include the 0th state to the 7th state. Referring to FIG8 , the 8 states are respectively the 0th state E, the 1st state P1, the 2nd state P2…the 7th state P7, and the binary data corresponding to the 8 states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three types of pages, namely, the lower page, the middle page, and the upper page. Here, the three storage bits corresponding to the 8 states are stored in the lower page, the middle page, and the upper page, respectively. Taking the memory cell shown in FIG8 as an example, the three-bit memory cell reads its three-bit eight-state storage data through a 7-level read voltage.

[0232] Exemplarily, each type of page corresponds to multiple levels of read voltages. As shown in FIG8 , the lower page corresponds to a first-level read voltage L1 and a fifth-level read voltage L5. For the first-level read voltage L1 and the fifth-level read voltage L5 corresponding to the lower page, the valley voltage of the first-level read voltage L1 can be determined based on multiple first results corresponding to the multiple read voltages of the first-level read voltage L1. Then, the valley voltage of the fifth-level read voltage L5 can be determined based on multiple first results corresponding to the multiple read voltages of the fifth-level read voltage L5. In this way, the valley voltage of each level of the multiple levels of read voltages corresponding to the lower page can be obtained.

[0233] The process of determining the valley voltage of each level of the multi-level read voltage corresponding to the middle page and the upper page is similar to that of the lower page and will not be repeated here.

[0234] In some embodiments, a memory cell array includes a plurality of memory blocks, each memory block includes a plurality of memory rows, and each memory row includes a plurality of memory cells; a preset number of memory cells form a codeword; and the peripheral circuit is configured to: write specified data at a specified location in the memory cell array during a write operation on the memory cell array; wherein the specified location includes at least one of each memory block, each memory row, and each codeword.

[0235] In some embodiments, during a write operation performed on a memory cell array, designated data is written into a codeword of the memory cell array.

[0236] In some embodiments, the peripheral circuit is configured to: obtain a first preset value and a third preset value; the first preset value can be obtained based on historical data; the first preset value is less than or equal to the upper limit of the failed bit count supported by the memory device.

[0237] In some embodiments, the peripheral circuit is configured to: store specified data; read the specified data stored at the specified location at an initial target read voltage to obtain a second result; perform a logical operation on the stored specified data and the second result to obtain a third result; when the first result includes a relationship between the number of bits representing that the read result at the specified location at the target read voltage is flipped compared to the actual stored specified data and a first preset value, compare the number of bits in the third result representing that the second result is flipped compared to the specified data with the first preset value, and use the result of the comparison as the first result.

[0238] In some embodiments, the peripheral circuit includes: a first latch D1, a second latch D2, and a third latch D3; wherein the first latch D1 is configured to store specified data; the second latch D2 is configured to store a second result; and the third latch D3 is configured to store a third result.

[0239] Exemplarily, the first latch D1 , the second latch D2 , and the third latch D3 are located in a page buffer of a peripheral circuit.

[0240] In some embodiments, the first latch D1 includes M sub-latches, and the M sub-latches are respectively used to store data of M types of pages.

[0241] For example, taking the memory cell shown in FIG8 as an example, the first latch includes three sub-latches (Latch1-1, Latch1-2, Latch1-3), and the specified data 110110110…110 is stored in the three sub-latches of the first latch. Among them, Latch1-1 is used to store the upper page data, Latch1-2 is used to store the middle page data, and Latch1-3 is used to store the lower page data, that is, Latch1-1 is used to store 111…1, Latch1-2 is used to store 111…1, and Latch1-3 is used to store 000…0.

[0242] As shown in FIG10 , the specified data stored in the codeword is read at an initial target read voltage V1 to obtain a second result. Specifically, the data stored in the lower page of the memory cells in the codeword is read at the initial target read voltage V1. Memory cells with threshold voltages less than the initial target read voltage V1 are marked as bit 1, and memory cells with threshold voltages greater than the initial target read voltage V1 are marked as bit 0. This results in a second result that is stored in a second latch of the memory device.

[0243] In some embodiments, an exclusive OR (XOR) operation is performed on the data stored in the sub-latches Latch1-3 of the first latch and the second result to obtain a third result; and the third result is stored in a third latch of the memory device.

[0244] For example, each codeword includes 2 3 TLC storage cells, the specified data of the written codeword is 110110110110110110110110, that is, the specified data stored in the first latch is 110110110110110110110110, the data stored in the sub-latch Latch1-1 of the first latch is 11111111, the data stored in the sub-latch Latch1-2 of the first latch is 11111111, and the data stored in the sub-latch Latch1-3 of the first latch is 00000000. The next page data of the specified data stored in the storage cell of the codeword read at the initial target read voltage V1 is 01010101, then the third result is 01010101, and the part of the third result with bits being 1 is the number of bits that are flipped in the read data at the specified position compared with the write data at the same specified position.

[0245] In some embodiments, the first result includes a relationship between the number of bits that are flipped compared to the actually stored specified data in the read result at the target read voltage at the specified position and a first preset value; the peripheral circuit is configured to: determine whether the number of bits in the third result that are flipped compared to the specified data in the second result is greater than the first preset value, and use the comparison result as the first result.

[0246] Further, the peripheral circuit is configured to: when the number of bits in the third result representing that the second result is flipped compared to the specified data is greater than a first preset value, judge the first result to be a fail state; when the number of bits in the third result representing that the second result is flipped compared to the specified data is less than or equal to the first preset value, judge the first result to be a pass state.

[0247] In some embodiments, the peripheral circuit is configured to: when adjusting the initial target read voltage multiple times, perform a first adjustment on the read voltage adjusted previously each time; and the step size of the first adjustment is a fixed value.

[0248] Exemplarily, referring to Table 1 and FIG10 , the first result corresponding to the initial target read voltage V1 obtained in the first iteration is a failure state. The initial target read voltage V1 is adjusted multiple times. Specifically, the initial target read voltage V1 is adjusted first to obtain a target adjusted voltage (V2 shown in FIG10 ), which is recorded as the target read voltage V2 after the first adjustment. The first result corresponding to the target read voltage V2 after the first adjustment obtained in the second iteration is a failure state. A first voltage difference ΔV1 exists between the initial target read voltage V1 and the target read voltage V2 after the first adjustment. The magnitude of this first voltage difference is the step size of the first adjustment. The step size of the first adjustment is relatively large, and the first adjustment can be understood as a large-scale adjustment.

[0249] In some embodiments, the peripheral circuit is configured to: perform a second adjustment on the read voltage after the previous adjustment after the first pass state occurs after one or more failure states appear in multiple first results corresponding to the target read voltage after multiple adjustments; the step size of the second adjustment is smaller than the step size of the first adjustment.

[0250] Exemplarily, a first adjustment is performed on the target read voltage V2 after the first adjustment to obtain a target read voltage V3 after the second adjustment, and a third iteration is performed to obtain a first result corresponding to the target read voltage V3 after the second adjustment, which is a pass state, that is, the first pass state after a fail state appears in multiple first results corresponding to the target read voltages after multiple adjustments.

[0251] A second adjustment is performed on the second-adjusted target read voltage V3 to obtain a third-adjusted target read voltage V4. The fourth iteration results in a first result corresponding to the third-adjusted target read voltage V4, which is a pass state. A second voltage difference ΔV2 exists between the second-adjusted target read voltage V3 and the third-adjusted target read voltage V4. The magnitude of the second voltage difference ΔV2 is the step size of the second adjustment. The step size of the second adjustment is smaller than the step size of the first adjustment, i.e., the second voltage difference ΔV2 is smaller than the first voltage difference ΔV1. The amplitude of the second adjustment step size is relatively small, and the second adjustment can be understood as a smaller amplitude adjustment. A second adjustment is continued on the third-adjusted target read voltage V4 to obtain a fourth-adjusted target read voltage V5. The fifth iteration results in a first result corresponding to the fourth-adjusted target read voltage V5, which is a pass state.

[0252] In other embodiments, the peripheral circuit is configured to: after a first pass state occurs after one or more fail states appear in multiple first results corresponding to the target read voltage after multiple adjustments, perform a third adjustment on the read voltage after the previous adjustment based on the statistical number of third results corresponding to the first pass state; the step size of the third adjustment is based on the change in the number of bits in the third result that represent the flipping of the second result compared to the specified data.

[0253] For example, the first result corresponding to the third adjusted target read voltage V4 obtained in the fourth iteration is the first pass state after a fail state occurs in multiple first results corresponding to the multiple adjusted target read voltages. Based on the statistical number of third results corresponding to the third adjusted target read voltage V4, a third adjustment is made to the third adjusted target read voltage V4. Specifically, the number of bits in the third result corresponding to the third adjusted target read voltage V4 that indicate a flipped bit in the second result compared to the specified data is counted. If the statistical result is less than 0.5 times the first preset value, it can be determined that the number of flipped bits is small, indicating that the error rate of the read result obtained by performing the read operation with the third adjusted target read voltage V4 is very low. In this case, the step size of the third adjustment can be adjusted to be larger than the step size of the first adjustment. Increasing the step size allows for faster exploration of possible states, thereby improving efficiency.

[0254] If the statistical result is greater than or equal to 0.5 times the first preset value, it can be determined that although the number of flipped bits is within the upper limit of the failed bit count supported by the memory device, the number of flipped bits is large, indicating that the error rate of the read result obtained by performing a read operation at the third adjusted target read voltage V4 is high. In this case, the step size of the third adjustment can be adjusted to be smaller than the step size of the second adjustment. Reducing the step size can obtain more first pass state results near the third adjusted target read voltage V4 in the first pass state, thereby increasing the basis for determining the valley voltage.

[0255] In some embodiments, the peripheral circuit is configured to: when the initial target read voltage is adjusted multiple times, stop adjusting the read voltage when multiple first results corresponding to the target read voltage after the multiple adjustments reflect a change from a fail state to at least one pass state and then to a fail state.

[0256] If the multiple first results corresponding to the target read voltage after multiple adjustments do not reflect a change from a fail state to at least one pass state and then back to a fail state, a first adjustment is performed on the target read voltage V5 after the fourth adjustment to obtain a fifth adjusted target read voltage V6. A sixth iteration is performed to obtain a first result corresponding to the fifth adjusted target read voltage V6 that is a fail state. At this point, if the multiple first results corresponding to the target read voltage after multiple adjustments reflect a change from a fail state to at least one pass state and then back to a fail state, adjustment of the read voltage is stopped, and the operation ends.

[0257] In some embodiments, the peripheral circuit is configured as follows: when the multiple first results corresponding to the adjusted read voltage include one pass state in the middle of the fail states at both ends, the adjusted read voltage corresponding to the one pass state is used as the valley voltage; when the multiple first results corresponding to the adjusted read voltage include multiple pass states in the middle of the fail states at both ends, the adjusted read voltage corresponding to the one pass state in the middle position among the multiple pass states is used as the valley voltage.

[0258] Exemplarily, the multiple first results corresponding to the adjusted read voltages shown in Table 1 reflect three pass states that are between the fail states at both ends, and the adjusted read voltage corresponding to the pass state at the middle position among the three pass states is used as the valley voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is used as the valley voltage.

[0259] It can be understood that the read voltage corresponding to the first result obtained in the fourth iteration is the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG. 8 .

[0260] Exemplarily, the multiple first results corresponding to the adjusted read voltages shown in Table 2 reflect two pass states between the fail states at both ends, and the average value of the read voltages corresponding to the first results obtained in the 4th and 5th iterations is taken as the valley voltage.

[0261] Exemplarily, the multiple first results corresponding to the adjusted read voltages shown in Table 3 reflect a pass state between the fail states at both ends, and the read voltage corresponding to the first result obtained in the third iteration is used as the valley voltage.

[0262] In some embodiments, the peripheral circuit is configured to: increase the step size corresponding to the first adjustment when multiple first results corresponding to the target read voltage after multiple adjustments are all in a failure state; and reduce the reading amount of the specified data stored at the specified location when the increased step size of the first adjustment exceeds a third preset value.

[0263] In some embodiments, the third preset value serves as a limit or constraint, controlling the step size of the first adjustment to balance speed and accuracy. The size of the third preset value is related to the type and storage density of the memory device. The third preset value can be an empirical value or a factory-configured default value for the memory device, derived from extensive simulation experiments. For example, the third preset value is set in the range of 80mV to 100mV.

[0264] It can be understood that when the increased first adjustment step size is greater than the third preset value, a balance between speed and accuracy can be achieved by reducing the amount of designated data stored at the designated location that is read. Specifically, the amount of designated data stored in the first latch remains unchanged, and the amount of designated data stored at the designated location that is read is reduced. Because the designated data serves as functional data for verifying the difference between the read data and the actual stored data and is representative, even if the amount of designated data stored at the designated location is reduced, necessary information is not lost. The threshold voltage changes of the storage cells containing some of the designated data can still reflect the threshold voltage changes of the storage cells containing the user data stored together with the designated data.

[0265] When obtaining the first result corresponding to the specified position at the corresponding voltage, the total amount of data included in the second result can be reduced. After performing a logical operation on the second result using the second result and the corresponding portion of the specified data stored in the first latch, the total amount of data included in the third result will also be reduced. This reduction in the total amount can, to a certain extent, reduce the number of bits counted from the total amount, that is, the number of bits in the third result indicating that the second result has been flipped compared to the specified data will also be reduced, making the number of bits in the third result indicating that the second result has been flipped compared to the specified data more likely to fall within the range of the first preset value. This makes it easier to find the first pass state after one or more failure states have occurred in multiple first results corresponding to the target read voltages after multiple adjustments.

[0266] In some embodiments, the first result includes a characterization of the number of bits that are flipped in the read result at the specified position under the target read voltage compared to the actually stored specified data; the peripheral circuit is configured to: when the first result corresponding to the initial target read voltage is less than or equal to a first preset value, perform a first adjustment on the initial target read voltage according to the first result to obtain a target adjusted read voltage; and obtain the first result corresponding to the specified position under the target adjusted read voltage.

[0267] In some embodiments, the peripheral circuit is configured to: when the first result corresponding to the target adjusted read voltage at the specified position is less than or equal to the first preset value and greater than the second preset value, continue to perform a first adjustment on the target adjusted read voltage, and obtain the first result corresponding to the adjusted read voltage at the specified position, until the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value; the step size of the first adjustment changes according to the value of the first result.

[0268] In some embodiments, the peripheral circuit is configured to use the read voltage corresponding to the smallest first result among the plurality of first results as the valley voltage when the first result corresponding to the final adjusted read voltage is less than or equal to a second preset value.

[0269] Exemplarily, the first preset value is set to 120, and the second preset value is set to 10. The read voltage corresponding to the smallest first result among the multiple first results in Table 4 is taken as the valley voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is taken as the valley voltage.

[0270] In some embodiments, the peripheral circuit is configured to: increase the step size corresponding to the first adjustment when multiple first results corresponding to the target read voltage after multiple adjustments are greater than a first preset value; and reduce the reading amount of the specified data stored at the specified location when the increased step size of the first adjustment exceeds a third preset value.

[0271] An embodiment of the present application provides a memory system, as shown in FIG13 , wherein the memory system 102 includes: one or more memory devices 104 as described in the above embodiments; and a memory controller 106 coupled to the memory device 104 and controlling the memory device 104 .

[0272] In some embodiments, the memory controller 106 is configured to: before performing a read operation on data stored in the memory device, send a first instruction instructing to obtain a valley voltage; the memory device 104 is configured to: receive the first instruction, obtain the valley voltage, and send the obtained valley voltage to the memory controller 106; the memory controller 106 is further configured to: perform a read operation on the data stored in the memory device 104 based on the valley voltage; and perform an error correction code decoding operation on the read result of the read operation.

[0273] In some embodiments, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0274] In this way, the memory controller directly receives the valley voltage from the memory device, reducing data transmission time between the memory controller and the memory device and reserving sufficient time for subsequent error correction code (ECC) decoding of the read results. Furthermore, the memory controller directly performs a read operation and an ECC decoding operation based on the valley voltage, shortening overall operation time.

[0275] An embodiment of the present application provides an operating method for a memory system, the operating method comprising: before performing a read operation on data stored in a memory device of the memory system, sending a first instruction, the first instruction instructing to obtain a valley voltage; the valley voltage is obtained by the operating method described in any of the above embodiments; performing a read operation on the data stored in the memory device based on the valley voltage; and performing an error correction code decoding operation on the read result of the read operation.

[0276] Another embodiment of the present application provides a memory system, as shown in Figure 13, the memory system 102 includes: at least one memory device 104; a memory controller 106, coupled to the at least one memory device 104 and configured to: obtain a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device; the first result includes a number of bits representing the number of bits that are flipped in the read result at the target read voltage at the specified position compared to the actual stored specified data, and the specified data is stored at the specified position; the initial target read voltage is adjusted multiple times, and the first result corresponding to the specified position at each adjusted target read voltage is obtained respectively; based on the multiple first results obtained, a valley voltage is determined; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0277] In some embodiments, the memory controller 106 is configured to: before performing a read operation on the data stored in the memory device 104, send a second instruction, the second instruction instructing to obtain a first result at a specified location under multiple different target read voltages; the memory device 104 is configured to: receive the second instruction, obtain multiple first results at the specified location under multiple different target read voltages, and send the obtained first results to the memory controller 106; the memory controller 106 is further configured to: determine a valley voltage based on the multiple first results corresponding to the multiple different read voltages; and perform a read operation on the data stored in the memory device based on the valley voltage.

[0278] In some embodiments, a memory cell array of a memory device includes a plurality of memory blocks, each memory block includes a plurality of memory rows, each memory row includes a plurality of memory cells; a preset number of memory cells form a codeword.

[0279] In some embodiments, the designated location includes at least one of each memory block, each memory row, and each codeword.

[0280] In some embodiments, the memory device 106 is configured to: read the specified data stored at the specified location at an initial target read voltage to obtain a second result; perform a logical operation on the stored specified data and the second result to obtain a third result; when the first result includes the number of bits representing that the read result at the specified location at the target read voltage is flipped compared with the actually stored specified data, count the number of bits in the third result representing that the second result is flipped compared with the specified data and use the counted result as the first result; when the first result includes the relationship between the number of bits representing that the read result at the specified location at the target read voltage is flipped compared with the actually stored specified data and a first preset value, compare the number of bits in the third result representing that the second result is flipped compared with the specified data with the first preset value, and use the comparison result as the first result.

[0281] In some embodiments, the data volume of the first result is less than a preset data volume threshold.

[0282] 15 is a timing diagram of performing a reread operation according to an embodiment of the present application. DQx may be represented as a data bus signal, and Cycle Type may further represent the type of the data bus signal.

[0283] As shown in FIG15 , a read command may include, for example, two sub-commands (e.g., 00h and 30h). For example, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the non-memory device receives sub-command 30h, it may first cache the data DATA (e.g., Dn) corresponding to the page of the received address in a page buffer within the read time, and then read the data DATA on demand. It should be noted that in the above embodiment, when performing a reread operation, the memory device and the memory controller need to frequently transmit data corresponding to a page, and transmitting this data takes a long time.

[0284] Figure 16 is a timing diagram for determining the valley voltage and performing a read operation in an embodiment of the present application. As shown in Figure 16, in addition to a conventional read command (e.g., a read command including two sub-commands (e.g., 00h and 30h)), an embodiment of the present application also includes a second instruction, for example, the second instruction including sub-commands EBh and 70h / 78h. In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After receiving sub-command 30h, the memory device 104 receives sub-commands EBh and 70h / 78h of the second instruction. Under the direction of the second instruction, the memory device 104 obtains a first result corresponding to a target read voltage at a specified location in the memory cell array of the memory device and sends the obtained first result to the memory controller. The memory controller determines the valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device and performs a read operation on the data stored in the memory device based on the valley voltage.

[0285] It should be noted that the second instruction provided in the embodiment of the present application is only an example and should not unduly limit the scope of protection of the present application.

[0286] In some embodiments, the data volume of the first result is less than a preset data volume threshold, for example, the data volume of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0287] Another embodiment of the present application provides a method for operating a memory system, including: obtaining a first result corresponding to an initial target read voltage at a specified position in a memory cell array of a memory device; the first result includes a number of bits representing the number of bits that are flipped in the read result at the target read voltage at the specified position compared to the actual stored specified data, and the specified data is stored at the specified position; adjusting the initial target read voltage multiple times, and obtaining the first result corresponding to the specified position at each adjusted target read voltage; determining a valley voltage based on the multiple first results obtained; the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0288] In some embodiments, the method further includes: before performing a read operation on the data stored in the memory device, sending a second instruction, the second instruction instructing to obtain multiple first results at a specified location under multiple different target read voltages; determining a valley voltage based on the multiple first results corresponding to the multiple different read voltages; and performing a read operation on the data stored in the memory device based on the valley voltage.

[0289] In some embodiments, the data volume of the first result is less than a preset data volume threshold, for example, the data volume of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0290] In some embodiments, the method further includes: reading the specified data stored at the specified position at the initial target read voltage to obtain a second result; performing a logical operation on the stored specified data and the second result to obtain a third result; when the first result includes the number of bits representing that the read result at the specified position at the target read voltage is flipped compared with the actually stored specified data, counting the number of bits in the third result representing that the second result is flipped compared with the specified data and using the statistical result as the first result; when the first result includes the relationship between the number of bits representing that the read result at the specified position at the target read voltage is flipped compared with the actually stored specified data and the first preset value, comparing the number of bits in the third result representing that the second result is flipped compared with the specified data with the first preset value, and using the comparison result as the first result.

[0291] Another embodiment of the present application provides a memory device, as shown in FIG5 , the memory device includes: a memory cell array 301, including a plurality of memory cells; a peripheral circuit coupled to the memory cell array 301, including a control logic 512 and a page buffer 504; the control logic 512 is configured to: store specified data in a first latch of the page buffer; read the specified data stored in the first latch at a target read voltage to obtain a second result, and store the second result in a second latch of the page buffer; perform a logical operation on the stored specified data and the second result to obtain a third result, and store the third result in the page buffer; in the third latch of the device; when the first result includes the number of bits that are flipped in the read result at the target read voltage at the specified position compared with the actually stored specified data, the number of bits that are flipped in the third result compared with the specified data is counted and the statistical result is used as the first result; when the first result includes the relationship between the number of bits that are flipped in the read result at the target read voltage at the specified position compared with the actually stored specified data and the first preset value, the number of bits that are flipped in the third result compared with the specified data is compared with the first preset value, and the result of the comparison is used as the first result.

[0292] The first result includes a number of bits representing the number of bits flipped when the reading result at the designated position under the target reading voltage is compared with the designated data actually stored.

[0293] In some embodiments, a memory cell array of a memory device includes a plurality of memory blocks, each memory block includes a plurality of memory rows, each memory row includes a plurality of memory cells; a preset number of memory cells form a codeword.

[0294] In some embodiments, the designated location includes at least one of each memory block, each memory row, and each codeword.

[0295] Yet another embodiment of the present application provides an operating method for a memory device, the memory device comprising a memory cell array and a page buffer. The method comprises: storing specified data in a first latch of the page buffer; reading the specified data stored at a specified location at a target read voltage to obtain a second result, and storing the second result in a second latch of the page buffer; performing a logical operation on the stored specified data and the second result to obtain a third result, and storing the third result in a third latch of the page buffer; when the first result includes a number of bits representing a flipped position in the read result at the target read voltage compared to the actual stored specified data, counting the number of bits in the third result representing a flipped position in the second result compared to the specified data and using the counted result as the first result; when the first result includes a relationship between the number of bits representing a flipped position in the read result at the target read voltage compared to the actual stored specified data and a first preset value, comparing the number of bits in the third result representing a flipped position in the second result compared to the specified data with the first preset value and using the comparison result as the first result; the first result includes a number of bits representing a flipped position in the read result at the target read voltage compared to the actual stored specified data.

[0296] Referring to FIG17 , FIG17 is a block diagram of a computer-readable storage medium provided in an embodiment of the present application. As shown in FIG17 , an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium 200 stores a computer program 210. When the computer program 210 is executed by a processor, it can implement an operating method of a memory system as described in the above technical solution. The operating method includes: obtaining a first result corresponding to an initial target read voltage at a specified position in a memory cell array of a memory device; the first result includes a number of bits representing the number of bits flipped in the read result at the target read voltage at the specified position compared to the actual stored specified data, wherein the specified data is stored at the specified position; adjusting the initial target read voltage multiple times, and obtaining the first result corresponding to each adjusted target read voltage at the specified position; determining a valley voltage based on the multiple first results obtained; and the valley voltage is used as a read voltage when performing a read operation on the memory cell array.

[0297] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0298] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application. Industrial Applicability

[0299] The memory device and operating method thereof, as well as the memory system and operating method thereof, provided in the embodiments of the present application, effectively avoid the time-consuming and incomplete scenario coverage issues associated with using a trial-and-error table. This saves space occupied by the trial-and-error table, allows for faster and more accurate determination of the valley voltage, and effectively reduces the latency associated with determining the valley voltage. Furthermore, performing a read operation based on the obtained valley voltage significantly increases the probability of correctly reading stored data, improving product reliability and user experience.

Claims

1. A memory device, comprising: A memory cell array; A peripheral circuit is coupled to the memory cell array and is configured to: Obtaining a first result corresponding to an initial target read voltage at a designated position in the memory cell array; the first result includes a number of bits representing a flip of a read result at the designated position at the target read voltage compared to designated data actually stored, wherein the designated position stores the designated data; Adjusting the initial target read voltage multiple times, and respectively obtaining first results corresponding to the target read voltage after each adjustment at the designated position; A valley voltage is determined according to the obtained plurality of first results; the valley voltage is used as a read voltage when a read operation is performed on the memory cell array.

2. The memory device according to claim 1, wherein: The memory cell array includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory rows, each of the memory rows includes a plurality of memory cells; a preset number of the memory cells form a codeword; The peripheral circuit is configured as: In the process of performing a write operation on the memory cell array, writing the specified data at a specified position in the memory cell array; The designated location includes at least one of each of the storage blocks, each of the storage rows, and each of the codewords.

3. The memory device according to claim 1, wherein: The peripheral circuit is configured as: storing the specified data; reading the designated data stored at the designated location at the initial target read voltage to obtain a second result; Performing a logical operation on the stored designated data and the second result to obtain a third result; When the first result includes a reading result indicating that the specified position is at a target reading voltage, When the number of bits of the actually stored designated data that are flipped is determined, the number of bits in the third result that represent the second result being flipped compared to the designated data is counted and the counted result is used as the first result; When the first result includes the relationship between the number of bits that are flipped in the read result at the specified position under the target read voltage compared to the actually stored specified data and a first preset value, the number of bits that are flipped in the second result compared to the specified data in the third result is compared with the first preset value, and the result of the comparison is used as the first result.

4. The memory device according to claim 3, wherein: The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to: store the specified data; The second latch is configured to: store the second result; The third latch is configured to store the third result.

5. The memory device according to claim 3, wherein: The first result includes a relationship between the number of bits of the read result at the designated position under the target read voltage that are flipped compared to the designated data actually stored and a first preset value; When the number of bits in the third result indicating that the second result is flipped compared to the specified data is greater than the first preset value, the first result is in a failure state; When the number of bits in the third result indicating that the second result is flipped compared to the specified data is less than or equal to the first preset value, the first result is in a pass state.

6. The memory device according to claim 5, wherein: The peripheral circuit is configured as: When the initial target read voltage is adjusted multiple times, a first adjustment is performed each time on the read voltage adjusted last time; the step length of the first adjustment is a fixed value.

7. The memory device according to claim 6, wherein: The peripheral circuit is configured as: When the initial target read voltage is adjusted multiple times, the read voltage is stopped from being adjusted when multiple first results corresponding to the target read voltage after the multiple adjustments reflect a change from a fail state to at least one pass state and then to a fail state.

8. The memory device according to claim 7, wherein: The peripheral circuit is configured as: When the multiple first results corresponding to the adjusted read voltage are in the middle of the failure state at both ends When the passing state includes one time, the adjusted read voltage corresponding to the passing state once is used as the valley bottom voltage; When the plurality of first results corresponding to the adjusted read voltages reflect multiple pass states between the fail states at both ends, the adjusted read voltage corresponding to a pass state at an intermediate position among the multiple pass states is used as the valley voltage.

9. The memory device according to claim 7, wherein: The peripheral circuit is configured as: After the first pass state after the failure state appears in the multiple first results corresponding to the target read voltage after multiple adjustments, a second adjustment is performed on the read voltage after the previous adjustment; the step size of the second adjustment is smaller than the step size of the first adjustment.

10. The memory device according to claim 6, wherein: The peripheral circuit is configured as: After a first pass state after a failure state appears in a plurality of first results corresponding to the target read voltage after multiple adjustments, a third adjustment is performed on the read voltage after the previous adjustment according to a statistical number of third results corresponding to the first pass state; The step size of the third adjustment is based on a change in the number of bits in the third result that represent the flipping of the second result compared to the designated data.

11. The memory device according to claim 3, wherein: The first result includes a number of bits representing that a read result at the designated position under the target read voltage is flipped compared to designated data actually stored; The peripheral circuit is configured as: When a first result corresponding to the initial target read voltage is less than or equal to the first preset value, performing a first adjustment on the initial target read voltage according to the first result to obtain a target adjusted read voltage; A first result corresponding to the designated position under the target adjusted read voltage is obtained.

12. The memory device according to claim 11, wherein: The peripheral circuit is configured as: When the first result corresponding to the designated position under the target adjusted read voltage is less than the first preset value and greater than the second preset value, the first adjustment is continued on the target adjusted read voltage, and the first result corresponding to the designated position under the adjusted read voltage is obtained, until the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value; the first adjustment step The length changes according to the value of the first result.

13. The memory device according to claim 12, wherein: The peripheral circuit is configured as: When the first result corresponding to the finally adjusted read voltage is less than or equal to the second preset value, the read voltage corresponding to the smallest first result among the plurality of first results is used as the valley voltage.

14. The memory device according to claim 6 or 12, wherein: The peripheral circuit is configured as: When a plurality of first results corresponding to the target read voltage after multiple adjustments are all in a failed state or a plurality of first results are all greater than the first preset value, increasing a step size corresponding to the first adjustment; When the increased step size of the first adjustment exceeds a third preset value, the amount of reading of the designated data stored at the designated position is reduced.

15. The memory device according to claim 3, wherein: The peripheral circuit is configured as: The first preset value is obtained; the first preset value is obtained according to historical data; the first preset value is less than or equal to an upper limit of a failure bit count supported by the memory device.

16. The memory device of claim 1, wherein: The peripheral circuit is configured as: Before obtaining the first result corresponding to the specified position under the initial target read voltage, the read mode of the memory device is set to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in the storage cell through a first-level read voltage.

17. The memory device of claim 16, wherein: The memory cell array includes M bits of memory cells, the memory device includes M pages, and the M-bit memory cells read their M-bit storage data through N-level read voltages; M and N are both integers greater than 1, and N=2 M -1; The peripheral circuit is configured as: For each level of read voltage among the multiple levels of read voltage corresponding to each type of page, a valley voltage of each level is determined according to the multiple first results corresponding to the multiple read voltages of each level.

18. A memory system comprising: One or more memory devices as claimed in any one of claims 1 to 17; as well as A memory controller is coupled to the memory device and controls the memory device.

19. The memory system of claim 18, wherein: The memory controller is configured to: before performing a read operation on data stored in the memory device, send a first instruction, wherein the first instruction instructs obtaining a valley voltage; The memory device is configured to: receive the first instruction, obtain a valley voltage, and send the obtained valley voltage to the memory controller; The memory controller is further configured to: perform a read operation on data stored in the memory device according to the valley voltage; An error correction code decoding operation is performed on a read result of the read operation.

20. A memory system comprising: at least one memory device; a memory controller coupled to the at least one memory device and configured to: Obtaining a first result corresponding to an initial target read voltage at a designated position in a memory cell array of the memory device; the first result includes a number of bits representing a flip of a read result at the designated position at the target read voltage compared to designated data actually stored, wherein the designated position stores the designated data; Adjusting the initial target read voltage multiple times, and respectively obtaining first results corresponding to the target read voltage after each adjustment at the designated position; A valley voltage is determined according to the obtained plurality of first results; the valley voltage is used as a read voltage when a read operation is performed on the memory cell array.

21. The memory system of claim 20, wherein: The memory controller is configured to: Before performing a read operation on data stored in the memory device, sending a second instruction, wherein the second instruction instructs obtaining a first result of the designated location under a plurality of different target read voltages; The memory device is configured to: receive the second instruction, obtain a plurality of first results at the designated location under a plurality of different target read voltages, and send the obtained first results to the memory controller; The memory controller is further configured to: determine a valley voltage according to a plurality of first results corresponding to a plurality of different read voltages; and perform read operations on the data stored in the memory device according to the valley voltage. Read operation.

22. The memory system of claim 21, wherein: The memory device is configured to: read the designated data stored at the designated location under the initial target read voltage to obtain a second result; Performing a logical operation on the stored designated data and the second result to obtain a third result; When the first result includes the number of bits representing that the read result at the designated position at the target read voltage is flipped compared to the designated data actually stored, counting the number of bits representing that the second result is flipped compared to the designated data in the third result and using the counted result as the first result; When the first result includes the relationship between the number of bits that are flipped in the read result at the specified position under the target read voltage compared to the actually stored specified data and a first preset value, the number of bits that are flipped in the second result compared to the specified data in the third result is compared with the first preset value, and the result of the comparison is used as the first result.

23. The memory system of claim 20, wherein: The data volume of the first result is less than a preset data volume threshold.

24. A method for operating a memory device, comprising: Acquire a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device; The first result includes a number of bits representing the number of bits flipped in the read result at the specified position under the target read voltage compared with the actually stored specified data, and the specified data is stored at the specified position; Adjusting the initial target read voltage multiple times, and respectively obtaining first results corresponding to the target read voltage after each adjustment at the designated position; A valley voltage is determined according to the obtained plurality of first results; the valley voltage is used as a read voltage when a read operation is performed on the memory cell array.

25. The operating method according to claim 24, wherein: The memory cell array includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory rows, and each of the memory rows includes a plurality of memory cells; A preset number of storage units form a codeword; The method further comprises: In the process of performing a write operation on the memory cell array, writing the specified data at a specified position in the memory cell array; The designated location includes at least one of each of the storage blocks, each of the storage rows, and each of the codewords.

26. The operating method according to claim 24, wherein: The method further comprises: storing the specified data; The obtaining of a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device comprises: reading the designated data stored at the designated location at the target voltage to obtain a second result; Performing a logical operation on the stored designated data and the second result to obtain a third result; When the first result includes the number of bits representing that the read result at the designated position at the target read voltage is flipped compared to the designated data actually stored, counting the number of bits representing that the second result is flipped compared to the designated data in the third result and using the counted result as the first result; When the first result includes the relationship between the number of bits that are flipped in the read result at the specified position under the target read voltage compared to the actually stored specified data and a first preset value, the number of bits that are flipped in the second result compared to the specified data in the third result is compared with the first preset value, and the result of the comparison is used as the first result.

27. The operating method according to claim 26, wherein: The method further comprises: storing the specified data in a first latch of the memory device, storing the second result in a second latch of the memory device; The third result is stored in a third latch of the memory device.

28. The operating method according to claim 26, wherein: The first result includes a relationship between the number of bits of the read result at the designated position under the target read voltage that are flipped compared to the designated data actually stored and a first preset value; The using the comparison result as the first result includes: The number of bits in the third result indicating that the second result is flipped compared to the specified data is greater than the When the first preset value is reached, the first result is a failure state; When the number of bits in the third result indicating that the second result is flipped compared to the first result is less than or equal to the first preset value, the first result is in a pass state.

29. The operating method according to claim 28, wherein: The method further comprises: When the initial target read voltage is adjusted multiple times, a first adjustment is performed each time on the read voltage adjusted last time; the step length of the first adjustment is a fixed value.

30. The operating method according to claim 29, wherein: The method further comprises: When the initial target read voltage is adjusted multiple times, the read voltage is stopped from being adjusted when multiple first results corresponding to the target read voltage after the multiple adjustments reflect a change from a fail state to at least one pass state and then to a fail state.

31. The operating method according to claim 30, wherein: The determining the valley voltage according to the obtained plurality of first results comprises: When the plurality of first results corresponding to the adjusted read voltages reflect a pass state between the fail states at both ends including one, the adjusted read voltage corresponding to the pass state is used as the valley voltage; When the plurality of first results corresponding to the adjusted read voltages reflect multiple pass states between the fail states at both ends, the adjusted read voltage corresponding to a pass state at an intermediate position among the multiple pass states is used as the valley voltage.

32. The operating method according to claim 30, wherein: The method further comprises: After the first pass state after the failure state appears in the multiple first results corresponding to the target read voltage after multiple adjustments, a second adjustment is performed on the read voltage after the previous adjustment; the step size of the second adjustment is smaller than the step size of the first adjustment.

33. The operating method according to claim 29, wherein: The method further comprises: After the first pass state after a failure state appears in multiple first results corresponding to the target read voltage after multiple adjustments, a third adjustment is made to the read voltage after the previous adjustment according to the statistical number of third results corresponding to the first pass state; the step size of the third adjustment is based on the change in the number of bits in the third result that characterize the flipping of the second result compared to the specified data.

34. The operating method according to claim 26, wherein: The first result includes a number of bits representing that a read result at the designated position under the target read voltage is flipped compared to designated data actually stored; The method further comprises: When a first result corresponding to the initial target read voltage is less than or equal to the first preset value, performing a first adjustment on the initial target read voltage according to the first result to obtain a target adjusted read voltage; A first result corresponding to the designated position under the target adjusted read voltage is obtained.

35. The operating method according to claim 34, wherein: The method further comprises: When the first result corresponding to the designated position under the target adjustment read voltage is less than the first preset value and greater than the second preset value, continue to perform the first adjustment on the target adjustment read voltage, and obtain the first result corresponding to the designated position under the adjusted read voltage, until the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value; the step size of the first adjustment changes according to the value of the first result.

36. The operating method according to claim 35, wherein: The determining the valley voltage according to the obtained plurality of first results comprises: When the first result corresponding to the finally adjusted read voltage is less than or equal to the second preset value, the read voltage corresponding to the smallest first result among the plurality of first results is used as the valley voltage.

37. The operating method according to claim 29 or 35, wherein: The method further comprises: When a plurality of first results corresponding to the target read voltage after multiple adjustments are all in a failed state or a plurality of first results are all greater than the first preset value, increasing a step size corresponding to the first adjustment; When the increased step size of the first adjustment exceeds a third preset value, the amount of reading of the designated data stored at the designated position is reduced.

38. The operating method according to claim 26, wherein: The method further comprises: The first preset value is obtained; the first preset value is obtained according to historical data; the first preset value is less than or equal to an upper limit of a failure bit count supported by the memory device.

39. The operating method according to claim 24, wherein: The method further comprises: Before obtaining the first result corresponding to the specified position under the initial target read voltage, the read mode of the memory device is set to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in the storage cell through a first-level read voltage.

40. The operating method according to claim 39, wherein: The memory cell array includes M bits of memory cells, the memory device includes M pages, and the M-bit memory cells read their M-bit storage data through N-level read voltages; M and N are both integers greater than 1, and N=2 M -1; The method further includes: for each level of read voltage among the multiple levels of read voltage corresponding to each type of page, determining a valley voltage of each level according to the multiple read voltages of each level corresponding to multiple first results.

41. A method for operating a memory system, comprising: Before performing a read operation on data stored in a memory device of the memory system, sending a first instruction, wherein the first instruction instructs obtaining a valley voltage; The valley voltage is obtained by the operating method according to any one of claims 24 to 40; performing a read operation on data stored in a memory device according to the valley voltage; An error correction code decoding operation is performed on a read result of the read operation.

42. A method for operating a memory system, comprising: Acquire a first result corresponding to an initial target read voltage at a specified position in a memory cell array of the memory device; The first result includes a number of bits representing the number of bits flipped in the read result at the specified position under the target read voltage compared with the actually stored specified data, and the specified data is stored at the specified position; Adjusting the initial target read voltage multiple times, and respectively obtaining first results corresponding to the target read voltage after each adjustment at the designated position; A valley voltage is determined according to the obtained plurality of first results; the valley voltage is used as a read voltage when a read operation is performed on the memory cell array.

43. The operating method according to claim 42, wherein: The method further comprises: Before performing a read operation on data stored in the memory device, sending a second instruction, wherein the second instruction instructs obtaining a plurality of first results at the designated location under a plurality of different target read voltages; A valley voltage is determined according to a plurality of the first results respectively corresponding to a plurality of different read voltages; and a read operation is performed on the data stored in the memory device according to the valley voltage.

44. The operating method according to claim 43, wherein: The method further comprises: reading the designated data stored at the designated location at the initial target read voltage to obtain a second result; Performing a logical operation on the stored designated data and the second result to obtain a third result; When the first result includes the number of bits representing that the read result at the designated position at the target read voltage is flipped compared to the designated data actually stored, counting the number of bits representing that the second result is flipped compared to the designated data in the third result and using the counted result as the first result; When the first result includes the relationship between the number of bits that are flipped in the read result at the specified position under the target read voltage compared to the actually stored specified data and a first preset value, the number of bits that are flipped in the second result compared to the specified data in the third result is compared with the first preset value, and the result of the comparison is used as the first result.

45. A memory device comprising: A memory cell array, comprising a plurality of memory cells; A peripheral circuit coupled to the memory cell array, including a control logic and a page buffer; The control logic is configured to: storing specified data in a first latch of the page buffer; Reading the designated data stored in the first latch at a target read voltage to obtain a second result, and storing the second result in a second latch of the page buffer; Performing a logic operation on the stored designated data and the second result to obtain a third result, and storing the third result in a third latch of the page buffer; When the first result includes the number of bits representing that the read result at the specified position under the target read voltage is flipped compared to the actually stored specified data, counting the number of bits in the third result representing that the second result is flipped compared to the specified data and using the counted result as the first result; When the first result includes a relationship between the number of bits representing the flipping of the reading result at the specified position under the target reading voltage compared with the actually stored specified data and the first preset value, the The number of bits in the third result indicating that the second result is flipped compared to the specified data is compared with the first preset value, and the result of the comparison is used as the first result.

46. ​​A method for operating a memory device, the memory device comprising a memory cell array and a page buffer; the method comprising: storing specified data in a first latch of the page buffer; Reading the designated data stored at a designated location at a target read voltage to obtain a second result, and storing the second result in a second latch of the page buffer; Performing a logic operation on the stored designated data and the second result to obtain a third result, and storing the third result in a third latch of the page buffer; When the first result includes the number of bits representing that the read result at the designated position at the target read voltage is flipped compared to the designated data actually stored, counting the number of bits in the third result representing that the second result is flipped compared to the designated data and using the counted result as the first result; When the first result includes the relationship between the number of bits that are flipped in the read result at the specified position under the target read voltage compared to the actually stored specified data and a first preset value, the number of bits that are flipped in the second result compared to the specified data in the third result is compared with the first preset value, and the result of the comparison is used as the first result.

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