Semiconductor memory device and transistor device

Abstract

A semiconductor memory device having good manufacturability while having a small size is provided. The semiconductor memory device includes: a semiconductor substrate including a thin film transistor; a first wiring and a second wiring stacked on the semiconductor substrate; a contact portion including a first conductive pillar electrically connecting the thin film transistor and the first wiring; and a capacitor portion including a second conductive pillar electrically connecting the thin film transistor and the second wiring. A height position of an upper end of the first conductive pillar on the opposite side of the semiconductor substrate and a height position of an upper end of the second conductive filler on the opposite side of the semiconductor substrate substantially coincide with each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device and a transistor device. Background Art

[0002] A CMOS (complementary MOS) circuit (each including an n-type field effect transistor (nMOSFET) and a p-type field effect transistor (pMOSFET) provided on the same substrate) is known as a circuit that consumes little power and can operate at high speed. In addition, miniaturization and high integration of the circuit are easy.

[0003] Therefore, CMOS circuits are used in a large number of LSI (large scale integration) devices. It should be noted that these LSI devices have been commercialized in recent years as SoCs (System on a Chip) that integrate analog circuits, memories, logic circuits, etc. into one chip.

[0004] For example, a memory such as a static RAM (static random access memory: SRAM) is used for mounting on an LSI device. In recent years, it has been considered to use a dynamic RAM (DRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), etc. instead of SRAM to further reduce costs and power consumption of LSI devices. Here, FeRAM is a semiconductor memory device that stores information by using the direction of the remanent polarization of a ferroelectric. A semiconductor memory device used as such a FeRAM using a ferroelectric capacitor has been proposed (for example, PTL 1).

[0005] Citation List

[0006] Patent Document

[0007] PTL 1: Japanese Unexamined Patent Application Publication No. 2019-160841 Summary of the Invention

[0008] Incidentally, in the field of electronic devices such as semiconductor memory devices, miniaturization of size is desired.

[0009] Therefore, it is desired to provide a semiconductor memory device that is small in size and excellent in manufacturability.

[0010] A semiconductor memory device according to an embodiment of the present disclosure includes: a semiconductor substrate including thin film transistors; a first wiring and a second wiring each stacked on the semiconductor substrate; a contact portion including a first conductive pillar that extends in a stacking direction in which the first wiring and the second wiring are stacked on the semiconductor substrate and electrically couples the thin film transistors and the first wiring to each other; and a capacitor portion including a second conductive pillar that extends in the stacking direction and electrically couples the thin film transistors and the second wiring to each other. Here, a height position of an upper end of the first conductive pillar on a relative side of the semiconductor substrate is substantially the same as a height position of an upper end of the second conductive pillar on the relative side of the semiconductor substrate.

[0011] The semiconductor memory device according to an embodiment of the present disclosure is suitable for miniaturization and can be easily manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a circuit diagram showing an example of an equivalent circuit of a semiconductor memory device according to a first embodiment of the present disclosure.

[0013] Figure 2 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of the semiconductor memory device shown in Figure 1

[0014] Figure 3 is a schematic diagram showing an example of a planar configuration of the semiconductor memory device shown in Figure 1

[0015] Figure 4 is a schematic diagram showing an example of a cross-sectional configuration along an in-plane direction of the semiconductor memory device shown in Figure 1

[0016] Figure 5A is a schematic diagram describing steps of a method of manufacturing the semiconductor memory device shown in Figure 1

[0017] Figure 5B is a schematic diagram showing a step after the step in Figure 5A

[0018] Figure 5C is a schematic diagram showing a step after the step in Figure 5B

[0019] Figure 5D is a schematic diagram showing a step after the step in Figure 5C

[0020] Figure 5E is a schematic diagram showing a step after the step in Figure 5D ​​​​​​​​

[0021] Figure 5F is a schematic diagram showing a step after the step in Figure 5E .

[0022] Figure 5G is a schematic diagram showing a step after the step in Figure 5F .

[0023] Figure 5H is a schematic diagram showing a step after the step in Figure 5G .

[0024] Figure 6 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a first modification of a first embodiment of the present disclosure.

[0025] Figure 7 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a second modification of a first embodiment of the present disclosure.

[0026] Figure 8 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a third modification of a first embodiment of the present disclosure.

[0027] Figure 9 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a fourth modification of a first embodiment of the present disclosure.

[0028] Figure 10 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a fifth modification of a first embodiment of the present disclosure.

[0029] Figure 11 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a sixth modification of a first embodiment of the present disclosure.

[0030] Figure 12A is a schematic diagram showing an example of a cross-sectional configuration of a transistor device according to a second embodiment of the present disclosure.

[0031] Figure 12B is another schematic diagram showing an example of a cross-sectional configuration of a transistor device according to a second embodiment of the present disclosure.

[0032] Figure 13 is a schematic diagram showing an example of a cross-sectional configuration of a transistor device according to a reference example.

[0033] Figure 14It is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to another first modification of the present disclosure.

[0034] Figure 15 It is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to another second modification of the present disclosure. Detailed Description of the Embodiments

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are specific examples of the present disclosure. The technology according to the present disclosure should not be limited to the following modes. In addition, the arrangement, dimensions, dimensional ratios, etc. of the respective components according to the present disclosure are not limited to the modes shown in the drawings.

[0036] It should be noted that the description will be made in the following order.

[0037] 1. First Embodiment

[0038] 1.1. Overview

[0039] 1.2. Configuration Example

[0040] 1.3. Manufacturing Method

[0041] 1.4. Operation and Effects

[0042] 1.5. Modifications

[0043] 2. Second Embodiment

[0044] 2.1. Configuration Example

[0045] 2.2. Operation and Effects

[0046] 3. Other Modifications

[0047] [1. First Embodiment]

[0048] [1.1. Overview]

[0049] First, Figure 1 the overview of the semiconductor memory device 100 according to the first embodiment of the present disclosure will be described with reference to Figure 1 It is a circuit diagram showing an example of an equivalent circuit of the semiconductor memory device 100 according to the present embodiment.

[0050] As Figure 1 shown, the semiconductor memory device 100 according to the present embodiment includes a capacitor C that stores information and a transistor T that controls the selection and non-selection of the capacitor C.

[0051] The capacitor C is a ferroelectric capacitor including a first electrode, a second electrode, and a ferroelectric film sandwiched between the first electrode and the second electrode. The capacitor C can store 1-bit information by using the direction of the remanent polarization of the ferroelectric film. The capacitor C is electrically coupled to the source line SL at the first electrode and to the source of the transistor T at the second electrode.

[0052] The transistor T is a field-effect transistor that controls the voltage application to the capacitor C. The transistor T is electrically coupled to the second electrode of the capacitor C at the source and to the bit line BL at the drain. Further, the transistor 21 is electrically coupled to the word line WL at the gate. Applying a voltage from the word line WL enables control of the state of the channel.

[0053] In the case of writing information into the capacitor C, first a voltage is applied to the word line WL in the semiconductor memory device 100. This causes the channel of the transistor T to turn into an on state. Then, potentials are applied to the source line SL and the bit line BL, respectively. This applies an electric field corresponding to the information to be written into the ferroelectric film of the capacitor C. This allows the semiconductor memory device 100 to write information into the capacitor C by controlling the direction of the remanent polarization of the ferroelectric film of the capacitor C using an external electric field.

[0054] Conversely, in the case of reading information from the capacitor C, a voltage is first applied to the word line WL in the semiconductor memory device 100. This causes the channel of the transistor T to turn into an on state. After that, a predetermined potential is applied to both the source line SL and the bit line BL. This causes the polarization direction of the ferroelectric film of the capacitor C to turn to a predetermined direction. In this case, the magnitude of the current flowing into the capacitor C during the turning changes according to the polarization direction of the ferroelectric film before the turning. Therefore, the semiconductor memory device 100 can read the information stored in the capacitor C by measuring the magnitude of the current flowing into the capacitor C.

[0055] This allows the semiconductor memory device 100 to operate as a FeRAM (ferroelectric random access memory) that stores information in the capacitor C including a ferroelectric film.

[0056] [1.2. Configuration example]

[0057] Subsequently, refer to Figures 2 to 4 to describe a specific configuration example of the semiconductor memory device 100 according to the present embodiment. Figure 2 An example of a cross-sectional configuration along the stacking direction of the semiconductor memory device 100 is shown. Figure 3 An example of a planar configuration of the semiconductor memory device 100 is shown. Figure 4 is a cross-sectional view showing a part of the semiconductor memory device 100 in the in-plane direction in an enlarged manner. It should be noted that Figure 3The insulating films Z1 to Z4 are omitted to clarify the arrangement of components. The insulating films Z1 to Z4 are formed to extend over the entire surface of the semiconductor substrate 2. Additionally, Figure 2 The cross-sectional view shows a cross-section taken along the line II-II shown in Figure 3 In addition, in this specification, the direction along the plane in which the semiconductor substrate 2 extends is referred to as the in-plane direction, and the direction orthogonal to the in-plane direction is referred to as the height direction or the stacking direction. Furthermore, Figure 4 shows one capacitor section 25 (to be described later) included in the semiconductor memory device 100 and a part of the second wiring 5 (to be described later), and other components are omitted. In Figures 2 to 4 the in-plane direction is represented by the XY plane, and the height direction (stacking direction) is represented by the Z-axis direction.

[0058] As shown in Figure 2 the semiconductor memory device 100 includes a semiconductor substrate 2, a first wiring 4, a second wiring 5, a contact portion 15, and a capacitor section 25 as a capacitor C.

[0059] The semiconductor substrate 2 includes a semiconductor material. The semiconductor substrate 2 may be a silicon substrate. Alternatively, the semiconductor substrate 2 may be an SOI (Silicon On Insulator) substrate in which an insulating film such as SiO2 is inserted into a silicon substrate. In addition, the semiconductor substrate 2 may be a substrate containing other elemental semiconductors such as germanium. Alternatively, the semiconductor substrate 2 may be a substrate containing compound semiconductors such as GaAs (gallium arsenide), GaN (gallium nitride), and SiC (silicon carbide).

[0060] For example, the semiconductor substrate 2 is provided with a plurality of thin film transistors 1 and an element isolation layer 3. The element isolation layer 3 includes an insulating material and electrically isolates the plurality of thin film transistors 1 provided in the active regions of the semiconductor substrate 2 from each other. The element isolation layer 3 may include an insulating material such as SiO x (silicon oxide), SiN x (silicon nitride), or SiON (silicon oxynitride).

[0061] For example, by etching using the STI (Shallow Trench Isolation) method or the like to remove a part of a predetermined region of the semiconductor substrate 2 and then filling the opening formed by etching or the like with SiO x (silicon oxide), the element isolation layer 3 can be formed. Alternatively, the element isolation layer 3 can be formed by thermally oxidizing the semiconductor substrate 2 in a predetermined region using the LOCOS (LOCal Oxidation of Silicon) method.

[0062] The region isolated from the periphery by the element isolation layer 3 serves as an active region AA (refer to Figure 3 ), in which a thin film transistor 1 is provided. For example, impurities of a first conductivity type (e.g., p-type impurities such as boron (B) or aluminum (Al)) are introduced into the active region AA.

[0063] A plurality of thin film transistors 1 are provided near the surface of the semiconductor substrate 2. As Figure 2 shown, the thin film transistor 1 is, for example, a MOS (metal oxide semiconductor)-FET (field effect transistor), which includes a gate electrode 1G, sidewall insulating films 1W, a gate insulating film 1Z, a drain region 1D, and a source region 1S.

[0064] The gate insulating film 1Z includes an insulating material and is provided on the active region AA of the semiconductor substrate 2. The gate insulating film 1Z may include an insulating material known as the gate insulating film of a field effect transistor. For example, the gate insulating film 1Z can be formed by using an oxide such as silicon oxide (SiO x ).

[0065] The gate electrode 1G includes a conductive material and is provided on the gate insulating film 1Z. Specifically, the gate electrode 1G extends, for example, in Figure 3 the vertical direction (hereinafter referred to as the first direction) of the paper surface of

[0066] . Note that the gate electrode 1G is provided to extend beyond the element isolation layer 3 and over a plurality of active regions AA. This makes the gate electrode 1G serve as a word line WL that electrically couples the gates of the plurality of thin film transistors 1.

[0067] The drain region 1D and the source region 1S are each a region of a second conductivity type formed in the semiconductor substrate 2. Specifically, the drain region 1D and the source region 1S are provided to face each other across the gate electrode 1G. The drain region 1D and the source region 1S are each a region in the semiconductor substrate 2 where impurities of a second conductivity type (e.g., n-type impurities such as phosphorus (P) or arsenic (As)) are introduced into the active region AA. In addition, a silicide layer 6 is formed in a part of the surface 2FS of the semiconductor substrate 2 in each of the drain region 1D and the source region 1S.

[0068] The drain region 1D is electrically coupled to a first wiring 4 such as a bit line BL ( Figure 1 ) via a contact portion 15. The source region 1S is electrically coupled to a second wiring 5 such as a source line SL ( Figure 1 ) via a capacitor portion 25 of a capacitor C.

[0069] The sidewall insulating film 1W includes an insulating material and is provided on the side surface of the gate electrode 1G as a sidewall. The sidewall insulating film 1W can be formed by uniformly disposing an insulating film in a region including the gate electrode 1G and then performing a vertical anisotropic etching on the insulating film. For example, the sidewall insulating film 1W can be formed as a single layer or multiple layers using an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).

[0070] As Figure 2 shown, insulating films Z1 to Z4 are sequentially stacked on the thin film transistor 1. Each of the insulating films Z1, Z3, and Z4 is, for example, a silicon oxide film, and the insulating film Z2 is, for example, a silicon nitride film.

[0071] As Figure 2 shown, the contact portion 15 includes a first conductive column 10, a ferroelectric layer 13, and an electrode layer 14. The first conductive column 10 is a columnar member having a height H10. The first conductive column 10 extends in the Z-axis direction through the insulating films Z1 to Z3, for example, from a height position P0 on the surface 2FS of the semiconductor substrate 2 to a height position P10 on the upper surface of the insulating film Z3. The first conductive column 10 is located between the semiconductor substrate 2 and the first wiring 4 in the Z-axis direction and electrically couples the thin film transistor 1 and the first wiring 4 to each other. As Figures 2 to 4 shown, the first conductive column 10 includes, for example, a conductor layer 11 having a substantially cylindrical shape and a barrier metal layer 12 having a substantially cylindrical shape surrounding the periphery of the conductor layer 11. For example, the conductor layer 11 can contain a conductor material such as W (tungsten) or polysilicon. For example, the barrier metal layer 12 can include a metal material such as Ti (titanium), TiN (titanium nitride), or Ru (ruthenium). For example, the ferroelectric layer 13 and the electrode layer 14 are provided in the same layer as the insulating film Z3. The ferroelectric layer 13 is provided to cover the periphery of the barrier metal layer 12. The electrode layer 14 is provided to cover the periphery of the ferroelectric layer 13. The material contained in the ferroelectric layer 13 is, for example, the same as the material contained in the ferroelectric layer 23 described later. The material contained in the electrode layer 14 is, for example, the same as the material contained in the electrode layer 24 described later. It should be noted that the ferroelectric layer 13 and the electrode layer 14 are not necessarily required to exist.

[0072] As Figure 2As shown, the lower end of the first conductive pillar 10 is in contact with the silicide layer 6 provided in the drain region 10D. The upper end 10UT of the first conductive pillar 10 (i.e., on the opposite side of the semiconductor substrate 2) is connected to the lower surface of, for example, the first wiring 4. The first wiring 4 is provided in the same layer as the insulating film Z4. The first wiring 4 includes, for example, a barrier layer 4A and an embedded layer 4B. The barrier layer 4A may include, for example, each of the elemental substances of Co (cobalt), W (tungsten), Mo (molybdenum), Ru (ruthenium), Ta (tantalum), and Cu (copper), or a compound containing at least one of these elements. The embedded layer 4B may include a conductive material containing Cu (copper) and Ru (ruthenium).

[0073] As Figure 2 and Figure 4 shown in, the capacitor unit 25 includes a second conductive pillar 20, a ferroelectric layer 23, and an electrode layer 24. The ferroelectric layer 23 is interposed between the second conductive pillar 20 and the electrode layer 24. The second conductive pillar 20 is a columnar member having a height H20. The second conductive pillar 20 extends, for example, in the Z-axis direction through the insulating films Z1 to Z3, from the height position P0 of the surface 2FS of the semiconductor substrate 2 to the height position P20 of the upper end 20UT. Here, the height position P20 coincides with the height position of the upper surface of the insulating film Z3. In other words, the height position P10 of the upper end 10UT of the first conductive pillar 10 and the height position P20 of the upper end 20UT of the second conductive pillar 20 are substantially the same as each other. The second conductive pillar 20 electrically couples the thin film transistor 1 and the second wiring 5 to each other. As Figures 2 to 4 shown in, the second conductive pillar 20 includes, for example, a conductor layer 21 having a substantially cylindrical shape and a barrier metal layer 22 having a substantially cylindrical shape surrounding the periphery of the conductor layer 21. For example, the conductor layer 21 may include a conductor material such as W (tungsten) or polysilicon. For example, the barrier metal layer 22 may include a metal material such as Ti (titanium), TiN (titanium nitride), or Ru (ruthenium). The material contained in the conductor layer 21 is, for example, the same as the material contained in the conductor layer 11. The material contained in the barrier metal layer 22 is, for example, the same as the material contained in the barrier metal layer 12. For example, the ferroelectric layer 23 and the electrode layer 24 are provided in the same layer as the insulating film Z3. The ferroelectric layer 23 is provided to cover the periphery of the barrier metal layer 22. The electrode layer 24 is provided to cover the periphery of the ferroelectric layer 23. The ferroelectric layer 23 may include, for example, a ferroelectric material containing at least one of HfO2 (hafnium oxide), Si (silicon), Zr (zirconium), La (lanthanum), Nb (niobium), Y (yttrium), Ge (germanium), or Sc (scandium). The ferroelectric layer 23 may further include PZT (lead zirconate titanate), SBT (strontium bismuth tantalate), or BLT. The electrode layer 24 may include, for example, a metal material such as Ti (titanium), TiN (titanium nitride), or Ru (ruthenium).

[0074] The lower end of the second conductive pillar 20 is in contact with the silicide layer 6 provided in the source region 1S. The side surface 24S of the electrode layer 24 surrounding the second conductive pillar 20 (i.e., on the opposite side of the second conductive pillar 20) abuts against, for example, the side surface 5S of the second wiring 5. The second wiring 5 is provided in the same level as a part of the insulating film Z3 and a part of the insulating film Z4. The second wiring 5 includes, for example, a barrier layer 5A and an embedded layer 5B. The barrier layer 5A may contain, for example, each of Co (cobalt), W (tungsten), Mo (molybdenum), Ru (ruthenium), Ta (tantalum), and Cu (copper) in elemental form, or a compound containing at least one of these elements. The embedded layer 5B may include a conductive material containing Cu (copper) and Ru (ruthenium). The material contained in the barrier layer 5A is, for example, the same as the material contained in the barrier layer 4A. The material contained in the embedded layer 5B is, for example, the same as the material contained in the embedded layer 4B.

[0075] It should be noted that, as Figure 3 shown, the second wiring 5 may be shared by the adjacent capacitor portions 25.

[0076] [1.3. Manufacturing method]

[0077] Next, with reference to Figures 5A to 5H the manufacturing method of the semiconductor memory device 100 according to the present embodiment will be described. Figures 5A to 5H are schematic views each depicting the steps of the manufacturing method of the semiconductor memory device 100.

[0078] First, as Figure 5A shown, an element isolation layer 3 is formed in the semiconductor substrate 2.

[0079] Specifically, a semiconductor substrate 2 containing Si is prepared, and then a SiO2 film is formed on the semiconductor substrate 2 by dry oxidation or the like. In addition, a Si3N4 film is formed by low-pressure CVD or the like. Subsequently, a resist layer is formed on the Si3N4 film, and the resist layer is patterned to protect the region where the active region AA is to be provided. After that, the SiO2 film, the Si3N4 film, and the semiconductor substrate 2 are etched to a depth of 350 nm to 400 nm. Then, SiO2 is deposited to have a film thickness of 650 nm to 700 nm and fill the opening formed by etching. This enables the formation of the element isolation layer 3. For example, high-density plasma CVD can be used to deposit SiO2. High-density plasma CVD exhibits good step coverage and can form a dense SiO2 film.

[0080] Subsequently, the over-deposited SiO2 film is removed by using CMP (chemical mechanical polishing) or the like, thereby planarizing the surface of the semiconductor substrate 2. The SiO2 film is removed by CMP, for example, until the Si3N4 film is exposed.

[0081] In addition, hot phosphoric acid or the like is used to remove the Si3N4 film. Subsequently, the surface of the region of the semiconductor substrate 2 corresponding to the active region AA is oxidized to a thickness of about 10 nm to form an oxide film. Thereafter, by ion-implanting impurities of the first conductivity type (e.g., boron (B), etc.), the semiconductor substrate 2 of the active region AA is converted into a well of the first conductivity type.

[0082] Subsequently, a gate insulating film 1Z is deposited. Thereafter, a gate electrode 1G is formed on the gate insulating film 1Z.

[0083] Specifically, first, an oxide film covering the surface of the semiconductor substrate 2 is removed using a hydrofluoric acid solution or the like. Thereafter, a gate insulating film 1Z containing SiO2 is formed on the semiconductor substrate 2 to have a film thickness of 1.5 nm to 10 nm by, for example, dry oxidation using O2 or RTA (rapid thermal annealing) treatment. It should be noted that, in addition to O2, a mixed gas of H2 / O2, N2O, or NO can also be used as the gas for dry oxidation. In addition, forming the gate insulating film 1Z using plasma nitridation can also dope nitrogen in the SiO2 film.

[0084] Subsequently, polysilicon having a film thickness of 50 nm to 150 nm is deposited by using low-pressure CVD, wherein SiH4 gas is used as a source gas and the deposition temperature is set at 580 °C to 620 °C. Thereafter, anisotropic etching is performed on the deposited polysilicon using a patterned resist as a mask, thereby forming the gate electrode 1G. For anisotropic etching, for example, an HBr-based gas or a Cl-based gas can be used.

[0085] It should be noted that the gate electrodes 11G and 21G can be formed simultaneously and can be formed to be shared with the gate electrode of another transistor provided in a logic region or the like of the circuit portion.

[0086] Subsequently, a drain region 1D and a source region 1S are formed in the active region AA of the semiconductor substrate 2. At this time, sidewall insulating films 1W are formed on each of the two side surfaces of the gate electrode 1G.

[0087] Specifically, SiO2 is deposited by plasma CVD to have a film thickness of 10 nm to 30 nm. Thereafter, Si3N4 is deposited by plasma CVD to have a film thickness of 30 nm to 50 nm to form an insulating film for the sidewall. Thereafter, anisotropic etching is performed on the insulating film for the sidewall to form sidewall insulating films 1W on each of the two side surfaces of the gate electrode 1G.

[0088] Thereafter, arsenic (As) as an impurity of the second conductivity type is implanted at 20 keV to 50 keV at 1×10 15 ions / cm 2 to 2×10 15ions / cm 2 The concentration of 2 is subjected to ion implantation, and impurities of the second conductivity type are introduced to both sides of the gate electrode 1G. This forms a drain region 1D and a source region 1S in the active regions AA on both sides of the gate electrode 1G. In addition, RTA (Rapid Thermal Annealing) is performed at 1000 °C for 5 seconds to activate the ion-implanted impurities. Thus, the thin film transistor 1 is formed. It should be noted that the impurities can also be activated by spike RTA to accelerate the activation of the introduced impurities and suppress the diffusion of the impurities.

[0089] Subsequently, in order to bury the thin film transistor 1, an insulating film Z1 is formed to extend over the entire surface of the semiconductor substrate 2. Specifically, on the semiconductor substrate 2 on which the thin film transistor 1 is formed, for example, SiO2 is deposited by using CVD or the like, and then planarized by, for example, a CMP method. This thereby forms the insulating film Z1. In addition, on the insulating film Z1, an insulating film Z2 containing, for example, SiN and a sacrificial layer ZG containing SiO2 are sequentially stacked by using CVD or the like. At this time, for example, the sacrificial layer ZG can be planarized by a CMP method so that the upper surface ZGS of the sacrificial layer ZG is parallel to the surface 2FS of the semiconductor substrate 2.

[0090] Next, as Figure 5B shown in, openings 10K and 20K are formed, and both the opening 10K and the opening 20K penetrate the stacked film including the insulating film Z1, the insulating film Z2, and the sacrificial layer ZG. At this time, the silicide layer 6 provided in the drain region 1D is exposed at the bottom of the opening 10K. In addition, the silicide layer 6 provided in the source region 1S is exposed at the bottom of the opening 20K.

[0091] Next, as Figure 5C shown in, a first conductive column 10 is formed to fill the inside of the opening 10K, and a second conductive column 20 is formed to fill the inside of the opening 20K. At this time, the height position P10 of the upper end 10UT of the first conductive column 10 and the height position P20 of the upper end 20UT of the second conductive column 20 coincide with the height position of the upper surface ZGS of the sacrificial layer ZG. That is, the height H10 of the first conductive column 10 and the height H20 of the second conductive column 20 are substantially the same as each other based on the height position P0 of the surface 2FS.

[0092] Next, as Figure 5D shown in, the sacrificial layer ZG is removed. Here, for example, by performing wet processing using hydrofluoric acid, the sacrificial layer ZG including the silicon oxide film can be selectively removed from the insulating film Z2 including the silicon nitride film, and the first conductive column 10 and the second conductive column 20 both including a metal material or the like.

[0093] Next, as Figure 5EAs shown in the figure, the ferroelectric material film 3A and the electrode material film 4A are sequentially formed to cover the insulating film Z2, the first conductive pillar 10, and the second conductive pillar 20. At this time, for example, the ferroelectric material film 3A and the electrode material film 4A can be formed by, for example, an ALD (Atomic Layer Deposition) apparatus so that the ferroelectric material film 3A and the electrode material film 4A are sufficiently deposited on the side surfaces of the second conductive pillar 20.

[0094] Next, as Figure 5F shown in the figure, a part of the ferroelectric material film 3A and the electrode material film 4A formed along the XY surface is selectively removed (that is, a part covering the insulating film Z2, a part covering the upper end 10UT of the first conductive pillar 10, and a part covering the upper end 20UT of the second conductive pillar 20). By anisotropic dry etching, the ferroelectric material film 3A and the electrode material film 4A can be selectively removed. Therefore, the ferroelectric layer 13 and the electrode layer 14 are stacked and formed on the side surface of the first conductive pillar 10, and the ferroelectric layer 23 and the electrode layer 24 are stacked and formed on the side surface of the second conductive pillar 20. Therefore, the contact portion 15 and the capacitor portion 25 are formed.

[0095] Next, as Figure 5G shown in the figure, an insulating film Z3 is formed on the insulating film Z2 to fill the periphery of the contact portion 15 and the periphery of the capacitor portion 25. In addition, an insulating film Z4 is formed to cover the insulating film Z3, the upper end 10UT, and the upper end 20UT. It should be noted that the insulating film Z3 and the insulating film Z4 can be formed together such that the insulating film Z3 and the insulating film Z4 are integrated with each other. The insulating film Z3 and the insulating film Z4 are formed by, for example, forming a silicon oxide film by a CVD apparatus and then planarizing it by a CMP method. Alternatively, the insulating film Z3 and the insulating film Z4 can each be formed of a Spin-on-Dielectric film.

[0096] Finally, the first wiring 4 and the second wiring 5 are formed by, for example, a damascene process. Specifically, as Figure 5H shown in the figure, a part of the insulating film Z3 and a part of the insulating film Z4 are selectively removed by a photolithography method to form an opening 4K and an opening 5K, respectively. Next, a barrier layer 4A is formed on the opening 4K, and a barrier layer 5A is formed on the opening 5K. Thereafter, an embedded layer 4B is formed to fill the opening 4K covered by the barrier layer 4A by electroplating or the like, and an embedded layer 5B is formed to fill the opening 5K covered by the barrier layer 5A.

[0097] The above steps enable the formation of Figure 2 the semiconductor memory device 100 as shown in, for example,

[0098] [1.4. Function and Effect]

[0099] In the capacitor section 25 of such a semiconductor memory device 100, information "1" or information "0" is stored according to the polarization state of the ferroelectric layer 23. The polarization state of the ferroelectric layer 23 can be controlled by applying an electric field to the ferroelectric layer 23. The electric field to be applied to the ferroelectric layer 23 can be controlled by the potential difference between the potential of the gate electrode 1G of the word line WL ( Figure 1 ) and the potential of the second wiring 5 of the source line SL ( Figure 1 ). In the ferroelectric layer 23, the application of the electric field causes polarization, and the polarization state continues even when the electric field is lost. Associating the positive and negative remnant polarizations (spontaneous polarizations) caused by the hysteresis of the ferroelectric layer 23 with the logic values "1" or "0" enables the capacitor section 25 to be used as a non-volatile memory.

[0100] As described above, the semiconductor memory device 100 of the present embodiment includes: a semiconductor substrate 2 including a thin film transistor 1, a first wiring 4 and a second wiring 5, a contact section 15 including a first conductive post 10 that electrically couples the thin film transistor 1 to the first wiring 4, and a capacitor section 25 including a second conductive post 20 that electrically couples the thin film transistor 1 to the second wiring 5. Here, the height position P10 of the upper end 10UT of the first conductive post 10 and the height position P20 of the upper end 20UT of the second conductive post 20 are substantially the same as each other. Therefore, the first conductive post 10 and the second conductive post 20 can be formed jointly in the same step. However, for example, if the first conductive post 10 is formed and then the second conductive post 20 is to be formed on the same semiconductor substrate 2, an additional mask for protecting the already formed first conductive post 10 must be formed when forming the second conductive post 20. In contrast, in the semiconductor memory device 100, the first conductive post 10 and the second conductive post 20 are formed jointly in the same step. This enables the step of forming such an additional mask to be omitted. Therefore, the semiconductor memory device 100 can be easily manufactured.

[0101] In addition, the semiconductor storage device 100 of the present embodiment has a configuration in which the ferroelectric layer 23 and the electrode layer 24 are stacked to cover the side surface of the second conductive pillar 20. Therefore, this configuration is simpler than the configuration of a so-called cup-shaped capacitor in which a ferroelectric layer and an upper electrode are inserted into a narrow groove of a lower electrode, for example, as described in the above-mentioned PTL 1. That is, the barrier metal layer 22, the ferroelectric layer 23, and the electrode layer 24, which serve as the lower electrode, all have a substantially columnar shape and do not have an uneven shape. Therefore, there are various material types suitable for the materials to be included in the barrier metal layer 22, the ferroelectric layer 23, and the electrode layer 24. Therefore, a material type suitable as a capacitor, such as W (tungsten), becomes suitable for the lower electrode, and a capacitor portion 25 with a high capacitance can be realized. In addition, the capacitor portion 25 has a simple configuration, which enables the realization of a capacitor portion 25 with high-precision dimensions even when the size of the capacitor portion 25 is reduced. Therefore, the semiconductor storage device 100 is suitable for miniaturization.

[0102] In addition, in the semiconductor storage device 100 of the present embodiment, the side surface 5S of the second wiring 5 is coupled to the side surface 24S of the electrode layer 24, that is, on the opposite side of the second conductive pillar 20. Therefore, for example, compared with the case where the ferroelectric layer 23 and the electrode layer 24 are stacked to cover the upper end 20UT of the second conductive pillar 20, the manufacturing of the semiconductor storage device 100 becomes easier, and there is a possibility that the coupling resistance between the electrode layer 24 and the second wiring 5 is reduced.

[0103] [1.5. Modified Example]

[0104] [First Modified Example]

[0105] Reference Figure 6 A semiconductor storage device 100A according to a first modified example of the first embodiment of the present disclosure is described. Figure 6 is a schematic diagram showing an example of a cross-sectional configuration of the semiconductor storage device 100A. It should be noted that Figure 6 corresponds to Figure 2 showing an example of the cross-sectional configuration of the semiconductor storage device 100 of the above-described first embodiment.

[0106] In Figure 6 the semiconductor storage device 100A, the portion of the conductor layer 11 of the first conductive pillar 10 above the insulating film Z2 is surrounded by the counter electrode layer 16 instead of the barrier metal layer 12. In the semiconductor storage device 100A, the portion of the conductor layer 21 of the second conductive pillar 20 above the insulating film Z2 is surrounded by the counter electrode layer 26 instead of the barrier metal layer 22. That is, Figure 6 the configuration of the semiconductor storage device 100A of Figure 2 is basically the same as the configuration of the semiconductor storage device 100 ofFigure 2 A part of the barrier metal layer 12 of the semiconductor memory device 100 is replaced by the counter electrode layer 16, and a part of the barrier metal layer 22 is replaced by the counter electrode layer 26. That is, the counter electrode layer 16 is the upper part surrounded by the ferroelectric layer 13 and the electrode layer 14, and the barrier metal layer 12 is the lower part except for the upper part surrounded by the ferroelectric layer 13 and the electrode layer 14. Similarly, the counter electrode layer 26 is the upper part surrounded by the ferroelectric layer 23 and the electrode layer 24, and the barrier metal layer 22 is the lower part except for the upper part surrounded by the ferroelectric layer 23 and the electrode layer 24. Examples of the materials included in each of the counter electrode layer 16 and the counter electrode layer 26 include Al (aluminum), La (lanthanum), TiN (titanium nitride), and TiO (titanium oxide).

[0107] For example, it can be manufactured as follows Figure 6 the semiconductor memory device 100A. Specifically, after the step described in the manufacturing method of the semiconductor memory device 100 of the first embodiment Figure 5D , for example, the corresponding exposed portions of the counter electrode layer 16 and the counter electrode layer 26 (that is, a part of the counter electrode layer 16 above the insulating film Z2 and a part of the counter electrode layer 26 above the insulating film Z2) are removed by, for example, a wet etching process. Thereafter, the counter electrode layer 16, the ferroelectric layer 13, and the electrode layer 14 are sequentially stacked to surround the side surface of the conductor layer 11, and at the same time, the counter electrode layer 26, the ferroelectric layer 23, and the electrode layer 24 are sequentially stacked to surround the side surface of the conductor layer 21. Subsequent steps can be performed in a manner similar to the method of manufacturing the semiconductor memory device 100 of the first embodiment, thereby manufacturing Figure 6 the semiconductor memory device 100A.

[0108] In Figure 6 the semiconductor memory device 100A, a more preferable material can be used as the capacitor portion 25 to configure the counter electrode layer 26 as the lower electrode. Therefore, compared with Figure 2 the semiconductor memory device 100, an improvement in the performance of the capacitor portion 25 can be expected, including, for example, an increase in the residual polarization in the capacitor portion 25, an improvement in the rewrite resistance, or an improvement in the data retention characteristics.

[0109] [Second Modified Example]

[0110] Refer to Figure 7 the semiconductor memory device 100B according to the second modified example of the first embodiment of the present disclosure. Figure 7 is a schematic diagram showing an example of the cross-sectional configuration of the semiconductor memory device 100B. It should be noted that Figure 7 corresponds to Figure 2 showing the cross-sectional configuration example of the semiconductor memory device 100 of the above-described first embodiment.

[0111] In Figure 7 the semiconductor memory device 100B, the portion of the conductor layer 11 of the first conductive pillar 10 above the insulating film Z2 is removed. Further, in the semiconductor memory device 100B, the portion of the conductor layer 21 of the second conductive pillar 20 above the insulating film Z2 is removed. In addition, Figure 7 the configuration of the semiconductor memory device 100B of Figure 2 is substantially the same as the configuration of the semiconductor memory device 100 of

[0112] For example, Figure 7 the semiconductor memory device 100B of Figure 5D can be manufactured as follows. Specifically, for example, after the steps described in the manufacturing method of the semiconductor memory device 100 of the first embodiment, the corresponding exposed portions of the counter electrode layer 16 and the counter electrode layer 26 (i.e., a part of the counter electrode layer 16 above the insulating film Z2 and a part of the counter electrode layer 26 above the insulating film Z2) are removed by, for example, a wet etching process. Thereafter, the ferroelectric layer 13 and the electrode layer 14 are sequentially stacked to surround the side surface of the conductor layer 11, and at the same time, the ferroelectric layer 23 and the electrode layer 24 are sequentially stacked to surround the side surface of the conductor layer 21. Subsequent steps can be performed in a manner similar to the method of manufacturing the semiconductor memory device 100 of the first embodiment, thereby manufacturing Figure 7 the semiconductor memory device 100B of

[0113] In Figure 7 the semiconductor memory device 100B of Figure 7 the configuration of each of the contact portion 15 and the capacitor portion 25 can be simplified, and the size of each of the contact portion 15 and the capacitor portion 25 in the in-plane direction can be reduced. In Figure 2 the semiconductor memory device 100B of

[0114] [Third Modification Example]

[0115] Refer to Figure 8 to describe the semiconductor memory device 100C according to the third modification example of the first embodiment of the present disclosure. Figure 8 is a schematic diagram showing a cross-sectional configuration example of the semiconductor memory device 100C. It should be noted that Figure 8 corresponds to Figure 2 showing the cross-sectional configuration example of the semiconductor memory device 100 of the above-described first embodiment.

[0116] InFigure 8 In the semiconductor memory device 100C, the second wiring 5 is disposed at a position overlapping with the second conductive pillar 20 in the Z-axis direction. The ferroelectric layer 23 and the electrode layer 24 are provided to also cover the upper end 20UT of the second conductive pillar 20. Accordingly, the capacitor portion 25 is coupled to the second wiring 5 not at the side surface 24S of the electrode layer 24 but at the upper surface 24US of the electrode layer 24. That is, in the semiconductor memory device 100C, the upper surface 24US of the electrode layer 24 contacts the lower surface of the barrier layer 5A of the second wiring 5. In addition, in Figure 8 the semiconductor memory device 100C, the contact portion 15 has neither the ferroelectric layer 13 nor the electrode layer 14. That is, the contact portion 15 includes only the first conductive pillar 10. In addition to this, Figure 8 the configuration of the semiconductor memory device 100C of Figure 2 is substantially the same as the configuration of the semiconductor memory device 100 of

[0117] For example, Figure 8 the semiconductor memory device 100C of Figure 5E can be manufactured as follows. Specifically, for example, after the steps described in the manufacturing method of the semiconductor memory device 100 of the first embodiment, the corresponding portions of the ferroelectric material film 3A and the electrode material film 4A covering the first conductive pillar 10 and the insulating film Z2 are selectively removed by anisotropic dry etching so as to leave only the portions of the ferroelectric material film 3A and the electrode material film 4A covering the second conductive pillar 20. The subsequent steps can be performed similarly to the manufacturing method of the semiconductor memory device 100 of the first embodiment. However, an opening 5K is formed directly above the second conductive pillar 20 such that the upper surface 24US of the electrode layer 24 is exposed at the bottom of the opening 5K. Thus, the semiconductor memory device 100C of Figure 8 can be manufactured.

[0118] In Figure 8 the semiconductor memory device 100C, the second conductive pillar 20 and the second wiring 5 are positioned to overlap each other in the Z-axis direction such that the upper surface 24US of the electrode layer 24 of the capacitor portion 25 is coupled to the second wiring 5. Accordingly, compared with the semiconductor memory device 100 of Figure 2 the area of the semiconductor memory device 100C in the in-plane direction can be reduced. In addition, in Figure 8 the semiconductor memory device 100C, the contact portion 15 includes neither the ferroelectric layer 13 nor the electrode layer 14, which makes it possible to reduce the parasitic capacitance of the contact portion 15 compared with the semiconductor memory device 100 of Figure 2 Accordingly, a stable voltage can be applied to the thin film transistor 1.

[0119] [Fourth Modification Example]

[0120] Referring toFigure 9 Describe the semiconductor memory device 100D according to the fourth modification of the first embodiment of the present disclosure. Figure 9 It is a schematic diagram showing an example of the cross-sectional configuration of the semiconductor memory device 100D. It should be noted that Figure 9 corresponds to the Figure 2 cross-sectional configuration example of the semiconductor memory device 100 shown in the above first embodiment.

[0121] In Figure 9 the semiconductor memory device 100D, the second wiring 5 is provided at a position overlapping the second conductive pillar 20 in the Z-axis direction. The ferroelectric layer 23 is provided to also cover the upper end 20UT of the second conductive pillar 20. In addition, the electrode layer 24 is integral with the barrier layer 5A of the second wiring 5. That is, the materials included in the electrode layer 24 and the barrier layer 5A are the same as each other, and the electrode layer 24 also serves as the barrier layer 5A. It should be noted that the contact portion 15 does not include the electrode layer 14. That is, the contact portion 15 includes the first conductive pillar 10 and the ferroelectric layer 13 surrounding a part of the first conductive pillar 10. In addition to this, Figure 9 the configuration of the semiconductor memory device 100D is substantially the same as the Figure 2 configuration of the semiconductor memory device 100C.

[0122] In Figure 9 the semiconductor memory device 100D, the second conductive pillar 20 and the second wiring 5 are positioned to overlap each other in the Z-axis direction such that the upper surface 24US of the electrode layer 24 of the capacitor portion 25 is coupled to the second wiring 5. Therefore, compared with the Figure 2 semiconductor memory device 100, the in-plane area of the semiconductor memory device 100D can be reduced. In addition, in Figure 9 the semiconductor memory device 100D, the electrode layer 14 of the contact portion 15 does not exist, and the electrode layer 24 of the capacitor portion 25 and the barrier layer 5A of the second wiring 5 are integral with each other. This enables the steps of forming the electrode layer 14 and the electrode layer 24 to be omitted in the manufacturing steps of the semiconductor memory device 100D. Therefore, the manufacturing process of the semiconductor memory device 100D can be simplified.

[0123] [Fifth Modification Example]

[0124] Refer to Figure 10 Describe the semiconductor memory device 100E according to the fifth modification of the first embodiment of the present disclosure. Figure 10 It is a schematic diagram showing an example of the cross-sectional configuration of the semiconductor memory device 100E. It should be noted that Figure 10 corresponds to the Figure 2 cross-sectional configuration example of the semiconductor memory device 100 shown in the above first embodiment.

[0125] In Figure 2 the semiconductor memory device 100 shown in, the ferroelectric layers 13 and 23 are respectively provided on the planarized insulating films Z1 and Z2. In contrast, in Figure 10 the semiconductor memory device 100E of, the insulating films Z1 and Z2 are not planarized, and the insulating films Z1 and Z2 both have a conformal shape along the shape of the upper surface of the thin film transistor 1. Therefore, in Figure 10 the semiconductor memory device 100E of, compared with Figure 2 the semiconductor memory device 100 of, the height H10 of the first conductive column 10 and the height H20 of the second conductive column 20 can be reduced. Therefore, the semiconductor memory device 100E can reduce the resistance between the thin film transistor 1 and the first wiring 4 and the resistance between the thin film transistor 1 and the second wiring 5, which enables stable operation as a memory device.

[0126] [Sixth Modified Example]

[0127] Refer to Figure 11 to describe the semiconductor memory device 100F according to the sixth modified example of the first embodiment of the present disclosure. Figure 11 is a schematic diagram showing an example of a cross-sectional configuration of the semiconductor memory device 100F. It should be noted that Figure 11 corresponds to Figure 2 the one showing the cross-sectional configuration example of the semiconductor memory device 100 of the above-described first embodiment.

[0128] In Figure 11In the semiconductor memory device 100F, a plurality of wiring layers W1 to W3 stacked in the Z-axis direction are interposed between the first conductive pillar 10 and the contact portion 15, and a plurality of wiring layers W1 to W3 stacked in the Z-axis direction are interposed between the second conductive pillar 20 and the capacitor portion 25. The periphery of the wiring layer W1 is filled with the insulating film Z1, the periphery of the wiring layer W2 is filled with the insulating film Z2, and the periphery of the wiring layer W3 is filled with the insulating film Z3. Further, instead of the first conductive pillar 10, the contact portion 15 includes a conductor layer 17 having a substantially cylindrical shape and a barrier metal layer 18 surrounding the periphery of the conductor layer 17. The ferroelectric layer 13 and the electrode layer 14 are provided on the periphery of the barrier metal layer 18. The lower end of the conductor layer 17 is coupled to the wiring layer W3, and the upper end 17UT of the conductor layer 17 is coupled to the first wiring 4. Further, instead of the second conductive pillar 210, the capacitor portion 25 includes a conductor layer 27 having a substantially cylindrical shape and a barrier metal layer 28 surrounding the periphery of the conductor layer 27. The ferroelectric layer 23 and the electrode layer 24 are provided on the periphery of the barrier metal layer 28. The lower end of the conductor layer 27 is coupled to the wiring layer W3 and the side surface 24S of the electrode layer 24 is coupled to the side surface 5S of the second wiring 5. Also in the semiconductor memory device 100F having such a configuration, the height position P17 of the upper end 17UT of the conductor layer 17 and the height position P27 of the upper end 27UT of the conductor layer 27 can be substantially the same as each other. According to Figure 11 the semiconductor memory device 100F, the flexibility in setting the heights of the conductor layer 27 and the barrier metal layer 28 is improved, which enables the capacitor portion 25 to obtain, for example, a larger capacitance.

[0129] [2. Second Embodiment]

[0130] [2.1. Configuration Example]

[0131] Next, refer to Figure 12A and Figure 12B to describe the transistor device 200 according to the second embodiment of the present disclosure. Figure 12A and Figure 12B are respectively schematic views showing cross-sectional configuration examples of the transistor device 200. It should be noted that Figure 12A shows a cross-section taken along the direction of the XIIA-XIIA line in Figure 12B . Figure 12B shows a cross-section taken along the direction of the XIIB-XIIB line in Figure 12A . That is, the cross-section of the transistor device 200 shown in Figure 12A is orthogonal to the cross-section of the transistor device 200 shown in Figure 12B .

[0132] Figure 12A and Figure 12BThe transistor device 200 shown in [description] includes a transistor 201 of an advanced technology node. The transistor 201 provided in the semiconductor substrate 2 has a structure of a so-called fully surrounding gate structure. Specifically, the transistor 201 includes a plurality of channel layers 202, each having a sheet shape, a gate electrode 203, a source region 204, and a drain region 205. The gate electrode 203 is formed to cover each of the plurality of channel layers 202. Each of the plurality of channel layers 202 extends along the surface 2FS of the semiconductor substrate 2 and passes through the gate electrode 203 along the surface 2FS. The source region 204 and the drain region 205 face each other with the gate electrode 203 and the channel layer 202 therebetween, and are respectively provided vertically on the semiconductor substrate 2. For example, each of the source region 204 and the drain region 205 is a region including Si (silicon) formed by epitaxial growth. The side surface 203S of the gate electrode 203, the side surface 204S of the source region 204, and the side surface 205S of the drain region 205 are respectively coupled to the corresponding side surfaces of the contact plugs 206 to 208.

[0133] [2.2. Function and Effect]

[0134] In the transistor device 200 of the present embodiment, as Figure 12A shown, the side surface 204S of the source region 204 and the side surface 207S of the contact plug 207 are in contact with each other, and the side surface 205S of the drain region 205 and the side surface 208S of the contact plug 208 are in contact with each other. Additionally, as Figure 12B shown, in the transistor device 200, the side surface 203S of the gate electrode 203 and the side surface 206S of the contact plug 206 are in contact with each other. Therefore, compared with, for example, the transistor device 1200 which is a reference example shown in Figure 13 , the contact area between the gate electrode 203 and the contact plug 206, the contact area between the source region 204 and the contact plug 207, and the contact area between the drain region 205 and the contact plug 208 can be increased. The transistor device 1200 is configured such that the upper surface of the gate electrode 203 is in contact with the lower surface of the contact plug 1206, the upper surface of the source region 204 is in contact with the lower surface of the contact plug 207, and the upper surface of the drain region 205 is in contact with the lower surface of the contact plug 208. Transistors of advanced technology nodes occupy a very small area in the in-plane direction. Therefore, in such a transistor device 1200 of the reference example, the ohmic contact characteristics tend to deteriorate. In contrast, in the transistor device 200 of the present embodiment, as described above, the respective side surfaces of the gate electrode 203, the source region 204, and the drain region 205 are each in contact with a corresponding one of the respective side surfaces of the contact plugs 206 to 208 to ensure a sufficient contact area. Therefore, according to the transistor device 200 of the present embodiment, more favorable ohmic characteristics can be obtained even when the transistor device 200 is miniaturized.

[0135] [3. Other Modification Examples]

[0136] The technology according to the present disclosure has been described above with reference to the embodiments and modification examples. However, the technology according to the present disclosure is not limited to the above embodiments and the like, but various modifications can be made.

[0137] For example, in the semiconductor memory device 100 of the first embodiment described above (see Figure 2 etc.), the conductor layers 11 and 21 and the barrier metal layers 12 and 22 are each configured as a single piece. However, in the present disclosure, for example, in the semiconductor memory device 300 shown in Figure 14 , the conductor layers 11 and 21 and the barrier metal layers 12 and 22 can each be configured by two or more parts separated in the Z-axis direction. That is, in the semiconductor memory device 300, the conductor layer 11 has a double-layer structure including a first-stage layer portion 11A and a second-stage layer portion 11B, and the conductor layer 21 has a double-layer structure including a first-stage layer portion 21A and a second-stage layer portion 21B. Similarly, the barrier metal layer 12 has a double-layer structure including a first-stage layer portion 12A and a second-stage layer portion 12B, and the barrier metal layer 22 has a double-layer structure including a first-stage layer portion 22A and a second-stage layer portion 22B. Also in the semiconductor memory device 300, the height position P10 of the upper end 10UT of the first conductive pillar 10 and the height position P20 of the upper end 20UT of the second conductive pillar 20 are substantially the same as each other. Therefore, the second-stage layer portion 11B of the first conductive pillar 10 and the second-stage layer portion 21B of the second conductive pillar 20 can be formed together in the same step, and the second-stage layer portion 12B of the first conductive pillar 10 and the second-stage layer portion 22B of the second conductive pillar 20 can be formed together in the same step.

[0138] However, for example, if the first conductive pillar 10 is formed and then the second conductive pillar 20 is to be formed on the same semiconductor substrate 2, an additional mask for protecting the first conductive pillar 10 (which has already been formed when forming the second conductive pillar 20) must be formed. In contrast, in the semiconductor memory device 300, the second-stage layer portion 11B of the first conductive pillar 10 and the second-stage layer portion 21B of the second conductive pillar 20 can be formed together in the same step, and the second-stage layer portion 12B of the first conductive pillar 10 and the second-stage layer portion 22B of the second conductive pillar 20 can be formed together in the same step. This makes it possible to omit the step of forming such an additional mask. Therefore, the semiconductor memory device 300 can be easily manufactured.

[0139] In addition, in the semiconductor memory device 300, the materials included in each of the first-stage layer portions 11A and 21A and the materials included in each of the second-stage layer portions 11B and 21B can be made different from each other. Similarly, the materials included in each of the first-stage layer portions 12A and 22A and the materials included in each of the second-stage layer portions 12B and 22B can be made different from each other.

[0140] In addition, the cross-sectional areas of the first-stage layer portion 21A and the second-stage layer portion 21B can be made different from each other. For example, in the semiconductor memory device 300A shown in Figure 15 . In the semiconductor memory device 300A, compared with the semiconductor memory device 300, the area of the relative portion where the second-stage layer portion 22B and the electrode layer 24, which are a pair of electrodes, face each other with the ferroelectric layer 23 therebetween can be increased. Therefore, the capacitance of the capacitor portion 25 can be increased.

[0141] In addition, not all of the components and operations described in each of the embodiments are necessary as components and operations according to the present disclosure. For example, among the components according to the corresponding embodiments, the components not described in the independent claims that describe the most general concept of the present disclosure should be understood as optional components.

[0142] The terms used in this specification and the appended claims should be interpreted as "non-limiting" terms. For example, the term "including" or "included" should be interpreted as "not limited to what is described as being included". The term "having" should be interpreted as "not limited to what is described as having".

[0143] The terms used in this specification are for convenience of description only and include terms that do not limit the configuration and operation. For example, terms such as "right", "left", "up", and "down" only indicate the directions in the drawings referred to. In addition, the terms "inside" and "outside" respectively only indicate the direction toward the center of the target component and the direction away from the center of the target component. This also applies to terms similar to these terms and terms having similar purposes.

[0144] It should be noted that the technology according to the present disclosure can have the following configuration. The semiconductor memory device of the present disclosure having the following configuration is small in size and excellent in manufacturability.

[0145] It should be noted that the effects obtained by the technology according to the present disclosure are not necessarily limited to the effects described herein, but can include any effects described in the present disclosure.

[0146] (1) A semiconductor memory device, comprising:

[0147] A semiconductor substrate including thin film transistors;

[0148] A first wiring and a second wiring, both stacked on the semiconductor substrate;

[0149] A contact portion including a first conductive pillar that extends in a stacking direction in which the first wiring and the second wiring are stacked on the semiconductor substrate and electrically couples the thin film transistor and the first wiring to each other; and

[0150] A capacitor portion including a second conductive pillar that extends in the stacking direction and electrically couples the thin film transistor and the second wiring to each other, wherein

[0151] A height position of an upper end of the first conductive pillar on an opposite side of the semiconductor substrate is substantially the same as a height position of an upper end of the second conductive pillar on an opposite side of the semiconductor substrate.

[0152] (2) The semiconductor memory device according to (1), wherein the capacitor portion includes:

[0153] A second conductive pillar,

[0154] An electrode layer surrounding a part of a side surface of the second conductive pillar, and

[0155] A ferroelectric layer interposed between the second conductive pillar and the electrode layer.

[0156] (3) The semiconductor memory device according to (2), wherein the second conductive pillar includes:

[0157] A conductor layer having a columnar shape, and

[0158] A barrier metal layer surrounding a periphery of the conductor layer.

[0159] (4) The semiconductor memory device according to (3), wherein the conductor layer includes a conductor containing W (tungsten).

[0160] (5) The semiconductor memory device according to (3) or (4), wherein the barrier metal layer includes a metal material containing at least one of Ti, TiN, or Ru.

[0161] (6) The semiconductor memory device according to any one of (2) to (5), wherein the second wiring is coupled to a side surface of the electrode layer on an opposite side of the second conductive pillar.

[0162] (7) The semiconductor memory device according to any one of (2) to (6), wherein the ferroelectric layer contains HfO2.

[0163] (8) The semiconductor memory device according to (2), wherein at least a part of the electrode layer and the second wiring are integrated with each other.

[0164] (9) The semiconductor memory device according to (2), wherein a portion of the second conductive pillar surrounded by the electrode layer includes only a conductor layer having a columnar shape.

[0165] (10) The semiconductor memory device according to (2), wherein

[0166] the second conductive pillar includes:

[0167] a conductor layer having a columnar shape,

[0168] a barrier metal layer surrounding the periphery of the lower portion of the conductor layer in the stacking direction, and

[0169] an opposing electrode layer surrounding the periphery of the upper portion of the conductor layer in the stacking direction and opposing the electrode layer, and

[0170] wherein materials included in the barrier metal layer and materials included in the opposing electrode layer are different from each other.

[0171] (11) A transistor device, comprising:

[0172] a transistor, comprising:

[0173] a gate electrode vertically provided on the surface of a substrate,

[0174] a channel layer having a sheet shape passing through the gate electrode along the surface, and

[0175] a source region and a drain region, the source region and the drain region being opposed to each other with the gate electrode and the channel layer therebetween, and the source region and the drain region being vertically provided on the substrate respectively; and

[0176] at least one of a first wiring or a second wiring, the first wiring being electrically coupled to a side surface of the source region, and the second wiring being electrically coupled to a side surface of the drain region.

[0177] This application claims the benefit of Japanese Patent Application No. JP2022 - 201800, filed with the Japan Patent Office on December 19, 2022, the entire contents of which are incorporated herein by reference.

[0178] Those skilled in the art should understand that various modifications, combinations, sub - combinations and changes can be made according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A semiconductor memory device, comprising: A semiconductor substrate including thin film transistors; A first wiring and a second wiring, each stacked on the semiconductor substrate; A contact portion including a first conductive pillar, the first conductive pillar extending in a stacking direction in which the first wiring and the second wiring are stacked on the semiconductor substrate and electrically coupling the thin film transistor and the first wiring to each other; And A capacitor portion including a second conductive pillar, the second conductive pillar extending in the stacking direction and electrically coupling the thin film transistor and the second wiring to each other, wherein A height position of an upper end of the first conductive pillar on an opposite side of the semiconductor substrate is substantially consistent with a height position of an upper end of the second conductive pillar on an opposite side of the semiconductor substrate.

2. The semiconductor memory device according to claim 1, wherein, The capacitor portion includes: The second conductive pillar; An electrode layer surrounding a part of a side surface of the second conductive pillar; and A ferroelectric layer interposed between the second conductive pillar and the electrode layer.

3. The semiconductor memory device according to claim 2, wherein, The second conductive pillar includes: A conductor layer having a columnar shape; and A barrier metal layer surrounding a periphery of the conductor layer.

4. The semiconductor memory device according to claim 3, wherein, The conductor layer includes a conductor containing tungsten (W).

5. The semiconductor memory device according to claim 3, wherein, The barrier metal layer includes a metal material containing at least one of titanium (Ti), titanium nitride (TiN), and ruthenium (Ru).

6. The semiconductor memory device according to claim 2, wherein, The second wiring is coupled to a side surface of the electrode layer on an opposite side of the second conductive pillar.

7. The semiconductor memory device according to claim 2, wherein, The ferroelectric layer contains HfO2.

8. The semiconductor memory device according to claim 2, wherein, At least a part of the electrode layer and the second wiring are integral with each other.

9. The semiconductor memory device according to claim 2, wherein, A part of the second conductive pillar surrounded by the electrode layer only includes a conductor layer having a columnar shape.

10. The semiconductor memory device according to claim 2, wherein The second conductive pillar includes: A conductor layer having a columnar shape; A barrier metal layer surrounding a periphery of the conductor layer in a lower part in the stacking direction; and An opposing electrode layer surrounding a periphery of the conductor layer in an upper part in the stacking direction and opposing the electrode layer, and Wherein materials included in the barrier metal layer and materials included in the opposing electrode layer are different from each other.

11. A transistor device, comprising: A transistor including A gate electrode vertically provided on a surface of a substrate; A channel layer having a sheet shape passing through the gate electrode along the surface; And A source region and a drain region, the source region and the drain region being opposed to each other with the gate electrode and the channel layer therebetween, and the source region and the drain region being respectively vertically provided on the substrate; and At least one of a first wiring and a second wiring, the first wiring being electrically coupled to a side surface of the source region, and the second wiring being electrically coupled to a side surface of the drain region.

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