A test meter switching circuit

Abstract

The application discloses a kind of test instrument switching circuit, and the circuit includes PLC board, instrument switching board, first test board, second test board and third test board;PLC board includes CPU chip, operational amplifier chip and analog input chip, and the CPU is connected with instrument switching board by input pin and output pin, to realize the switching of instrument;CPU chip is connected with operational amplifier chip to realize pulse counting function, and analog input chip is connected with first test board, second test board and third test board respectively, to realize the detection of the test piece connected with each test board under the control of CPU chip.The application can realize the quick switching of each important instrument in actuator test process, can be an important part of a general test platform, and can greatly improve test efficiency by using modular design for different linear actuator test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing and control, in particular to a test instrument switching circuit. BACKGROUND

[0002] Many valves on the aircraft use linear actuators, and the linear actuators need to measure various parameters during production and maintenance, including: tension and pressure measurement, stroke measurement, speed measurement, stroke time recording, etc.

[0003] The existing test platform has poor test comprehensiveness, and it is difficult to realize the rapid switching of various instruments during the measurement process, resulting in low test efficiency. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a test instrument switching circuit. The test instrument switching circuit can realize the rapid switching of the test instrument, thereby improving the test efficiency.

[0005] The purpose of the present application is realized by the following technical solutions:

[0006] The test instrument switching circuit comprises a PLC board, an instrument switching board, a first test board, a second test board and a third test board.

[0007] The PLC board comprises a CPU chip, an operational amplifier chip and an analog input chip, and the CPU is connected to the instrument switching board through input pins and output pins to realize the switching of the instrument.

[0008] The CPU chip is connected to the operational amplifier chip to realize pulse counting function, and the analog input chip is connected to the first test board, the second test board and the third test board respectively to realize the detection of the test piece connected to each test board under the control of the CPU chip.

[0009] Further, the output pins Q0.5-Q0.7 and the input pins I0.3-I0.5 of the CPU chip are connected to the instrument switching board through the pins of the connector CN4, the input pins I0.3-I0.5 of the CPU chip are respectively connected to the instrument panel 24V DC power supply through the first to third pins of the CN4, and then connected to the instrument panel 24V DC power supply through the switches panel1, panel2 and panel3 respectively; the output pins Q0.5-Q0.7 of the CPU chip are connected to the panel switching circuit through the fifth to seventh pins of the connector CN4.

[0010] The input pin I0.0 and I0.1 of the CPU chip are respectively connected to two output pins of the operational amplifier chip, the output pin Q0.0 of the CPU chip is connected to the coil of the relay R1, and two groups of normally open contacts of the relay R1 are respectively arranged on the connection lines of the input pin I0.0 and I0.1 of the CPU chip and the two output pins of the operational amplifier chip;

[0011] The output pin Q0.2 of the CPU chip is connected to the first test board through the first cable and the interface seat CN1, the output pin Q0.3 of the CPU chip is connected to the second test board through the second cable and the interface seat CN2, and the output pin Q0.4 of the CPU chip is connected to the third test board through the third cable and the interface seat CN3.

[0012] Further, the output pin Q0.1 of the CPU chip is connected to the coil of the relay R2, the relay R2 is a double conversion contact relay, the 0+ pin of the analog input chip is connected to the moving contact of the first group of double conversion contacts of the relay R2, the normally open static contact of the group of double conversion contacts is connected to the fourth pin of the terminal block, the 1+ pin of the analog input chip is connected to the moving contact of the second group of double conversion contacts of the relay R2, the normally open static contact of the group of double conversion contacts is connected to the first pin of the terminal block, the 2+ pin of the analog input chip is connected to the moving contact of the third group of double conversion contacts of the relay R2, the normally open static contact of the group of double conversion contacts is connected to the seventh pin of the terminal block, the 2- pin of the analog input chip is connected to the moving contact of the fourth group of normally open contacts of the relay R2, the static contact of the four groups of normally open contacts is connected to the ninth pin of the terminal block, the normally closed static contacts of the first to third groups of double conversion contacts of the relay R2 are all grounded, the first to third pins of the terminal block are connected in parallel through the jumper wires, the fourth to sixth pins are connected in parallel through the jumper wires, the seventh to eighth pins are connected in parallel through the jumper wires, and the ninth to eleventh pins are connected in parallel through the jumper wires.

[0013] The 0- pin, 1- pin, 2- pin and M pin of the analog input chip are all grounded, and a group of analog input pins of the analog input chip are connected to the displacement sensor.

[0014] Further, a group of negative phase end pins of the operational amplifier chip are connected to the 15V DC power supply through a connection resistor, a corresponding group of positive phase end pins are loaded with the 10V DC power supply, one negative phase end pin is connected to the U jack of the test interface of the first test board through the cable and the interface CN1, the other negative phase end pin is connected to the V jack of the test interface of the first test board through the cable and the interface CN1, and the U jack and the V jack of the test interface of the first test board are connected to the U terminal and the V terminal inside the first test board.

[0015] Further, the input of 15V DC power supply and 10V DC power supply of the operational amplifier chip is provided by the DC-DC power module.

[0016] Further, the E jack of the test interface of the first test block is connected to the 1M pin of the pulse counting module of the CPU chip through the first cable and the interface seat CN1; the D jack of the test interface of the first test block is connected to the voltage output terminal of the voltage stabilizer chip through the first cable and the interface seat CN1; the C jack of the test interface of the first test block is connected to the first pin of the terminal block through the first cable and the interface seat CN1; the B jack of the test interface of the first test block is connected to the fourth pin of the terminal block through the first cable and the interface seat CN1; the A jack of the test interface of the first test block is connected to the ninth pin of the terminal block through the first cable and the interface seat CN1; the D jack, the C jack, the B jack and the A jack of the test interface of the first test block are connected to the D terminal, the C terminal, the B terminal and the A terminal inside the first test block, respectively.

[0017] The output pin Q0.2 of the CPU chip is connected to the coil part of the eleventh relay R11 and the twelfth relay R12 in parallel through the first cable and the interface seat CN1, and then grounded; the three normally open contacts of the eleventh relay R11 are arranged on the connection lines between the U, V, E jacks of the test interface of the first test block and the U, V, E terminals inside the first test block, respectively, wherein the E jack and the E terminal are grounded; the three normally open contacts of the twelfth relay R12 are arranged on the connection lines between the C, B, A jacks of the test interface of the first test block and the C, B, A terminals inside the first test block, respectively; wherein the C jack and the A jack are also connected to the positive and negative poles of the 10V DC power supply, respectively.

[0018] Further, the V jack and the R jack of the test interface of the second test block are connected to the second pin of the terminal block through the second cable and the interface seat CN2; the T jack of the test interface of the second test block is connected to the seventh pin of the terminal block through the second cable and the interface seat CN2; the S jack and the N jack of the test interface of the second test block are connected to the tenth pin of the terminal block through the second cable and the interface seat CN2; the P jack of the test interface of the second test block is connected to the fifth pin of the terminal block through the second cable and the interface seat CN2.

[0019] The V jack, R jack, S jack, R jack, T jack, N jack of the test interface of the second test block are connected with the V terminal, R terminal, S terminal, R terminal, T terminal, N terminal inside the second test block; the V terminal and R terminal inside the second test block are connected in series and the S terminal and N terminal are connected in series; the output pin Q0.3 of the CPU chip is connected to the coil part of the twenty-first relay R21 through the second cable and the interface seat CN2, and the four normally open contacts of the twenty-first relay R21 are respectively arranged on the connection lines of the V jack, T jack, P jack, S jack of the test interface of the second test block and the V terminal, T terminal, P terminal, S terminal inside the second test block; wherein the V jack and N jack are respectively connected to the positive and negative poles of the 10V DC power supply.

[0020] Further, the F jack and C jack of the test interface of the third test block are connected to the third pin of the terminal block through the third cable and the interface seat CN3; the E jack of the test interface of the third test block is connected to the eighth pin of the terminal block through the third cable and the interface seat CN3; the D jack and A jack of the test interface of the third test block are connected to the eleventh pin of the terminal block through the third cable and the interface seat CN3; the B jack of the test interface of the third test block is connected to the sixth pin of the terminal block through the third cable and the interface seat CN3;

[0021] The F jack, E jack, D jack, C jack, B jack, A jack of the test interface of the third test block are connected with the F terminal, E terminal, D terminal, C terminal, B terminal, A terminal inside the third test block; the D terminal and A terminal inside the third test block are connected in series; the output pin Q0.4 of the CPU chip is connected to the coil part of the thirty-first relay R31 through the third cable and the interface seat CN3, and the four normally open contacts of the thirty-first relay R31 are respectively arranged on the connection lines of the F jack, E jack, B jack, A jack of the test interface of the third test block and the F terminal, E terminal, B terminal, D terminal inside the second test block; wherein the F jack and A jack are respectively connected to the positive and negative poles of the 10V DC power supply.

[0022] Furthermore, the panel switching circuit includes an initial switching control relay K0 and first switching control relays K1 to eleventh switching control relays K11. The fifth pin of the connector CN4 is connected in series with the normally closed contact K3-3 of the third switching control relay K3, the normally closed contact K6-3 of the sixth switching control relay K6, and the coil of the second switching control relay K2 before being grounded. The sixth pin of the connector CN4 is connected in series with the normally closed contact K3-2 of the third switching control relay K3, the normally closed contact K9-3 of the ninth switching control relay K9, and the coil of the first switching control relay K1 before being grounded. The seventh pin of the connector CN4 is connected in series with the normally closed contact K6-2 of the sixth switching control relay K6, the normally closed contact K9-2 of the ninth switching control relay K9, and the coil of the initial switching control relay K0 before being grounded.

[0023] The coils of the third switching control relay K3, the fourth switching control relay K4, and the fifth switching control relay K5 are connected in parallel, with one end's common contact connected to the instrument panel's 24V DC power supply via the normally open contact of the initial switching control relay K0, and the other end's common contact connected to the negative terminal of each instrument. The coils of the sixth switching control relay K6, the seventh switching control relay K7, and the eighth switching control relay K8 are connected in parallel, with one end's common contact connected to the instrument panel's 24V DC power supply via the normally open contact of the first switching control relay K1, and the other end's common contact connected to the negative terminal of each instrument. The coils of the ninth switching control relay K9, the tenth switching control relay K10, and the eleventh switching control relay K11 are connected in parallel, with one end's common contact connected to the instrument panel's 24V DC power supply via the normally open contact of the second switching control relay K2, and the other end's common contact connected to the negative terminal of each instrument. The positive terminals of each instrument are all connected to the instrument panel's 24V DC power supply.

[0024] The beneficial effects of this invention are: this invention can realize the rapid switching of various important instruments during actuator testing, and can be used as an important component of a general testing platform. It adopts a modular design for testing linear actuators of different part numbers, thereby greatly improving testing efficiency.

[0025] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained from the following description and the foregoing claims. Attached Figure Description

[0026] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings, in which:

[0027] Figure 1 is a detection switching schematic diagram of the present application;

[0028] Figure 2 is a control panel switching schematic diagram;

[0029] Figure 3 is a counter power supply control schematic diagram;

[0030] Figure 4 is an industrial control cabinet panel view;

[0031] Figure 5 is a medium frequency AC voltage meter, DC voltage meter, timer, DC current meter switching principle step diagram;

[0032] Figure 6 and Figure 7 is a counter switching principle step diagram;

[0033] Figure 8 is a displacement switching principle step diagram. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present application will be described in detail below with reference to the drawings. It should be understood that the preferred embodiments are only for illustrating the present application, but not for limiting the protection scope of the present application.

[0035] As shown in Figure 1 , in the present embodiment, the circuit includes a PLC board, an instrument switching board, a first test board, a second test board and a third test board;

[0036] The PLC board includes a CPU chip, an operational amplifier chip and an analog input chip, the CPU is connected to the instrument switching board through input pins and output pins to realize the switching of the instruments;

[0037] The CPU chip realizes the pulse counting function by being connected to the operational amplifier chip, and the analog input chip is connected to the first test board, the second test board and the third test board respectively to realize the detection of the to-be-tested components connected to the test boards under the control of the CPU chip.

[0038] In this embodiment, the CPU chip adopts Siemens ST20 standard type CPU module, containing 12 inputs and 8 outputs, using 24V DC power supply; the operational amplifier chip adopts LM324, which is a low-cost four-channel operational amplifier with true differential input; the analog input chip adopts Siemens EM AE08 analog input module, which can process analog signals and convert them into digital signals for PLC processing and control.

[0039] The output pins Q0.5-Q0.7 and the input pins I0.3-I0.5 of the CPU chip are connected to the instrument switching board block through the pins of the connector CN4, wherein the input pins I0.3-I0.5 of the CPU chip are respectively connected to the instrument panel 24V DC power supply through the first to third pins of CN4, and then through the switches panel1, panel2 and panel3 respectively; the output pins Q0.5-Q0.7 of the CPU chip are connected to the panel switching circuit through the fifth to seventh pins of CN4.

[0040] The input pins I0.0 and I0.1 of the CPU chip are respectively connected to the two output pins of the operational amplifier chip, and the output pin Q0.0 of the CPU chip is connected to the coil of the relay R1; the two groups of normally open contacts of the relay R1 are respectively arranged on the connection lines of the input pins I0.0 and I0.1 of the CPU chip and the two output pins of the operational amplifier chip.

[0041] The output pin Q0.2 of the CPU chip is connected to the first test board block through the first cable and the interface seat CN1; the output pin Q0.3 of the CPU chip is connected to the second test board block through the second cable and the interface seat CN2; the output pin Q0.4 of the CPU chip is connected to the third test board block through the third cable and the interface seat CN3.

[0042] The output pin Q0.1 of the CPU chip is connected to the coil of the relay R2, the relay R2 is a double conversion contact relay, the 0+ pin of the analog input chip is connected to the moving contact of the first group of double conversion contacts of the relay R2, the normally open static contact of the group of double conversion contacts is connected to the fourth pin of the terminal block JP; the 1+ pin of the analog input chip is connected to the moving contact of the second group of double conversion contacts of the relay R2, the normally open static contact of the group of double conversion contacts is connected to the first pin of the terminal block JP; the 2+ pin of the analog input chip is connected to the moving contact of the third group of double conversion contacts of the relay R2, the normally open static contact of the group of double conversion contacts is connected to the seventh pin of the terminal block; the 2- pin of the analog input chip is connected to the moving contact of the fourth group of normally open contacts of the relay R2, the static contact of the four groups of normally open contacts is connected to the ninth pin of the terminal block; the normally closed static contacts of the first to third groups of double conversion contacts of the relay R2 are all grounded; the first to third pins of the terminal block JP are connected in parallel through a jumper wire, the fourth to sixth pins are connected in parallel through a jumper wire; the seventh to eighth pins are connected in parallel through a jumper wire; the ninth to eleventh pins are connected in parallel through a jumper wire;

[0043] The 0- pin, 1- pin, 2- pin and M pin of the analog input chip are all grounded; a group of analog input pins of the analog input chip are connected to the displacement sensor.

[0044] In the embodiment, a group of negative phase end pins of the operational amplifier chip are connected to a 15V DC power supply through a connection resistor, and a corresponding group of positive phase end pins are loaded with a 10V DC power supply; and one negative phase end pin is connected to the U jack of the test interface of the first test board through the first cable and the interface seat CN1, and the other negative phase end pin is connected to the V jack of the test interface of the first test board through the first cable and the interface seat CN1, and the U jack and the V jack of the test interface of the first test board are connected to the U terminal and the V terminal inside the first test board.

[0045] The inputs of the 15V DC power supply and the 10V DC power supply of the operational amplifier chip are provided by a DC-DC power supply module. In the embodiment, the DC-DC power supply module uses a B2415S-2WR2 chip, which is a 24V to 15V single-channel DC-DC power supply module.

[0046] One end of the fourth connecting pin of the connector CN4 is connected to a 24V DC power supply through a counting switch, the other end is connected to the coil of the third relay in series, and then connected to one end of the ninth connecting pin of the connector CN4, the other end of the ninth connecting pin is connected to the port of the counter; the IN pin of the counter is connected to the eighth connecting pin of the connector CN4, the other end of the eighth connecting pin of the connector CN4 is connected to one normally closed contact of the third relay R3 in series, and then connected to the U jack of the test interface of the first test board through the first connecting pin of the interface seat CN1; at the same time, the other end of the eighth connecting pin of the connector CN4 is connected to one normally open contact of the third relay R3 in series, and then connected to the V jack of the test interface of the first test board through the second connecting pin of the interface seat CN1, the normally closed contact and the normally open contact of the third relay R3 are linked contacts; in addition, a group of negative phase pins of the operational amplifier chip connected to a 15V DC power supply are connected to the eighth connecting pin of the connector CN4 after being connected to the normally closed contact and the normally open contact of the third relay R3 in series.

[0047] The E jack of the test interface of the first test board is connected to the 1M pin of the pulse counting module of the CPU chip through the first cable and the interface seat CN1; the D jack of the test interface of the first test board is connected to the voltage output end of the voltage stabilizer chip through the first cable and the interface seat CN1; the C jack of the test interface of the first test board is connected to the first pin of the terminal block through the first cable and the interface seat CN1; the B jack of the test interface of the first test board is connected to the fourth pin of the terminal block through the first cable and the interface seat CN1; the A jack of the test interface of the first test board is connected to the ninth pin of the terminal block through the first cable and the interface seat CN1; the D jack, the C jack, the B jack and the A jack of the test interface of the first test board are connected to the D terminal, the C terminal, the B terminal and the A terminal inside the first test board;

[0048] The output pin Q0.2 of the CPU chip is connected to the ground through the first cable and the interface seat CN1 after being connected to the coil of the eleventh relay R11 and the twelfth relay R12 in parallel, the three normally open contacts of the eleventh relay R11 are arranged on the connection lines of the U, V, E jacks of the test interface of the first test board and the U, V, E terminals inside the first test board, wherein the E jack and the E terminal are grounded; the three normally open contacts of the twelfth relay R12 are arranged on the connection lines of the C, B, A jacks of the test interface of the first test board and the C, B, A terminals inside the first test board; wherein the C jack and the A jack are also connected to the positive and negative poles of a 10V DC power supply.

[0049] The V and R jacks of the test interface of the second test board are connected to the second pin of the terminal block through the second cable and the interface seat CN2; the T jack of the test interface of the second test board is connected to the seventh pin of the terminal block through the second cable and the interface seat CN2; the S and N jacks of the test interface of the second test board are connected to the tenth pin of the terminal block through the second cable and the interface seat CN2; and the P jack of the test interface of the second test board is connected to the fifth pin of the terminal block through the second cable and the interface seat CN2.

[0050] The V, R, S, R, T and N jacks of the test interface of the second test board are connected to the V, R, S, R, T and N terminals inside the second test board; the V and R terminals inside the second test board are connected in series, and the S and N terminals are connected in series; the output pin Q0.3 of the CPU chip is connected to the coil part of the twenty-first relay R21 through the second cable and the interface seat CN2, and the four normally open contacts of the twenty-first relay R21 are arranged on the connection lines of the V, T, P and S jacks of the test interface of the second test board and the V, T, P and S terminals inside the second test board respectively; and the V and N jacks are connected to the positive and negative poles of the 10V DC power supply respectively.

[0051] The F and C jacks of the test interface of the third test board are connected to the third pin of the terminal block through the third cable and the interface seat CN3; the E jack of the test interface of the third test board is connected to the eighth pin of the terminal block through the third cable and the interface seat CN3; the D and A jacks of the test interface of the third test board are connected to the eleventh pin of the terminal block through the third cable and the interface seat CN3; and the B jack of the test interface of the third test board is connected to the sixth pin of the terminal block through the third cable and the interface seat CN3.

[0052] The F, E, D, C, B and A jacks of the test interface of the third test board are connected to the F, E, D, C, B and A terminals inside the third test board; the D and A terminals inside the third test board are connected in series; the output pin Q0.4 of the CPU chip is connected to the coil part of the thirty-first relay R31 through the third cable and the interface seat CN3, and the four normally open contacts of the thirty-first relay R31 are arranged on the connection lines of the F, E, B and D jacks of the test interface of the third test board and the F, E, B and D terminals inside the second test board respectively; and the F and A jacks are connected to the positive and negative poles of the 10V DC power supply respectively.

[0053] The panel switching circuit comprises an initial switching control relay K0 and first to eleventh switching control relays K1-K11. The fifth pin of the connector CN4 is connected in series with the third normally closed contact K3-3 of the third switching control relay K3, the third normally closed contact K6-3 of the sixth switching control relay K6 and the coil of the second switching control relay K2 in turn and grounded. The sixth pin of the connector CN4 is connected in series with the second normally closed contact K3-2 of the third switching control relay K3, the third normally closed contact K9-3 of the ninth switching control relay K9 and the coil of the first switching control relay K1 in turn. The seventh pin of the connector CN4 is connected in series with the second normally closed contact K6-2 of the sixth switching control relay K6, the second normally closed contact K9-2 of the ninth switching control relay K9 and the coil of the initial switching control relay K0 in turn.

[0054] The coils of the third, fourth and fifth switching control relays K3-K5 are connected in parallel and one end of the common connection is connected to the dashboard 24V DC power supply through the normally open contact of the initial switching control relay K0, and the other end of the common connection is connected to the negative terminal of each instrument. For the convenience of monitoring and display, the coils are further connected in parallel with the indicator lamp LAMP2. The coils of the sixth, seventh and eighth switching control relays K6-K8 are connected in parallel and one end of the common connection is connected to the dashboard 24V DC power supply through the normally open contact of the first switching control relay K1, and the other end of the common connection is connected to the negative terminal of each instrument. The coils are further connected in parallel with the indicator lamp LAMP3. The coils of the ninth, tenth and eleventh switching control relays K9-K11 are connected in parallel and one end of the common connection is connected to the dashboard 24V DC power supply through the normally open contact of the second switching control relay K2, and the other end of the common connection is connected to the negative terminal of each instrument. The coils are further connected in parallel with the indicator lamp LAMP4. The positive terminal of each instrument is connected to the dashboard 24V DC power supply.

[0055] In this embodiment, the instrument includes a medium frequency AC voltage meter, a DC voltage meter, a timer, a medium frequency AC current meter, a DC current meter, and a counter. The access terminal I of the medium frequency AC voltage meter is connected to the first terminal of the air actuator of the first test board through the first normally open contact K4-1 of the fourth switching control relay K4, and the access terminal II of the medium frequency AC voltage meter is connected to the second terminal of the air actuator of the first test board through the second normally open contact K4-2 of the fourth switching control relay K4. The access terminal I of the medium frequency AC voltage meter is connected to the first terminal of the air actuator of the second test board through the first normally open contact K7-1 of the seventh switching control relay K7, and the access terminal II of the medium frequency AC voltage meter is connected to the second terminal of the air actuator of the second test board through the second normally open contact K7-2 of the seventh switching control relay K7. The access terminal I of the medium frequency AC voltage meter is connected to the first terminal of the air actuator of the third test board through the first normally open contact K10-1 of the tenth switching control relay K10, and the access terminal II of the medium frequency AC voltage meter is connected to the second terminal of the air actuator of the third test board through the second normally open contact K10-2 of the tenth switching control relay K10.

[0056] The access terminal I of the DC voltage meter is connected to the third terminal of the air actuator of the first test board through the third normally open contact K4-3 of the fourth switching control relay K4, and the access terminal II of the DC voltage meter is connected to the fourth terminal of the air actuator of the first test board through the fourth normally open contact K4-4 of the fourth switching control relay K4. The access terminal I of the DC voltage meter is connected to the third terminal of the air actuator of the second test board through the third normally open contact K7-3 of the seventh switching control relay K7, and the access terminal II of the DC voltage meter is connected to the fourth terminal of the air actuator of the second test board through the fourth normally open contact K7-4 of the seventh switching control relay K7. The access terminal I of the DC voltage meter is connected to the third terminal of the air actuator of the third test board through the third normally open contact K10-3 of the tenth switching control relay K10, and the access terminal II of the DC voltage meter is connected to the fourth terminal of the air actuator of the third test board through the fourth normally open contact K10-4 of the tenth switching control relay K10.

[0057] Wherein the access terminal I of the timer is connected to the fifth terminal of the air actuator of the first test board through the No. 1 normally open contact K5-1 of the fifth switch control relay K5, the access terminal II of the timer is connected to the sixth terminal of the air actuator of the first test board through the No. 2 normally open contact K5-2 of the fifth switch control relay K5; the access terminal I of the timer is connected to the fifth terminal of the air actuator of the second test board through the No. 1 normally open contact K8-1 of the eighth switch control relay K8, the access terminal II of the direct current voltmeter is connected to the sixth terminal of the air actuator of the second test board through the No. 2 normally open contact K8-2 of the eighth switch control relay K8; the access terminal I of the timer is connected to the fifth terminal of the air actuator of the third test board through the No. 1 normally open contact K11-1 of the eleventh switch control relay K11, the access terminal II of the timer is connected to the sixth terminal of the air actuator of the third test board through the No. 2 normally open contact K11-2 of the eleventh switch control relay K11.

[0058] Wherein the access terminal I of the intermediate frequency alternating current ammeter is connected to the seventh terminal of the air actuator of the first test board through the No. 1 normally open contact KM2-1 of the second alternating current relay KM2, the access terminal II of the intermediate frequency alternating current ammeter is connected to the eighth terminal of the air actuator of the first test board through the No. 2 normally open contact KM2-2 of the second alternating current relay KM2; the access terminal I of the intermediate frequency alternating current ammeter is connected to the seventh terminal of the air actuator of the second test board through the No. 1 normally open contact KM3-1 of the third alternating current relay KM3, the access terminal II of the intermediate frequency alternating current ammeter is connected to the eighth terminal of the air actuator of the second test board through the No. 2 normally open contact KM3-2 of the third alternating current relay KM3; the access terminal I of the intermediate frequency alternating current ammeter is connected to the seventh terminal of the air actuator of the third test board through the No. 1 normally open contact KM4-1 of the fourth alternating current relay KM4, the access terminal II of the intermediate frequency alternating current ammeter is connected to the eighth terminal of the air actuator of the third test board through the No. 2 normally open contact KM4-2 of the fourth alternating current relay KM4.

[0059] Wherein the access terminal I of the direct current ammeter is connected to the ninth terminal of the air actuator of the first test board through the third normally open contact K5-3 of the fifth switching control relay K5, and the access terminal II of the direct current ammeter is connected to the tenth terminal of the air actuator of the first test board through the fourth normally open contact K5-4 of the fifth switching control relay K5; the access terminal I of the direct current ammeter is connected to the ninth terminal of the air actuator of the second test board through the third normally open contact K8-3 of the eighth switching control relay K8, and the access terminal II of the direct current ammeter is connected to the tenth terminal of the air actuator of the second test board through the fourth normally open contact K8-4 of the eighth switching control relay K8; the access terminal I of the direct current ammeter is connected to the ninth terminal of the air actuator of the third test board through the third normally open contact K11-3 of the eleventh switching control relay K11, and the access terminal II of the direct current ammeter is connected to the tenth terminal of the air actuator of the third test board through the fourth normally open contact K11-4 of the eleventh switching control relay K11.

[0060] The COM pin of the counter is connected to the negative terminal of the intermediate frequency AC voltage meter, the direct current voltage meter, the timer, the intermediate frequency AC current meter and the direct current ammeter respectively, the IN pin of the counter is connected to the eighth pin of the connector CN4, the RST pin of the counter is connected to the reset button, the + pin of the counter is connected to 220 VL, and the - pin of the counter is connected to 220 V N. Three groups of relay coils are connected in parallel between the + pin and the - pin of the counter. The first group is the series combination of the coil of the second AC relay KM2 and the fourth normally open contact K3-4 of the third switching control relay K3, the second group is the series combination of the coil of the third AC relay KM3 and the fourth normally open contact K6-4 of the sixth switching control relay K6, and the third group is the series combination of the coil of the fourth AC relay KM4 and the fourth normally open contact K9-4 of the ninth switching control relay K9. Through the energization control of the coils, the control of the intermediate frequency AC current meter is realized.

[0061] As shown in Figure 2 and Figure 3 In the embodiment, the first test board is the 1809A inlet air channel ram air actuator test board (i.e. the JP2 panel 1 signal interface in Figure 2 is formed), the second test board is the 975A inlet air channel ram air actuator test board (i.e. the JP3 panel 2 signal interface in Figure 2 is formed), and the third test board is the 761A inlet and outlet air channel ram air actuator test board (i.e. the JP3 panel 3 signal interface in Figure 2 is formed). Of course, in actual application, the test items and test sequence of each test board can also be adjusted according to actual needs.

[0062] As shown in Figure 4As shown, this invention is integrated into an industrial control cabinet as an important part of a testing platform. The cabinet includes: a common instrument area, control buttons / switches, test modules, a power supply for the control cabinet, drawer trays, and a voltage regulator. The common instrument area is located at the top of the control cabinet, with a metering port (for online verification) next to the instruments. An internal / external switch button on the right side of the displacement instrument is used to switch between external instruments and the device's own instruments. When the button is released, the status indicator light is off, allowing data to be detected using the device's touchscreen and counter; when the button is pressed, the light illuminates, allowing the connection of an oscilloscope, recorder, or other equipment to the panel terminals for testing. Three test modules are located in the middle of the control cabinet, each designed for a specific part number series of linear actuators.

[0063] Test Section 1 / 2 / 3 Buttons: These three buttons are used to switch between the three test sections; pressing one button will disable the other buttons.

[0064] Example of switching test sections (this example is the first test section):

[0065] 1. Principle

[0066] Instrument switching panel (black border), PLC panel (red border).

[0067] a. Switching between medium-frequency AC voltmeter, DC voltmeter, timer, and DC ammeter

[0068] like Figure 5 As shown, the execution sequence is as follows: Panel1 switch is turned on → a switching signal is connected to the PLC board via CN4-1 → the switching signal is input to the PLC board CPU input port I0.3 → the switching signal is output to the instrument switching board CN4-7 via the PLC board CPU output port Q0.5, and the output port Q0.2 controls the external test port of the first test board → the switching signal is output through CN4-7 and connected to the NC contact K6-2 of relay K6 in the switching control relay combination (including K3, K6, K9) → NC contact K6-2 → CO M contact K6-10 → NC contact K9-2 of electrical appliance K9 → NC contact K9-2 of K9 → COM contact K9-10 → coil of electrical appliance K3 K3-14 → switching relay group (K3, K4, K5) coil of the first test section is energized*[1] → NO contacts of K3, K4, K5 are energized, connecting the intermediate frequency AC voltmeter, DC voltmeter, timer, DC ammeter → due to the energization of contacts K3-12 and K3-8, coils A1 and A2 of KM2 are energized, KM2 contacts are energized, connecting the intermediate frequency AC ammeter.

[0069] *[1]: At this time, due to the mutual control among the switching control relay combination (including K3, K6, K9), only the switching relay group (K3, K4, K5) of the first test board has the coil K0 energized, and only the terminal JP2 of the first test board is connected to the instrument.

[0070] b. Counter switching

[0071] As shown in Figure 6 and Figure 7 , the overall operation logic is as follows:

[0072] If the counting switch is not turned on, the relay R3 coil is not energized, and the counting pulse is from CN1-1 to NC contact R3-1 to COM contact R3-5 to CN4-8 to the counter IN.

[0073] If the counting switch is turned on, the switching signal is connected to the PLC board through CN4-4, the relay R3 coil is energized and attracted, and the counting pulse is from CN1-2 to NO contact R3-3 to COM contact R3-5 to CN4-8 to the counter IN.

[0074] In addition, regardless of whether the counting switch is turned on or not, the CPU output port Q0.0 of the PLC board outputs the activation relay R1, and the CN1-1 / 2 counting pulse can be input to the CPU input port I0.0, I0.2 through the operational amplifier LM324.

[0075] c. Displacement switching (only when the internal displacement analog quantity of the measured actuator needs to be retrieved)

[0076] As shown in Figure 8 , the operation logic is as follows:

[0077] The CPU output port Q0.1 of the PLC board outputs the activation relay R2, the COM contact of the relay R2 contacts the NO contact, the displacement analog quantity of the measured actuator, CN1-12 / 8 / 11, NO contact R2-5 / 6 / 7, COM contact R2-9 / 1011, and the analog quantity input module EM AE08 input end.

[0078] The following interface definitions are the correspondence between the test module terminals JP2 / 3 / 4 and the switching module relay contacts, the instrument interface JP1-10, and the instrument terminals. More actuator test modules can be developed based on this correspondence.

[0079]

[0080]

[0081] Finally, it is to be explained that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the purpose and scope of the technical solutions, and all should be covered in the scope of the claims of the present application.

Claims

1. A test meter switching circuit, characterized by: The circuit comprises a PLC board, an instrument switching board, a first test board, a second test board and a third test board; The PLC board comprises a CPU chip, an operational amplifier chip and an analog input chip, the CPU chip is connected to the instrument switching board through input pins and output pins to realize switching of instruments; The CPU chip is connected to the operational amplifier chip to realize pulse counting, and the analog input chip is connected to the first test board, the second test board and the third test board to realize detection of a to-be-detected device connected to each test board under the control of the CPU chip; The output pin Q0.1 of the CPU chip is connected to the coil of a relay R2, the relay R2 is a double-changeover contact relay, the 0+ pin of the analog input chip is connected to the moving contact of a first group of double-changeover contacts of the relay R2, the normally open static contact of the first group of double-changeover contacts is connected to the fourth pin of a terminal block, the 1+ pin of the analog input chip is connected to the moving contact of a second group of double-changeover contacts of the relay R2, the normally open static contact of the second group of double-changeover contacts is connected to the first pin of the terminal block, the 2+ pin of the analog input chip is connected to the moving contact of a third group of double-changeover contacts of the relay R2, the normally open static contact of the third group of double-changeover contacts is connected to the seventh pin of the terminal block, the 2- pin of the analog input chip is connected to the moving contact of a fourth group of normally open contacts of the relay R2, the static contacts of the four groups of normally open contacts are connected to the ninth pin of the terminal block, the normally closed static contacts of the first to third groups of double-changeover contacts of the relay R2 are grounded, the first to third pins of the terminal block are connected in parallel through jumpers, the fourth to sixth pins of the terminal block are connected in parallel through jumpers, the seventh to eighth pins of the terminal block are connected in parallel through jumpers, and the ninth to eleventh pins of the terminal block are connected in parallel through jumpers; The 0-, 1-, 2- and M pins of the analog input chip are grounded, and a group of analog input pins of the analog input chip are connected to a displacement sensor.

2. A test meter switching circuit according to claim 1, characterized in that: The output pins Q0.5-Q0.7 and the input pins I0.3-I0.5 of the CPU chip are connected to the instrument switching board through the pins of an interface seat CN4, wherein the input pins I0.3-I0.5 of the CPU chip are connected to a 24V DC power supply of an instrument board through the first to third pins of the interface seat CN4 and then connected to the instrument board through switches panel1, panel2 and panel3 respectively, and the output pins Q0.5-Q0.7 of the CPU chip are connected to a panel switching circuit through the fifth to seventh pins of the interface seat CN4; The input pins I0.0 and I0.1 of the CPU chip are connected to two output pins of the operational amplifier chip, and the output pin Q0.0 of the CPU chip is connected to the coil of a relay R1, and two groups of normally open contacts of the relay R1 are arranged on the connection lines of the input pins I0.0 and I0.1 of the CPU chip and the two output pins of the operational amplifier chip. The output pin Q0.2 of the CPU chip is connected to the first test board through the first cable and the interface seat CN1; the output pin Q0.3 of the CPU chip is connected to the second test board through the second cable and the interface seat CN2; the output pin Q0.4 of the CPU chip is connected to the third test board through the third cable and the interface seat CN3.

3. The test meter switching circuit of claim 1, wherein: A group of negative phase terminal pins of the operational amplifier chip are connected to the 15V DC power supply through a connecting resistor, and a corresponding group of positive phase terminal pins are loaded with the 10V DC power supply; and one negative phase terminal pin is connected to the U jack of the test interface of the first test board through the first cable and the interface seat CN1, and the other negative phase terminal pin is connected to the V jack of the test interface of the first test board through the first cable and the interface seat CN1, and the U jack and the V jack of the test interface of the first test board are connected with the U terminal and the V terminal inside the first test board.

4. A test meter switching circuit according to claim 3, wherein: The input of the 15V DC power supply and the 10V DC power supply of the operational amplifier chip is provided by the DC-DC power supply module.

5. A test meter switching circuit according to claim 3, wherein: The E jack of the test interface of the first test board is connected to the 1M pin of the pulse counting module of the CPU chip through the first cable and the interface seat CN1; the D jack of the test interface of the first test board is connected to the voltage output terminal of the voltage stabilizer chip through the first cable and the interface seat CN1; the C jack of the test interface of the first test board is connected to the first pin of the terminal row through the first cable and the interface seat CN1; the B jack of the test interface of the first test board is connected to the fourth pin of the terminal row through the first cable and the interface seat CN1; the A jack of the test interface of the first test board is connected to the ninth pin of the terminal row through the first cable and the interface seat CN1; the D jack, the C jack, the B jack and the A jack of the test interface of the first test board are connected with the D terminal, the C terminal, the B terminal and the A terminal inside the first test board. The output pin Q0.2 of the CPU chip is connected to the ground through the first cable and the interface seat CN1 after being connected with the coil part of the parallel eleventh relay R11 and the twelfth relay R12; the three normally open contacts of the eleventh relay R11 are arranged on the connection lines of the U, V and E jacks of the test interface of the first test board and the U, V and E terminals inside the first test board, and the E jack and the E terminal are grounded; the three normally open contacts of the twelfth relay R12 are arranged on the connection lines of the C, B and A jacks of the test interface of the first test board and the C, B and A terminals inside the first test board; and the C jack and the A jack are also connected to the positive and negative poles of the 10V DC power supply, respectively.

6. A test meter switching circuit according to claim 5, wherein: The V and R jacks of the test interface of the second test block are connected to the second pin of the terminal block through the second cable and the interface seat CN2; the T jack of the test interface of the second test block is connected to the seventh pin of the terminal block through the second cable and the interface seat CN2; the S and N jacks of the test interface of the second test block are connected to the tenth pin of the terminal block through the second cable and the interface seat CN2; the P jack of the test interface of the second test block is connected to the fifth pin of the terminal block through the second cable and the interface seat CN2; The V, R, S, R, T and N jacks of the test interface of the second test block are connected to the V, R, S, R, T and N terminals inside the second test block; the V and R terminals inside the second test block are connected in series, and the S and N terminals are connected in series; the output pin Q0.3 of the CPU chip is connected to the coil part of the twenty-first relay R21 through the second cable and the interface seat CN2, and the four normally open contacts of the twenty-first relay R21 are arranged on the connection lines of the V, T, P and S jacks of the test interface of the second test block and the V, T, P and S terminals inside the second test block respectively; wherein the V and N jacks are connected to the positive and negative poles of the 10V DC power supply respectively.

7. A test meter switching circuit according to claim 6, wherein: The F and C jacks of the test interface of the third test block are connected to the third pin of the terminal block through the third cable and the interface seat CN3; the E jack of the test interface of the third test block is connected to the eighth pin of the terminal block through the third cable and the interface seat CN3; the D and A jacks of the test interface of the third test block are connected to the eleventh pin of the terminal block through the third cable and the interface seat CN3; the B jack of the test interface of the third test block is connected to the sixth pin of the terminal block through the third cable and the interface seat CN3; The F, E, D, C, B and A jacks of the test interface of the third test block are connected to the F, E, D, C, B and A terminals inside the third test block; the D and A terminals inside the third test block are connected in series; the output pin Q0.4 of the CPU chip is connected to the coil part of the thirty-first relay R31 through the third cable and the interface seat CN3, and the four normally open contacts of the thirty-first relay R31 are arranged on the connection lines of the F, E, B and D jacks of the test interface of the third test block and the F, E, B and D terminals inside the second test block respectively; wherein the F and A jacks are connected to the positive and negative poles of the 10V DC power supply respectively.

8. The test meter switching circuit of claim 2, wherein: The panel switching circuit comprises an initial switching control relay K0 and first to eleventh switching control relays K1-K11. The fifth pin of the interface seat CN4 is connected in series with the third normally closed contact K3-3 of the third switching control relay K3, the third normally closed contact K6-3 of the sixth switching control relay K6 and the coil of the second switching control relay K2 in turn and grounded. The sixth pin of the interface seat CN4 is connected in series with the second normally closed contact K3-2 of the third switching control relay K3, the third normally closed contact K9-3 of the ninth switching control relay K9 and the coil of the first switching control relay K1 in turn and grounded. The seventh pin of the interface seat CN4 is connected in series with the second normally closed contact K6-2 of the sixth switching control relay K6, the second normally closed contact K9-2 of the ninth switching control relay K9 and the coil of the initial switching control relay K0 in turn and grounded. The coil of the third switching control relay K3, the coil of the fourth switching control relay K4 and the coil of the fifth switching control relay K5 are connected in parallel and one end of the common connection point is connected to the dashboard 24V DC power supply through the normally open contact of the initial switching control relay K0, and the other end of the common connection point is connected to the negative terminal of each instrument. The coil of the sixth switching control relay K6, the coil of the seventh switching control relay K7 and the coil of the eighth switching control relay K8 are connected in parallel and one end of the common connection point is connected to the dashboard 24V DC power supply through the normally open contact of the first switching control relay K1, and the other end of the common connection point is connected to the negative terminal of each instrument. The coil of the ninth switching control relay K9, the coil of the tenth switching control relay K10 and the coil of the eleventh switching control relay K11 are connected in parallel and one end of the common connection point is connected to the dashboard 24V DC power supply through the normally open contact of the second switching control relay K2, and the other end of the common connection point is connected to the negative terminal of each instrument. The positive terminal of each instrument is connected to the dashboard 24V DC power supply.

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