A high-speed high-frequency beam-loss diagnostic method and system

Abstract

The application discloses a high-speed high-frequency beam loss diagnostic method and system. The application mainly develops and realizes algorithms based on a low-level digital signal processing board card, the board card collects high-frequency incident power, reflected power, cavity field power and beam signals in real time, and stores the collected signals into a DDR3 memory in real time, when interlocking failure occurs, a pulse count of a set time length is triggered, and when the counting is completed, the storage of high-frequency beam loss diagnostic signal data is stopped; an embedded system of the digital signal processing board card monitors the state of a specified register of the DDR3 in real time, when the high-frequency beam loss signal is monitored, high-frequency beam loss diagnostic data is obtained from the DDR3 and packaged, a data analysis system processes the packaged data information and draws a beam loss waveform, through analyzing the waveform characteristics of a certain time period before and after the fault beam loss time, the fault reason of the high-frequency beam loss is diagnosed, and the diagnostic efficiency is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of accelerators, and particularly relates to a high-speed high-frequency beam-loss diagnostic method and system, which is used for fault diagnosis of a high-frequency system in an accelerator device and can be widely applied in the fields of high-frequency signal data acquisition and waveform analysis. BACKGROUND

[0002] In an accelerator device, high-frequency system faults are the most common and main fault types, and are a key factor affecting the reliability of the accelerator. According to statistics, in two representative high-performance superconducting accelerators, BEPCII storage ring and Shanghai synchrotron radiation storage ring, superconducting high-frequency cavity faults are one of the main reasons for accelerator faults.

[0003] A high-frequency safety interlock system has the function of displaying high-frequency fault states, but it can only display fault results and cannot determine the causes of the faults; a high-frequency database system records main state parameters of high frequencies in real time, which provides strong guarantee for high-frequency fault analysis, but at the same time, since the fastest acquisition frequency of the database system is 10 Hz, it belongs to a slow signal acquisition system, and main signals of the high-frequency system, including amplitudes and phases of cavity field signals, amplitudes and phases of forward power and reflected power, beam signals, and internal signals of low-level control systems, all belong to high-speed signals, and usually, signal acquisition needs to be performed at a sampling rate of 100 kHz or more, and waveforms in a period of time before and after a fault moment are analyzed, and according to waveform curve characteristics, the real causes of high-frequency faults can be accurately determined, and then, the fault source can be quickly locked, the fault can be accurately and quickly solved, the high-frequency system can be quickly recovered, and the accelerator fault time can be reduced. Therefore, a high-speed high-frequency fault system is crucial for analyzing high-frequency faults.

[0004] The current high-frequency beam-loss diagnostic system of Beijing Electron-Positron Collider (BEPCII) uses a Yokogawa DL750 oscilloscope. The instrument includes 16 channels, with a maximum sampling rate of 10 MS / s, and can achieve a maximum of 1 GB of instantaneous data storage. The oscilloscope can automatically print captured data, issue an alarm, and save data when a fault condition is detected. The Yokogawa DL750 oscilloscope is a standard commercial product with high sampling rate, large storage capacity, and stable operation, but also has the following disadvantages: first, the high-frequency beam-loss diagnostic system mainly analyzes RF high-frequency signals, while the input channel of the DL750 oscilloscope can only be a direct current (DC) voltage signal, so an appropriate RF signal detector and phase discriminator are needed before the oscilloscope input to convert the amplitude and phase of the RF signal into a DC signal, increasing the complexity of the device; second, the DL750 oscilloscope can automatically save fault waveforms when a fault condition is detected, but it cannot send data to a low-level database server, and manual data extraction is required for data analysis, which is not convenient for data processing and analysis, and also not convenient for sharing with other systems for data sharing and analysis; finally, the DL750 oscilloscope is relatively expensive, and the cost will be higher if the detector and phase discriminator are included. SUMMARY

[0005] In view of the importance of high-speed high-frequency beam-loss fault diagnosis and the shortcomings of the existing BEPCII high-frequency beam-loss diagnostic system, the purpose of the present application is to provide a high-speed high-frequency beam-loss diagnostic method and system. The present application is based on a low-level digital signal processing board for algorithm development and implementation. The board real-time collects high-frequency incident power Pf, reflected power Pr, cavity field power Pt', and beam signals, and stores the collected signals in a DDR3 memory in real time. When an interlock fault occurs, a pulse count of a set duration is triggered, and when the counting is complete, the storage of high-frequency beam-loss diagnostic related signal data is stopped. The embedded system of the digital signal processing board runs a data acquisition program to monitor the state of the DDR3 specified address register in real time. When a high-frequency beam-loss signal is detected, the high-frequency beam-loss diagnostic data is obtained from the DDR3 and packaged for data file storage. The database system reads the data storage file and processes the packaged data information to draw the beam-loss waveform. By analyzing the waveform characteristics of a certain time period before and after the fault beam-loss time, the cause of the high-frequency beam-loss fault is diagnosed.

[0006] The technical solution of the present application is:

[0007] A high-speed high-frequency beam-loss diagnostic method, the steps of which include:

[0008] 1. Acquisition of beam loss diagnostic data signal: The main signals collected by the high-frequency beam loss fault diagnosis system include high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt, and beam current signal Pb. These RF high-frequency signals are first down-converted by the RF front-end board to obtain corresponding intermediate-frequency signals, which are then sent to the ADC acquisition board for analog-to-digital conversion to obtain corresponding digital signals. The ADC acquisition board is connected to the digital signal processing board through a bridge interface, and the collected digital signals are then sent to the FPGA of the digital signal processing board for data acquisition and processing. The digital intermediate-frequency signals obtained by ADC data acquisition are converted to the I / Q domain of the corresponding signals by the Non-IQ sampling method.

[0009] 2. Beam loss diagnostic data packaging module: The I / Q quadrature signals of the real-time and fast-acquired high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt, and beam current signal Pb are packaged into data packet signals trip_data_in, which are then sent to the external DDR3 through the axi4-full-master module in burst mode for data storage. The data bit number of the collected signal is 32 bits, and when the 4-channel signal described in the foregoing is collected, the data packet signal trip_data_in is a 16 Byte signal.

[0010] 3. Beam loss diagnostic data parameter processing module: The setting parameters of beam loss diagnostic include beam loss diagnostic clock frequency selection signal clk_sel, beam loss diagnostic data storage depth signal Length_trip, beam loss diagnostic waveform trigger position signal Ratio_trip, etc. The clock input signal of beam loss diagnostic is clk_trigger, and the internal clock selection module can flexibly output beam loss diagnostic acquisition clock signals clk_trip with multiple frequency sizes according to the setting value clk_sel, so as to meet the different setting requirements of the sampling rate of beam loss diagnostic storage data. The beam loss diagnostic data storage depth signal Length_trip represents the number of data packet signals trip_data_in stored at each beam loss trigger, which is used to calculate the storage address space size Length_trip_addr of the beam loss waveform stored by DDR3 and the total time length T_trip of the beam loss waveform, etc. For example, if the frequency of clk_trip is 1 MHz, i.e. the period is 1 us, and the setting Length_trip length is 2^16, then Length_trip_addr = 2^16*16 = 1 MB, and the waveform time length T_trip = 2^16*1 us = 65.536 ms. The beam loss diagnostic waveform trigger position signal Ratio_trip represents the proportion value of the time length of the time period before the beam loss trigger time to the entire beam loss diagnostic storage waveform curve time length. The product of Length_trip minus Ratio_trip and Length_trip is the beam loss trigger delay pulse number Count_trip_delay, which will be used as the trigger delay number in the subsequent beam loss trigger enable signal generation module to obtain the trigger enable signal trip_enable.

[0011] 4. The module of the enable signal of the beam trip trigger: the input signals of the module include the manual trigger signal of the beam trip manual_trip and the cavity field power signal Pt. The high frequency beam trip diagnostic method has two trigger modes, which are manual mode and automatic mode. The manual trigger signal of the beam trip manual_trip is usually a high level signal, which is manually controlled by the upper OPI. When it is set from high level to low level, the manual trigger mode of the high frequency beam trip diagnostic method will be triggered, and the waveforms of the signals collected by the high frequency beam trip diagnostic system in the time period before and after the manual trigger moment are stored. In the automatic mode, the beam trip diagnostic system needs to set the manual_trip signal to high level to work normally. When the amplitude of the cavity field power signal Pt is less than 70% of the theoretical value of Pt power (this is a typical value, which can usually be set in the interval of 60%-80%), the beam trip trigger signal auto_en0 will be set to low level. The logical and of the two signals of manual_trip and auto_en0 gets the enable signal of the beam trip auto_en1, and then the auto_en1 is delayed by the pulse number of Count_trip_delay to get the beam trip trigger enable signal trip_enable.

[0012] 5. The module of the burst clock signal of the beam trip diagnostic: the input signals of the module include the acquisition clock signal of the beam trip diagnostic clk_trip and the beam trip trigger enable signal trip_enable. The logical and of clk_trip signal and trip_enable gets the clk_axi_txn signal, which is used as the burst clock of the subsequent axi4_full_master bus module. When trip_enable is high level, the clk_axi_txn signal is the clk_trip pulse signal, which continuously bursts the data packets to the axi4_full_master bus module; when trip_enable is low level, the clk_axi_txn signal is also low level, which stops the burst transmission of data packets to the axi4_full_master bus module.

[0013] 6. The beam loss diagnostic wheel cycle address generation module: the beam loss diagnostic data storage depth signal Length_trip and the burst clock signal clk_axi_txn of the axi4_full_master bus module are input signals of the module. When the clk_axi_txn signal has a pulse rising edge, the beam loss wheel cycle address axi_awaddr is added once. The addition step depends on the size of the data packet signal trip_data_in of the beam loss diagnostic system, which is 16 bytes for a 4-way signal. Length_trip determines the bit width of the beam loss wheel cycle address axi_awaddr. When the beam loss wheel cycle address axi_awaddr is added to 16*Length_trip, it will automatically overflow to 0 address. After receiving a pulse, it will start to add from 0 address again. When trip_enable is low, the burst clock clk_axi_txn signal will also be low, and at this time the wheel cycle address axi_awaddr will stop adding.

[0014] 7. Data burst transmission of the axi4-full-master module: The data packet signal trip_data_in of the beam loss diagnostic system is a register reg type signal belonging to the programmable logic (PL) part of the FPGA. This data packet signal needs to be continuously stored in the DDR3 memory address segment of the processing system (PS) end of the FPGA. The data communication between the PL part and the PS part of the FPGA is realized by the data interaction of the axi4_full_master bus module, and the PL part completes the logic algorithm function of the beam loss diagnostic. The axi4_full_master bus module uses the axi4-full bus as the master end and adopts the burst mode to write the packaged data packet signal trip_data_in into the corresponding address m_axi_awaddr of the storage space of the axi4_full_master bus module in the DDR3 memory after receiving a pulse of clk_axi_txn. The DDR3 memory allocates a maximum of 1GB of storage interval for the axi4_full_master bus module. It is particularly pointed out that the 1 burst data packet space with a size of 16 bytes at the starting address of this storage interval stores not the data packet signal trip_data_in, but the special packaged data composed of the beam loss trigger enable signal trip_enable, the beam loss wheel cycle address axi_awaddr and the beam current cycle count signal when trip_enable is low, and the data packet signal trip_data_in is normally stored in other address space.

[0015] 8. The beam loss diagnostic system automatically stores the data packet at the beam loss time: an automatic data packet acquisition algorithm is run in the embedded system running on the digital signal processing board card, which acquires the data packet stored in the 16 Byte space starting from the first address of the beam loss diagnostic data packet storage interval in the DDR3 in real time, parses the beam loss trigger enable signal trip_enable and the beam loss time beam loss round-robin address axi_awaddr. When the monitoring of the beam loss trigger enable signal trip_enable is low, it indicates that a high-frequency fault has just occurred, at this time the data stored in the storage interval corresponding to the beam loss diagnostic data packet in the DDR3 is the waveform data of the sampled signal in the set time period before and after the beam loss time. Then create a data packet file, start reading the data packet from the corresponding storage space of the DDR3 and store it in the newly created file. The reading of the data packet starts from m_axi_awaddr+16, when the maximum address of the corresponding interval of the DDR3 is read, jump to the offset address 16 to continue reading the data packet until the axi_awaddr address is read, this address stores the data value at the last time of the beam loss waveform. After the data reading is completed, wait for the next trip_enable signal to be low, repeat the previous action. The newly created data packet file is transmitted to the database system specified beam loss diagnostic directory through the network.

[0016] 9. The database system data packet analysis module: the database system monitors the data packet file under the beam loss diagnostic directory in real time, when a new data packet file is found, according to the packaging method of the data packet, the data is unpacked, the stored forward power signal Pf, reflected power signal Pr, cavity field power signal Pt and beam current signal Pb are parsed; and the parsed data is plotted, according to the performance characteristics of the plotted curve, the analysis of the high-frequency beam loss reason can be carried out.

[0017] Further, the high-frequency signals to be collected by the beam loss diagnostic method can be increased or reduced.

[0018] Further, the maximum sampling rate of the beam loss diagnostic method is 1MHz.

[0019] Further, the automatic storage method of the beam loss diagnostic system data packet at the beam loss time is realized by using the bash script under the linux system.

[0020] Further, the database system data packet analysis method is realized by using the python programming language.

[0021] The application discloses a high-speed high-frequency beam loss diagnostic system, which comprises a beam loss diagnostic data packaging module, a beam loss diagnostic data parameter processing module, a beam loss trigger enabling signal generating module, a clock selecting module, a beam loss diagnostic burst clock signal generating module, a beam loss diagnostic round address generating module, an axi4-full-master module, an automatic storage module and an analysis module.

[0022] The beam loss diagnostic data packaging module is used for collecting the I / Q domain quadrature quantities of the high-frequency cavity incident power Pf, the reflected power Pr, the cavity field power Pt and the beam current signal Pb of the high-frequency system in real time, and generating a data packet signal trip_data_in through data packaging.

[0023] The beam loss diagnostic data parameter processing module is used for setting a beam loss diagnostic clock frequency selection signal clk_sel, a beam loss diagnostic data storage depth signal Length_trip, a beam loss diagnostic waveform trigger position signal Ratio_trip and a beam loss diagnostic clock input signal clk_trigger, and calculating a beam loss trigger delay pulse number Count_trip_delay=Length_trip-Ratio_trip*Length_trip.

[0024] The clock selecting module is used for outputting a beam loss diagnostic acquisition clock signal clk_trip according to the beam loss diagnostic clock frequency selection signal clk_sel, so as to meet different setting requirements of the beam loss diagnostic storage data sampling rate.

[0025] The beam loss trigger enabling signal generating module is used for storing the acquisition signal waveform in a certain time period before and after the current time when a beam loss manual trigger signal manual_trip is received, setting the beam loss enabling signal auto_en0 to a low level if the amplitude of the cavity field power Pt at the current time is less than a Pt power theoretical value, performing a logical AND operation on the manual_trip and the auto_en0 to obtain a beam loss enabling signal auto_en1, delaying the beam loss enabling signal auto_en1 by a pulse number of Count_trip_delay to obtain a beam loss trigger enabling signal trip_enable, and the beam loss manual trigger signal manual_trip being a high-level signal.

[0026] The beam loss diagnosis burst clock signal generation module is configured to obtain a beam loss diagnosis collection clock signal clk_trip from the clock selection module through an input clock signal clk_trigger of the beam loss diagnosis, and then store data packets at the frequency of the beam loss diagnosis collection clock signal clk_trip; obtain a clk_axi_txn signal through logical AND operation between the beam loss diagnosis collection clock signal clk_trip and a beam loss trigger enable signal trip_enable, and use the clk_axi_txn signal as a burst clock of an axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a high level, the clk_axi_txn signal is a clk_trip pulse signal, and the data packets are continuously burst transmitted to the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a low level, it indicates that a high-frequency fault occurs, the clk_axi_txn signal is at a low level, and the burst transmission of the data packets to the axi4_full_master bus module is stopped;

[0027] The beam loss diagnosis round-robin address generation module is configured to accumulate the beam loss round-robin address axi_awaddr once when there is a pulse rising edge of the clk_axi_txn signal; when the beam loss trigger enable signal trip_enable is at a low level, the burst clock clk_axi_txn signal becomes at a low level, and the round-robin address axi_awaddr stops accumulation; when the beam loss round-robin address axi_awaddr is accumulated to a plurality of Length_trip and automatically overflows to 0 address, the accumulation is restarted from the 0 address.

[0028] The axi4-full-master module is configured to burst write the data packet signal trip_data_in into a storage space corresponding address m_axi_awaddr of the axi4_full_master bus module in the DDR3 memory after receiving the clk_axi_txn signal.

[0029] The automatic storage is configured to create a data packet file when it is monitored that the beam loss trigger enable signal trip_enable is at a low level; then read the data packet signal trip_data_in from the corresponding storage space of the DDR3 and store the data packet signal trip_data_in into the created data packet file; after the data reading is completed, wait for the next beam loss trigger enable signal trip_enable to be at a low level, and transmit the created data packet file to a beam loss diagnosis directory of a database system through a network.

[0030] The analysis module is used for monitoring the data packet files under the beam loss diagnosis directory in real time, and when a new data packet file is found, the data is unpacked according to the packing mode of the data packet, the stored forward power signal Pf, the reflected power signal Pr, the cavity field power signal Pt and the beam signal Pb are analyzed, and the analyzed data are plotted.

[0031] Compared with the prior art, the application has the following advantages:

[0032] 1) Compared with the independent device characteristics of the oscilloscope recorder, the beam loss diagnosis data can be packed online, and data interaction and data analysis between multiple systems can be realized.

[0033] 2) Compared with the oscilloscope recorder which can only perform local function adjustment, the beam loss diagnosis method can realize remote online parameter adjustment and function control.

[0034] 3) The hardware architecture is simple, and the beam loss diagnosis function can be realized by using a hardware architecture similar to a high-frequency low-level control system, or even the beam loss diagnosis function can be integrated into a low-level control system.

[0035] 4) The beam loss diagnosis method is based on a self-developed digital signal processing board card to realize the function, which not only improves the diagnosis efficiency, but also greatly reduces the equipment cost. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a hardware framework diagram of the high-frequency beam loss diagnosis system.

[0037] Figure 2 It is a schematic diagram of the technical scheme of the high-frequency beam loss diagnosis system.

[0038] Figure 3 It is a functional logic algorithm block diagram of the high-frequency beam loss diagnosis system.

[0039] Figure 4 It is a timing diagram of the burst clock and other signals of the high-frequency beam loss diagnosis system. DETAILED DESCRIPTION

[0040] The application will be further described in detail below with reference to the drawings, and the examples are only used to explain the application and not to limit the scope of the application.

[0041] 1, top-level design

[0042] The forward power signal Pf, the reflected power signal Pr, the cavity field power signal Pt and the beam current signal Pb collected by the high-speed high-frequency beam loss diagnostic method are all RF high-frequency signals. The signal collection first needs to be down-converted by a radio frequency front-end board to obtain an intermediate frequency IF signal, and then the intermediate frequency IF signal is converted to a digital signal through an ADC collection board. The ADC collection board is connected to a digital signal processing board through an FMC bridge interface. The digital signal processing board uses a Non-IQ algorithm to obtain the I / Q discrete data value of the sampling signal, and then stores the data packet of the power signal at the beam loss time through the beam loss diagnostic function algorithm. The embedded linux system running on the digital signal processing board acquires the data packet stored in the DDR3 memory and stores a file. The stored data file is sent to a database system, the database system unpacks the data file, parses the stored collection signal, and draws a curve waveform. According to the characteristics of the curve waveform, the cause of the beam loss can be diagnosed.

[0043] The hardware framework diagram of the high-speed high-frequency beam loss diagnostic system is shown in Figure 1 The system hardware mainly includes a digital signal processing board, an ADC collection board, a radio frequency front-end board, a beam loss diagnostic system case, a database system and the like. The radio frequency front-end board completes the function of down-converting the RF signal to an IF intermediate frequency signal, and divides the RF reference signal to one way to the digital signal processing board, which is used to generate the clock signal inside the board and the ADC sampling clock signal. The ADC collection board completes the conversion of the intermediate frequency IF analog signal to a digital signal. The digital signal processing board completes the collection of the digital signal and the beam loss diagnostic algorithm function. The clock distribution unit generates the clock signal required by the digital signal processing according to the RF reference signal, the ADC sampling clock signal and the like. The beam loss diagnostic control case provides the power supply for the board and the interface with external equipment. The database system completes the analysis of the data packet at the beam loss time, data processing and analysis, and drawing of the signal waveform at the beam loss time.

[0044] 2. Hardware design

[0045] Altium designer is used to design the circuit schematic diagram and draw the PCB. The involved boards include the digital signal processing board, the ADC collection board, the radio frequency front-end board and the like. The FPGA of the digital signal processing board uses the XC7Z100-2FFG900I chip of the ZYNQ-7000 series of Xilinx company with an embedded arm system, and the peripheral configuration is a DDR3 DRAM memory. The ADC collection board includes 6 ADC input channels, and the maximum sampling rate reaches 125 MSPS. The radio frequency front-end board includes 6 down-conversion channels, which realize the down-conversion of the RF frequency to the IF intermediate frequency. The development of the hardware device is not the focus of the present application, and will not be described in detail.

[0046] 3. Program development

[0047] The technical solution of high-speed high-frequency beam loss diagnosis is as shown in Figure 2 .

[0048] The FPGA in the digital signal processing board card adopts a ZYNQ series chip with an embedded system, which includes a PL logic processing part and a PS processor system part. The communication between the PL part and the PS part adopts an axi4_full_master module based on the AXI4-FULL bus protocol to realize data interaction. The PS part of the FPGA is externally configured with a DDR3 memory and a network communication chip. The DDR3 is used to store beam loss diagnosis data packets, and the network chip realizes network data communication between the embedded system and the peripheral database system and OPI client.

[0049] The PL part of the FPGA is used to realize the main logic processing function of the beam loss diagnosis algorithm. The detailed function block diagram is as shown in Figure 3 .

[0050] The development of the beam loss diagnosis method is divided into the following parts according to the functional modules:

[0051] Signal acquisition of the high-frequency beam loss diagnosis system: 4-channel RF signals are collected, including cavity field power signal Pt, cavity forward power signal Pf, cavity reflected power signal Pr, and beam signal Pb. The 4-channel RF high-frequency signals are down-converted to intermediate frequency signals by the RF front-end board card, and then converted to digital signals by the ADC acquisition board card. The FPGA obtains the quadrature quantities of the 4-channel signals in the I / Q domain through the Non-IQ algorithm.

[0052] Clock selection module of the high-frequency beam loss diagnosis system: The input signals of the module include input clock pulse signal clk_trigger and clock selection signal clk_sel. The module will output a plurality of clock signals clk_trip with different proportional relationships with clk_trigger according to the size of clk_sel using the case statement, which is used to set the refresh frequency of the stored data of the beam loss diagnosis system.

[0053] Packing of data signals of the high-frequency beam loss diagnosis system: 4-channel I / Q domain acquisition signals, each with 32 bits, are obtained by concatenating the signals in front and back to obtain 128-bit packed data signals trip_data_in.

[0054] The input signals of this module include manual trigger enable signal manual_trip and I / Q of cavity field power signal Pt. The I / Q of Pt are squared and added respectively to get the power amplitude value. When the power amplitude value is less than 70% of the cavity field power set value, it indicates that high frequency beam loss occurs, and the beam loss trigger signal auto_en0 is low. The logical AND of manual_trip and auto_en0 is the beam loss enable signal auto_en1, which is sent to the beam loss trigger delay module.

[0055] The input signals of this module include beam loss diagnosis acquisition clock clk_trip, beam loss enable signal auto_en1, and beam loss trigger pulse delay number Count_trip_delay. The module delays the input auto_en1 by Count_trip_delay pulse number to get the beam loss trigger enable signal trip_enable.

[0056] The input signals of this module include beam loss diagnosis acquisition clock clk_trip and beam loss trigger enable signal trip_enable. The logical AND of the two signals is the burst clock clk_axi_txn, i.e. only when trip_enable is high, the burst clock exists pulse signal, and trip_enable is the enable switch of burst transmission. The timing diagram of the burst clock clk_axi_txn and other signals of the high frequency beam loss diagnosis system is shown in Figure 4

[0057] ​The input signals of the module include the beam loss trigger position setting signal ratio_trip and the beam loss diagnosis storage depth setting signal Length_trip. The product of Length_trip and Ratio_trip is subtracted from Length_trip to obtain the beam loss trigger pulse delay number Count_trip_delay, which is sent to the trigger delay module. The product of Length_trip and 16 is the size signal Length_trip_addr of the beam loss diagnosis storage address space, which is sent to the address cycle module. Address cycle of the high-frequency beam loss diagnosis system: the input signals of the module include the burst clock clk_axi_txn and the storage address space size Length_trip_addr. Every time a pulse of the burst clock clk_axi_txn is received, the cycle address axi_awaddr is added by 16 bytes. When the address is added to the maximum address, the address overflow is automatically assigned to 0. After the next burst pulse arrives, the addition continues. The cycle address axi_awaddr is output to the data packet processing module for subsequent processing.

[0058] Data packet processing of the high-frequency beam loss diagnosis system: the input signals of the module include the beam loss trigger enable signal trip_enable, the cycle address signal axi_awaddr, the beam current number, the beam loss data packet trip_data_in, etc. The output signals include the burst address m_axi_awaddr and the burst data packet m_axi_awdata. When trip_enable is 0, the trip_enable, cycle address signal axi_awaddr, beam current number, etc. at this moment are concatenated and packed into a 16-byte data, which is assigned to the output burst data packet signal m_axi_awdata. The burst address signal m_axi_awaddr is assigned to 0. When trip_enable is not 0, the beam loss data packet signal trip_data_in is assigned to the output burst data packet signal m_axi_awdata. At the same time, the cycle address signal axi_awaddr is assigned to the burst address signal m_axi_awaddr.

[0059] The input of the axi4_full_master module of the high-frequency beam-loss diagnosis includes burst pulse clk_axi_txn, burst address signal m_axi_awaddr and burst data packet m_axi_awdata. It serves as a master end and transmits the data packet m_axi_awdata to the m_axi_awaddr address of the PS end DDR3 specified storage address interval at the frequency of the burst clock clk_axi_txn based on the AXI4-FULL bus protocol, realizing the storage transmission of the data of the PL end to the PS end DDR3.

[0060] Data acquisition at the high-frequency beam-loss moment: the embedded system of the digital signal processing board card runs the reading program of the DDR3 storage in real time, reads the data in the corresponding DDR3 first address in real time and parses the beam-loss enabling signal trip_enable and the round-robin address axi_awaddr at the beam-loss moment. When the beam-loss enabling signal trip_enable is at a low level, it indicates that a high-frequency fault occurs at this time. After diagnosing the high-frequency fault, an empty file is created with the high-frequency station name + current time as the file name, and the storage data of the DDR3 address interval corresponding to the beam-loss diagnosis is read and written into the newly created file. After the reading is completed, the newly created data file is automatically transmitted to the specified directory of the database system through the network.

[0061] Data parsing and analysis at the high-frequency beam-loss moment: the database system monitors the files under the beam-loss diagnosis data directory in real time. When a new file is monitored, the new data packet file is read, the data packet is parsed, the I / Q quantity is converted into amplitude and phase quantity, the cavity field power signal, the cavity forward power signal, the cavity reflection signal and the beam signal are obtained, the signals at the real beam-loss moment are reordered according to the axi_awaddr, the real beam-loss signal waveform is obtained, and the waveform is drawn. According to the amplitude and phase curves of the four signals before and after the beam-loss moment, the reason for the high-frequency beam-loss is diagnosed. If the beam current decreases before the cavity field power signal, it indicates that the high-frequency fault is caused by the beam current, otherwise it is a high-frequency system fault. The reason for the high-frequency system fault can be analyzed and diagnosed by analyzing the specific waveform characteristics of the forward power, reflection power and cavity field power signals.

[0062] 4, System integration

[0063] After the hardware test and software development of the high-speed high-frequency beam-loss diagnosis system are completed, the case needs to be designed and integrated into a complete high-speed high-frequency beam-loss diagnosis system. The front panel of the case mainly includes a power switch, LED status lights, RF signal input interfaces, etc., and the back panel includes a reset switch, a trigger interface, a UART serial port, a network port and a 220V power input, etc.

[0064] While specific embodiments of the application have been disclosed to illustrate the present application and to enable its application to those skilled in the art, it is understood that various omissions and substitutions and changes of the method and systems described and illustrated can be made by those skilled in the art, without departing from the spirit and scope of the present application and of the following claims.

Claims

1. A high-speed high-frequency beam loss diagnostic method, comprising the steps of: 1) data packaging the I / Q domain quadrature quantities of the high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt and beam current signal Pb collected by the high-frequency beam loss diagnostic system in real time to generate a data packet signal trip_data_in; 2) setting a beam loss diagnostic clock frequency selection signal clk_sel, a beam loss diagnostic data storage depth signal Length_trip, a beam loss diagnostic waveform trigger position signal Ratio_trip and a beam loss diagnostic clock input signal clk_trigger; the clock selection module of the high-frequency beam loss diagnostic system outputs a beam loss diagnostic collection clock signal clk_trip according to the clock input signal clk_trigger and the beam loss diagnostic clock frequency selection signal clk_sel, which is used to meet different setting requirements of the sampling rate of the beam loss diagnostic storage data; calculating the number of beam loss trigger delay pulses Count_trip_delay = Length_trip - Ratio_trip*Length_trip; 3) when the high-frequency beam loss diagnostic system receives a beam loss manual trigger signal manual_trip, storing the collected signal waveform in a certain time period before and after the current time; if the amplitude of the cavity field power Pt at the current time is less than a certain proportion of the Pt power theoretical value, setting the beam loss enable signal auto_en0 to low level; then performing logical AND operation on the manual_trip and auto_en0 to obtain the beam loss enable signal auto_en1, delaying the beam loss enable signal auto_en1 by the number of pulses Count_trip_delay to obtain the beam loss trigger enable signal trip_enable; the beam loss manual trigger signal manual_trip is a high level signal; 4) storing the data packet at the frequency of the beam loss diagnostic collection clock signal clk_trip; performing logical AND operation on the beam loss diagnostic collection clock signal clk_trip and the beam loss trigger enable signal trip_enable to obtain the clk_axi_txn signal, which is used as the burst clock of the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at high level, the clk_axi_txn signal is the clk_trip pulse signal, which continuously bursts the data packet to the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at low level, it indicates that a high-frequency fault occurs, the clk_axi_txn signal is at low level, and the burst transmission of the data packet to the axi4_full_master bus module is stopped. ​ 5) When the clk_axi_txn signal has a rising edge, the bundle loss round-robin address axi_awaddr is incremented once; when the bundle loss trigger enable signal trip_enable is low, the burst clock clk_axi_txn signal becomes low, and the round-robin address axi_awaddr will stop incrementing; wherein, when the bundle loss round-robin address axi_awaddr is incremented to a plurality of Length_trip, an automatic overflow occurs, and the address becomes 0, and then the address is re-started to be incremented from 0; 6) After the axi4_full_master bus module receives a clk_axi_txn signal, the data packet signal trip_data_in is burst written into the DDR3 memory allocated to the storage space corresponding to the address m_axi_awaddr of the axi4_full_master bus module; 7) When it is monitored that the bundle loss trigger enable signal trip_enable is low, a data packet file is created; then the data packet signal trip_data_in is read from the corresponding storage space of the DDR3 and stored in the created data packet file; after the data reading is completed, the next time the bundle loss trigger enable signal trip_enable becomes low, and the created data packet file is transmitted to the bundle loss diagnosis directory of the database system through the network; 8) The database system monitors the data packet file in the bundle loss diagnosis directory in real time, when a new data packet file is found, the data is unpacked according to the packing mode of the data packet, the stored high-frequency cavity incident power Pf, reflected power signal Pr, cavity field power signal Pt and beam signal Pb are parsed, and the parsed data is plotted.

2. The method of claim 1, wherein, The method for obtaining the I / Q domain quadrature of the high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt and beam signal Pb of the high-frequency bundle loss diagnosis system is that the high-frequency bundle loss fault diagnosis system collects the high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt and beam signal Pb in real time, and converts the high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt and beam signal Pb to corresponding intermediate frequency signals through a radio frequency front-end board card, the intermediate frequency signals are analog-digital converted to corresponding digital signals through an ADC collection board card, and the digital signals are input into the FPGA of a digital signal processing board card to obtain the I / Q domain quadrature of the corresponding signals through a Non-IQ sampling method.

3. The method of claim 2, wherein, The DDR3 memory allocates a storage interval to the axi4_full_master bus module, the start address of the storage interval stores the bundle loss trigger enable signal trip_enable, and the other address space is used to store the data packet signal trip_data_in of the bundle loss diagnosis system.

4. The method according to claim 1 or 2 or 3, characterized in that, The step length of the bundle loss round-robin address axi_awaddr each time depends on the size of the data packet signal trip_data_in byte number.

5. The method according to claim 1 or 2 or 3, characterized in that, The beam loss diagnostic data storage depth signal Length_trip is the number of data packets stored each time the beam loss is triggered, and is used to calculate the storage address space size Length_trip_addr of the beam loss waveform stored by the DDR3 and the total time length T_trip of the beam loss waveform; the beam loss diagnostic waveform trigger position signal Ratio_trip is a proportion value of the time length before the beam loss trigger time to the entire beam loss diagnostic storage waveform curve length.

6. The method according to claim 1 or 2 or 3, characterized in that, The cause of the high-frequency beam loss is determined according to the performance characteristics of the drawn curve; and the value range of the Pt power theoretical value proportion is 60% to 80%.

7. A high-speed high-frequency beam-loss diagnostic system characterized by, The beam loss diagnostic data packaging module, the beam loss diagnostic data parameter processing module, the beam loss trigger enable signal generation module, the clock selection module, the beam loss diagnostic burst clock pulse signal generation module, the beam loss diagnostic round loop address generation module, the axi4-full-master module, the automatic storage module and the analysis module are included. The beam loss diagnostic data packaging module is used for real-time acquisition of the I / Q domain quadrature quantities of the high-frequency cavity incident power Pf, the reflected power Pr, the cavity field power Pt and the beam current signal Pb of the high-frequency system to generate a data packet signal trip_data_in through data packaging. The beam loss diagnostic data parameter processing module is used for setting the beam loss diagnostic clock frequency selection signal clk_sel, the beam loss diagnostic data storage depth signal Length_trip, the beam loss diagnostic waveform trigger position signal Ratio_trip and the beam loss diagnostic clock input signal clk_trigger, and calculating the beam loss trigger delay pulse number Count_trip_delay as follows: Count_trip_delay = Length_trip - Ratio_trip * Length_trip. The clock selection module is used for outputting the beam loss diagnostic acquisition clock signal clk_trip according to the clock input signal clk_trigger and the beam loss diagnostic clock frequency selection signal clk_sel, so as to meet different setting requirements of the beam loss diagnostic storage data sampling rate. The beam loss trigger enable signal generation module is used for storing the acquisition signal waveform in a certain time period before and after the current time when the beam loss manual trigger signal manual_trip is received; if the amplitude of the cavity field power Pt at the current time is less than the Pt power theoretical value, the beam loss enable signal auto_en0 is set to a low level; then, the beam loss enable signal auto_en1 is obtained through logical AND operation of the manual_trip and the auto_en0; the beam loss enable signal auto_en1 is delayed by the pulse number Count_trip_delay to obtain the beam loss trigger enable signal trip_enable; the beam loss manual trigger signal manual_trip is a high-level signal. The beam loss diagnosis burst clock signal generation module is configured to store data packets at the frequency of the beam loss diagnosis acquisition clock signal clk_trip, and obtain the clk_axi_txn signal by performing logical AND operation on the beam loss diagnosis acquisition clock signal clk_trip and the beam loss trigger enable signal trip_enable, as the burst clock of the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a high level, the clk_axi_txn signal is the clk_trip pulse signal, and the data packets are continuously burst transmitted to the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a low level, it indicates that a high-frequency fault occurs, the clk_axi_txn signal is at a low level, and the burst transmission of the data packets to the axi4_full_master bus module is stopped. The beam loss diagnosis round-robin address generation module is configured to accumulate the beam loss round-robin address axi_awaddr once when the clk_axi_txn signal has a pulse rising edge; when the beam loss trigger enable signal trip_enable is at a low level, the burst clock clk_axi_txn signal becomes a low level, and the round-robin address axi_awaddr stops accumulating; when the beam loss round-robin address axi_awaddr is accumulated to the multiple Length_trip and automatically overflows to 0 address, the accumulation is restarted from the 0 address. The axi4-full-master module is configured to burst write the data packet signal trip_data_in into the storage space corresponding address m_axi_awaddr of the axi4_full_master bus module in the DDR3 memory after receiving the clk_axi_txn signal. The automatic storage is configured to create a data packet file when it is monitored that the beam loss trigger enable signal trip_enable is at a low level, read the data packet signal trip_data_in from the corresponding storage space of the DDR3 and store it into the created data packet file, wait for the next beam loss trigger enable signal trip_enable to be at a low level after the data reading is completed, and transmit the created data packet file to the beam loss diagnosis directory of the database system through the network. The analysis module is configured to monitor the data packet files in the beam loss diagnosis directory in real time, unpack the data according to the packing mode of the data packet when a new data packet file is found, analyze the stored high-frequency cavity incident power Pf, reflected power signal Pr, cavity field power signal Pt and beam signal Pb, and draw curves of the analyzed data.

8. The system of claim 7, wherein, The DDR3 memory allocates a storage interval for the axi4_full_master bus module, the start address of the storage interval stores the beam loss trigger enable signal trip_enable, and the other address space is used to store the data packet signal trip_data_in of the beam loss diagnosis system.

9. The system of claim 7, wherein, The accumulated step length of the lost beam address axi_awaddr is determined by the size of the data packet signal trip_data_in.

10. The system of claim 7, wherein, The lost beam diagnostic data storage depth signal Length_trip is the number of data packets stored each time the lost beam is triggered, used to calculate the storage address space size Length_trip_addr of the DDR3 storage lost beam waveform and the total time length T_trip of the lost beam waveform; the lost beam diagnostic waveform trigger position signal Ratio_trip is the proportion value of the time length before the lost beam triggering time to the entire lost beam diagnostic storage waveform curve length.

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