Input control method and system for chip verification, electronic equipment and medium

Abstract

The invention provides an input control method and system for chip verification, electronic equipment and a storage medium. The verification method comprises the steps that an interface signal is acquired, and the interface signal is configured to be generated by a driver; acquiring a main path excitation and a first bypass excitation based on the interface signal; a main path excitation and a first bypass excitation are provided to the design under test, where the first bypass excitation includes a signal identical to at least a portion of the signal included by the main path excitation but different in timing. According to the method and the device, the required bypass excitation corresponding to the main path excitation is generated by processing the data on the interface, a basic test platform is slightly changed, the maintenance cost is low, and the expansibility is high.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an input control method and system for chip verification, an electronic device, and a medium. Background Art

[0002] Verification is a key step in the chip design process, usually implemented using a verification platform. Specifically, the verification platform can simulate the actual operating environment of the chip, enable the chip to run based on pre-designed test cases, and verify the correctness of the chip's functions according to the running results of the chip.

[0003] In the work of pre-silicon verification of chips, stimuli play an important role. Good stimuli can ensure that various situations that may occur in the actual usage scenario are simulated, providing guarantee for the sufficiency of verification. Generally speaking, during the construction of the verification platform, when constructing stimuli, it is expected to fit the actual usage scenario while maintaining the random characteristics as much as possible, so that the design under test can be fully verified in various scenarios, such as including the running of legal scenarios and the reporting of error scenarios. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides an input control method for chip verification, including: obtaining an interface signal, where the interface signal is configured to be generated by a driver; obtaining a main path stimulus and a first bypass stimulus based on the interface signal; and providing the main path stimulus and the first bypass stimulus to the design under test, where the first bypass stimulus includes signals that are the same as at least part of the signals included in the main path stimulus but have different timings.

[0005] For example, in an input control method provided by at least one embodiment of the present disclosure, the obtaining the main path stimulus and the first bypass stimulus based on the interface signal includes: loading a configuration component and obtaining a target configuration for the interface signal; operating on the interface signal based on the target configuration and performing a first stimulus control to obtain the main path stimulus and the first bypass stimulus.

[0006] For example, in an input control method provided by at least one embodiment of the present disclosure, the operating on the interface signal based on the target configuration and performing a first stimulus control to obtain the main path stimulus and the first bypass stimulus includes: generating the main path stimulus from the interface signal; the first stimulus control includes: selecting signals corresponding to at least part of the signals in the main path stimulus from the interface signal as a second bypass stimulus, and performing a delay control based on the second bypass stimulus and / or the main path stimulus, so that the first bypass stimulus is the same as the corresponding at least part of the signals in the main path stimulus but has an earlier timing than the corresponding at least part of the signals in the main path stimulus.

[0007] For example, in an input control method provided by at least one embodiment of the present disclosure, the first excitation control further includes at least one of the following: frequency control for controlling the generation frequency of the first bypass excitation, control of abnormal scenario simulation, and feedback signal adjustment control for adjusting based on a feedback signal fed back by the design under test.

[0008] For example, in an input control method provided by at least one embodiment of the present disclosure, the delay control is implemented in the following manner: using a first enable signal and a delay parameter value in a configuration object corresponding to the configuration component to control the delay between the first bypass excitation and the main path excitation, where the first enable signal is configured to enable or disable the delay processing of the second bypass excitation.

[0009] For example, in an input control method provided by at least one embodiment of the present disclosure, the frequency control is implemented in the following manner: using a second enable signal and a frequency parameter value in a configuration object corresponding to the configuration component to control the generation frequency of the first bypass excitation, where the second enable signal is configured to determine the frequency generation mode.

[0010] For example, in an input control method provided by at least one embodiment of the present disclosure, the control of abnormal scenario simulation includes: performing signal processing on the main path excitation to construct a first abnormal scenario in which the main path excitation corresponding to the first bypass excitation input to the design under test is cancelled; and / or, performing error injection processing based on the second bypass excitation to construct a second abnormal scenario in which the first bypass excitation input to the design under test has an error.

[0011] For example, in an input control method provided by at least one embodiment of the present disclosure, the feedback signal adjustment control includes: acquiring the feedback signal fed back by the design under test, and performing adjustment control on at least one of the existing signal selection control, delay control, and frequency control based on a third enable signal in a configuration object corresponding to the configuration component, where the third enable signal is configured to enable or disable the adjustment of the feedback signal on at least one of the signal selection control, the delay control, and the frequency control.

[0012] For example, in an input control method provided by at least one embodiment of the present disclosure, before loading the configuration component, it further includes: responding to a user input to set configuration parameters corresponding to the configuration component.

[0013] At least one embodiment of the present disclosure further provides a chip verification method, including the input control method described in any of the above examples. The chip verification method further includes: in response to the design under test obtaining the main path excitation and the first bypass excitation, verifying the design under test to obtain the verification result corresponding to the design under test.

[0014] At least one embodiment of the present disclosure further provides an input control system for chip verification, including: a driver configured to generate interface signals; an excitation module configured to: input the interface signals and obtain main path excitation and first bypass excitation based on the interface signals, wherein the main path excitation and the first bypass excitation are provided to the design under test, and the signals included in the first bypass excitation are the same as at least part of the signals included in the main path excitation but have different timings.

[0015] For example, in an input control system provided by at least one embodiment of the present disclosure, the excitation module includes a configuration component, a bypass excitation generation module, and a main path corresponding to the main path excitation. The configuration component is configured to obtain a target configuration for the interface signals by loading. The bypass excitation generation module and the main path are respectively connected to the configuration component, so that the bypass excitation generation module and the main path are configured to operate on the interface signals based on the target configuration to perform first excitation control to obtain the main path excitation and the first bypass excitation.

[0016] For example, in an input control system provided by at least one embodiment of the present disclosure, the configuration component includes a signal selection control unit and a signal delay control unit; the main path is configured to obtain the main path excitation generated from the interface signals; the bypass excitation generation module is connected to the signal selection control unit, so that signals corresponding to at least part of the signals in the main path excitation are selected from the interface signals as the second bypass excitation. The bypass excitation generation module and / or the main path are respectively connected to the signal delay control unit, so that delay control is performed based on the second bypass excitation and / or the main path excitation, so that the first bypass excitation is the same as at least part of the corresponding signals in the main path excitation but has an earlier timing than at least part of the corresponding signals in the main path excitation.

[0017] For example, in an input control system provided by at least one embodiment of the present disclosure, the configuration component further includes at least one of the following: a signal frequency control unit, an abnormal scenario simulation control unit, and a feedback signal adjustment control unit; the bypass excitation generation module is respectively connected to at least one of the signal frequency control unit, the abnormal scenario simulation control unit, and the feedback signal adjustment control unit to respectively implement frequency control for controlling the generation frequency of the first bypass excitation, control of abnormal scenario simulation, and feedback signal adjustment control for adjusting based on the feedback signal of the design under test; and / or, the main path is connected to the abnormal scenario simulation control unit to implement control of abnormal scenario simulation.

[0018] For example, in an input control system provided by at least one embodiment of the present disclosure, the bypass excitation generation module includes a first signal control module connected to the signal delay control unit, and the bypass excitation generation module further includes: a second signal control module connected to the signal delay control unit and further connected to at least one of the signal frequency control unit, the abnormal scenario simulation control unit, and the feedback signal adjustment control unit, and the first signal control module and the second signal control module are respectively connected to the signal selection control unit.

[0019] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the method described in any one of the above is implemented.

[0020] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the method described in any of the above examples is implemented. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a flowchart of an input control method for chip verification proposed by some embodiments of the present disclosure.

[0023] Figure 2 It is a schematic diagram of an input control system for chip verification provided by some embodiments of the present disclosure.

[0024] Figure 3A flowchart of an execution process of step S2 provided in some embodiments of the present disclosure.

[0025] Figure 4 A block diagram of a composition of an excitation module provided in some embodiments of the present disclosure.

[0026] Figure 5 A flowchart of excitation control in a chip verification method provided in some embodiments of the present disclosure.

[0027] Figure 6 A schematic structural diagram of an electronic device provided in some embodiments of the present disclosure. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the embodiments of the present disclosure.

[0030] The "first", "second" and similar terms used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Similarly, terms such as "include" or "comprise" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The term "connect" or "couple" does not limit to a physical or mechanical connection, but may include an electrical connection, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the steps before or after do not necessarily need to be carried out precisely in order. On the contrary, they can be carried out in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0031] Currently, the adoption of verification methodologies is one of the trends in chip verification, and the Universal Verification Methodology (UVM for short) is a typical representative among them. UVM is a general verification methodology mainly based on SystemVerilog classes. By using its reusable components, a functional verification environment with a standardized hierarchical structure and interfaces, that is, a UVM verification environment, can be constructed. The UVM verification environment defines the basic classes (i.e., reusable components) in UVM. For example, a sequencer (which can also be called a sequence generator), a driver, etc., as well as communication interfaces, etc.

[0032] The inventors of the present disclosure have found that: in some chip verification schemes, the requirements for stimuli in various scenarios cannot be well met; while in some other chip verification schemes, in order to meet the requirements for stimuli in multiple scenarios, there will be various problems such as large changes in the test platform, decreased reusability of IP (Intellectual Property) modules, poor scalability and maintainability, high resource consumption, and increased communication costs.

[0033] In response to this, at least one embodiment of the present disclosure provides an input control method for chip verification, including: obtaining an interface signal, where the interface signal is configured to be generated by a driver; obtaining a main path stimulus and a first bypass stimulus based on the interface signal; and providing the main path stimulus and the first bypass stimulus to the design under test, where the first bypass stimulus includes signals that are the same as at least some of the signals included in the main path stimulus but have different timings.

[0034] At least one embodiment of the present disclosure also provides an input control system for chip verification, including: a driver configured to generate an interface signal; and an excitation module configured to: input the interface signal and obtain a main path stimulus and a first bypass stimulus based on the interface signal, where the main path stimulus and the first bypass stimulus are provided to the design under test, and the first bypass stimulus includes signals that are the same as at least some of the signals included in the main path stimulus but have different timings.

[0035] The input control method or system for chip verification in the above embodiments of the present disclosure generates the required bypass stimulus corresponding to the main path stimulus by processing the data on the interface, with less modification to the basic test platform and low maintenance cost (for example, no need to modify the code of the stimulus generation component corresponding to the protocol). The generation of the bypass stimulus is very simple and has high scalability.

[0036] The embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 It is a flowchart of an input control method for chip verification proposed in some embodiments of the present disclosure.Figure 2 Schematic diagram of an input control system for chip verification provided by some embodiments of the present disclosure.

[0038] For example, as Figure 1 shown, an input control method for chip verification provided by at least one embodiment of the present disclosure includes steps S1 to S3.

[0039] Step S1: Obtain an interface signal, where the interface signal is configured to be generated by a driver.

[0040] Step S2: Obtain a main path excitation and a first bypass excitation based on the interface signal.

[0041] Step S3: Provide the main path excitation and the first bypass excitation to a design under test (DUT), where the first bypass excitation includes signals that are the same as at least some of the signals included in the main path excitation but have different timings.

[0042] For example, as Figure 2 shown, at least one embodiment of the present disclosure further provides an input control system 100 for generating and controlling excitation input in the verification of a design under test 200. The input control system 100 includes a driver 110 and an excitation module 120. For example, the input control system 100 of the embodiments of the present disclosure is at least a part of a chip verification system, and the chip verification system is a UVM verification platform for chip verification. The design under test 200 is a design for testability, which is the object mainly responsible for verification by a verification engineer.

[0043] For example, as Figure 2 shown, the driver 110 is configured to generate an interface signal, and the excitation module 120 is configured to input the interface signal and obtain a main path excitation and a first bypass excitation based on the interface signal. The design under test 200 is configured to receive the main path excitation and the first bypass excitation. Thus, input simulation of the design under test 200 can be achieved. The first bypass excitation includes signals that are the same as at least some of the signals included in the main path excitation but have different timings.

[0044] In an embodiment of the present disclosure, bypass stimulation (such as the first bypass stimulation or the second bypass stimulation described herein) is a verification technical concept relative to the main path stimulation. For example, for the design under test 200, the main path signals are various input signals specified by the standard bus protocol, and the bypass signals are signals related to the main path signals (for example, having a direct relationship in terms of delay and / or occurrence frequency, etc.). Then, the bypass stimulation is a stimulation related to the main path stimulation proposed in the verification work based on the requirements of such bypass signals and the fact that the standard protocol IP generally only generates main path stimulation. Exemplarily, in some scenarios, the bypass signal is required to remind the design under test 200 to perform data processing and other operations in advance. This is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0045] The above method or system of the embodiments of the present disclosure generates the required bypass stimulation corresponding to the main path stimulation by processing the data on the processing interface. In this way, the modification to the basic test platform is small and the maintenance cost is low (for example, there is no need to modify the code of the stimulation generation component corresponding to the protocol). The generation of the bypass stimulation is very simple and has high scalability.

[0046] It should be noted that in the embodiments of the present disclosure, the focus is on explaining the input control in chip verification (i.e., aspects such as stimulation generation and stimulation control). Regarding the related content of components such as agents, monitors, scoreboards, reference models, etc. in the general verification methodology of chip verification, it is not the focus of the description of the embodiments of the present disclosure. It can refer to the relevant prior art. For the sake of clarity and conciseness of the description herein, it will not be elaborated further here.

[0047] In some embodiments of the present disclosure, the relationship in time sequence between the signals of the first bypass stimulation and the corresponding part of the signals in the main path stimulation is that the first bypass stimulation is earlier than the main path stimulation, that is, the two have the same address, and in terms of time sequence, the input of the design under test 200 can first obtain the bypass signal.

[0048] The embodiments of the present disclosure provide a bypass stimulation in addition to the main path stimulation with a small modification to the test platform, which can well meet the requirements of the stimulation and can also more comprehensively cover various required scenarios.

[0049] In some examples, the obtaining of the interface signal in step S1 may include the following process or steps: obtaining the interface signal that is converted from the stimulation transaction packet by the driver 110 and driven to the interface 130 (such as Figure 2 the interface 130 between the driver 110 and the design under test 200).

[0050] For example, as Figure 2As shown, the excitation module 120 is disposed between the interface 130 and the design under test 200.

[0051] In some embodiments of the present disclosure, the excitation generation component A in the input control system 100 is constructed based on the random excitation required in chip verification and according to the requirements of test cases. For example, Figure 2 As shown, the excitation generation component A includes a sequence 150 (Sequence), a sequencer 140, and the above-mentioned driver 110. The sequence 150 is used to generate a target number of random transactions. The sequencer 140 is used to start the sequence. The sequencer 140 is connected to the sequence 150 and the driver 110. The driver 110 obtains transactions from the sequencer 140 and performs timing excitation on the design under test 200 at the interface after conversion. In an embodiment of the present disclosure, a transaction is the minimum granularity content required for the driver 110 to perform one excitation on the design under test 200. For example, a transaction generally includes an access address, a command operation type, data, a status value, and the like.

[0052] For example, the sequence 150 randomizes the signals to be transmitted and packs them into a transmission transaction, sends them to the driver 110 through the sequencer 140, and then uses the driver 110 to transfer the excitation information in the transaction to the interface signal, and finally transfers it to the design under test 200 in the test platform.

[0053] Embodiments of the present disclosure can obtain bypass excitation based on the signals coming out of the interface, achieving the purpose of reducing or not modifying the transaction packet. Embodiments of the present disclosure have small changes to the test platform and low maintenance costs, improving verification efficiency and having high scalability.

[0054] Figure 3 It is a flowchart of an execution process of step S2 provided for some embodiments of the present disclosure.

[0055] In some embodiments of the present disclosure, step S2 includes the following processes or steps:

[0056] S21. Load the configuration component and obtain the target configuration for the interface signal.

[0057] S22. Operate on the interface signal based on the target configuration and perform the first excitation control to obtain the main path excitation and the first bypass excitation.

[0058] Figure 4 It is a block diagram of the composition of the excitation module provided for some embodiments of the present disclosure.

[0059] For example, as Figure 4As shown, the excitation module 120 includes a configuration component 121, a bypass excitation generation module 122, and a main path 123 corresponding to the main path excitation. The configuration component 121 is configured to obtain a target configuration for the interface signal by loading. The bypass excitation generation module 122 and the main path 123 are respectively connected to the configuration component 121, so that the bypass excitation generation module 122 and the main path 123 are configured to operate on the interface signal based on the target configuration, perform a first excitation control, so as to obtain the main path excitation and the first bypass excitation.

[0060] In the embodiments of the present disclosure, the configuration component provides a processing method for the excitation input signal (that is, Figure 4 the interface signal output from the interface 130 in the figure). In the embodiments of the present disclosure, without modifying the component code of the original protocol IP, only the signals on the interface need to be configured and signal processed, so that the design under test can be fully verified in various scenarios, the IP component has high reusability, and the verification efficiency is high.

[0061] In some examples, the present disclosure generates the main path excitation from the interface signal. For example, as Figure 4 shown, the main path 123 is configured to obtain the main path excitation generated from the interface signal.

[0062] For example, as Figure 4 shown, the interface signal output from the interface 130 is input to the main path 123 to obtain the main path excitation, and the interface signal output from the interface 130 is also input to the bypass excitation generation module 122. For example, as Figure 4 shown, the interface signal output from the interface 130 is input to each signal controller in the bypass excitation generation module 122, and the signal controller will be described below.

[0063] In some embodiments of the present disclosure, the first excitation control in step S22 includes: selecting a signal corresponding to at least some signals in the main path excitation from the interface signal as the second bypass excitation, and performing a delay control based on the second bypass excitation and / or the main path excitation, so that the first bypass excitation is the same as at least some corresponding signals in the main path excitation but the timing is earlier than at least some corresponding signals in the main path excitation.

[0064] The embodiments of the present disclosure select some important signals from the input interface signal as the bypass excitation, and through the delay control, the bypass excitation provided to the design under test arrives at the design under test earlier than the main path excitation, preparing in advance for complex and time-consuming logical calculations. The method for generating the bypass excitation is simple and effective.

[0065] In some examples, which signals are selected from the input interface signals in the embodiments of the present disclosure can be determined according to actual requirements, and the embodiments of the present disclosure do not limit this. For example, a data packet in the interface signal has valid signals, addresses, data, handshake signals, user-defined signals, etc. When the target requirement is to pull up a certain bit of the corresponding address in advance, only the valid signal and the address can be selected from them. Of course, this is only exemplary and not a limitation on the embodiments of the present disclosure.

[0066] For example, as Figure 4 shown, the bypass excitation generation module 122 includes at least one signal controller, and each signal controller is connected to the configuration component 121. The configuration component 121 is used to integrate and manage user-defined configuration parameters. The configuration component 121 provides the configuration parameters to the corresponding signal controller, instructing the corresponding signal controller to perform signal operations on the interface signal or the bypass excitation. Thus, the behavior of the signal controller in the bypass excitation generation module 122 can be controlled by the configuration parameters issued by the configuration component 121, and different configurations correspond to different behaviors. Exemplarily, in the embodiments of the present disclosure, selecting the required signals from the input interface signals is achieved through the screening behavior of the signal controller.

[0067] By presetting or modifying the configuration objects of the configuration component, the embodiments of the present disclosure can customize the generated excitation according to actual needs, and at the same time can be applicable to various types of bus protocols, with high scalability.

[0068] In some embodiments of the present disclosure, the configuration component 121 can be a collection of multiple sub-configuration control units. Different sub-configuration control units correspond to different configurations, and these sub-configuration control units can be freely adjusted according to actual needs. For example, the multiple sub-configuration control units can include Figure 4 one or more of the signal selection control unit 301, signal delay control unit 302, signal frequency control unit 303, abnormal scenario simulation control unit 304, and feedback signal adjustment control unit 305 in, and the embodiments of the present disclosure do not limit this.

[0069] For example, as Figure 4 shown, the configuration component 121 includes a signal selection control unit 301 and a signal delay control unit 302. The bypass excitation generation module 122 is connected to the signal selection control unit 301, so as to select signals corresponding to at least some signals in the main path excitation from the interface signals as the second bypass excitation. For example, as Figure 4As shown, the bypass excitation generating module 122 and / or the main path 123 are respectively connected to the signal delay control unit 302, so that delay control is performed based on the second bypass excitation and / or the main path excitation, so that the first bypass excitation is identical to at least part of the corresponding signal in the main path excitation but the timing is earlier than at least part of the corresponding signal in the main path excitation.

[0070] In an embodiment of the present disclosure, the second bypass excitation is a signal obtained after signal selection (also referred to as signal screening or signal copying) is performed based on the input interface signal. The second bypass excitation can be understood as the initial signal of the bypass excitation obtained according to the signal selection configuration, and the first bypass excitation is an output signal obtained by performing other signal operations based on the second bypass excitation.

[0071] The embodiments of the present disclosure support excitation selection control, and the signal to be operated can be selected through signal selection to realize customization of the bypass excitation signal. It is not only applicable to various design requirements to be tested, but also the bus protocol type is not restricted, and different signals can be used as bypass excitation for the same bus protocol.

[0072] For example, taking the signals on the AXI (Advanced eXtensible Interface) bus as an example, the components of the AXI4 bus may include a read address channel, a read data channel, a write address channel, a write data channel, a write response channel, etc. If only the logic related to "write" needs to be processed in advance, in the embodiments of the present disclosure, the design to be tested only needs to know the write request and the address of the write request, so at this time, only the write address channel needs to be selected. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure, and will not be exhaustively listed or elaborated here.

[0073] In some embodiments of the present disclosure, before loading the configuration component 121, it also includes: setting the configuration parameters corresponding to the configuration component 121 in response to the user's input. For example, the user can configure the various parameters of the configuration object in the stimulus module by "passing in parameters through the command line", so that different types of incentives can be obtained. Therefore, the embodiments of the present disclosure realize the full configurability of the test scenario through the user's input (for example, by passing in parameters through the command line), and the generation of test incentives has the advantages of flexible control and dynamic optimization. It should be noted that the embodiments of the present disclosure are not limited to obtaining user-defined configurations by loading configuration information, but can also obtain default configurations, which can be determined according to actual conditions, and are not limited or elaborated here.

[0074] In some examples, the above delay control based on the second bypass excitation and / or the main path excitation includes the following: directly controlling the main path excitation to delay by a first delay value (e.g., 10 nanoseconds); or, controlling the main path excitation to delay by a second delay value (e.g., delaying by 7 nanoseconds) and controlling the first bypass excitation to delay by a third delay value (e.g., delaying by 3 nanoseconds), so as to achieve that the first bypass excitation and the main path excitation reaching the design under test 200 have a delay of the first delay value, where the sum of the second delay value and the third delay value is equal to the first delay value. Of course, this is merely exemplary and not a limitation of the embodiments of the present disclosure.

[0075] The embodiments of the present disclosure support excitation delay control, such that the delay between the main path excitation and the bypass excitation is controllable and customizable.

[0076] In some examples, in addition to including the signal selection control unit 301 and the signal delay control unit 302, the configuration component 121 may further include at least one of the following: a signal frequency control unit 303, an abnormal scenario simulation control unit 304, and a feedback signal adjustment control unit 305. Correspondingly, the first excitation control in step S22 may further include at least one of the following: frequency control for controlling the generation frequency of the first bypass excitation, control of abnormal scenario simulation, and feedback signal adjustment control for adjusting based on the feedback signal of the design under test.

[0077] In some examples, the bypass excitation generation module 122 is connected to at least one of the signal frequency control unit 303, the abnormal scenario simulation control unit 304, and the feedback signal adjustment control unit 305, so as to respectively implement the above frequency control, the control of the above abnormal scenario simulation (e.g., corresponding to the second abnormal scenario, see the description below), and the above feedback signal adjustment control.

[0078] The embodiments of the present disclosure support excitation frequency control and abnormal scenario simulation, and can also monitor the signal feedback by the design under test and change the excitation in real time by adding feedback signal adjustment control.

[0079] In some examples, the bypass excitation generation module 122 includes a first signal control module connected to the signal delay control unit 302, where the first signal control module is connected to the signal selection control unit 301. For example, the first signal control module is Figure 4 the signal controller 0 in

[0080] In some examples, the bypass excitation generation module 122 further includes: a second signal control module connected to the signal delay control unit 302 and also connected to at least one of the signal frequency control unit 303, the abnormal scenario simulation control unit 304, and the feedback signal adjustment control unit 305. The second signal control module is connected to the signal selection control unit 301. For example, the second signal control module may include a signal controller, or may include multiple signal controllers. For example, each signal controller in the second signal control module is connected to the signal selection control unit 301.

[0081] For example, as Figure 4 shown, the second signal control module includes signal controller 1, signal controller 2, and signal controller 3 (i.e., Figure 4 the signal controller n in

[0082] where n = 3). For example, the operations corresponding to the respective signal controllers in the bypass excitation generation module 122 are different. The respective signal controllers in the bypass excitation generation module 122 respectively correspond to the operations of different groups of signals, and the operations performed on the same group of signals are the same.

[0083] Exemplarily, the signal group corresponding to signal controller 0 (for example, a group of signals including signal A01, signal B02, and signal C03 shown below) is directly delayed and output after being selected. The signal group corresponding to signal controller 1 (for example, a group of signals including signal D04 and signal E05 shown below) can perform frequency control in addition to delay. The signal group corresponding to signal controller 2 (for example, a group of signals including signal F06, signal G07, and signal H08 shown below) can perform abnormal scenario simulation control in addition to delay and frequency control. The signal group corresponding to signal controller 3 (for example, a group of signals including signal J09 and signal K10 shown below) can perform feedback signal adjustment control in addition to delay, frequency, and abnormal scenario simulation control. Of course, this is merely exemplary and not a limitation of the embodiments of the present disclosure.

[0083] Exemplarily, for the signal group corresponding to signal controller 0 (for example, denoted as signal A01, signal B02, and signal C03), the corresponding operation is A + B, where operation A represents signal selection and operation B represents signal delay. For example, as Figure 4 shown, signal controller 0 is respectively connected to the signal selection control unit 301 and the signal delay control unit 302.

[0084] Exemplarily, for the signal group corresponding to signal controller 1 (for example, denoted as signal D04 and signal E05), the corresponding operation is A + B + C, where operation A represents signal selection, operation B represents signal delay, and operation C represents frequency control. For example, as Figure 4As shown, the signal controller 1 is respectively connected to the signal selection control unit 301, the signal delay control unit 302, and the signal frequency control unit 303.

[0085] Exemplarily, for the signal group corresponding to the signal controller 2 (such as denoted as signal F06, signal G07, and signal H08), the corresponding operations are A + B + C + D, where operation A represents signal selection, operation B represents signal delay, operation C represents frequency control, and operation D represents the control of abnormal scenario simulation. For example, as Figure 4 shown, the signal controller 2 is respectively connected to the signal selection control unit 301, the signal delay control unit 302, the signal frequency control unit 303, and the abnormal scenario simulation control unit 304.

[0086] Exemplarily, for the signal group corresponding to the signal controller 3 (such as denoted as signal J09, signal K10), the corresponding operations are A + B + C + D + E, where operation A represents signal selection, operation B represents signal delay, operation C represents frequency control, operation D represents the control of abnormal scenario simulation, and operation E represents the control of feedback signal adjustment. For example, as Figure 4 shown, the signal controller 3 is respectively connected to the signal selection control unit 301, the signal delay control unit 302, the signal frequency control unit 303, the abnormal scenario simulation control unit 304, and the feedback signal adjustment control unit 305.

[0087] Of course, this is only exemplary and not a limitation of the embodiments of the present disclosure. For example, Figure 4 the operations corresponding to the signal controller 2 in [[ ]] may not only be A + B + C + D, but also A + B + D. Another example is that Figure 4 the operations corresponding to the signal controller 3 in [[ ]] may not only be A + B + C + D + E, but also A + B + E or A + B + C + E. The embodiments of the present disclosure do not limit and exhaustively list this.

[0088] In the second signal control module of the embodiments of the present disclosure, signal controllers 0 to signal controllers n (n is an integer) are included. The embodiments of the present disclosure do not limit the value of n, that is, the embodiments of the present disclosure do not limit the number of signal groups corresponding to the second signal control module, and it can be freely adjusted according to the actual situation, which will not be elaborated here.

[0089] The embodiments of the present disclosure improve the flexibility, efficiency, and test coverage of bypass excitation generation by allocating independent controllers to different signal groups and defining differentiated operation rules, providing an efficient and scalable solution for multi-scenario verification of complex integrated circuits.

[0090] It should be noted that, for the clarity and simplicity of the illustrated lines and to avoid line intersections, Figure 4Taking the connection between the signal controller 0 and the configuration component 121 as an example for illustration, Figure 4 the connection lines between the signal controller 1 to the signal controller n in Figure 4 and the configuration component 121 are not marked with arrows in Figure 4 , Figure 4 but this does not affect the understanding and protection scope of the solutions of the embodiments of the present disclosure.

[0091] It should be noted that for the input control system 100 of the embodiments of the present disclosure, it may include more or fewer modules, and the connection relationships between the various modules are not restricted and can be determined according to actual requirements. The specific composition manners of the various modules are not restricted.

[0092] Each module in the above embodiments can be respectively configured as software, hardware, firmware, or any combination of the above items that execute specific functions. For example, these modules can correspond to dedicated integrated circuits, or pure software codes, or modules combining software and hardware.

[0093] It should be noted that although the input control system is divided into modules for respectively executing corresponding processes as described above, however, those skilled in the art are clear that the processes executed by each module can also be executed when there is no specific module division in the input control system or there is no clear demarcation between the modules.

[0094] In the embodiments of the present disclosure, for the specific implementation and technical effects of the input control system, reference can be made to the input control method provided in the embodiments of the present disclosure, and the repeated parts will not be elaborated here.

[0095] In some examples, the delay control is implemented in the following manner: using the first enable signal E1 and the delay parameter value B1 in the configuration object corresponding to the configuration component 121 to control the delay between the first bypass excitation and the main path excitation. The first enable signal E1 can also be referred to as the first enable switch. As a control parameter in the configuration object, the first enable signal E1 is configured to enable or disable the delay processing function of the signal controller for the bypass excitation (i.e., the second bypass excitation). For example, when the first enable signal E1 is 0 (i.e., in the disabled state at this time), the signal is directly output without any delay processing; when the first enable signal E1 is 1 (i.e., in the enabled state at this time), the signal controller also applies a delay to the signal according to the configured delay parameter value B1.

[0096] The embodiments of the present disclosure use the enable signal in the configuration object to complete the customization of the bypass excitation delay, and can achieve the delay control and customization between the bypass excitation and the main path excitation.

[0097] In some examples, when the configuration component 121 includes the signal frequency control unit 303, the first excitation control in step S22 includes frequency control, which is achieved by the following method: using the second enable signal E2 and the frequency parameter value F1 in the configuration object corresponding to the configuration component 121 to control the generation frequency of the first bypass excitation. The second enable signal E2 can also be referred to as the second enable switch. As a control parameter in the configuration object, the second enable signal E2 is configured to determine the frequency generation mode. For example, the second enable signal E2 determines whether the frequency generation mode is random or fixed.

[0098] For example, when the second enable signal is characterized as the random mode (e.g., sig_a_rand_enable = 1), the bypass excitation signal_a is generated at random intervals (e.g., based on the random seed random_seed); when the second enable signal is characterized as the fixed mode (e.g., sig_a_rand_enable = 0), the bypass excitation is generated at a fixed ratio M:1 (i.e., a bypass signal is generated every M main path data packets, and M is a positive integer). In some examples, the frequency parameter value F1 can be the fixed ratio value M:1 in the fixed mode or the random seed random_seed in the random mode.

[0099] Exemplarily, the relationship between the main path excitation and the first bypass excitation can be a one-to-one relationship (i.e., M:1 = 1:1), or the relationship between the main path excitation and the first bypass excitation can be a many-to-one relationship (i.e., M:1 is greater than 1). The one-to-one relationship means that every time a data packet (such as a write operation) is sent on the main path signal, the bypass excitation generation module 122 synchronously generates a corresponding bypass signal. The many-to-one relationship (taking three-to-one as an example) means that after sending the main path data 3 times, the bypass excitation generation module 122 generates a bypass signal once. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0100] The embodiments of the present disclosure use the enable signal in the configuration object to control the frequency control of the bypass excitation, which can realize the control and customization of the bypass excitation frequency.

[0101] In some examples, when the configuration component 121 includes a feedback signal adjustment control unit 305, the first excitation control in step S22 includes a feedback signal adjustment control, and the feedback signal adjustment control includes the following processes or steps: obtaining a feedback signal fed back by the design under test 200, and based on the third enable signal E3 in the configuration object corresponding to the configuration component 121, adjusting and controlling at least one of the existing signal selection control (such as the control of selecting a signal corresponding to at least part of the signals in the main path excitation from the interface signals as the second bypass excitation as described above), delay control, and frequency control. The third enable signal E3 can also be referred to as a third enable switch. The third enable signal E3 is used as a control parameter in the configuration object and is configured to enable or disable the dynamic adjustment function of the feedback signal for the configuration parameter. Exemplarily, the third enable signal E3 is configured to enable or disable the adjustment of at least one of the signal selection control, delay control, and frequency control by the feedback signal.

[0102] For example, when the third enable signal E3 is 0 (i.e., in the disabled state at this time), the original user configuration is maintained and the feedback signal is ignored; when the third enable signal E3 is 1 (i.e., in the enabled state at this time), the delay parameter value and / or frequency parameter value can be automatically adjusted according to the feedback signal (such as buffer status, error flag, etc.) fed back by the design under test 200. For example, when the third enable signal E3 is 1, the feedback signal fed back by the design under test 200 can overwrite the original configuration parameters of the user. For instance, the initial delay value is b0 and the frequency is in a one-to-eight ratio in the fixed mode. If the design under test 200 feeds back a timeout error, the configuration component 121 adjusts the delay from b0 to another value b1. If the design under test 200 feeds back that the buffer is idle, the frequency is adjusted to one-to-five. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0103] For example, whether the third enable signal E3 of the embodiments of the present disclosure is in the disabled state or the enabled state is controlled by whether the signal fed back by the design under test 200 to the configuration component 121 meets a preset condition. Of course, specific preset monitoring rules are configured to determine which signals of the design under test can trigger the third enable switch, and this can be freely adjusted according to the actual situation and will not be limited and elaborated here.

[0104] The embodiments of the present disclosure modify the configuration of the configuration component through the signal fed back by the design under test, realizing the intelligent generation and real-time optimization of test stimuli, and significantly improving the test efficiency and scenario coverage accuracy. The embodiments of the present disclosure can flexibly customize test scenarios through hierarchical enable signals, and at the same time, combine the feedback mechanism to achieve dynamic optimization.

[0105] In some examples, when the configuration component 121 includes the abnormal scenario simulation control unit 304, the first excitation control in step S22 includes the control of abnormal scenario simulation, and the control of abnormal scenario simulation includes the following processes or steps: performing signal processing on the main path excitation to construct a first abnormal scenario in which the main path excitation corresponding to the first bypass excitation input to the design under test 200 is cancelled; and / or, performing error injection processing based on the second bypass excitation to construct a second abnormal scenario in which the first bypass excitation input to the design under test 200 has an error.

[0106] Embodiments of the present disclosure support abnormal scenario simulation, which can comprehensively simulate complex scenarios such as cancellation of main path excitation and error injection of bypass excitation, making the test excitation very rich and the chip verification more comprehensive.

[0107] For example, as Figure 4 shown, the main path 123 can also be connected to the abnormal scenario simulation control unit 304 to implement the control of abnormal scenario simulation (for example, corresponding to the first abnormal scenario). For example, the first abnormal scenario includes an abnormal scenario in which the main path excitation corresponding to the first bypass excitation input to the design under test 200 is cancelled. By connecting the main path to the abnormal scenario simulation control unit of the configuration component, embodiments of the present disclosure can implement the simulation of a more controllable abnormal scenario, and the method is simple and effective.

[0108] For example, as Figure 4 shown, the bypass excitation generation module 122 is connected to the abnormal scenario simulation control unit 304 to implement the control of abnormal scenario simulation (for example, corresponding to the second abnormal scenario). For example, the second abnormal scenario is an abnormal scenario in which the first bypass excitation input to the design under test 200 has an error.

[0109] In some examples, embodiments of the present disclosure can achieve the purpose of simulating the first abnormal scenario by performing bit flipping processing on the signals of the main path. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. For example, it can also simulate the first abnormal scenario through signal masking processing, which can be determined according to the actual situation, and the embodiments of the present disclosure do not limit and elaborate on this.

[0110] In some examples, the error injection processing based on the second bypass excitation in the embodiments of the present disclosure can be achieved by flipping some bits of the address or data of the bypass excitation according to the relationship between the first bypass excitation and the main path excitation, thereby generating some useless signals and constructing the second abnormal scenario. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. It can perform specific error injection according to the actually required scenario, and the embodiments of the present disclosure do not limit and elaborate on this.

[0111] Figure 5Flowchart of the excitation control in the chip verification method provided by some embodiments of the present disclosure.

[0112] For example, as Figure 5 shown, the method of excitation control in the chip verification method provided by some embodiments of the present disclosure includes steps P1 to P14.

[0113] Step P1: Start.

[0114] Step P2: Connect the interface signal to the excitation module.

[0115] Step P3: Load the configuration component. For example, in step P3, by loading the configuration component, the target configuration for the interface signal can be obtained, and the target configuration is used to control the operation of the interface signal.

[0116] Step P4: The main path input interface signal obtains the main path excitation, and continue to step P12.

[0117] Step P5: The bypass input interface signal gets the bypass signal, and continue to step P6.

[0118] Step P6: According to the signal selection configuration, obtain the initial signal of the bypass excitation (i.e., the second bypass excitation described above), and continue at least one of the following steps P7 to P10.

[0119] Step P7: Execute the bypass excitation delay control.

[0120] Step P8: Execute the bypass excitation frequency control.

[0121] Step P9: Execute the abnormal scenario simulation control. For example, in step P9, the abnormal scenario includes the second abnormal scenario described above.

[0122] Step P10: Execute the feedback signal adjustment control. For example, in step P10, the feedback signal adjustment control can be executed according to the signal fed back by the design under test.

[0123] Step P11: Output the first bypass excitation.

[0124] Step P12: Determine whether to process the main path excitation. If yes, continue to step P13; if no, directly jump to step P14. For example, in step P12, the processing may refer to the flipping processing of the signal. Of course, this is only exemplary.

[0125] Step P13: Construct an abnormal scenario for the main path, and continue to step P14. For example, in step P13, the abnormal scenario includes the first abnormal scenario described above.

[0126] Step P14: Output the main path excitation.

[0127] Embodiments of the present disclosure obtain a target configuration (such as a default configuration or a user-defined configuration) by loading a configuration component, and perform different operations on an excitation input signal (i.e., an input interface signal), so as to generate a main path excitation and a first bypass excitation and provide them to the design under test. In this way, the modification to the basic test platform is small and the maintenance cost is low. The excitation generation is very simple, the scalability is high, and various required scenarios can be more comprehensively covered.

[0128] At least one embodiment of the present disclosure further provides a chip verification method. The chip verification method includes the input control method in any example herein, and the chip verification method further includes: in response to the design under test obtaining the main path excitation and the first bypass excitation, verifying the design under test to obtain a verification result corresponding to the design under test. It should be noted that the embodiments of the present disclosure focus on the excitation generation and control aspects in the chip verification method, and do not describe in detail the verification and obtaining of the verification result based on the design under test and the obtained main path excitation and first bypass excitation, which can refer to the prior art. For the specific implementation and technical effects of the chip verification method, reference can be made to the input control method provided in the embodiments of the present disclosure, and the repeated parts will not be elaborated.

[0129] Next, refer to Figure 6 , which shows a schematic structural diagram of an electronic device (such as a terminal device or a server) 600 suitable for implementing the embodiments of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device shown is only an example and should not impose any limitation on the functions and usage scopes of the embodiments of the present disclosure.

[0130] As Figure 6 shown, the electronic device 600 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 606 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0131] Typically, the following devices can be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 606 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 can allow the electronic device 600 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 6 the electronic device 600 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. More or fewer devices can be alternatively implemented or had.

[0132] Specifically, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication device 609, or installed from the storage device 606, or installed from the ROM 602. When the computer program is executed by the processing device 601, the above functions defined in the method of the embodiment of the present disclosure are executed.

[0133] It should be noted that the computer-readable medium described above in the present disclosure can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0134] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0135] The above computer-readable medium can be included in the above electronic device; or it can exist separately without being assembled into the electronic device.

[0136] The above computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: obtain an interface signal, where the interface signal is configured to be generated by a driver; obtain a main path excitation and a first bypass excitation based on the interface signal; and provide the main path excitation and the first bypass excitation to a design under test to verify the design under test, where the first bypass excitation includes signals that are the same as at least some of the signals included in the main path excitation but have different timings.

[0137] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or combinations thereof. The programming languages include, but are not limited to, object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0139] The units involved in the embodiments described in the present disclosure may be implemented in software or in hardware. Among them, the name of the unit does not constitute a limitation on the unit itself in some cases. For example, the excitation module may also be described as "a module for controlling or processing excitation".

[0140] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: Field Programmable Gate Arrays (FPGA), Application Specific Integrated Circuits (ASIC), Application Specific Standard Products (ASSP), System on a Chip (SOC), Complex Programmable Logic Devices (CPLD), and the like.

[0141] In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM or Flash memory), an optical fiber, a portable Compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0142] The above description is only a preferred embodiment of the present disclosure and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, a technical solution formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present disclosure.

[0143] In addition, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments may also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0144] The following points need to be noted:

[0145] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0146] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0147] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An input control method for chip verification, comprising: Obtaining interface signals, wherein the interface signals are configured to be generated by a driver; Obtaining a main path excitation and a first bypass excitation based on the interface signals; Providing the main path excitation and the first bypass excitation to a design under test, wherein the signals included in the first bypass excitation are the same as at least some of the signals included in the main path excitation but have different timings.

2. The input control method according to claim 1, wherein, The obtaining of the main path excitation and the first bypass excitation based on the interface signals comprises: Loading a configuration component and obtaining a target configuration for the interface signals; Operating on the interface signals based on the target configuration and performing a first excitation control to obtain the main path excitation and the first bypass excitation.

3. The input control method according to claim 2, wherein, The operating on the interface signals based on the target configuration and performing the first excitation control to obtain the main path excitation and the first bypass excitation comprises: Generating the main path excitation from the interface signals; The first excitation control comprises: selecting, from the interface signals, signals corresponding to at least some of the signals in the main path excitation as a second bypass excitation, and performing a delay control based on the second bypass excitation and / or the main path excitation, such that the first bypass excitation is the same as the corresponding at least some of the signals in the main path excitation but has an earlier timing than the corresponding at least some of the signals in the main path excitation.

4. The input control method according to claim 3, wherein The first excitation control further comprises at least one of the following: Frequency control for controlling the generation frequency of the first bypass excitation, control of abnormal scenario simulation, feedback signal adjustment control for adjusting based on a feedback signal fed back by the design under test.

5. The input control method according to claim 3, wherein, The delay control is implemented by: Using a first enable signal and a delay parameter value in a configuration object corresponding to the configuration component to control the delay between the first bypass excitation and the main path excitation, wherein the first enable signal is configured to enable or disable the delay processing of the second bypass excitation.

6. The input control method according to claim 4, wherein, The frequency control is implemented by: Using a second enable signal and a frequency parameter value in a configuration object corresponding to the configuration component to control the generation frequency of the first bypass excitation, wherein the second enable signal is configured to determine a frequency generation mode.

7. The input control method according to claim 4, wherein, The control of the abnormal scenario simulation comprises: Performing signal processing on the main path excitation to construct a first abnormal scenario in which the main path excitation corresponding to the first bypass excitation input to the design under test is cancelled; and / or, Performing error injection processing based on the second bypass excitation to construct a second abnormal scenario in which an error occurs in the first bypass excitation input to the design under test.

8. The input control method according to claim 4, wherein, The feedback signal adjustment control comprises: Obtaining the feedback signal fed back by the design under test, and performing an adjustment control on at least one of the existing signal selection control, delay control, and frequency control based on a third enable signal in a configuration object corresponding to the configuration component, wherein the third enable signal is configured to enable or disable the adjustment of the feedback signal on at least one of the signal selection control, the delay control, and the frequency control.

9. The input control method according to claim 3, wherein, Before loading the configuration component, further comprising: In response to the input of the user, set the configuration parameters corresponding to the configuration component.

10. The input control method according to claim 1, wherein, The obtaining of the interface signal includes: Obtain the interface signal that is converted by the driver based on the excitation transaction packet and driven to the interface between the driver and the design under test.

11. A chip verification method, including the input control method according to any one of claims 1 to 10, the chip verification method further comprising: In response to the design under test obtaining the main path excitation and the first bypass excitation, verify the design under test and obtain the verification result corresponding to the design under test.

12. An input control system for chip verification, including: A driver configured to generate an interface signal; An excitation module configured to: input the interface signal and obtain a main path excitation and a first bypass excitation based on the interface signal, wherein the main path excitation and the first bypass excitation are provided to the design under test, and the signals included in the first bypass excitation are the same as at least some of the signals included in the main path excitation but with different timings.

13. The input control system according to claim 12, wherein, The excitation module includes a configuration component, a bypass excitation generation module, and a main path corresponding to the main path excitation, wherein the configuration component is configured to obtain a target configuration for the interface signal by loading, and the bypass excitation generation module and the main path are respectively connected to the configuration component, so that the bypass excitation generation module and the main path are configured to operate on the interface signal based on the target configuration and perform a first excitation control to obtain the main path excitation and the first bypass excitation.

14. The input control system according to claim 13, wherein, The configuration component includes a signal selection control unit and a signal delay control unit; The main path is configured to obtain the main path excitation generated from the interface signal; The bypass excitation generation module is connected to the signal selection control unit, so that a signal corresponding to at least some of the signals in the main path excitation is selected from the interface signal as the second bypass excitation, The bypass excitation generation module and / or the main path are respectively connected to the signal delay control unit, so that delay control is performed based on the second bypass excitation and / or the main path excitation, so that the first bypass excitation is the same as the corresponding at least some of the signals in the main path excitation but with a timing earlier than the corresponding at least some of the signals in the main path excitation.

15. The input control system according to claim 14, wherein, The configuration component further includes at least one of the following: a signal frequency control unit, an abnormal scenario simulation control unit, a feedback signal adjustment control unit; The bypass excitation generation module is respectively connected to at least one of the signal frequency control unit, the abnormal scenario simulation control unit, and the feedback signal adjustment control unit to respectively implement frequency control for controlling the generation frequency of the first bypass excitation, control of abnormal scenario simulation, and feedback signal adjustment control for adjusting based on the feedback signal fed back by the design under test; and / or, the main path is connected to the abnormal scenario simulation control unit to implement control of abnormal scenario simulation.

16. The input control system according to claim 15, wherein, The bypass excitation generation module includes a first signal control module connected to the signal delay control unit, The bypass excitation generation module further includes: a second signal control module connected to the signal delay control unit and also connected to at least one of the signal frequency control unit, the abnormal scenario simulation control unit, and the feedback signal adjustment control unit. The first signal control module and the second signal control module are respectively connected to the signal selection control unit.

17. An electronic device, comprising: a processor and a memory, wherein, a computer program is stored on the memory, and when the computer program is executed by the processor, the method according to any one of claims 1 to 11 is implemented.

18. A computer-readable storage medium, wherein, A computer program is stored in the storage medium, and when the computer program is executed by the processor, the method according to any one of claims 1 to 11 is implemented.

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