Physical interface design method for extensible chip system

Abstract

The invention relates to the technical field of chip design, in particular to a physical interface design method for an extensible chip system, which comprises the following steps of: designing a universal interface architecture which comprises a data transmission layer, a control layer and a protocol layer; chip particles are interconnected to form a chip through modular design, and the number of the chip particles is dynamically expanded according to performance requirements; a physical interface fusion design is adopted, the high-density interface area is used for short-distance high-bandwidth transmission between the adjacent chip particles, and the high-strength interface area is used for long-distance transmission between the chips; a dynamic configuration mechanism is introduced, and interface parameters are adjusted through software programming. According to the method, the expansibility of the chips can be improved, the compatibility between the chips is good, the data transmission rate and the transmission stability can be effectively improved, and efficient operation of the system is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a physical interface design method for a scalable chip system. Background Art

[0002] A chip, also known as an integrated circuit (IC) in full, is a micro-device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) on a single semiconductor substrate (usually silicon). Its core function is to realize signal processing, logical operation, data storage and other functions through circuit design, and it is called the "brain" or "heart" of an electronic device. The processing power of a chip is jointly defined by its computing efficiency (such as FLOPS / TOPS) per unit time, energy efficiency ratio, and parallel architecture optimization (multi-core / heterogeneous design), supporting the full-scenario computing requirements from intelligent terminals to supercomputer systems.

[0003] The requirements for the processing power of chips vary in different application scenarios. By connecting a certain number of chips together, the required processing power can be obtained quickly. Information is transmitted between chips through a physical interface, and the transmission bandwidth is affected by the parasitic parameters caused by the chip pitch. Generally speaking, the larger the chip pitch, the greater the noise of the physical communication channel, the greater the transmission energy required by the transmitter, and the greater the energy consumption. On the contrary, when the chip pitch is small, the energy consumption is also small, the devices at the transmitter will be simpler, more transceivers can be accommodated per unit area, and the transmission bandwidth is larger.

[0004] In a scalable chip system, in different application scenarios, there is an urgent need for a new interface design method to achieve the largest possible connection bandwidth while ensuring the signal transmission quality. Summary of the Invention

[0005] The purpose of the present invention is to overcome the above-mentioned problems of the prior art, and provide a physical interface design method for a scalable chip system to solve the technical problems of low chip scalability, poor compatibility and low data transmission performance existing in the prior art.

[0006] The above purpose is achieved by the following technical solutions: A physical interface design method for a scalable chip system includes: (1) Design a general interface architecture, which includes a data transmission layer, a control layer and a protocol layer; wherein, the data transmission layer adopts high-speed differential signal transmission technology and includes a high-density interface area and a high-strength interface area; the control layer is used to manage interface operations, including data sending, receiving and caching; the protocol layer is used to define the communication protocol rules between the interface and external devices; (2) Interconnect chip particles through modular design to form a chip, and dynamically expand the number of the chip particles according to performance requirements; (3) Adopt physical interface integration design, use the high-density interface area for short-distance high-bandwidth transmission between adjacent chip particles, and use the high-strength interface area for long-distance transmission between the chips; (4) Introduce a dynamic configuration mechanism to adjust interface parameters through software programming.

[0007] Further, the high-speed differential signal transmission technology adopts low-voltage differential signals or current-mode logic.

[0008] Further, the high-strength interface area integrates multiple micro-spacing transceiver units.

[0009] Further, the interface parameters include one or more of driving strength, transmission rate, and signal modulation method.

[0010] Further, the chip includes at least one of the chip particles, and the chip particle includes at least one high-density interface area and at least one high-strength interface area; in the same chip, short-distance high-bandwidth transmission is achieved between adjacent chip particles through the high-density interface area; long-distance transmission is achieved between adjacent chips through the high-strength interface area.

[0011] A physical interface design method for a scalable chip system provided by the present invention can conveniently expand the functions of the chip system through modular design and dynamic configuration mechanism to meet the ever-changing application requirements, with strong scalability; adopting a standardized design enables the interface to be compatible with a variety of different types of chip modules and external devices, improving the versatility of the system; through the application of high-speed differential signal transmission technology and reasonable interface architecture design, the data transmission rate and transmission stability are effectively improved, ensuring the efficient operation of the system. Description of the Drawings

[0012] Figure 1 It is a schematic structural diagram of a chip particle in a physical interface design method for a scalable chip system according to the present invention; Figure 2 It is a schematic structural diagram of a sending and receiving channel between chips in a physical interface design method for a scalable chip system according to the present invention; Figure 3 It is a schematic diagram of chip particles in a chip being connected through a high-density interface area in a physical interface design method for a scalable chip system according to the present invention; Figure 4 It is a schematic diagram of chips being connected through a high-strength interface area in a physical interface design method for a scalable chip system according to the present invention. Detailed implementation manners

[0013] The present invention will be further described in detail below with reference to the drawings and embodiments. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative work belong to the scope of protection of the present invention.

[0014] This solution provides a physical interface design method for an expandable chip system to improve the expandability, compatibility, and data transmission performance of the chip system, including: (1) Design a general interface architecture, which includes a data transmission layer, a control layer, and a protocol layer; where: The data transmission layer is responsible for the actual transmission of data, and adopts high-speed differential signal transmission technology to improve the data transmission rate and anti-interference ability, and includes a high-density interface area and a high-strength interface area; The control layer is used to manage and coordinate various operations of the interface, including data sending, receiving, and caching, etc.; The protocol layer is used to define the communication protocol rules between the interface and external devices to ensure the correct transmission and parsing of data; (2) Interconnect chip particles through modular design to form a chip, and dynamically expand the number of chip particles according to performance requirements; (3) Adopt a physical interface fusion design, use the high-density interface area for short-distance high-bandwidth transmission between adjacent chip particles, and use the high-strength interface area for long-distance transmission between chips; (4) Introduce a dynamic configuration mechanism to adjust interface parameters through software programming; in this way, the same interface can adapt to different application scenarios and external device requirements.

[0015] In this embodiment, the high-speed differential signal transmission technology adopts low-voltage differential signal (LVDS) or current mode logic (CML).

[0016] As Figure 2 shown, in this embodiment, the high-strength interface area integrates multiple micro-pitch transceiver units, which are used to form a transmission and reception channel with adjacent chips to realize long-distance transmission of data between adjacent chips.

[0017] The interface parameters include one or more of drive strength, transmission rate, and signal modulation method; Among them, the drive strength is automatically matched according to the chip pitch; The transmission rate is hierarchically configured within the range of 10 Gbps to 100 Gbps.

[0018] AsFigure 1 As shown, the chip includes at least one chip particle, and the chip particle includes at least one high-density interface area and at least one high-strength interface area; In the same chip, short-distance high-bandwidth transmission is achieved between adjacent chip particles through the high-density interface area; Long-distance transmission is achieved between adjacent chips through the high-strength interface area The scale of the chip system is linearly extended by increasing the number of interconnected chip particles.

[0019] As Figure 3 shown, as a specific embodiment of this solution, it includes Chip 1 and Chip 2. Chip 1 is composed of 2 chip particles, and the interconnection between the 2 chip particles is achieved by using their respective high-density interface areas; Chip 2 is composed of 4 chip particles, and the interconnection between the 4 chip particles is achieved by using their respective high-density interface areas.

[0020] The interconnection between Chip 1 and Chip 2 is achieved by using the high-strength interface area.

[0021] As Figure 4 shown, as another specific embodiment of this solution, it includes 2 independent chips, each chip contains 2 chip particles, a total of 4 chip particles; the interconnection between the 2 chips is achieved by using the high-strength interface area.

[0022] The above is only to illustrate the implementation manner of the present invention and is not used to limit the present invention. For those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A physical interface design method for a scalable chip system, characterized in that: Comprising: (1) Designing a general interface architecture, where the general interface architecture includes a data transmission layer, a control layer, and a protocol layer; among them, the data transmission layer adopts high-speed differential signal transmission technology and includes a high-density interface area and a high-strength interface area; the control layer is used to manage interface operations, including data sending, receiving, and caching; the protocol layer is used to define the communication protocol rules between the interface and external devices; (2) Interconnecting chip particles through modular design to form a chip, and dynamically expanding the number of the chip particles according to performance requirements; (3) Adopting a physical interface fusion design, using the high-density interface area for short-distance high-bandwidth transmission between adjacent chip particles, and using the high-strength interface area for long-distance transmission between the chips; (4) Introducing a dynamic configuration mechanism to adjust interface parameters through software programming.

2. The physical interface design method for a scalable chip system according to claim 1, characterized in that: The high-speed differential signal transmission technology adopts low-voltage differential signals or current-mode logic.

3. A physical interface design method for a scalable chip system according to claim 1, characterized in that: The high-strength interface area integrates multiple micro-pitch transceiver units.

4. A physical interface design method for a scalable chip system according to claim 1, characterized in that: The interface parameters include one or more of driving strength, transmission rate, and signal modulation mode.

5. A physical interface design method for a scalable chip system according to claim 1, characterized in that: The chip includes at least one of the chip particles, and the chip particle includes at least one high-density interface area and at least one high-strength interface area; In the same chip, short-distance high-bandwidth transmission is achieved between adjacent chip particles through the high-density interface area; Long-distance transmission is achieved between adjacent chips through the high-strength interface area.

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