Separated three-dimensional processor

Abstract

A separate three-dimensional processor (100) includes a first chip (100a) and a second chip (100b). The first chip (100a) includes a three-dimensional memory (3D-M) array (170), and the memory array (170) includes a three-dimensional structure. The second chip (100b) comprises a logic circuit (180) and an off-chip peripheral circuit component (190) of a 3D-M array (170), and the second chip (100b) only comprises a standard back-end structure.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly, to processors. Background Art

[0002] Processors (including CPUs, GPUs, FPGAs, etc.) are widely used in fields such as mathematical calculations, computer simulations, programmable gate arrays, pattern processing, neural networks, etc. Traditional processor chips are based on two-dimensional integration, and their logic circuits (such as arithmetic logic units, control units, etc.) and storage circuits (internal memories, including RAM for caching and ROM for storing lookup tables, etc.) are on the same plane (i.e., the surface of the semiconductor substrate). Since the main function of the processor chip is arithmetic logic operations, the capacity of its internal memory is very small, resulting in limited performance.

[0003] With the emergence of three-dimensional memory (abbreviated as 3D-M), various difficulties encountered by the above-mentioned traditional processors and their architectures have been largely solved. The memory cells of 3D-M are distributed in three-dimensional space, that is, stacked on top of each other in a direction perpendicular to the substrate. Chinese Patent 02131089.0 (authorized publication number: CN 1285125C; authorization date: November 15, 2006) proposes a processor based on 3D-M (i.e., a three-dimensional processor), which integrates the logic circuit into the substrate under the 3D-M array to form an integrated three-dimensional processor. The integrated three-dimensional processor is in a single three-dimensional processor chip.

[0004] Figures 1A - 1B Shows an integrated three-dimensional processor 80, which includes a 3D-M array 77 and a logic circuit 78 integrated therewith. The 3D-M array 77 stores data, and the logic circuit 78 processes at least part of the data stored in the 3D-M array 77. In the three-dimensional processor chip, the chip area occupied by the storage array 77 is the array area 70, and the chip area outside the array area 70 is the non-array area 71 ( Figures 1A - 1B ) The array area 70 includes a substrate circuit 0K and a 3D-M array 77 stacked on the substrate circuit 0K ( Figure 1B). The substrate circuit 0K is formed on the semiconductor substrate 0, under the 3D-M array 77. It includes transistors 0t and substrate interconnect lines 0i. The transistors 0t are formed in the semiconductor substrate 0 and are electrically coupled to each other through the substrate interconnect lines 0i. The substrate interconnect lines 0i include two interconnect line layers 0m1 - 0m2, and each interconnect line layer (such as 0m1) includes multiple interconnect lines (such as 0m) in the same physical plane. The 3D-M array 77 includes four address line layers 0a1 - 0a4, and each address line layer (such as 0a1) includes multiple address lines (such as 1a) in the same physical plane. These address line layers 0a1 - 0a4 form two storage layers 16A, 16B. Among them, the storage layer 16A is stacked on the substrate circuit 0K, and the storage layer 16B is stacked on the storage layer 16A. The memory cells (such as 7aa) are located at the intersections of two address lines (such as 1a, 2a). The storage layers 16A, 16B are electrically coupled to the substrate circuit 0K through contact vias 1av, 3av respectively.

[0005] The non-array region 71 also includes a part of the substrate circuit 0K ( Figure 1B ). Since the non-array region 71 does not include the 3D-M array 77, the number of its back-end-of-line (BEOL) layers is much less than that of the array region 70. In this specification, the BEOL layer is an independent conductive layer of a back-end process (excluding vias). In Figure 1B , the array region 70 includes six BEOL layers, including the two interconnect line layers 0m1 - 0m2 of the substrate circuit 0i and the four address line layers 0a1 - 0a4 of the storage array 77; while the non-array region 71 only includes two BEOL layers, including the two interconnect line layers 0m1 - 0m2 of the substrate circuit 0i. In the non-array region 71, the space 72 on the substrate circuit 0K contains neither memory cells nor interconnect lines, and this space 72 is actually wasted.

[0006] The array region 70 includes multiple 3D-M arrays 77 and their attached local peripheral circuits 75 and logic circuits 78 ( Figure 1A ). The local peripheral circuits 75 and logic circuits 78 are formed in the substrate 0, and they are near the projection of the 3D-M array 77 on the substrate 0. Since the 3D-M array 77 is stacked on the local peripheral circuits 75 and the logic circuits 78 and is not located in the substrate 0, it is represented by a dotted line here. On the other hand, the non-array region 71 includes the global peripheral circuits 73 of the 3D-M array 77, which are formed in the substrate 0 and are located outside the projections of all 3D-M arrays 77 on the substrate 0. The local peripheral circuits 75 and the global peripheral circuits 73 are collectively referred to as the peripheral circuits 79. The peripheral circuits 73, 75, 79 located in the same chip 80 as the 3D-M array 77 are called on-chip peripheral circuit components.

[0007] In the three-dimensional processor chip 80, the non-array region 71 occupies a large amount of chip area. Currently, the non-array region 71 occupies ~30% of the chip area; for a large-capacity memory, this ratio will further increase. Therefore, the array efficiency of the integrated three-dimensional processor 80 is low. In this specification, the array efficiency is the ratio of the total projected area of the 3D-M array 77 on the substrate 0 in the chip to the total chip area.

[0008] The mainstream view of integrated circuits is that the higher the integration degree, the better, that is, integration can reduce costs and improve performance. Traditional integrated circuits tend to be monolithic integration, that is, all circuit components are integrated into one chip. Monolithic integration is effective for two-dimensional circuits, but it is no longer effective for three-dimensional circuits - especially when three-dimensional circuits (such as three-dimensional storage) are mixed with two-dimensional circuits. In this specification, a two-dimensional circuit means that the active components of the circuit (such as transistors, memory cells, etc.) are distributed on a two-dimensional plane (such as the positive surface of a semiconductor substrate); a three-dimensional circuit means that the active components of the circuit (such as transistors, memory cells, etc.) are distributed in a three-dimensional space (stacked on top of each other in a direction perpendicular to the positive surface of the semiconductor substrate).

[0009] When applied to the integration of three-dimensional circuits and two-dimensional circuits, the defects of monolithic integration are multi-faceted. First, since their back-end processes are not compatible. Blind integration will result in manufacturing logic circuits 78 and peripheral circuits 79 using the complex process for manufacturing the 3D-M array 77. Coupled with the fact that the integrated three-dimensional processor chip 80 has a low array efficiency, blind integration will increase the overall cost of the three-dimensional processor chip 80.

[0010] Secondly, since the 3D-M array 77 has high process requirements, the back-end process of the three-dimensional processor chip 80 needs to be optimized for the 3D-M array 77, which has to sacrifice the performance of the logic circuits 78 and peripheral circuits 79 to a certain extent. For the integrated three-dimensional processor 80, the logic circuits 78 and peripheral circuits 79 can only contain a few (such as two) interconnect layers 0m1 - 0m2 contained in the substrate interconnect layer 0i, or use slower high-temperature interconnect materials (materials that can withstand the high-temperature back-end process for manufacturing the 3D-M array 77, such as tungsten), which will reduce the overall performance of the three-dimensional processor chip 80.

[0011] Finally, after adopting monolithic integration, the chip area occupied by the logic circuits 78 is limited by the projected area of the 3D-M array 77 on the substrate, and it can only achieve limited processing functions. In addition, since the logic circuits 78 are solidified with the 3D-M array 77, the three-dimensional processor 80 can only achieve fixed functions. If the three-dimensional processor 80 also needs to implement other functions, then the entire three-dimensional processor 80 (including its 3D-M array 77 and logic circuits 78) needs to be redesigned and manufactured, which requires a large amount of time and cost. Summary of the Invention

[0012] The main object of the present invention is to provide a three-dimensional processor with a lower overall cost.

[0013] Another object of the present invention is to provide a three-dimensional processor with better overall performance.

[0014] Another object of the present invention is to provide a three-dimensional processor with more powerful and flexible functions.

[0015] To achieve these and other objects, the present invention follows design principles that are completely different from traditional processors: the computing system is divided according to dimensions rather than functions, that is, three-dimensional circuits and two-dimensional circuits are anti-integrated. Specifically, the three-dimensional circuit and the two-dimensional circuit are divided into different chips as much as possible so that they can be optimized separately. Accordingly, the present invention provides a separate three-dimensional processor (100), which is characterized by including: a plurality of storage and computing units (abbreviated as storage-computing units) (100aa-100mn), each storage-computing unit (100ij) including at least one three-dimensional storage (3D-M) array (170) and a logic circuit (180); a first chip (100a) and a second chip (100b), the first chip (100a) including the 3D-M array (170), and the second chip (100b) including at least part of the logic circuit (180) and at least one off-chip peripheral circuit component (190) of the 3D-M array (170); the first chip (100a) and the second chip (100b) are electrically coupled through a plurality of inter-chip connections (160). Briefly, the first chip is a storage chip that includes a plurality of functional layers; the second chip is a logic chip that has only one functional layer.

[0016] The separate three-dimensional processor is different from the integrated three-dimensional processor: in the integrated three-dimensional processor, all peripheral circuit components of the 3D-M array are located on the same chip as the 3D-M array; while in the separate three-dimensional processor, at least one peripheral circuit component of the 3D-M array is not located on the first chip but on the second chip. These peripheral circuit components located on the second chip are called off-chip peripheral circuit components. In design, the circuit partitioning strategy adopted by the separate three-dimensional processor is to make the second chip include as many off-chip peripheral circuit components as possible. The advantage of this partitioning is that the array efficiency of the first chip is greatly improved. Note that although the first chip includes the 3D-M array, since it does not include off-chip peripheral circuit components, the first chip cannot work properly as a storage chip independently, such as its performance does not meet the industry standards of similar storage chips.

[0017] In a separated three-dimensional processor, since the first chip and the second chip can be designed and manufactured separately, they can have completely different back-end structures. Since the back-end structure of the second chip can be optimized separately, its off-chip peripheral circuit components and logic circuits have lower costs and better performance than the corresponding circuits in an integrated three-dimensional processor. A comparison between the separated three-dimensional processor and the integrated three-dimensional processor is made below.

[0018] First, since at least part of the peripheral circuits and logic circuits are not included in the first chip, its array efficiency is relatively high. In addition, as a two-dimensional circuit, the number of back-end wiring layers of the second chip 100b is much lower than that of an integrated three-dimensional processor and can be manufactured using standard back-end processes. Since the wafer cost is basically proportional to the number of back-end wiring layers, the wafer cost of the second chip is much lower than that of an integrated three-dimensional processor. Therefore, the total chip cost of the separated three-dimensional processor (including the first and second chips) is lower than that of the integrated three-dimensional processor (which only contains one chip). Even when the additional bonding cost is included, the overall cost of the separated three-dimensional processor is lower than that of the integrated three-dimensional processor.

[0019] Second, since they can be optimized separately, the performance of the off-chip peripheral circuit components and logic circuits in the separated three-dimensional processor is better than that of the corresponding circuits in the integrated three-dimensional processor. In one embodiment, the number of interconnect layers (such as four or more) in the second chip (which contains off-chip peripheral circuit components) is greater than the number of interconnect layers (such as two) in the substrate circuit (which contains on-chip peripheral circuit components) in the integrated three-dimensional processor (or the first chip). In another embodiment, the second chip uses high-performance interconnect materials (such as copper), instead of the high-temperature interconnect materials (such as tungsten) used in the integrated three-dimensional processor (or the first chip). Therefore, the overall performance of the separated three-dimensional processor is better than that of the integrated three-dimensional processor.

[0020] Finally, in an integrated three-dimensional processor, since the logic circuits are confined to one chip (such as within the projected area of the 3D-M array on the substrate), its area is limited and its functions are also limited. In comparison, in a separated three-dimensional processor, since the logic circuits can be formed on two chips (the first part of the logic circuit is located within the projected area of the 3D-M array on the substrate in the first chip, and the second part of the logic circuit is located in the second chip), its larger area endows the separated three-dimensional processor with more powerful processing capabilities. In addition, since the second chip is designed and produced separately, it has greater flexibility in design and production. By combining the same first chip with second chips with different functions, processing functions suitable for different application scenarios can be realized. Even better, these different processing functions can be achieved within a shorter design cycle and with a lower design budget. Therefore, the separated three-dimensional processor is more powerful and flexible in function. Description of the Drawings

[0021] Figure 1A is a circuit layout diagram of an integrated three-dimensional processor (prior art); Figure 1B is a cross-sectional view of the three-dimensional processor.

[0022] Figures 2A - 2C is an overall introduction to a discrete three-dimensional processor: Figure 2A is its circuit block diagram; Figure 2B is a circuit block diagram of a storage and computing unit; Figure 2C is a circuit layout diagram of two chips in a discrete three-dimensional processor.

[0023] Figures 3A - 3D are cross-sectional views of four discrete three-dimensional processors.

[0024] Figures 4A - 4D are cross-sectional views of four first chips.

[0025] Figure 5 is a cross-sectional view of a second chip.

[0026] Figure 6A is a circuit layout diagram of a first chip; Figures 6BA - 6BB are circuit layout diagrams of two second chips.

[0027] Figures 7A - 7C are circuit block diagrams of three storage and computing units.

[0028] Figures 8A - 8C are circuit layout diagrams of three storage and computing units in the first and second chips.

[0029] Figure 9 is a circuit block diagram of a storage and computing unit in a three-dimensional pattern processor.

[0030] Figure 10 is a circuit block diagram of a storage and computing unit in a three-dimensional neural network processor.

[0031] Note that these drawings are only schematic diagrams and are not drawn to scale. For the sake of visibility and convenience, some dimensions and structures in the drawings may be enlarged or reduced. In different embodiments, the letter suffixes after the numbers represent different instances of the same type of structure; the same number prefixes represent the same or similar structures.

[0032] In this specification, " / " represents a relationship of "and" or "or". "Memory" generally refers to any semiconductor-based information storage device that can store information either permanently or temporarily. "Memory array" is a collection of memory cells that share at least one address line. "Circuit in substrate" means that the active components (such as transistors, memory cells) of the circuit are located in the substrate, although the interconnects connecting the active components in the circuit can be located above the substrate. "Circuit on substrate" means that both the active components (such as transistors, memory cells) and their interconnects of the circuit are located above the substrate. "Electrically coupled" means any form of coupling through which an electrical signal can be transmitted from one component to another. "Mode" can refer to either an abstract mode or the physical manifestation of a mode (i.e., the data associated with the mode), and this specification makes no distinction between them. Detailed Description of the Invention

[0033] Figures 2A - 2C This is an overall introduction to a separate three-dimensional processor 100. Figure 2A This is its circuit block diagram. The separate three-dimensional processor 100 can not only process data but also store data. More importantly, a large part of the data it processes is stored locally and in close proximity. The separate three-dimensional processor 100 includes a memory and computing array containing m x n memory and computing units 100aa - 100mn. Taking the memory and computing unit 100ij as an example, it has an input 110 and an output 120 ( Figure 2B ). Generally speaking, a three-dimensional processor 100 can include thousands of memory and computing units 100aa - 100mn, and it supports large-scale parallel computing.

[0034] Figure 2B This is a circuit block diagram of a memory and computing unit 100ij. The memory and computing unit 100ij includes a memory circuit 170 and a logic circuit 180, which are electrically coupled through a plurality of inter-chip connections 160 (see Figures 3A - 3D ). The memory circuit 170 includes at least one 3D-M array. The 3D-M array stores data, and the logic circuit 180 processes part of the data. Since the 3D-M array 170 and the logic circuit 180 are not located on the same chip (see Figure 2C ), the 3D-M array 170 is represented by a dashed line.

[0035] Figure 2CShows a specific implementation of a separated three-dimensional processor 100, which includes at least one first chip (also known as a memory chip) 100a and at least one second chip (also known as a logic chip) 100b. The first chip 100a contains three-dimensional circuits, which are 3D-M arrays 170 in this embodiment. In some embodiments, the first chip 100a may also contain on-chip peripheral circuit components of the 3D-M array 170. The second chip 100b contains two-dimensional circuits, which are logic circuits 180 and a peripheral circuit component 190 of the 3D-M array 170 in this embodiment. The inter-chip connection 160 realizes electrical coupling between the first chip 100a and the second chip 100b. Since the peripheral circuit component 190 and the 3D-M array 170 are in different chips, it is called an off-chip peripheral circuit component. Note that part of the logic circuits may be located in the first chip 100a. For example, some logic circuits may be integrated under the 3D-M array 170. For simplicity, in this specification, unless otherwise specified, the logic circuits refer to the logic circuits 180 located on the second chip 100b.

[0036] The circuit partitioning strategy adopted by the separated three-dimensional processor 100 is to make the second chip 100b contain as many off-chip peripheral circuit components 190 as possible. The peripheral circuit component 190 is an organic part of the memory chip; a memory chip lacking it (such as the first chip 100a) cannot independently implement the basic functions of a memory (such as its performance does not meet the industry standards of similar memory chips). Typical peripheral circuit components 190 may be an address decoder, a read amplifier circuit, a write circuit, a read voltage generation circuit, a write voltage generation circuit, a data buffer, or a part of them.

[0037] Since the read / write voltages are generally different from the value of the external power supply voltage, a read / write voltage generation circuit is required to convert the external power supply voltage into the read / write voltages of the 3D-M array 170. The voltage generator preferably uses a DC-DC converter. The DC-DC converter includes a booster and a buck converter. The output voltage of the booster is higher than the input voltage, and the output voltage of the buck converter is lower than the input voltage. Examples of the booster include a charge pump and a boost converter, etc. Examples of the buck converter include a low dropout regulator and a buck converter, etc.

[0038] Figures 3A - 3D Are cross-sectional views of four separated three-dimensional processors 100, which focus on showing various implementation methods of the inter-chip connection 160. In Figure 3AIn the embodiment, the first chip 100a and the second chip 100b are stacked on top of each other, that is, stacked in a direction perpendicular to the chip surface. Among them, the front sides (i.e., the surfaces containing circuits) of the first chip 100a and the second chip 100b are both facing upward (+z direction), and the inter-chip connection 160 is realized between them through bonding wires 160w.

[0039] In Figure 3B the embodiment, the first chip 100a and the second chip 100b are bonded face to face. Specifically, the front side of the first chip 100a faces upward (+z direction); while the second chip 100b is flipped so that its front side faces downward (-z direction). The inter-chip connection 160 is realized between them through micro-bumps 160x. In this embodiment, the first chip 100a and the second chip 100b have the same chip area, and all their sides are aligned. For example, the left edge of the first chip 100a is aligned with the left edge of the second chip 100b; the right edge of the first chip 100a is aligned with the right edge of the second chip 100b. This is because the separated three-dimensional processor 100 is formed by cutting a bonded wafer, where the bonded wafer aligns and bonds the first wafer containing the first chip 100a and the second wafer containing the second chip 100b.

[0040] Figure 3C the embodiment includes two memory chips 100a1, 100a2 and a logic chip 100b. To avoid confusion, in this figure, the first chip is referred to as memory chips 100a1, 100a2, and the second chip is referred to as logic chip 100b. Each of the memory chips 100a1, 100a2 contains a plurality of 3D-M arrays; they are stacked on top of each other and are electrically coupled through through-silicon vias (abbreviated as TSVs) 160y. The stacked memory chips 100a1, 100a2 and the logic chip 100b are electrically coupled through micro-bumps 160x. The TSVs 160y and the micro-bumps 160x are the inter-chip connections 160. In this embodiment, the logic circuit 180 in the logic chip 100b processes the data stored in the two memory chips 100a1, 100a2. Similar to Figure 3B the embodiment in, in this embodiment, the first chip 100a and the second chip 100b have the same chip area; all their sides are aligned.

[0041] Figure 3DHybrid bonding is adopted. Specifically, a first insulating medium 168a is formed on the front surface of the first chip 100a, and then a plurality of first channel holes 160za are formed in the first insulating medium 168a. In addition, a second insulating medium 168b is also formed on the front surface of the second chip 100b, and then a plurality of second channel holes 160zb are formed in the second insulating medium 168b. After flipping the second chip 100b, the first channel holes 160za and the second channel holes 160zb are aligned, and the first and second chips 100a, 100b are adhered. Accordingly, the first and second chips 100a, 100b achieve an inter-chip connection 160 through the electrically contacting first and second channel holes 160za, 160zb. Since the channel holes 160za, 160zb are formed through standard chip manufacturing processes, they can have very small sizes and a large number. Therefore, a high-bandwidth inter-chip connection 160 can be formed between the first chip 100a and the second chip 100b. In this embodiment, the channel holes 160za, 160zb are collectively referred to as vertical interconnect access (VIA). Similar to Figure 3B the embodiment in, in this embodiment, the first chip 100a and the second chip 100b have the same chip area, and all their sides are aligned In the above embodiment, the distance between the storage circuit 170 and the logic circuit 180 is relatively close (compared with the traditional von Neumann architecture). In addition, for Figures 3B - 3D the embodiment of — especially Figures 3C - 3D the embodiment of, the number of inter-chip connections (TSV or VIA) 160 is huge, and it can achieve ultra-high bandwidth between the storage circuit 170 and the logic circuit 180. Coupled with massive parallel processing ( Figure 2A ), the separated three-dimensional processor 100 has excellent performance.

[0042] Figures 4A - 4D are cross-sectional views of four first chips 100a, in which the 3D-M array 170 adopts monolithic integration, that is, its memory cells are stacked vertically with each other, and there is no semiconductor substrate between the memory cells.

[0043] According to its physical structure, 3D-M is divided into three-dimensional horizontal memory (abbreviated as 3D-M H ), and three-dimensional vertical memory (abbreviated as 3D-M V ). In 3D-M H all address lines are horizontal, and its memory cells form a plurality of horizontal memory layers, and the horizontal memory layers are vertically stacked on the substrate circuit. In 3D-MH A typical example of it is 3D-XPoint. 3D-M V At least one set of address lines of it is vertical, and its memory cells form multiple vertical memory strings which are arranged side by side on the substrate circuit. 3D-M V A typical example of it is 3D-NAND. 3D-M H is faster, while 3D-M V has a larger storage density.

[0044] According to the length of information storage time, 3D-M is divided into 3D-RAM (three-dimensional random access memory) and 3D-ROM (three-dimensional read-only memory). 3D-RAM can temporarily store information and it is mainly used for caching; 3D-ROM can store information for a long time. The data of various 3D-ROMs can be rewritten and they are a type of non-volatile memory (NVM).

[0045] According to its programmable degree, 3D-M is divided into three-dimensional writable memory (abbreviated as 3D-W) and three-dimensional printed memory (abbreviated as 3D-P). The information stored in 3D-W is entered by means of electrical programming. According to the number of times it can be programmed, 3D-W is further divided into three-dimensional one-time-programmable memory (abbreviated as 3D-OTP) and three-dimensional multiple-time-programmable memory (abbreviated as 3D-MTP, including repeated programming). A common 3D-MTP is 3D-XPoint and 3D-NAND. Other 3D-MTPs include memristor, resistive random access memory (RRAM), phase change memory (PCM), programmable metallization cell (PMC), conductive bridging random-access memory (CBRAM), etc.

[0046] The information stored in 3D-P is entered in a printing manner (printing method) during the factory production process. This information is permanently fixed and cannot be changed after leaving the factory. The printing method can be photo-lithography, nano-imprint, e-beam lithography, DUV scanning exposure, laser programming, etc. A common 3D-P is a three-dimensional mask-programmable read-only memory (3D-MPROM), which enters data through mask programming by photo-lithography. Since it has no requirement for electrical programming, the 3D-P memory cell can be biased at a higher voltage when reading. Therefore, the read speed of 3D-P is faster than that of 3D-W.

[0047] Figures 4A - 4B The first chip 100a in contains a substrate circuit 0Ka and a 3D-M stacked on the substrate circuit 0Ka H array 170. The substrate circuit 0Ka contains transistors 0t and interconnect lines 0ia. The transistors 0t are formed in the first semiconductor substrate 0a and are electrically coupled to each other through the substrate interconnect lines 0ia. The substrate interconnect lines 0ia contain two interconnect line layers 0m1a - 0m2a, and each interconnect line layer (such as 0m1a) contains multiple interconnect lines (such as 0m) in the same physical plane. 3D-M H array 170 contains four address line layers 0a1a - 0a4a, and each address line layer (such as 0a1a) contains multiple address lines (such as 1a) in the same physical plane. These address line layers 0a1a - 0a4a form two storage layers 16A, 16B. Among them, the storage layer 16A is stacked on the substrate circuit 0Ka, and the storage layer 16B is stacked on the storage layer 16A. The memory cell (such as 7aa) is located at the intersection of two address lines (such as 1a, 2a). The storage layers 16A, 16B are respectively connected to the substrate circuit 0Ka through contact via holes 1av, 3av to achieve on-chip connection 150. The contact via holes 1av, 3av contain multiple via holes, and each via hole penetrates at least one insulating layer and is electrically coupled to the via holes above and below it. In Figures 4A - 4B , the substrate circuit 0Ka contains at least part of the peripheral circuit of the 3D-M H array 170. In some embodiments, the substrate circuit 0Ka may contain part of the logic circuit.

[0048] Figure 4A The 3D-M in HThe array 170 is a 3D-W. Its memory cell 7aa contains a programming film 5 and a diode film 6. The programming film 5 can be an antifuse film (programmable once, for 3D-OTP), or a resistive RAM (RRAM) film (reprogrammable, for 3D-MTP). The diode film 6 has the following general characteristics: at the read voltage, its resistance is small; when the applied voltage is less than the read voltage or in the opposite direction of the read voltage, its resistance is large. The diode film can be a P-i-N diode, or a metal oxide (such as TiO2, etc.) diode, etc.

[0049] Figure 4B in the 3D-M H The array 170 is a 3D-P. It contains at least two types of memory cells: a high-resistance memory cell 7ab and a low-resistance memory cell 7ac. The low-resistance memory cell 7ac contains a diode film 6, which is similar to the diode film 6 in the 3D-W. The high-resistance memory cell 7ab also contains a high-resistance film 9, which is an insulating film (such as silicon oxide / silicon nitride). In the production process, the high-resistance film 9 at the location of the low-resistance memory cell 7ac is physically removed.

[0050] Figures 4C - 4D The first chip 100a in contains a substrate circuit 0Ka and a 3D-M V array 170 stacked on the substrate circuit 0Ka. The substrate circuit 0Ka is similar to the Figures 4A - 4B substrate circuit in. In some embodiments, there is no substrate circuit 0Ka under the 3D-M V array 170. The 3D-M V array 170 contains multiple vertically stacked horizontal address line layers 0a1a - 0a8a, and each horizontal address line layer (such as 0a5a) contains multiple horizontal address lines (such as 15) in the same physical plane. The 3D-M V array 170 also contains a group of vertical address lines, which are perpendicular to the substrate 0a (i.e., along the +z direction). The 3D-M V has the highest storage density among all semiconductor memories. For simplicity, Figures 4C - 4D in the 3D-M V the on-chip connections 150 for the electrical coupling between the array 170 and the substrate circuit 0Ka are not drawn, and they are well-known to those skilled in the art.

[0051] Figure 4C in the 3D-M VThe array 170 uses transistors or transistor-like devices as memory cells. It includes a plurality of vertical and side-by-side arranged memory strings 16X, 16Y. Each memory string (such as 16Y) includes a plurality of vertically stacked memory cells (such as 18ay - 18hy). Each memory cell (such as 18fy) includes a vertical transistor, and the vertical transistor includes a gate (a horizontal address line) 15, a memory film 17, and a vertical channel (a vertical address line) 19. The memory film 17 may include composite films such as silicon oxide - silicon nitride - silicon oxide, silicon oxide - polysilicon - silicon oxide, etc. This 3D-M V The array 170 is a 3D-NAND, and its manufacturing process is well-known to those skilled in the art.

[0052] Figure 4D in the 3D-M V The array 170 uses diodes or diode-like devices as memory cells. It includes a plurality of vertically arranged and side-by-side memory strings 16U - 16W. Each memory string 16U includes a plurality of vertically stacked memory cells 18au - 18hu. 3D-M V The array 170 includes a plurality of vertically stacked horizontal address lines (word lines) 15. After etching a plurality of memory wells 11 that penetrate these horizontal address lines 15, a programming film 13 is covered on the sidewalls of the memory wells 11, and a conductor material is filled to form vertical address lines 19 (bit lines). The conductor material can be a metal material or a doped semiconductor material. The memory cells 18au - 18hu are formed at the intersections of the word lines 15 and the bit lines 19. The programming film 13 can be one-time programmable (OTP, such as an anti-fuse film) or multi-time programmable (MTP, such as an RRAM film).

[0053] To reduce the mutual interference between memory cells, it is preferably to form a diode between the word line 15 and the bit line 19. In one embodiment, the programming film 13 itself can have certain diode electrical characteristics. In another embodiment, a separate diode film (not shown here) can be deposited on the sidewalls of the memory wells 11. In a third embodiment, a built-in diode (such as a P-N diode, a Schottky diode) can be naturally formed between the word line 15 and the bit line 19. Details about the built-in diode can be referred to Chinese Patent Application 201811117502.7 (filing date: September 20, 2018).

[0054] In Figures 4A - 4D the embodiment of, the number (N A ) of the back-end wiring layers of the 3D-M array 170 is the total number of back-end wiring layers within the chip area where the 3D-M array 170 is located (starting from the surface of the substrate 0a and not including the via layer). For example, Figures 4A - 4B in which N A is 6 (0m1a - 0m2a, 0a1a - 0a4a), Figure 4CN in the middle A is 10 (0m1a - 0m2a, 0a1a - 0a8a), Figure 4D N in the middle A is 11 (0m1a - 0m2a, 0a1a - 0a8a, BL1). The thickness (T A ) of the back-end wiring layer of the 3D-M array 170 is the height from the substrate surface 0a to the highest interconnect line within the chip area where the 3D-M array 170 is located.

[0055] Figure 5 The second chip 100b in [] is a traditional two-dimensional circuit 0Kb, which only contains a standard back-end structure and is used to implement the logic circuit 180 and off-chip peripheral circuit components 190. The second chip 100b contains transistors 0t and interconnect lines 0ib. The transistors 0t are formed in the second semiconductor substrate 0b and are electrically coupled to each other through the interconnect lines 0ib. In this embodiment, the interconnect lines 0ib contain four interconnect layers 0m1b - 0m4b, and each interconnect layer (such as 0m1b) contains multiple interconnect lines (such as 0m) in the same physical plane. Similar to Figures 4A - 4D , the number (N L ) of the back-end wiring layers of the logic circuit 180 is the total number of back-end wiring layers within the chip area where the logic circuit 180 is located (starting from the surface of the substrate 0b, excluding the via layer); the height (T L ) of the back-end wiring layer of the logic circuit 180 is the height from the surface of the substrate 0b to the highest interconnect line within the chip area where the logic circuit 180 is located. Similarly, the number (N P ) of the back-end wiring layers of the off-chip peripheral circuit components 190 is the total number of back-end wiring layers within the chip area where the off-chip peripheral circuit components 190 are located (starting from the surface of the substrate 0b, excluding the via layer); the height (T P ) of the back-end wiring layer of the off-chip peripheral circuit components 190 is the height from the surface of the substrate 0b to the highest interconnect line within the chip area where the off-chip peripheral circuit components 190 are located. Note that although the logic circuit 180 and the off-chip peripheral circuit components 190 are also located in the second chip 100b, the numbers (N L , N P ) of their back-end wiring layers are not necessarily the same; the thicknesses (T L , T P ) of the back-end wiring layers are also not necessarily the same.

[0056] To determine whether anti-integration is necessary, the back-end structures of the first chip 100a ( Figures 4A - 4D ) and the second chip 100b ( Figure 5 ) can be compared. The number (N a ) of the back-end wiring layers in the first chip 100a is greater than the number (N b). For example, Figures 4A - 4B the first chip 100a in Figures 4A - 4B has six back-end wiring layers (0m1a - 0m2a, 0a1a - 0a4a), Figures 4C - 4D the first chip 100a in Figures 4C - 4D has ten back-end wiring layers (0m1a - 0m2a, 0a1a - 0a8a), and their numbers are both greater than Figure 5 the four back-end wiring layers (0m1b - 0m4b) of the second chip 100b in Figure 5 . Even if only considering the number of address line layers in the first chip 100a, it is greater than or equal to the number of back-end wiring layers in the second chip 100b. Especially for the 3D-M V array 170, the number of address line layers in the first chip 100a (approximately equal to the number of all memory cells in the memory string, greater than a hundred layers) is much greater than the number of back-end wiring layers in the second chip 100b (such as four layers), at least twice as much.

[0057] In addition to comparing the number (N) of back-end wiring layers of the first chip 100a and the second chip 100b, it is also possible to determine whether anti-integration is necessary by comparing the number (N) or thickness (T) of back-end wiring layers of the three core components (3D-M array 170, logic circuit 180, off-chip peripheral circuit components 190) in the split three-dimensional processor 100. There are the following two cases: A) If the difference in the number of back-end wiring layers between the 3D-M array 170 and the off-chip peripheral circuit components 190 is much greater than the difference in the number of back-end wiring layers between the logic circuit 180 and the off-chip peripheral circuit components 190 (i.e., |N A - N P | >> |N L - N P |, preferably greater than 3 times), then it is of positive significance to anti-integrate (split) the 3D-M array 170 and the off-chip peripheral circuit components 190 into two chips. B) If the difference in the thickness of the back-end wiring layers between the 3D-M array 170 and the off-chip peripheral circuit components 190 is greater than the difference in the thickness of the back-end wiring layers between the logic circuit 180 and the off-chip peripheral circuit components 190 (i.e., |T A - T P | > |T L - T P |), then it is also of positive significance to anti-integrate (split) the 3D-M array 170 and the off-chip peripheral circuit components 190 into two chips. Obviously, even if the memory array 170 is not 3D-M, as long as it meets the above conditions A) or B), it is also suitable for anti-integration. For example, the back-end structure of a conventional DRAM memory (the capacitor in its memory cell has a three-dimensional structure) is very different from the back-end structures of the logic circuit and the peripheral circuit, and it is also suitable for anti-integration.

[0058] In the discrete three-dimensional processor 100, since the first chip 100a and the second chip 100b can be designed and manufactured separately, they can have quite different backend structures. Since the backend structure of the second chip 100b can be optimized separately, its off-chip peripheral circuit components 190 and logic circuit 180 have lower costs and better performance than the corresponding circuits in the integrated three-dimensional processor 80.

[0059] First, since the first chip 100a does not contain off-chip peripheral circuit components 190 and logic circuit 180, its array efficiency is relatively high. In addition, as a two-dimensional circuit, the number of backend wiring layers of the second chip 100b is much lower than that of the integrated three-dimensional processor 80 and can be manufactured using conventional processes. Since the wafer cost is basically proportional to the number of backend wiring layers, the wafer cost of the second chip 100b is much lower than that of the integrated three-dimensional processor 80. Therefore, the total chip cost of the discrete three-dimensional processor 100 (including the first and second chips 100a, 100b) is lower than that of the integrated three-dimensional processor 80 (which contains only one chip). Even when the additional bonding cost is included, the overall cost of the discrete three-dimensional processor 100 is still lower.

[0060] Second, since they can be optimized separately, the performance of the off-chip peripheral circuit components 190 and logic circuit 180 in the discrete three-dimensional processor 100 is better than that of the corresponding circuits in the integrated three-dimensional processor 80. In one embodiment, the number of wiring layers in the interconnecting wires 0ib of the second chip 100b is greater than the number of wiring layers in the substrate interconnecting wires 0ia (including in-chip peripheral circuits) of the first chip 100a. For example, Figure 5 the second chip 100b has four wiring layers (0m1b - 0m4b), which is greater than Figures 4A - 4D the two wiring layers (0m1a - 0m2a) of the first chip 100a (which may contain in-chip peripheral circuit components). Therefore, the circuit layout of the second chip 100b is easier than that of the first chip 100a. In another embodiment, the second chip 100b (including logic circuit 180 and off-chip peripheral circuit 190) can use high-speed interconnecting wire materials (such as copper), while the first chip 100a (including in-chip peripheral circuits) can only use high-temperature interconnecting wire materials (such as tungsten). Since the resistivity of at least some of the backend wiring layers in the in-chip peripheral circuit components is greater than that of the same backend wiring layers in the off-chip peripheral circuit components (190), the in-chip peripheral circuit components are slower.

[0061] Finally, in the integrated three-dimensional processor 80, since the logic circuit 78 is confined to one chip 80 (such as Figure 1AIn the projection area of the 3D-M array 77 on the substrate 0), its area is limited and its function is also limited. In contrast, in the separate three-dimensional processor 100, since the logic circuit 180 can be formed in two chips 100a, 100b (for example, the first part of the logic circuit is located Figure 6A below the 3D-M array 170ij of the first chip 100a, similar to Figure 1A the logic circuit 78 located below the 3D-M array 77; the second part of the logic circuit is located Figure 6BA in the second chip 100b), its larger area endows the three-dimensional processor 100 with more powerful processing capabilities. In addition, since the second chip is designed and produced separately, it has greater flexibility in design and production. By combining the same first chip 100a with second chips 100b with different functions, processing functions suitable for different application scenarios can be achieved. Better yet, these different processing functions can be achieved within a shorter design cycle and with a smaller design budget. Therefore, the separate three-dimensional processor 100 is more powerful and flexible.

[0062] Figures 6A - 6BB are circuit layout diagrams of the first and second chips 100a, 100b in two separate three-dimensional processors 100, which show more details than Figure 2C The embodiment corresponds to Figure 7A and Figure 8A The embodiment. Professionals familiar with the field can easily generalize it to Figure 7B and Figure 8B , as well as Figure 7C and Figure 8C The embodiment.

[0063] Figure 6A represents the first chip 100a, which contains multiple 3D-M arrays 170aa - 170mn. Figure 6BA represents the second chip 100b, which contains multiple logic circuits 180aa - 180mn and a global peripheral circuit component 190G. The global peripheral circuit component 190G is located outside the projection of all 3D-M arrays 170aa - 170mn on the second chip 100b. Figure 6A and Figure 6BA The three-dimensional processor 100 of adopts the "fully aligned" technology, that is, the circuit layouts on the two chips 100a, 100b meet the following requirements: when the two chips 100a, 100b are stacked, each logic circuit (such as 180ij) is vertically aligned and electrically coupled with at least one 3D-M array (such as 170ij) (see Figures 8A - 8C ). Since each logic circuit (such as 180ij) can have multiple 3D-M arrays (such as 170ijA - 170ijD) aligned with it (see Figures 8B - 8C), the period of the logic circuit (such as 180ij) on the second chip 100b is an integer multiple of the period of the 3D-M array (such as 170ij) on the first chip 100a.

[0064] Figure 6BB Represents another second chip 100b, which also contains a plurality of local peripheral circuit components 190aa-190mn. Obviously, Figure 6A and Figure 6BB The three-dimensional processor 100 of can also adopt the "fully aligned" technology. Among them, each local peripheral circuit component 190aa-190mn is vertically aligned and electrically coupled with a 3D-M array (such as 170ij). In addition to the local peripheral circuit components 190aa-190mn, Figure 6BB The embodiments in can also contain a global peripheral circuit component 190G. In this specification, all local peripheral circuit components 190aa-190mn and the global peripheral circuit component 190G are collectively referred to as off-chip peripheral circuit components 190.

[0065] In Figures 6A - 6BB The embodiments of, the local peripheral circuit component (such as 190ij) generally contains a partial address decoder, a partial read amplifier circuit, or a partial write circuit, etc., and it completes at least partial read and write operations on the memory elements in each 3D-M array (such as 170ij). The global peripheral circuit component 190G generally contains a read voltage generation circuit, a write voltage generation circuit, or a data buffer, etc., and it generates read / write voltages, etc. Of course, the division of these local and global peripheral circuit components is not absolute. For example, the local peripheral circuit component can contain at least part of the read / write circuit generation circuit.

[0066] Figures 7A - 8C Represents three storage and computing units 100ij. Figures 7A - 7C Is its circuit block diagram (for simplicity, the off-chip peripheral circuit component 190ij is not drawn in Figures 7A - 7C ); Figures 8A - 8C Is its circuit layout diagram. In these embodiments, a logic circuit 180ij serves different numbers of 3D-M arrays 170ij.

[0067] Figure 7A The logic circuit 180ij in serves one 3D-M array 170ij: It processes the data stored in the 3D-M array 170ij. Figure 7B The logic circuit 180ij in serves four memory arrays 170ijA-170ijD: It processes the data stored in the 3D-M arrays 170ijA-170jiD. Figure 7CThe logic circuit 180ij in [it] serves eight memory arrays 170ijA - 170ijD and 170ijW - 170ijZ: it processes the data stored in the 3D - M arrays 170ijA - 170ijD and 170ijW - 170ijZ. As can be seen from the following Figures 8A - 8C The logic circuit 180ij that serves more 3D - M arrays 170ij generally occupies a larger chip area and has stronger functions. In Figures 7A - 7C Since the 3D - M array 170ij and the logic circuit 180ij are located on different chips (see Figure 2C and Figures 6A - 6BB ), the 3D - M array 170ij is represented by a dotted line.

[0068] Figures 8A - 8C shows the circuit layout of the second chip 100b and the projection of the 3D - M array 170 (located in the first chip 100a) on the second chip 100b (represented by a dotted line). Figure 8A The embodiment of [it] corresponds to the embodiment of Figure 7A In this embodiment, the logic circuit 180ij and the local peripheral circuit components 190ij in the storage - computing unit 100ij are located in the second semiconductor substrate 0b of the second chip 100b. The logic circuit 180ij and the off - chip peripheral circuit components 190ij are at least partially covered by the 3D - M array 170ij.

[0069] In this embodiment, the period of the logic circuit 180ij is equal to the period of the 3D - M array 170ij, and the area cannot exceed the projected area of the 3D - M array 170ij on the second chip 100b, so the function is limited. This embodiment is more suitable for implementing relatively simple data processing. Figures 8B - 8C Discloses two complex logic circuits 180.

[0070] Figure 8B The embodiment of [it] corresponds to the embodiment of Figure 7B In this embodiment, the logic circuit 180ij and the off - chip peripheral circuit components 190ij of the storage - computing unit 100ij are located in the second chip 100b, and they are at least partially covered by four 3D - M arrays 170ijA - 170ijD. Below the four 3D - M arrays 170ijA - 170ijD, the logic circuit 180ji can be freely laid out. Figure 8B The period of the logic circuit 180ij in [it] is Figure 8A twice the period of the 3D - M array 170ij in [it], and the area is four times that of it, so it can implement relatively complex processing functions.

[0071] Figure 8C The embodiment of [it] corresponds to the embodiment of Figure 7CExample in []. In this example, the logic circuit 180ij and the off-chip peripheral circuit components 190ij in the storage and computing unit 100ij are located in the second chip 100b. These eight 3D-M arrays 170ijA - 170ijD, 170ijW - 170ijZ are divided into two groups 170ijSA, 170jiSB. Each group (such as 170ijSA) includes four 3D-M arrays (such as 170ijA - 170ijD). Below the four 3D-M arrays 170ijA - 170ijD of the first group 170SA, the first logic circuit component 180ijA can be freely arranged. Similarly, below the four 3D-M arrays 170ijW - 170ijZ of the second group 170ijSB, the second logic circuit component 180ijB can be freely arranged. The first logic circuit component 180ijA and the second logic circuit component 180ijB constitute the logic circuit 180ij. In this example, gaps (such as G) are left between adjacent off-chip peripheral circuit components to form wiring channels 182, 184, 186 for realizing electrical coupling between different logic circuit components 180ijA, 180ijB, or between different logic circuits. Figure 8C The period of the logic circuit 180ij in [] is Figure 8A Four times the period (in the x direction) and eight times the area of the 3D-M array 170ij in [], so more complex processing functions can be achieved.

[0072] In Figures 8A - 8C [], each storage and computing unit (100ij) occupies a first area on the first chip (100a) and a second area on the second chip (100b), and the first and second areas basically coincide. Specifically, all 3D-M arrays (170) in each storage and computing unit (100ij) occupy the first area, and all logic circuits (180) and all off-chip peripheral circuit components (190) occupy the second area. The projection of the first area on the second chip (100b) is basically the same as the second area.

[0073] The "separated three-dimensional processor (abbreviated as 3D-P)" proposed by the present invention and the "separated three-dimensional memory (3D-M)" in the prior art (such as CN103765516B, etc.) are both based on the concept of "anti-integration". The separated 3D-P is a further development of the separated 3D-M. First, the separated 3D-M and the separated 3D-P belong to different fields (memory, processor). Applying anti-integration to the processor brings about the reconstruction of the computing system, which is a technical effect that the separated 3D-M cannot anticipate or achieve. Second, the separated 3D-P solves a new problem brought about by the separated 3D-M. Here, it is necessary to review the development process of three-dimensional integration technology (from "integrated 3D-M" to "separated 3D-M" and then to "separated 3D-P"): Initially, the array efficiency of the integrated 3D-M chip was relatively low, about 70% (the 3D-M array and the peripheral circuit respectively occupied about 70%: 30% of the area). In order to improve the array efficiency of the 3D-M chip, the separated 3D-M stripped the peripheral circuit from the 3D-M chip to form two chips (3D-M array chip + peripheral circuit chip). This measure increased the array efficiency of the 3D-M array chip to about 90%. However, the peripheral circuit only accounted for about 20% of the area of the second chip (see Figures 8A - 8C ). Therefore, most of the area on the peripheral circuit chip was left vacant and wasted, which is a new problem that the prior art failed to realize. By forming logic (processing) circuits in these vacant areas, the separated 3D-P not only makes better use of the area of the peripheral circuit chip, but also brings significant performance improvement by embedding processing capabilities into the 3D-M. More importantly, because the logic circuit and the peripheral circuit are manufactured simultaneously, the above advantages do not require additional costs.

[0074] The separated three-dimensional processor 100 can be applied to fields such as mathematical calculation, computer simulation, programmable computing array, pattern processing, neural network processing, etc. Specific examples can be seen in the parent application of this case (CN111290994B). Figures 9 - 10 Only an introduction to its applications in pattern processing and neural network processing is given.

[0075] When used for pattern processing, the separated three-dimensional processor 100 can be used as a three-dimensional pattern processor. Figure 9 Denote its storage and computing unit 100ij, which contains a pattern storage circuit 170 and a pattern processing circuit 180PPC (that is, the logic circuit 180 is the pattern processing circuit 180PPC), and they are electrically coupled through the inter-chip connection 160 ( Figures 3A - 3D ). The pattern storage circuit 170 contains a 3D-M array 170, which stores at least part of the pattern; the pattern processing circuit 180PPC processes the pattern.

[0076] The separated three-dimensional pattern processor 100 can be used in two ways - the processor-like way and the memory-like way. The processor-like three-dimensional pattern processor 100 is a three-dimensional processor with a built-in retrieval pattern library. It can perform pattern processing on the target pattern from the input 110 using the retrieval patterns stored locally. Specifically, the retrieval pattern library (such as virus library, keyword library, acoustic / language model library, image model library, etc.) is stored in the 3D-M array 170; the input data 110 includes the target pattern (such as network data packet, computer file, big data, voice data, image data, etc.); the pattern processing circuit 180PPC performs pattern processing on the target pattern according to the retrieval pattern. Due to the large number of storage and computing units 100ij (tens of thousands, Figure 9 ), which support large-scale parallel processing, and the inter-chip connection 160 has a large bandwidth ( Figures 3B - 3D ), the retrieval speed of the three-dimensional processor 100 is fast and the efficiency is high.

[0077] The memory-like three-dimensional pattern processor 100 is a three-dimensional memory with a built-in pattern processing function. Its main function is to store the target pattern library, and its secondary function is to retrieve the stored target pattern using the retrieval pattern from the input 110. Specifically, the target pattern library (such as computer files on the entire hard disk, big data database, voice archive, image archive) is stored and distributed in the 3D-M array 170; the input data 110 is the retrieval pattern (such as virus identifier, keyword, acoustic / language model, image model, etc.); the pattern processing circuit 180PPC performs pattern processing on the target pattern according to the retrieval pattern. Due to the large number of storage and computing units 100ij (tens of thousands, Figure 2A ), which support large-scale parallel processing, and the inter-chip connection 160 has a large bandwidth ( Figures 3B - 3D ), the pattern processing speed of the three-dimensional memory 100 is fast and the efficiency is high.

[0078] Similar to flash memory, multiple three-dimensional memories 100 with built-in pattern processing functions can be packaged into memory cards (such as SD cards, TF cards) or solid-state drives (i.e., SSDs) for storing the target pattern library with massive data. Particularly importantly, they also have built-in pattern processing (such as retrieval) functions. Since each storage and computing unit 100ij has a built-in pattern processing circuit 180PPC, it only needs to retrieve the target pattern stored in the local (in the same storage and computing unit 100ij) 3D-M array 170. Therefore, regardless of the capacity of the memory card or solid-state drive, the retrieval time is close to the time required to retrieve a single 3D-M array 170. In other words, the retrieval time of the database is independent of the capacity of the database and is mostly in the order of seconds.

[0079] In contrast, in the traditional von Neumann architecture, the processor (CPU) and the memory (hard disk) are physically separated from each other. For database retrieval, the database first needs to be read out from the hard disk. Since the bandwidth of the system bus between the CPU and the hard disk is limited, the retrieval time of the database is limited by the readout time of the database. Therefore, the retrieval time of the database is proportional to the size of the database. Generally speaking, based on the size of the database, the retrieval time ranges from several minutes to several hours, or even longer. In contrast, the three-dimensional memory 100 with built-in pattern processing function has obvious advantages in database retrieval.

[0080] When the three-dimensional memory 100 with built-in pattern processing function performs pattern processing on a large database (i.e., the target pattern library), the pattern processing circuit 180PPC only needs to complete part of the pattern processing functions. For example, the pattern processing circuit 180PPC only needs to perform simple preliminary pattern processing on the database (such as string matching, code matching). The remaining data (i.e., the target pattern) after being screened by this preliminary pattern processing is then sent to a more powerful external processor (such as a CPU, GPU) through the output 120 to complete the final pattern processing. Since most of the data in the database will be screened out by the simple pattern processing, the data output from the three-dimensional memory 100 only accounts for a small part of the entire database, which can greatly reduce the bandwidth pressure of the output 120.

[0081] The separated three-dimensional processor 100 can also be used as a three-dimensional neural network processor. Figure 10 Denote its storage and computing unit 100ij, which contains a neural storage circuit 170 and a neural computing circuit 180NPC (the logic circuit 180 is the neural computing circuit 180NPC), and they are electrically coupled through the inter-chip connection 160 ( Figures 3A - 3D ). The neural storage circuit 170 contains a 3D-M array, which stores at least part of the synaptic weights; the neural computing circuit 180NPC uses the synaptic weights to perform neural computations.

[0082] It should be understood that, without departing from the spirit and scope of the present invention, changes may be made to the form and details of the present invention, which does not prevent the application of the spirit of the present invention. For example, the processor in the present invention may be a central processing unit (CPU), a controller or a microcontroller, a digital signal processor (DSP), a graphics processing unit (GPU), a network security processor, an encryption / decryption processor, an encoding / decoding processor, a neural network processor, an artificial intelligence (AI) processor, etc. In addition, the 3D-M array 170 in this specification can be extended to any semiconductor memory array 170, as long as the back-end structure of the memory array 170 (the first chip 100a) has a significant difference from the back-end structure of the logic circuit 180 and the off-chip peripheral circuit components 190 (the second chip 100b) (such as the number of back-end wiring layers is different; the thickness of the back-end wiring layers is different; or, 170 contains a three-dimensional structure, while 180 and 190 only contain a standard back-end structure). Additionally, the logic circuit 180 in this specification can also be extended to any non-memory circuit 180, as long as the non-memory circuit 180 is not a peripheral circuit of the memory array 170. Therefore, the present invention should not be limited in any way except in accordance with the spirit of the appended claims.

Claims

1. An isolated three-dimensional processor (100), characterized in that Comprising: A plurality of storage and computing units (100aa - 100mn), each storage and computing unit (100ij) comprising at least one memory array (170) and a non - memory circuit (180), the non - memory circuit (180) being electrically coupled to the memory array (170) but not being a peripheral circuit of the memory array (170); A first chip (100a), the first chip (100a) comprising the memory array (170) among the plurality of storage and computing units (100aa - 100mn), the memory array (170) comprising a three - dimensional structure; A second chip (100b), the second chip (100b) comprising the non - memory circuit (180) among the plurality of storage and computing units (100aa - 100mn) and off - chip peripheral circuit components (190) of the memory array (170) among the plurality of storage and computing units (100aa - 100mn), the second chip (100b) comprising only a standard back - end structure; A plurality of inter - chip connections (160), the plurality of inter - chip connections (160) electrically coupling the first chip (100a) to the second chip (100b).

2. A separated three-dimensional processor (100), characterized in that Comprising: A plurality of storage and computing units (100aa - 100mn), each storage and computing unit (100ij) comprising a non - memory circuit (180), at least one memory array (170) and its off - chip peripheral circuit components (190); the off - chip peripheral circuit components (190) being a kind of peripheral circuit of the memory array (170), the non - memory circuit (180) not being a peripheral circuit of the memory array (170); A first chip (100a), the first chip (100a) comprising the memory array (170) among the plurality of storage and computing units (100aa - 100mn), the memory array (170) comprising a three - dimensional structure; A second chip (100b), the second chip (100b) comprising the non - memory circuit (180) and off - chip peripheral circuit components (190) among the plurality of storage and computing units (100aa - 100mn), the second chip (100b) comprising only a standard back - end structure; A plurality of inter - chip connections (160), the plurality of inter - chip connections (160) electrically coupling the first chip (100a) to the second chip (100b).

3. The separated three-dimensional processor (100) according to claim 1 or 2, further characterized in that: The first chip (100a) and the second chip (100b) are vertically stacked.

4. The separated three-dimensional processor (100) according to claim 3, further characterized in that: The memory array (170) is a random access memory (RAM) array or a non - volatile memory (NVM) array.

5. The separated three-dimensional processor (100) according to claim 3, further characterized in that: The non - memory circuit (180) is a logic circuit or a processing circuit.

6. The separated three-dimensional processor (100) according to claim 3, further characterized in that: The chip areas of the first chip (100a) and the second chip (100b) are the same.

7. The separated three-dimensional processor (100) according to claim 3, further characterized in that: All sides of the first chip (100a) and the second chip (100b) are aligned.

8. The separated three-dimensional processor (100) according to claim 3, further characterized in that: Each storage and computing unit (100ij) occupies a first area on the first chip (100a) and a second area on the second chip (100b), and the first and second areas substantially coincide.

9. The separated three-dimensional processor (100) according to claim 8, further characterized in that: The storage array (170) is a random access memory (RAM) array or a non-volatile memory (NVM) array.

10. The separated three-dimensional processor (100) according to claim 8, further characterized in that: The non-storage circuit (180) is a logic circuit or a processing circuit.

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