Discrete memristor driving type neuron design method and implementation circuit thereof

Abstract

The invention discloses a design method of a discrete memristor driving type neuron and an implementation circuit thereof. The design method comprises the following steps: determining a discrete iteration form of a voltage-controlled discrete local active memristor; designing a discrete local active memristor model based on a trigonometric function; then determining a discrete neuron model based on two-dimensional mapping; introducing the obtained discrete local active memristor into a discrete neuron model to obtain a discrete memristor driven neuron model; and finally, constructing a nonlinear function based on a trigonometric function, and substituting the nonlinear function into the obtained neuron model to complete the design of the discrete memristor driven neuron. The invention also provides corresponding analog and digital circuit construction, which has the advantages of stable operation, accurate response, excellent performance and the like, and shows good application prospects and engineering practicability.

Description

Technical Field

[0001] The present invention belongs to the field of electronic circuit design, and particularly relates to a design method for a discrete memristor-driven neuron and its implementation circuit. Background Art

[0002] With the development of artificial intelligence and neuromorphic computing, neuron models and their hardware implementations have become a current research hotspot. Biological neurons rely on the nonlinear dynamic characteristics in ion channels and synapses to achieve efficient processing of complex information. Currently, although traditional continuous neuron models can characterize the electrical activity characteristics of neurons, there are bottlenecks in simulating discrete behaviors such as refractory periods and threshold triggering, and traditional continuous neuron models often have high computational redundancy when transplanted into digital systems. In contrast, discrete neuron models can more efficiently simulate the impulse firing process of neurons through iterative mechanisms, and have advantages such as low computational overhead, simple structure, and easy hardware implementation. Therefore, discrete neuron models have received extensive attention in neural network research.

[0003] As a new type of nonlinear electronic component, the memristor can effectively simulate the nonlinear dynamic characteristics in the biological nervous system, and it is suitable for describing the complex process of neurons generating action potentials. Therefore, in recent years, the application research of memristors in neuromorphic circuits and artificial neural networks has been continuously deepened. However, the current research mainly focuses on introducing memristors into continuous neuron models to enhance their nonlinear characteristics. The deep integration of memristors and discrete neuron models is not sufficient, and there is still a lack of a discrete memristive neuron model that has both rich dynamic characteristics and low computational complexity. Summary of the Invention

[0004] One object of the present invention is to provide a design method for a discrete memristor-driven neuron model that combines the advantages of computational efficiency and complex dynamic characteristics.

[0005] Another object of the present invention is to provide an implementation circuit for a discrete memristor-driven neuron.

[0006] The design method for the discrete memristor-driven neuron provided by the present invention includes the following steps: S1. Based on the forward difference theory, determine the discrete iterative form of a voltage-controlled discrete local active memristor; S2. According to the discrete iterative form determined in step S1, design a discrete local active memristor model based on trigonometric functions; S3. Based on two-dimensional mapping, determine the discrete neuron model; S4. Substitute the discrete local active memristor model obtained in step S2 into the discrete neuron model in step S3 to obtain a discrete memristor-driven neuron model; including the following steps: Substitute the discrete local active memristor model obtained in step S2 into the discrete neuron model obtained in step S3. Use the magnetic flux term in the memristor to represent the ionic current recovery variable term in the model expression of the discrete neuron, and map the magnetic flux variable of the memristor to the ionic current recovery variable to obtain a discrete memristor-driven neuron model; S5. Construct a non-linear function based on trigonometric functions and substitute it into the discrete memristor-driven neuron model obtained in step S4 to complete the design of the discrete memristor-driven neuron.

[0007] The said step S1 specifically includes the following steps: Based on the forward difference theory, use the following formula as the discretized iterative operation form of the voltage-controlled discrete local active memristor: In the formula, is the N input voltage at time is the N output current at time is the N internal state variable of the memristor at time is the memductance function; is the non-linear modulation function; is the scale factor.

[0008] The said step S2 specifically includes the following steps: Select the memductance function as , and select the non-linear modulation function as ; where a is the amplitude parameter of the non-linear modulation function ; Thus, the discrete local active memristor model is determined as: .

[0009] The said step S3 specifically includes the following steps: Based on two-dimensional mapping, use the following formula to represent the discrete neuron model: In the formula is the n th iteration value of the neuron membrane potential; I is the externally applied excitation current; is the n th iteration value of the ionic current recovery variable; is the set first parameter; q is the set second parameter; is the set third parameter.

[0010] The described step S4 specifically includes the following steps: The novel discrete memristor-driven neuron model is represented by the following formula: In the formula is a non-linear function with N type characteristics; k is the memristor coupling strength.

[0011] The described step S5 specifically includes the following steps: Based on the sine function, a non-linear curve function is constructed as , where g is the set non-linear strength parameter, and ; Substitute the non-linear curve function into the discrete memristor-driven neuron model obtained in step S4 to obtain , completing the design of the discrete memristor-driven neuron model.

[0012] The present invention also provides an implementation circuit for a discrete memristor-driven neuron, including an analog implementation circuit and a digital implementation circuit; Based on a sample and hold circuit, an operational amplifier, and an operational function editor, an analog implementation circuit for the discrete memristor-driven neuron model is implemented; Based on a control chip, a digital implementation circuit for the discrete memristor-driven neuron model is implemented.

[0013] The described analog implementation circuit includes a first staircase wave function generator, a second staircase wave function generator, a third staircase wave function generator, a first sample and hold circuit, a second sample and hold circuit, a third sample and hold circuit, a fourth sample and hold circuit, a NOT gate, a first function editor, a second function editor, a third function editor, a multiplier, a first proportional gain amplifier, a second proportional gain amplifier, a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, and a first resistor to a fourteenth resistor; The negative terminal of the first staircase wave function generator is grounded. The first staircase wave function generator is used to generate a first initial staircase wave signal , and output the first initial staircase wave signal to the first input terminal of the first sample and hold circuit, the first input terminal of the third sample and hold circuit, and the input terminal of the NOT gate; The NOT gate is used to invert the first initial staircase wave signal In the reverse direction, the output terminal of the NOT gate is simultaneously connected to the first input terminal of the second sample and hold circuit and the first input terminal of the fourth sample and hold circuit; the output terminal of the first sample and hold circuit is connected to the second input terminal of the second sample and hold circuit, and the output terminal of the third sample and hold circuit is connected to the second input terminal of the fourth sample and hold circuit; the signal output from the output terminal of the second sample and hold circuit is divided into three paths. The first path is connected to the input terminal of the first function editor, the second path is connected to the first input terminal of the multiplier, and the third path is connected to the inverting input terminal of the third operational amplifier through the serially connected eighth resistor; the first function editor is used to convert the input signal into a sine signal for output; the output terminal of the first function editor is connected to the inverting input terminal of the first operational amplifier through the serially connected first resistor; the non-inverting input terminal of the first operational amplifier is grounded; the inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through the serially connected fifth resistor; the output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier through the serially connected sixth resistor; the non-inverting input terminal of the second operational amplifier is grounded; the inverting input terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier through the seventh resistor; the output terminal of the second operational amplifier is directly connected to the second input terminal of the first sample and hold circuit; the second input terminal of the multiplier is connected to the output terminal of the second function editor, and the second mathematical function editor is used to convert the input signal into a cosine signal for output; the output terminal of the multiplier is connected to the inverting input terminal of the first operational amplifier through the second resistor; the negative terminal of the second ramp function generator is grounded, and the second ramp function generator is used to generate a second initial ramp signal , and the second initial ramp signal is connected to the inverting input terminal of the first operational amplifier through the serially connected third resistor; the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the first operational amplifier through the fourth resistor; the output terminal of the fourth operational amplifier is also connected to the input terminal of the second function editor through the first proportional gain device; the output terminal of the fourth sample and hold circuit is connected to the inverting input terminal of the third operational amplifier through the ninth resistor; the output terminal of the fourth sample and hold circuit is also connected to the inverting input terminal of the third operational amplifier through the serially connected second proportional gain device, third function editor, and tenth resistor; the third function editor is used to convert the input signal into a sine signal for output; the negative terminal of the third ramp function generator is grounded, and the third ramp function generator is used to generate a third initial ramp signal , and the third initial ramp signal The inverting input terminal of the third operational amplifier is connected through a series-connected twelfth resistor; the non-inverting input terminal of the third operational amplifier is grounded, and the inverting input terminal of the third operational amplifier is also connected to the output terminal of the third operational amplifier through an eleventh resistor; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier through a series-connected thirteenth resistor; the inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier through a fourteenth resistor; the output terminal of the fourth operational amplifier is directly connected to the second input terminal of the third sample and hold circuit.

[0014] The digital implementation circuit described above is specifically a digital circuit composed of a control chip of model TMS320F28335; the iterative operation of the discrete memristor-driven neuron model is realized through the control chip, so as to realize the discrete memristor-driven neuron model with a digital circuit.

[0015] This discrete memristor-driven neuron design method and implementation circuit provided by the present invention combines the non-linear characteristics of the memristor with the discrete neuron model, effectively reducing the system calculation complexity while significantly enhancing the dynamic characteristics of the neuron model. It not only completes the modeling design of the new discrete memristor-driven neuron, but also realizes the construction of the corresponding analog and digital circuits, with advantages such as stable operation, accurate response, and excellent performance, showing good application prospects and engineering practicability. Brief Description of the Drawings

[0016] Figure 1 It is a schematic flow chart of the design method of the present invention.

[0017] Figure 2 It is the composite non-linear function in the design method of the present invention , and the schematic diagram of the characteristic curve under different parameters g .

[0018] Figure 3 It is the global dynamic characteristic diagram of the discrete memristor-driven neuron model in the present invention design method changing within the interval.

[0019] Figure 4 It is the different discharge modes presented by the discrete memristor-driven neuron model in the present invention design method under different parameters g . Among them, Figure 4 (a) is the time series diagram under the multi-period discharge mode when ; Figure 4 (b) is the phase trajectory diagram under the multi-period discharge mode when ; Figure 4 (c) is the time series diagram under the type chaotic discharge mode when .Figure 4 (d) is the phase trajectory diagram under the type chaotic discharge mode at Figure 4 (e) is the time series diagram under the type chaotic discharge mode at Figure 4 (f) is the phase trajectory diagram under the type chaotic discharge mode at

[0020] Figure 5 Schematic diagram of the analog implementation circuit of the circuit implemented by the present invention.

[0021] Figure 6 Simulation experiment result diagram of the analog implementation circuit of the circuit implemented by the present invention. Among them Figure 6 (a) is the time series diagram under the multi-period discharge mode at Figure 6 (b) is the phase trajectory diagram under the multi-period discharge mode at Figure 6 (c) is the time series diagram under the type chaotic discharge mode at Figure 6 (d) is the phase trajectory diagram under the type chaotic discharge mode at Figure 6 (e) is the time series diagram under the type chaotic discharge mode at Figure 6 (f) is the phase trajectory diagram under the type chaotic discharge mode at

[0022] Figure 7 Composition diagram of the digital implementation circuit of the circuit implemented by the present invention.

[0023] Figure 8 Hardware experiment result diagram of the digital implementation circuit of the circuit implemented by the present invention, where Figure 8 (a) is the time series diagram under the multi-period discharge mode at Figure 8 (b) is the phase trajectory diagram under the multi-period discharge mode at Figure 8 (c) is the time series diagram under the type chaotic discharge mode at Figure 8 (d) is the phase trajectory diagram under the type chaotic discharge mode at Figure 8 (e) is the At Time series diagram under the chaotic discharge mode of type Figure 8 (f) is At Phase trajectory diagram under the chaotic discharge mode of type Detailed implementation manner

[0024] As Figure 1 Shown is the schematic diagram of the method flow of the design method of the present invention: The design method of the discrete memristor-driven neuron disclosed by the present invention includes the following steps: S1. Based on the forward difference theory, determine the discrete iteration form of the voltage-controlled discrete local active memristor, which specifically includes the following steps: The local active memristor introduced by the present invention is a general type of memristor with local negative differential resistance characteristics, and the included local active characteristics are the root cause of system complexity; based on the forward difference theory, the following formula is used as the discretized iterative operation form of the voltage-controlled discrete local active memristor: In the formula, is N The input voltage at the moment of is N The output current at the moment of is N The internal state variable of the memristor at the moment of is the memductance function; is the non-linear modulation function; is the scaling factor.

[0025] S2. According to the discrete iteration form determined in step S1, design a discrete local active memristor model based on trigonometric functions, which specifically includes the following steps: Select the memductance function as , select the non-linear modulation function as ; where a is the amplitude parameter of the non-linear modulation function ; Thus, the discrete local active memristor model is determined as .

[0026] S3. Based on the two-dimensional mapping, determine the discrete neuron model, which specifically includes the following steps: Traditional discrete neuron models are mostly based on the Integrate-and-Fire (IF) model, and slow variables are widely introduced to regulate the dynamic behavior of the neuron membrane potential; based on the two-dimensional mapping, the following formula is used to represent the discrete neuron model: In the formula is the n iteration value of the neuron membrane potential; I is the externally applied excitation current; is the n iteration value of the ion current recovery variable; is the set first parameter, which is a positive parameter, and value is less than the set positive threshold (the purpose is to ensure is much less than 1); q is the set second parameter; is the set third parameter; , q and are used to regulate different firing states of the discrete neuron model.

[0027] In this model, the ion current recovery variables are all linear terms, which are difficult to describe the real non - linear recovery mechanism existing in the nerve firing process, restricting the applicability of the model in complex neural dynamics simulation.

[0028] S4. Substitute the discrete local active memristor model obtained in step S2 into the discrete neuron model in step S3 to obtain a discrete memristor - driven neuron model, including the following steps: The core of the present invention lies in that a discrete local active memristor is introduced into the neuron model based on two - dimensional mapping in the present invention. The flux state variable in the memristor is used to replace the ion current recovery variable in the neuron model, so as to realize the non - linear regulation mechanism of the coupling between the neuron membrane potential and the magnetic flux, and construct a new discrete memristor - driven neuron model; this design enables the neuron model to have stronger non - linear expression ability and can present diverse dynamic behaviors; Substitute the expression of the discrete local active memristor obtained in step S2 into the discrete neuron model in step S3, use the magnetic flux term in the memristor to represent the ion current recovery variable term in the model expression of the discrete neuron, and map the magnetic flux variable of the memristor to the ion current recovery variable , thus obtaining a discrete memristor - driven neuron model; Specifically in implementation, the following arithmetic formula is used as the obtained discrete memristor - driven neuron model: In the formula is a non - linear curve function with N type characteristics; k is the memristor coupling strength.

[0029] S5. Construct a non - linear function based on trigonometric functions and substitute it into the discrete memristor - driven neuron model obtained in step S4 to complete the design of the discrete memristor - driven neuron, which specifically includes the following steps: Construct a non - linear curve function based on the sine function as , where g is the set non - linear strength parameter, and ; meanwhile, set ; when the parameter g takes values greater than 1 and shows a N type characteristic within the controllable parameter range; Figure 2 shows the g when taking 3 different values ( ), the N type characteristic curves constructed based on the sine function vary in the interval, and the 3 non - linear functions exhibit odd symmetry; Substitute the non - linear curve function into the discrete memristor - driven neuron model obtained in step S4 to get , and complete the design of the discrete memristor - driven neuron.

[0030] For the obtained discrete memristor - driven neuron model, under the condition of setting the parameter and the initial state as , by constructing a bifurcation diagram based on the membrane potential iteration sequence and the Lyapunov exponent spectrum (LEs) of quantitative analysis, characterize the global dynamic characteristics of the system changing within the controllable parameter range; specifically as Figure 3 shown.

[0031] Among them, the bifurcation diagram reflects the system state evolution by extracting the periodic characteristics of the iteration sequence, while the sign change of the maximum Lyapunov exponent ( characterizes chaos, corresponds to periodicity, indicates quasi - periodicity), providing a strict mathematical criterion for the dynamic evolution of the system. Figure 3 The bifurcation diagram and the Lyapunov exponent spectrum in g show a high degree of consistency in characterizing dynamic characteristics. When the parameter gradually increases, the system experiences changes in the quasi - periodic state multi - periodic state

[0032] chaotic state, accompanied by the generation of period - doubling bifurcations and multiple periodic windows. is close to zero within the initial interval, and the system is in a quasi - periodic state; As g increases, multiple narrow periodic windows appear near , and at this time Less than 0; Within a wider area, Continuously maintaining a positive value reveals a dominant chaotic state.

[0033] To observe the discharge patterns under different parameters, the parameters g are set to three different groups of values, and the resulting and time series and the phase trajectories are as Figure 4 shown. When , the discrete memristor-driven neuron model is in a multi-periodic discharge mode ( , ), and the time iteration sequences of the membrane potential and the ionic current recovery variable are as Figure 4 (a) shows, and the corresponding phase diagram is as Figure 4 (b) shows; when , the neuron model is in a type chaotic discharge mode ( , ), and its time series and phase diagram are respectively as Figure 4 (c) and Figure 4 (d) show; when , the neuron model is in different type chaotic discharge modes ( , ), and its time iteration sequences and phase diagrams are respectively shown in Figure 4 (e) and Figure 4 (f).

[0034] The discrete memristor-driven neuron model lays a solid theoretical foundation for the hardware implementation of neuromorphic systems, and the realization of its physical model requires the engineering transformation of the technical prototype relying on analog circuits and digital circuits. Based on the dynamic characteristics of the model, the present invention constructs a dual verification platform for analog simulation circuits and digital hardware circuits respectively. By reproducing the dynamic behavior of the model at the circuit level, the correctness of its theoretical description is verified; at the same time, the feasibility of the engineering application of the model in neuromorphic systems is further proved by the implementation of the hardware circuit.

[0035] The implementation circuit of the discrete memristor-driven neuron disclosed in the present invention includes an analog implementation circuit and a digital implementation circuit; An analog implementation circuit for realizing the discrete memristor-driven neuron model based on a sample and hold circuit, an operational amplifier, and an operational function editor; A digital implementation circuit for realizing the discrete memristor-driven neuron model based on a control chip.

[0036] In specific implementation, the present invention adopts a simulation experimental circuit based on the PSIM platform to systematically verify the feasibility of the analog circuit implementation scheme.

[0037] The analog implementation circuit described in the present invention, such as Figure 5 shown, includes a first staircase function generator, a second staircase function generator, a third staircase function generator, a first sample and hold circuit ( ), a second sample and hold circuit ( ), a third sample and hold circuit ( ), a fourth sample and hold circuit ( ), a NOT gate (D), a first function editor ( ), a second function editor ( ), a third function editor ( ), a multiplier ( M ), a first proportional gain amplifier ( ), a second proportional gain amplifier ( ), a first operational amplifier ( ), a second operational amplifier ( ), a third operational amplifier ( ), a fourth operational amplifier ( ) and a first resistor to a fourteenth resistor ( ); The negative electrode of the first staircase function generator is grounded. The first staircase function generator is used to generate a first initial staircase wave signal , and output the first initial staircase wave signal to the first input terminal of the first sample and hold circuit, the first input terminal of the third sample and hold circuit and the input terminal of the NOT gate; the NOT gate is used to invert the first initial staircase wave signal In the reverse direction, the output terminal of the NOT gate is simultaneously connected to the first input terminal of the second sample and hold circuit and the first input terminal of the fourth sample and hold circuit; the output terminal of the first sample and hold circuit is connected to the second input terminal of the second sample and hold circuit, and the output terminal of the third sample and hold circuit is connected to the second input terminal of the fourth sample and hold circuit; the signal output from the output terminal of the second sample and hold circuit is divided into three paths. The first path is connected to the input terminal of the first function editor, the second path is connected to the first input terminal of the multiplier, and the third path is connected to the inverting input terminal of the third operational amplifier through the eighth resistor connected in series; the first mathematical function editor is used to convert the input signal into a sine signal for output; the output terminal of the first function editor is connected to the inverting input terminal of the first operational amplifier through the first resistor connected in series; the non-inverting input terminal of the first operational amplifier is grounded; the inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through the fifth resistor connected in series; the output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier through the sixth resistor connected in series; the non-inverting input terminal of the second operational amplifier is grounded; the inverting input terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier through the seventh resistor connected in series; the output terminal of the second operational amplifier is directly connected to the second input terminal of the first sample and hold circuit; the second input terminal of the multiplier is connected to the output terminal of the second function editor, and the second mathematical function editor is used to convert the input signal into a cosine signal for output; the output terminal of the multiplier is connected to the inverting input terminal of the first operational amplifier through the second resistor connected in series; the negative terminal of the second ramp function generator is grounded, and the second ramp function generator is used to generate a second initial ramp signal , and the second initial ramp signal is connected to the inverting input terminal of the first operational amplifier through the third resistor connected in series; the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the first operational amplifier through the fourth resistor connected in series; the output terminal of the fourth operational amplifier is also connected to the input terminal of the second function editor through the first proportional gain device; the output terminal of the fourth sample and hold circuit is connected to the inverting input terminal of the third operational amplifier through the ninth resistor connected in series; the output terminal of the fourth sample and hold circuit is also connected to the inverting input terminal of the third operational amplifier through the second proportional gain device, the third function editor, and the tenth resistor connected in series in sequence; the third function editor is used to generate a sine signal; the negative terminal of the third ramp function generator is grounded, and the third ramp function generator is used to generate a third initial ramp signal , and the third initial ramp signal The inverting input terminal of the third operational amplifier is connected through a series-connected twelfth resistor; the non-inverting input terminal of the third operational amplifier is grounded, and the inverting input terminal of the third operational amplifier is also connected to the output terminal of the third operational amplifier through an eleventh resistor; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier through a series-connected thirteenth resistor; the inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier through a fourteenth resistor; the output terminal of the fourth operational amplifier is directly connected to the second input terminal of the third sample and hold circuit.

[0038] Among them, the operational amplifier is used to implement signal addition, subtraction, proportional and inversion operations; the voltage difference between the sample and hold circuits is used to implement the difference calculation in the model iteration equation; the mathematical function editor is responsible for implementing the non-linear function in the model and operations. The above circuit units cooperate to form the analog circuit structure of the discrete memristor-driven neuron, and its circuit state equation can be expressed as: Where and are the voltage forms of the neuron membrane potential and the ion current recovery variable, and the multiplier gain is set to ; the resistance parameters are specifically: , , ; and The ratio of is used to adjust the parameter g in the model; the proportional gainers and are both set to ; the peak-to-peak voltage set by the staircase wave function generator is 3V, the frequency is 10 kHz, and the duty cycle is 50%; and are set to -0.1 V and 0.01 V respectively to match the initial voltage conditions, and the step duration is 0.1 ms.

[0039] During the PSIM simulation process, the simulation parameters are set as follows: the time step is , the total simulation duration is 2.1 s, and the data sampling duration is 2.0 s; by adjusting the resistance value, different parameter g values can be flexibly switched, so as to verify the diverse dynamic characteristics of the model in the simulation circuit. When the resistors are respectively configured as , and , the captured and time series and phase trajectories are as Figure 6 shown.Figure 6 The experimental simulation results of the PSIM circuit in Figure 4 are basically consistent with the numerical simulation results in

[0040] The digital implementation circuit described in the present invention is specifically a digital circuit composed of a control chip of model TMS320F28335; the iterative operation of the discrete memristor-driven neuron model is realized through the control chip, so as to realize the discrete memristor-driven neuron model with a digital circuit.

[0041] DSP has the advantages of high integration, strong reliability and low operating power consumption. Therefore, the present invention selects a digital hardware platform based on DSP to verify the foregoing simulation experiment results; the digital hardware implementation not only verifies the correctness of the discrete memristor-driven neuron model, but also provides a feasible path for its application in the engineering field.

[0042] Figure 7 shows the corresponding digital circuit implementation scheme. The hardware part includes: 1 computer, 1 emulator (XDS100-V2), 1 DSP development board (TMS320F28335), 1 digital-to-analog converter (DAC 8552) and 1 oscilloscope. Firmware compilation and debugging are carried out on the DSP integrated development environment CCS11.0 using the C language to generate machine code that can run on the DSP. Figure 7 In

[0043] Connect the output signal of the DAC module to the two channels of the oscilloscope for synchronous output observation. Channel A of the oscilloscope displays the voltage signal related to the membrane potential , and channel B displays the voltage signal of the ionic current recovery variable , and then construct the X-Y oscilloscope observation mode. Figure 8 shows the and time series corresponding to the discrete memristor-driven neuron model under different parameter conditions, as well as phase trajectories. The obtained experimental waveforms are highly consistent with the numerical simulation results shown in Figure 4

[0044] Based on the simulation results of the analog simulation on the PSIM platform and the digital hardware verification results on the DSP platform, it fully proves the effectiveness of the discrete memristor-driven neuron model in practical applications, verifies the rationality of the design scheme, and confirms the engineering feasibility of the circuit implementation through the consistency of the experimental and simulation results.

Claims

1. A design method for a discrete memristor-driven neuron, characterized in that It includes the following steps: S1. Based on the forward difference theory, determine the discrete iterative form of the voltage-controlled discrete local active memristor; S2. According to the discrete iterative form determined in step S1, design a discrete local active memristor model based on trigonometric functions; S3. Based on two-dimensional mapping, determine the discrete neuron model; S4. Substitute the discrete local active memristor model obtained in step S2 into the discrete neuron model in step S3 to obtain a discrete memristor-driven neuron model; It includes the following steps: Substitute the discrete local active memristor model obtained in step S2 into the discrete neuron model obtained in step S3. Use the magnetic flux term in the memristor to represent the ion current recovery variable term in the model expression of the discrete neuron, and map the magnetic flux variable of the memristor to the ion current recovery variable, so as to obtain a discrete memristor-driven neuron model; S5. Construct a non-linear function based on trigonometric functions and substitute it into the discrete memristor-driven neuron model obtained in step S4 to complete the design of the discrete memristor-driven neuron.

2. The design method of the discrete memristor-driven neuron according to claim 1, wherein The specific steps of step S1 are as follows: Based on the forward difference theory, the following formula is used as the discretized iterative operation form of the voltage-controlled discrete local active memristor: Wherein, is N the input voltage at time is N the output current at time is N the internal state variable of the memristor at time is the memductance function; is the non-linear modulation function; is the scaling factor.

3. The design method of the discrete memristor-driven neuron according to claim 2, characterized in that The specific steps of step S2 are as follows: Selected memory guiding function is ; select the non-linear modulation function as ; among them, a is the amplitude parameter of the non-linear modulation function ; Thus, the discrete local active memristor model is determined as follows: .

4. The design method of the discrete memristor-driven neuron according to claim 3, wherein The specific steps of step S3 are as follows: Based on a two-dimensional mapping, the discrete neuron model is represented by the following equation: Wherein is the n -th iteration value of the neuron membrane potential; I is the externally applied excitation current; is the n -th iteration value of the ionic current recovery variable; is the set first parameter; q is the set second parameter; is the set third parameter.

5. The design method of the discrete memristor-driven neuron according to claim 1, characterized in that The specific steps of step S4 are as follows: The new discrete memristor-driven neuron model is represented by the following equation: In the formula is a non-linear function with N type characteristics; k is the memristor coupling strength.

6. The design method of the discrete memristor-driven neuron according to claim 5, characterized in that The specific steps of step S5 are as follows: Construct a non-linear curve function based on the sine function as , where g is the set non-linear strength parameter, and ; Substitute the non-linear curve function into the discrete memristor-driven neuron model obtained in step S4 to obtain , and complete the design of the discrete memristor-driven neuron model.

7. An implementation circuit of a discrete memristor-driven neuron obtained by using the design method of the discrete memristor-driven neuron described in any one of claims 1 to 6, including an analog implementation circuit and a digital implementation circuit; An analog implementation circuit of a discrete memristor-driven neuron model is realized based on a sample and hold circuit, an operational amplifier, and an operational function editor; A digital implementation circuit of a discrete memristor-driven neuron model is realized based on a control chip.

8. The implementation circuit according to claim 7, wherein The analog implementation circuit includes a first staircase wave function generator, a second staircase wave function generator, a third staircase wave function generator, a first sample and hold circuit, a second sample and hold circuit, a third sample and hold circuit, a fourth sample and hold circuit, a NOT gate, a first function editor, a second function editor, a third function editor, a multiplier, a first proportional gain amplifier, a second proportional gain amplifier, a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, and a first resistor to a fourteenth resistor; The negative electrode of the first stepped wave function generator is grounded, and the first stepped wave function generator is used to generate a first initial stepped wave signal , and output the first initial stepped wave signal to the first input terminal of the first sample and hold circuit, the first input terminal of the third sample and hold circuit, and the input terminal of the NOT gate; the NOT gate is used to invert the first initial stepped wave signal , and the output terminal of the NOT gate is simultaneously connected to the first input terminal of the second sample and hold circuit and the first input terminal of the fourth sample and hold circuit; the output terminal of the first sample and hold circuit is connected to the second input terminal of the second sample and hold circuit, and the output terminal of the third sample and hold circuit is connected to the second input terminal of the fourth sample and hold circuit; the signal output from the output terminal of the second sample and hold circuit is divided into three paths, the first path is connected to the input terminal of the first function editor, the second path is connected to the first input terminal of the multiplier, and the third path is connected to the inverting input terminal of the third operational amplifier through the serially connected eighth resistor; the first function editor is used to convert the input signal into a sine signal and output it; the output terminal of the first function editor is connected to the inverting input terminal of the first operational amplifier through the serially connected first resistor; the non-inverting input terminal of the first operational amplifier is grounded; the inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through the serially connected fifth resistor; the output terminal of the first operational amplifier is connected to the inverting input terminal of the second operational amplifier through the serially connected sixth resistor; the non-inverting input terminal of the second operational amplifier is grounded; the inverting input terminal of the second operational amplifier is also connected to the output terminal of the second operational amplifier through the seventh resistor; the output terminal of the second operational amplifier is directly connected to the second input terminal of the first sample and hold circuit; the second input terminal of the multiplier is connected to the output terminal of the second function editor, and the second mathematical function editor is used to convert the input signal into a cosine signal and output it; the output terminal of the multiplier is connected to the inverting input terminal of the first operational amplifier through the second resistor; the negative electrode of the second stepped wave function generator is grounded, and the second stepped wave function generator is used to generate a second initial stepped wave signal , and output the second initial stepped wave signal to the inverting input terminal of the first operational amplifier through the serially connected third resistor; the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the first operational amplifier through the fourth resistor; the output terminal of the fourth operational amplifier is also connected to the input terminal of the second function editor through the first proportional gain device; the output terminal of the fourth sample and hold circuit is connected to the inverting input terminal of the third operational amplifier through the ninth resistor; the output terminal of the fourth sample and hold circuit is also connected to the inverting input terminal of the third operational amplifier through the serially connected second proportional gain device, the third function editor, and the tenth resistor; the third function editor is used to convert the input signal into a sine signal and output it; the negative electrode of the third stepped wave function generator is grounded, and the third stepped wave function generator is used to generate a third initial stepped wave signal , and output the third initial stepped wave signal The inverting input terminal of the third operational amplifier is connected through a series-connected twelfth resistor; the non-inverting input terminal of the third operational amplifier is grounded, and the inverting input terminal of the third operational amplifier is also connected to the output terminal of the third operational amplifier through an eleventh resistor; the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier through a series-connected thirteenth resistor; the inverting input terminal of the fourth operational amplifier is also connected to the output terminal of the fourth operational amplifier through a fourteenth resistor; the output terminal of the fourth operational amplifier is directly connected to the second input terminal of the third sample and hold circuit.

9. The implementation circuit according to claim 7, characterized in that The digital implementation circuit is specifically a digital circuit composed of a control chip with the model number TMS320F28335; The iterative operation of the discrete memristor-driven neuron model is realized through the control chip, so as to realize the discrete memristor-driven neuron model with a digital circuit.

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