Semiconductor chip, semiconductor device, and data storage system

Abstract

The invention relates to a semiconductor chip, a semiconductor device and a data storage system. A semiconductor die operating using a first clock signal and a semiconductor die operating using a second clock signal control data transmission during an operation period using a mask circuit included in each semiconductor die, to prevent or reduce data transmission and reception failures due to clock signal differences between semiconductor dies. Communication performance between semiconductor dies is improved.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0003353, filed with the Korean Intellectual Property Office on January 9, 2024, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a semiconductor chip, a semiconductor device, and a data storage system. Background Art

[0004] For example, a semiconductor device may be configured using a single semiconductor chip or multiple semiconductor chips.

[0005] When a semiconductor device is configured using a single semiconductor chip, the single semiconductor chip may communicate with another semiconductor chip located outside the semiconductor device. When a semiconductor device is configured using multiple semiconductor chips, the multiple semiconductor chips may communicate with another semiconductor chip located outside the semiconductor device or may communicate with each other among the multiple semiconductor chips inside the semiconductor device.

[0006] Therefore, when communicating between semiconductor chips with different characteristics, errors may occur during communication between the semiconductor chips due to the characteristic differences between the semiconductor chips. Summary of the Invention

[0007] Various embodiments of the disclosed technology are directed to providing a solution capable of preventing or reducing errors that occur due to characteristic differences of semiconductor chips when sending and receiving data between semiconductor chips.

[0008] In an embodiment, a semiconductor device may include: a first semiconductor die including a first transmission circuit, a first reception circuit, and a first masking circuit, the first masking circuit being configured to receive first data output by the first transmission circuit according to a first clock signal, output the first data to the outside during a first operation period, and stop outputting the first data during a second operation period; and a second semiconductor die including a second reception circuit, the second reception circuit being configured to read the first data transmitted and buffered from the first semiconductor die according to a second clock signal different from the first clock signal.

[0009] In an embodiment, a semiconductor chip may include: a transmission circuit configured to output data according to a clock signal; and a masking circuit configured to receive the clock signal and the data output from the transmission circuit, wherein the masking circuit bypasses and outputs the data during a first operation period and a second operation period, or bypasses and outputs the data during one of the first operation period and the second operation period and stops outputting the data during the other period.

[0010] In an embodiment, a data storage system may include: at least one memory device; and a controller configured to control operations of the at least one memory device, the controller including: a first chiplet including a masking circuit that receives data according to a first clock signal, outputs the data to the outside during a first operation period, and stops outputting the data during a second operation period; and a second chiplet including a buffer memory and a receiving circuit, the buffer memory receiving and storing the data, the receiving circuit reading the data stored in the buffer memory according to a second clock signal different from the first clock signal.

[0011] According to an embodiment of the disclosed technology, communication performance between semiconductor chips can be improved by preventing or reducing errors that occur when sending and receiving data between semiconductor chips with different characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing a schematic configuration of a data storage system according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram showing a method of sending and receiving data between die included in a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram showing a method of operating a masking circuit in a semiconductor die according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram showing a structure of a masking circuit included in a semiconductor die according to an embodiment of the present disclosure.

[0017] Figure 6 is a diagram showing a method of sending and receiving data between die included in a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 7 is a diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 8 is a diagram showing a method of the mask circuit included in the semiconductor die shown in Figure 7 operation. DETAILED DESCRIPTION

[0020] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which, even if the same reference numerals and symbols are shown in different drawings, these reference numerals and symbols can be used to represent the same or similar components. Further, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may obscure the subject matter in some embodiments of the present disclosure, the detailed description will be omitted. Terms such as "including", "having", "containing", "constituting", "comprising", "forming" as used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0021] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or number, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0022] When referring to a first element being "connected or coupled to", "in contact with or overlapping", etc. a second element, it should be interpreted that not only can the first element be "directly connected or coupled to" or "directly in contact with or overlapping" the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "in contact with or overlapping", etc. with each other through a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "in contact with or overlapping", etc. with each other.

[0023] When relative time terms such as "after", "subsequently", "then", "before", etc. are used to describe a process or operation of an element or configuration or a flow or step in an operation, processing, or manufacturing method, these terms can also be used to describe a non - continuous or non - sequential process or operation unless these terms are used together with the term "directly" or "immediately".

[0024] In addition, when referring to any dimensions, relative dimensions, etc., even if no relevant description is specified, the numerical values or corresponding information of the elements or features (e.g., levels, ranges, etc.) should be considered, including tolerances or error margins that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Further, the term "can" fully encompasses all meanings of the term "able to".

[0025] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] Figure 1 is a diagram showing a schematic configuration of a data storage system according to an embodiment of the present disclosure.

[0027] Referring to Figure 1 , the data storage system 100 may include at least one memory device 110. The data storage system 100 may include a controller 120 that controls the operation of the memory device 110.

[0028] The memory device 110 may be, for example, a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, but the embodiments of the disclosed technology are not limited thereto.

[0029] The memory device 110 may be a non-volatile memory. For example, the memory device 110 may be implemented as various types such as: NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory, phase change random access memory, magnetoresistive random access memory, ferroelectric random access memory, and spin transfer torque random access memory. The memory device 110 may be implemented as a three-dimensional array structure. The embodiments disclosed herein may be used for flash memories in which the charge storage layer is configured by a floating gate and charge trapping flash memories in which the charge storage layer is configured by an insulating layer.

[0030] The data storage system 100 may include a plurality of memory devices 110, and some of the plurality of memory devices 110 may be volatile memories while others may be non-volatile memories.

[0031] The controller 120 may control the operation of the memory device 110. For example, the controller 120 may control the operation of writing data to the memory device 110 or reading or erasing the data written to the memory device 110 according to a command input from the outside. The controller 120 may control the operation of the memory device 110 without considering or without an external request.

[0032] For example, the controller 120 may control the operation of the memory device 110 according to a request from the host device 200.

[0033] For example, the host device 200 may be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a telematics network, an RFID (radio frequency identification) device, a mobile device capable of being driven manually or automatically by a human (e.g., a vehicle, a robot, or a drone), etc. Optionally, the host device 200 may be a virtual reality / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. Additionally, the host device 200 may be any of various electronic devices that require the data storage system 100 capable of storing data.

[0034] The host device 200 may include at least one operating system. The operating system may manage and control the overall functions and operations of the host device 200. The operating system may control the interoperability between the host device 200 and the data storage system 100. Depending on the mobility of the host device 200, the operating system may be classified into a general operating system and a mobile operating system.

[0035] The host device 200 may use the memory included in the host device 200 to perform data processing. The host device 200 may also use the data storage system 100 located outside the host device 200 to perform data processing.

[0036] The host device 200 may communicate with the data storage system 100 through a preset interface.

[0037] For example, the host device 200 may communicate with the data storage system 100 through a Compute Express Link (CXL) interface. The host device 200 may be set as a CXL root port, and the data storage system 100 may be set as a CXL endpoint. Since the host device 200 communicates with the data storage system 100 through the CXL interface, a low-latency high-bandwidth access environment may be implemented with a high-capacity structure for communicating with the data storage system 100.

[0038] In other embodiments, the host device 200 may communicate with the data storage system 100 through an interface other than the CXL interface.

[0039] As a non-limiting example, the host device 200 and the data storage system 100 may communicate through at least one of various interface protocols such as: USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (PCI Express) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0040] Therefore, the type and number of host devices 200 that communicate with the data storage system 100 and the communication interface between the data storage system 100 and the host device 200 may vary.

[0041] The controller 120 included in the data storage system 100 that communicates with the host device 200 may communicate with the memory device 110 through a bus.

[0042] Each of the controller 120 and the memory device 110 may be configured using a single chip, or may be configured using multiple die chips. For example, the controller 120 may include a first die chip 121 and a second die chip 122. The first die chip 121 and the second die chip 122 may perform separate functions. For example, the first die chip 121 may provide an interface function with the host device 200, and the second die chip 122 may provide an interface function with the memory device 110, but the embodiments of the present disclosure are not limited thereto. For example, the controller 120 may be configured using at least three die chips.

[0043] Therefore, when the controller 120 included in the data storage system 100 is configured using multiple die chips, data can be transmitted and received between the multiple die chips.

[0044] The disclosed embodiments may provide a solution capable of improving communication performance during data transmission and reception between die chips. Embodiments of the disclosed technology may be used as an example of the controller 120, and may also be used as an example of communication between die chips of a semiconductor device including multiple die chips or between chips of a semiconductor device including multiple semiconductor chips.

[0045] Figure 2 is a diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present disclosure.

[0046] Refer to Figure 2, the semiconductor device 300 may include a first semiconductor die 310 and a second semiconductor die 320. Each of the first semiconductor die 310 and the second semiconductor die 320 may be a semiconductor chip. Optionally, each of the first semiconductor die 310 and the second semiconductor die 320 may be a die. In the die form, each of the first semiconductor die 310 and the second semiconductor die 320 may be packaged to configure the semiconductor device 300.

[0047] The first semiconductor die 310 may include a first transmission circuit 311 and a first reception circuit 312. The first transmission circuit 311 may output data to be transmitted to the outside. The first reception circuit 312 may read data received from the outside.

[0048] The first semiconductor die 310 may include a first masking circuit 313. The first masking circuit 313 may receive the data output from the first transmission circuit 311 and control the output of the corresponding data.

[0049] The first semiconductor die 310 may include a first buffer memory 314. The first buffer memory 314 may buffer the data received from the outside. The first buffer memory 314 may be a volatile memory such as SRAM, but the example is not limited thereto.

[0050] The first semiconductor die 310 may include a first clock source 315. The first clock source 315 may output a first clock signal CLK1 to the first transmission circuit 311, the first reception circuit 312, and the first masking circuit 313. The first transmission circuit 311, the first reception circuit 312, and the first masking circuit 313 may operate based on the first clock signal CLK1.

[0051] The first semiconductor die 310 may include a first interface 316. The first interface 316 may represent a physical layer and may transmit data to the outside of the first semiconductor die 310 or receive data from the outside.

[0052] The second semiconductor die 320 may include a second transmission circuit 321, a second reception circuit 322, a second masking circuit 323, a second buffer memory 324, a second clock source 325, and a second interface 326.

[0053] At least some of the components included in the second semiconductor die 320 may correspond to the components included in the first semiconductor die 310.

[0054] The second transmission circuit 321 may output data to be transmitted to the outside, and the second reception circuit 322 may read data received from the outside. The second masking circuit 323 may receive the data output from the second transmission circuit 321 and control the output of the corresponding data.

[0055] The second buffer memory 324 can buffer data received from the outside.

[0056] The second clock source 325 can output a second clock signal CLK2 to the second transmission circuit 321, the second reception circuit 322, and the second masking circuit 323. The second reception circuit 322 and the second masking circuit 323 can operate based on the second clock signal CLK2.

[0057] The second interface 326 can send data to the outside of the second semiconductor die 320 or receive data from the outside.

[0058] Data can be transmitted and received between the first semiconductor die 310 and the second semiconductor die 320 through the first interface 316 and the second interface 326.

[0059] When data is sent from the first semiconductor die 310 to the second semiconductor die 320, the first semiconductor die 310 can correspond to the sending die, and the second semiconductor die 320 can correspond to the receiving die. When data is sent from the second semiconductor die 320 to the first semiconductor die 310, the second semiconductor die 320 can correspond to the sending die, and the first semiconductor die 310 can correspond to the receiving die.

[0060] The first clock signal CLK1 output by the first clock source 315 can be different from the second clock signal CLK2 output by the second clock source 325. For example, the frequency of the first clock signal CLK1 can be greater than the frequency of the second clock signal CLK2. Optionally, the frequency of the first clock signal CLK1 can be less than the frequency of the second clock signal CLK2.

[0061] Therefore, since the frequency of the first clock signal CLK1 used in the first transmission circuit 311 that outputs data from the first semiconductor die 310 and the first reception circuit 312 that reads data is different from the frequency of the second clock signal CLK2 used in the second transmission circuit 321 that outputs data from the second semiconductor die 320 and the second reception circuit 322 that reads data, errors or failures may occur when data is transmitted and received between the first semiconductor die 310 and the second semiconductor die 320.

[0062] The first masking circuit 313 and the first buffer memory 314 included in the first semiconductor die 310 and the second masking circuit 323 and the second buffer memory 324 included in the second semiconductor die 320 can prevent or reduce errors or failures that may occur when data is transmitted and received between the first semiconductor die 310 and the second semiconductor die 320.

[0063] The first masking circuit 313 and the second masking circuit 323 can respectively control the output of the data received from the first transmitting circuit 311 and the second transmitting circuit 321. The first masking circuit 313 and the second masking circuit 323 can adjust the timing of outputting the data from the first transmitting circuit 311 and the second transmitting circuit 321 to the outside. These functions can prevent failures such as overflows in the buffer memory due to the difference between the data transmission timing and the data reading timing.

[0064] Each of the first buffer memory 314 and the second buffer memory 324 can buffer the data received from the outside, thereby preventing or reducing failures caused by the difference between the data reception timing and the reading timing of each of the first receiving circuit 312 and the second receiving circuit 322.

[0065] For example, the first transmitting circuit 311 can output the first data Data1 according to the first clock signal CLK1. The first masking circuit 313 can receive the first data Data1. The first masking circuit 313 can control whether to output the first data Data1 while operating according to the first clock signal CLK1.

[0066] The first masking circuit 313 can output the first data Data1 to the outside during the first operation period. The first masking circuit 313 can stop outputting the first data Data1 to the outside during the second operation period. Stopping the first masking circuit 313 from outputting the first data Data1 can be referred to as a masking operation or a gating operation.

[0067] The first data Data1 output by the first masking circuit 313 through the first interface 316 and the second interface 326 can be stored in the second buffer memory 324 included in the second semiconductor die 320.

[0068] The second receiving circuit 322 included in the second semiconductor die 320 can read the first data Data1 stored in the second buffer memory 324 according to the second clock signal CLK2.

[0069] Since the first masking circuit 313 outputs the first data Data1 during the first operation period and stops outputting the first data Data1 during the second operation period, the frequency at which data can be transmitted from the first semiconductor die 310 to the second semiconductor die 320 can be adjusted to a frequency different from that of the first clock signal CLK1. Even when the frequency of the first clock signal CLK1 is different from the frequency of the second clock signal CLK2, the frequency at which data can be transmitted from the first semiconductor die 310 to the second semiconductor die 320 can be adjusted to a frequency different from that of the first clock signal CLK1. Therefore, it is possible to prevent or reduce failures during data transmission and reception due to the difference between the frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2.

[0070] Similarly, the second transmission circuit 321 can output the second data Data2 according to the second clock signal CLK2. The second masking circuit 323 can receive the second data Data2 and can control whether to output the second data Data2 while operating according to the second clock signal CLK2.

[0071] For example, the second masking circuit 323 can output the second data Data2 to the outside during the third operation period. The second masking circuit 323 can stop outputting the second data Data2 to the outside during the fourth operation period.

[0072] The second data Data2 output from the second masking circuit 323 and transmitted to the first semiconductor die 310 can be stored in the first buffer memory 314.

[0073] The first receiving circuit 312 can read the second data Data2 stored in the first buffer memory 314 according to the first clock signal CLK1.

[0074] The frequency at which the second masking circuit 323 transmits the second data Data2 output from the second transmission circuit 321 to the first semiconductor die 310 can be adjusted to a frequency different from that of the second clock signal CLK2. Therefore, it is possible to prevent or reduce failures that may occur during the operation of the first receiving circuit 312 reading the second data Data2 due to the difference between the frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2.

[0075] One of the first masking circuit 313 and the second masking circuit 323 can perform a masking or gating operation, while the other may not perform a masking or gating operation.

[0076] The operation methods of the first masking circuit 313 and the second masking circuit 323 can be determined by considering the differences between the first clock signal CLK1 and the second clock signal CLK2, the sizes of the first buffer memory 314 and the second buffer memory 324, and other similar factors.

[0077] Figure 3 FIG. is a diagram illustrating a method for a die included in a semiconductor device to transmit and receive data according to an embodiment of the present disclosure.

[0078] In Figure 3 the first semiconductor die 310 transmits data to the second semiconductor die 320. Figure 3 It mainly shows the data transmission configuration among the components included in the first semiconductor die 310 and the data reception configuration among the components included in the second semiconductor die 320.

[0079] The first transmission circuit 311 included in the first semiconductor die 310 may output first data Data1 according to the first clock signal CLK1. The first data Data1 may be transmitted to the first masking circuit 313.

[0080] The first masking circuit 313 may control the output of the first data Data1.

[0081] For example, the first masking circuit 313 may operate based on a configuration value. Using the configuration value, the first masking circuit 313 may output the first data Data1 to the outside during the first operation period and may not output the first data Data1 to the outside during the second operation period. The first masking circuit 313 may stop the output of the first data Data1 during the second operation period.

[0082] The first operation period and the second operation period of the first masking circuit 313 may be set based on the configuration value.

[0083] For example, the configuration value may be a value set based on the difference between the frequency of the first clock signal CLK1 output from the first clock source 315 of the first semiconductor die 310 and the frequency of the second clock signal CLK2 output from the second clock source 325 of the second semiconductor die 320.

[0084] Optionally, the configuration value may be a value obtained during the process of training the data transmission and reception operations of the first semiconductor die 310 and the second semiconductor die 320. The configuration value may be a value obtained through a training process that reflects at least one of the difference between the frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2 and the difference between the characteristics of the first semiconductor die 310 and the characteristics of the second semiconductor die 320.

[0085] Optionally, the configuration value may be a value set based on the size of a second buffer memory 324 included in the second semiconductor die 320, which corresponds to the receiving die. When the size of the first buffer memory 314 included in the first semiconductor die 310 is the same as the size of the second buffer memory 324 included in the second semiconductor die 320, the configuration value input to the first masking circuit 313 may be regarded as a value set based on the size of the first buffer memory 314.

[0086] The operation of the first masking circuit 313 is divided into a first operation period and a second operation period by the configuration value. Dividing the operation into two operation periods controls whether the first transmission circuit 311 outputs the first data Data1.

[0087] For example, the first transmission circuit 311 may output five pieces of the first data Data1 during a predetermined period according to the first clock signal CLK1. The first masking circuit 313 may receive the first data Data1 output by the first transmission circuit 311 and control whether to output the first data Data1. The first masking circuit 313 may output only three pieces of the first data Data1 during the predetermined period when the first transmission circuit 311 outputs five pieces of the first data Data1 according to the first clock signal CLK1. During the period when five pieces of the first data Data1 can be output according to the first clock signal CLK1, the first masking circuit 313 may output only three pieces of the first data Data1.

[0088] For example, the first masking circuit 313 may output the first data Data1 to the outside during the same period when the first transmission circuit 311 outputs three pieces of the first data Data1. Then, the first masking circuit 31 may stop outputting the first data Data1, but the first transmission circuit 311 continues to output two pieces of the first data Data1. Since the first masking circuit 313 controls whether to output the first data Data1, and in this example, when the first transmission circuit 311 outputs five pieces of the first data Data1, the first masking circuit 313 outputs only three pieces of the first data Data1, the transmission frequency of the first data Data1 sent from the first semiconductor die 310 to the outside can be controlled to be different from the frequency of the first clock signal CLK1.

[0089] The first data Data1 output by the first masking circuit 313 may be stored in the second buffer memory 324 included in the second semiconductor die 320 through the first interface 316 and the second interface 326.

[0090] The second receiving circuit 322 may receive a second clock signal CLK2 from a second clock source 325. The second receiving circuit 322 may read the first data Data1 stored in the second buffer memory 324 according to the second clock signal CLK2.

[0091] During the period when the first transmission circuit 311 transmits five first data Data1 according to the first clock signal CLK1, the first masking circuit 313 may transmit three first data Data1 to the second semiconductor die 320 for storage in the second buffer memory 324. During the corresponding period, the second receiving circuit 322 may read three first data Data1 from the second buffer memory 324.

[0092] The case where the second receiving circuit 322 reads at least four first data Data1 based on the frequency of the second clock signal CLK2 or the size of the second buffer memory 324 may fail. Since the first data Data1 to be transmitted to the second semiconductor die 320 is adjusted by the first masking circuit 313, the operation of reading the first data Data1 can be performed without failure, such as an overflow of the second buffer memory 324 or a failure in the reading operation of the second receiving circuit 322.

[0093] As described in the above example, the configuration value input to the first masking circuit 313 may be a value preset according to the difference between the frequencies of the clock signals, the difference between the characteristics of the semiconductor dies, the size of the buffer memory, etc., or may be a value variably set according to the operation of the semiconductor device 300.

[0094] Figure 4 It is a diagram showing a method of operating a masking circuit in a semiconductor die according to an embodiment of the present disclosure.

[0095] Refer to Figure 4 , which shows the first masking circuit 313, the first clock source 315, and the first interface 316 included in the first semiconductor die 310.

[0096] The first masking circuit 313 may receive the first clock signal CLK1 and the first data Data1.

[0097] The first masking circuit 313 may output the first data Data1 to the outside through the first interface 316 during the first operation period. The first masking circuit 313 may stop outputting the first data Data1 during the second operation period.

[0098] The first operation period and the second operation period may be preset based on the characteristics of the semiconductor die or through training of the semiconductor die.

[0099] For example, the duration of the first operation period and the duration of the second operation period may be set based on the difference between the frequency of the first clock signal CLK1 used in the first semiconductor die 310 and the frequency of the second clock signal CLK2 used in the second semiconductor die 320 communicating with the first semiconductor die 310.

[0100] In another example, the duration of the first operation period and the duration of the second operation period can be set based on the size of the buffer memory included in the first semiconductor die 310 and the second semiconductor die 320.

[0101] The duration of the first operation period and the duration of the second operation period can be set such that data sent from the first semiconductor die 310 to the second semiconductor die 320 does not experience transmission or read failure due to differences in clock signal frequency or buffer memory size limitations.

[0102] The duration of the first operation period and the duration of the second operation period can be set based on the configuration value input to the first masking circuit 313, and this configuration value can be a fixed value.

[0103] For example, as shown in <EX 1>, the durations t11, t12, and t13 of the first operation period can be constant. The durations t21, t22, and t23 of the second operation period can be constant. The first operation period and the second operation period can be consecutive periods. The first operation period and the second operation period can alternate.

[0104] The duration of the first operation period can be greater than the duration of the second operation period. The frequency at which the first masking circuit 313 sends the first data Data1 can be adjusted, and by setting the duration of the first operation period to be greater than the duration of the second operation period, a decrease in transmission performance can be prevented or reduced. Optionally, depending on the characteristics or operating conditions of the semiconductor die, the duration of the second operation period can be greater than the duration of the first operation period.

[0105] In another example, the duration of the first operation period and the duration of the second operation period can vary. As in the example shown in <EX 2>, the durations t11, t12, and t13 of the first operation period can be different. The durations t21, t22, and t23 of the second operation period can be different.

[0106] The duration of the first operation period and the duration of the second operation period can be changed by adjusting the configuration value input to the first masking circuit 313.

[0107] For example, the configuration value can be set based on condition information including at least one of the process, voltage, and temperature of the first semiconductor die 310. The configuration value can be set based on condition information including at least one of the process, voltage, and temperature of the second semiconductor die 320.

[0108] When a condition change that may affect the data transmission / reception and reading performance of the first semiconductor die 310 or the second semiconductor die 320 occurs, by inputting a changed configuration value to the first mask circuit 313, the duration of the first operation period and the duration of the second operation period can be adjusted. The transmission frequency of the first data Data1 output to the outside through the first mask circuit 313 can be changed.

[0109] Optionally, the configuration value can be set based on the length of the first data Data1 transmitted from the first semiconductor die 310. When the length of the first data Data1 is greater than a predetermined value, the configuration value can be adjusted in consideration of the length of the first data Data1, so that the duration of the first operation period and the duration of the second operation period can be changed. For example, the configuration value can be adjusted so that the duration of the second operation period is increased before transmitting the first data Data1 to allow the second buffer memory 324 to be emptied, and the duration of the first operation period is increased or adjusted according to the period of transmitting the first data Data1 to allow the first data Data1 to be transmitted without failure.

[0110] By variably controlling the configuration value that sets the duration of the first operation period during which the first mask circuit 313 outputs the first data Data1 and the duration of the second operation period during which the first mask circuit 313 stops outputting the first data Data1, data transmission and reception can be performed according to the condition changes that occur during the operation of the first semiconductor die 310 and the second semiconductor die 320.

[0111] The configuration value can be input to at least a part of the components included in the first mask circuit 313. The structure of the first mask circuit 313 can be implemented in various ways. For example, the first mask circuit 313 can be implemented as a structure including multiple counters.

[0112] Figure 5 is a diagram showing the structure of a mask circuit included in a semiconductor die according to an embodiment of the present disclosure.

[0113] Refer to Figure 5 , and the structure of the first mask circuit 313 is taken as an example for illustration. The first mask circuit 313 can include a first counter 410 and a second counter 420.

[0114] The first mask circuit 313 can include at least one combinational logic circuit 430. The at least one combinational logic circuit 430 is used to control the operations of the first counter 410 and the second counter 420 or output a signal for controlling whether to output the first data Data1. As a circuit that outputs an output signal based on an input signal, the combinational logic circuit 430 can be implemented in various ways.

[0115] The first counter 410 may be a counter that controls the first operation period. The second counter 420 may be a counter that controls the second operation period. The first mask circuit 313 may output the first data Data1 during the period when the first counter 410 operates, and may not output the first data Data1 during the period when the second counter 420 operates.

[0116] The first counter 410 and the second counter 420 may operate based on a counter threshold. The counter threshold may be a value set based on the duration of the first operation period and the duration of the second operation period. The counter threshold may be the above-mentioned configuration value input to the first mask circuit 313, or may be a value obtained based on the configuration value.

[0117] The first counter 410 may operate based on a bypass counter threshold. The second counter 420 may operate based on an idle counter threshold.

[0118] The first counter 410 and the second counter 420 may operate based on a valid signal input together with the first data Data1. The first counter 410 and the second counter 420 may operate alternately.

[0119] For example, the first counter 410 may perform a counting operation according to a valid signal input to the first mask circuit 313 together with the first data Data1.

[0120] The period during which the first counter 410 performs the counting operation may correspond to the first operation period. The first counter 410 may end the counting based on the bypass counter threshold. The bypass counter threshold may be a value set based on the first operation period, or may be a value set in proportion to the first operation period.

[0121] During the period when the first counter 410 performs the counting operation, the first mask circuit 313 may bypass and output the first data Data1 to the outside.

[0122] When the count value of the first counter 410 reaches the bypass counter threshold, the counting operation of the first counter 410 may end. When the counting operation of the first counter 410 ends, a counter enable signal may be input to the second counter 420. The counting operation of the second counter 420 may start.

[0123] The second counter 420 may perform a counting operation based on a valid signal input to the first mask circuit 313. Optionally, the second counter 420 may perform a counting operation based on the first clock signal CLK1 input to the first mask circuit 313. In other examples, the second counter 420 may perform a counting operation without a valid signal.

[0124] The period during which the second counter 420 performs a counting operation may correspond to a second operation period. The second counter 420 may end counting based on an idle counter threshold. The second counter 420 may perform a counting operation based on a valid signal or a first clock signal CLK1 until the count value reaches the idle counter threshold. Optionally, the second counter 420 may perform a counting operation without receiving a valid signal during at least part of the second operation period. During the second operation period when data needs to be masked or gated, the second counter 420 may operate both when data is being transmitted and when no data is being transmitted. The idle counter threshold may be a value set based on the second operation period, or may be a value set in proportion to the second operation period.

[0125] During the period when the second counter 420 performs a counting operation, the first masking circuit 313 may stop outputting the first data Data1. When the counting operation of the first counter 410 ends and the counting operation of the second counter 420 starts, the first masking circuit 313 may output a transmission stop signal to the first transmission circuit 311. The first masking circuit 313 may not receive the first data Data1 from the first transmission circuit 311 during the second operation period.

[0126] When the count value of the second counter 420 reaches the idle counter threshold, the counting operation of the second counter 420 may end. When the counting operation of the second counter 420 ends, a counter enable signal may be input to the first counter 410. The counting operation of the first counter 410 may start.

[0127] When the counting operation of the second counter 420 ends, the first masking circuit 313 may output a transmission ready signal to the first transmission circuit 311. The first masking circuit 313 may receive the first data Data1 from the first transmission circuit 311, and may retransmit and output the received first data Data1 to the outside.

[0128] The duration of the first operation period and the duration of the second operation period may be adjusted according to a bypass counter threshold input to the first counter 410 and an idle counter threshold input to the second counter 420, and the first masking circuit 313 may be controlled to output the first data Data1.

[0129] The output of the first data Data1 may be controlled by the first masking circuit 313, and the transmission frequency of the first data Data1 output to the outside through the first masking circuit 313 may be adjusted to a frequency different from that of the first clock signal CLK1.

[0130] During the operation period, the masking circuit may not stop outputting data to the outside, but may retransmit and output the data.

[0131] Figure 6 It is a diagram showing a method for a die included in a semiconductor device to transmit and receive data according to an embodiment of the present disclosure.

[0132] In Figure 6 as an example, the second data Data2 is transmitted from the second semiconductor die 320 to the first semiconductor die 310. The first semiconductor die 310 may operate based on the first clock signal CLK1 output from the first clock source 315. The second semiconductor die 320 may operate based on the second clock signal CLK2 output from the second clock source 325.

[0133] The frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2 may be different. For example, the frequency of the first clock signal CLK1 may be greater than the frequency of the second clock signal CLK2.

[0134] When transmitting the first data Data1 from the first semiconductor die 310 to the second semiconductor die 320, it may be necessary to perform a masking or gating operation through the first masking circuit 313.

[0135] On the other hand, when transmitting the second data Data2 from the second semiconductor die 320 to the first semiconductor die 310, it may not be necessary to perform a masking or gating operation through the second masking circuit 323.

[0136] For example, the second transmission circuit 321 may output the second data Data2 according to the second clock signal CLK2. The second masking circuit 323 may receive the second data Data2.

[0137] The second masking circuit 323 may have a structure similar to that of Figure 5 the first masking circuit 313 shown. The counter threshold of the counter included in the second masking circuit 323 may be different from the counter threshold of the counter included in the first masking circuit 313.

[0138] During the operation period, the second masking circuit 323 may retransmit and output the second data Data2 input from the second transmission circuit 321 to the second masking circuit 323 to the outside. Among the counters included in the second masking circuit 323, the counters operating during the retransmission period may operate continuously.

[0139] The second data Data2 output from the second masking circuit 323 may be stored in the first buffer memory 314 included in the first semiconductor die 310. The first receiving circuit 312 may read the second data Data2 stored in the first buffer memory 314 according to the first clock signal CLK1.

[0140] Since the frequency of the first clock signal CLK1 is greater than that of the second clock signal CLK2, the read period of the second data Data2 can be less than the transmission period of the second data Data2. Since the probability of overflow in the first buffer memory 314 or read failure in the first receiving circuit 312 is low, the second masking circuit 323 can retransmit and output the second data Data2.

[0141] The configuration value of the second masking circuit 323 can vary according to the condition information of the first semiconductor die 310 and the second semiconductor die 320, the length of the second data Data2, and other similar factors. The second masking circuit 323 can temporarily perform masking or gating operations. The duration and timing of the period during which the second masking circuit 323 performs masking or gating operations can be different from those of the first masking circuit 313.

[0142] The transmission circuit and the receiving circuit included in the semiconductor die can operate using different clock signals. By implementing masking or gating operations using a masking circuit, failures in transmitting and receiving data between semiconductor dies can be prevented or reduced.

[0143] Figure 7 is a diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present disclosure. Figure 8 is a diagram showing Figure 7 a method of operating the masking circuit included in the semiconductor die shown in

[0144] Referring to Figure 7 , the first semiconductor die 310 may include a first transmission circuit 311, a first receiving circuit 312, a first masking circuit 313, a first buffer memory 314, and a first interface 316. The first semiconductor die 310 may include a first clock source 315 and a fourth clock source 317.

[0145] The first clock source 315 can output a first clock signal CLK1 to the first transmission circuit 311 and the first masking circuit 313. The first transmission circuit 311 and the first masking circuit 313 can operate based on the first clock signal CLK1 and can output first data Data1 to the outside.

[0146] The fourth clock source 317 can output a fourth clock signal CLK4 to the first receiving circuit 312. The first receiving circuit 312 can operate based on the fourth clock signal CLK4 and can read second data Data2 received from the second semiconductor die 320.

[0147] The second semiconductor die 320 may include a second transmission circuit 321, a second reception circuit 322, a second masking circuit 323, a second buffer memory 324, and a second interface 326. The second semiconductor die 320 may include a second clock source 325 and a third clock source 327.

[0148] The second clock source 325 may output a second clock signal CLK2 to the second reception circuit 322. The second reception circuit 322 may operate based on the second clock signal CLK2 and may read the first data Data1 received from the first semiconductor die 310.

[0149] The third clock source 327 may output a third clock signal CLK3 to the second transmission circuit 321 and the second masking circuit 323. The second transmission circuit 321 and the second masking circuit 323 may operate based on the third clock signal CLK3 and may output the second data Data2 to the outside.

[0150] The first clock signal CLK1 used when the first semiconductor die 310 transmits data may be different from the second clock signal CLK2 used when the second semiconductor die 320 reads data. The third clock signal CLK3 used when the second semiconductor die 320 transmits data may be different from the fourth clock signal CLK4 used when the first semiconductor die 310 reads data.

[0151] By performing masking or gating operations using the first masking circuit 313 and the second masking circuit 323, the transmission frequencies of the first data Data1 and the second data Data2 may be adjusted respectively.

[0152] For example, referring to Figure 8 , when the first data Data1 is transmitted from the first semiconductor die 310 to the second semiconductor die 320, the first masking circuit 313 may transfer and output the first data Data1 during a first operation period and may stop outputting the first data Data1 during a second operation period.

[0153] When the second data Data2 is transmitted from the second semiconductor die 320 to the first semiconductor die 310, the second masking circuit 323 may transfer and output the second data Data2 during a third operation period and may stop outputting the second data Data2 during a fourth operation period.

[0154] The durations t11, t12 of the first operation period and the durations t21, t22 of the second operation period may be set based on the difference between the frequencies of the first clock signal CLK1 and the second clock signal CLK2.

[0155] The durations t31, t32 of the third operation period and the durations t41, t42 of the fourth operation period can be set based on the difference between the frequency of the third clock signal CLK3 and the frequency of the fourth clock signal CLK4.

[0156] Since the difference between the frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2 can be different from the difference between the frequency of the third clock signal CLK3 and the frequency of the fourth clock signal CLK4, the ratio of the duration of the first operation period to the duration of the second operation period can be different from the ratio of the duration of the third operation period to the duration of the fourth operation period.

[0157] Based on the characteristics of the data transmission operation from the first semiconductor die 310 to the second semiconductor die 320 and the characteristics of the data transmission operation from the second semiconductor die 320 to the first semiconductor die 310, the configuration values of the first masking circuit 313 and the second masking circuit 323 can be set independently.

[0158] In addition, based on the condition information of the semiconductor die or the change in the length of the data to be transmitted, the configuration values of the first masking circuit 313 and the second masking circuit 323 can be variably set.

[0159] The clock signals used in each semiconductor die can be set to prevent transmission failures while increasing the data transmission speed.

[0160] For example, the frequency of the first clock signal CLK1 used when transmitting the first data Data1 can be greater than the frequency of the second clock signal CLK2 used when reading the first data Data1. The frequency of the third clock signal CLK3 used when transmitting the second data Data2 can be greater than the frequency of the fourth clock signal CLK4 used when reading the second data Data2.

[0161] By increasing the frequency of the clock signal used when transmitting data and controlling data transmission failures caused by differences between clock signals through a masking circuit, the data transmission and reception performance between semiconductor dies can be improved.

[0162] According to an embodiment of the disclosed technology, since the masking circuit included in the transmitting die controls the output of data in each operation period, data can be transmitted at a frequency different from the frequency of the clock signal used in the transmitting die. Communication performance can be improved while preventing or reducing data transmission and reception failures caused by differences between the clock signal of the transmitting die and the clock signal of the receiving die.

[0163] Although various embodiments of the disclosed technology have been described using specific details and variations for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the spirit and scope of the disclosed technology as defined by the appended claims, based on what is disclosed or illustrated in the disclosed technology.

Claims

1. A semiconductor device, comprising: A first semiconductor die, including a first transmission circuit, a first reception circuit, and a first masking circuit, wherein the first masking circuit receives first data output by the first transmission circuit according to a first clock signal, outputs the first data to the outside during a first operation period, and stops outputting the first data during a second operation period; And A second semiconductor die, including a second reception circuit, wherein the second reception circuit reads the first data transmitted and buffered from the first semiconductor die according to a second clock signal different from the first clock signal.

2. The semiconductor device according to claim 1, wherein At least one of the duration of the first operation period and the duration of the second operation period is set based on a difference between the frequency of the first clock signal and the frequency of the second clock signal.

3. The semiconductor device according to claim 1, wherein At least one of the duration of the first operation period and the duration of the second operation period is set based on the size of a buffer memory included in the second semiconductor die and buffering the first data.

4. The semiconductor device according to claim 1, wherein At least one of the duration of the first operation period and the duration of the second operation period is set based on condition information including at least one of the process, voltage, and temperature of the first semiconductor die.

5. The semiconductor device according to claim 1, wherein At least one of the duration of the first operation period and the duration of the second operation period is set based on the length of the first data.

6. The semiconductor device according to claim 1, wherein At least one of the duration of the first operation period and the duration of the second operation period is variable.

7. The semiconductor device according to claim 1, wherein, The second operation period is a period consecutive to the first operation period.

8. The semiconductor device according to claim 1, wherein The first operation period and the second operation period alternate.

9. The semiconductor device according to claim 1, wherein The frequency of the first clock signal is greater than the frequency of the second clock signal.

10. The semiconductor device according to claim 1, wherein The first masking circuit outputs a transmission ready signal to the first transmission circuit before the start of the first operation period.

11. The semiconductor device according to claim 1, wherein The first masking circuit outputs a transmission stop signal to the first transmission circuit before the start of the second operation period.

12. The semiconductor device according to claim 1, wherein, The first masking circuit includes: A first counter, operating based on a valid signal input together with the first data during the first operation period; and A second counter, operating during the second operation period.

13. The semiconductor device according to claim 12, wherein The second counter operates without the valid signal during at least a part of the second operation period.

14. The semiconductor device according to claim 12, wherein When the first counter operates, the first masking circuit forwards and outputs the first data, and when the second counter operates, the first masking circuit stops outputting the first data.

15. The semiconductor device according to claim 12, wherein, At least one of the first counter and the second counter receives a counter threshold set in proportion to at least one of the duration of the first operation period and the duration of the second operation period, and adjusts the counting operation period according to the counter threshold.

16. The semiconductor device according to claim 1, wherein, The second semiconductor die further includes a second transmission circuit and a second masking circuit, and The second masking circuit receives the second data output by the second transmission circuit according to the second clock signal, and forwards and outputs the second data to the outside.

17. The semiconductor device according to claim 1, wherein, The second semiconductor die further includes a second transmission circuit and a second masking circuit, and The second masking circuit receives the second data output by the second transmission circuit according to a third clock signal different from the second clock signal, outputs the second data to the outside during a third operation period, and stops outputting the second data during a fourth operation period.

18. The semiconductor device according to claim 17, wherein, The first receiving circuit reads the second data transmitted and buffered from the second semiconductor die according to the first clock signal or according to a fourth clock signal different from the first clock signal.

19. A semiconductor chip, comprising: A transmission circuit that outputs data according to a clock signal; A masking circuit that receives the clock signal and the data output from the transmission circuit, wherein the masking circuit forwards and outputs the data during a first operation period and a second operation period, or forwards and outputs the data during one of the first operation period and the second operation period and stops outputting the data during the other period.

20. A data storage system, comprising: At least one memory device; and A controller that controls the operation of the at least one memory device, The controller includes: A first die including a masking circuit that receives data according to a first clock signal, outputs the data to the outside during a first operation period, and stops outputting the data during a second operation period; and A second die including a buffer memory and a receiving circuit, the buffer memory receives and stores the data, and the receiving circuit reads the data stored in the buffer memory according to a second clock signal different from the first clock signal.

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