Storage chip, storage device and electronic equipment

Abstract

The embodiment of the invention discloses a storage chip. The storage chip comprises a storage array and a detection circuit. The detection circuit can detect whether a first electric signal of a first signal line meets the expectation or not under the condition that a second voltage is applied to signal lines, except the first signal line, in a plurality of signal lines of the storage array; therefore, whether the resistance condition on the first signal line or the capacitor charging and discharging condition on the first signal line meets the expectation or not is judged, and the electric leakage condition of the first signal line is efficiently and quickly determined.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and particularly to a storage chip, a storage device, and an electronic device. Background Art

[0002] A storage array in a storage device generally includes multiple storage units. Currently, in storage units of types such as one switch one resistor (1S1R), a selection tube and a memory are generally included, and read operations and write operations of the storage unit are implemented through bit lines and word lines connected to the storage unit.

[0003] Since the storage array generally has a large capacity, the storage units connected to each word line or bit line are often counted in the order of k (1024). Therefore, once leakage occurs in the storage array, the reliability of the storage device will be greatly affected. Therefore, there is an urgent need for a method that can quickly and effectively identify the leakage of word lines or bit lines in a storage device. Summary of the Invention

[0004] An embodiment of this application provides a storage chip that can quickly and effectively identify the leakage of word lines or bit lines in a storage device. This application also provides corresponding storage devices, electronic devices, etc.

[0005] In a first aspect of this application, a storage chip is provided. The storage chip includes: a storage array, which includes multiple storage units, and the multiple storage units are connected by multiple signal lines, and the multiple signal lines include word lines and bit lines; a detection circuit, configured to: apply a first voltage to a first signal line among the multiple signal lines, apply a second voltage to the signal lines other than the first signal line among the multiple signal lines, where the first voltage is different from the second voltage; detect a first electrical signal on the first signal line; and determine whether the first signal line is leaking according to the value of the first electrical signal.

[0006] In the first aspect, when the detection circuit applies the second voltage to the signal lines other than the first signal line of the multiple signal lines of the storage array, it can detect whether the first electrical signal of the first signal line meets the expectation, so as to determine whether the resistance situation on the first signal line or the capacitor charging and discharging situation on the first signal line meets the expectation, etc., so as to efficiently and quickly determine the leakage situation of the first signal line.

[0007] Among them, in some examples, the first voltage can be a very small voltage, that is, a voltage with an absolute value close to 0, so as to quickly detect the short-circuit leakage situation of the first signal line itself. Exemplarily, the first voltage can be 0.3V.

[0008] In a possible implementation of the first aspect, the second voltage causes the signal lines other than the first signal line among the multiple signal lines to be at zero level.

[0009] In this possible implementation, when detecting the leakage of the first signal line, only a non-0 voltage needs to be applied to the first signal line, and there is no need to apply a non-0 voltage to the other signal lines among the multiple signal lines except the first signal line. Compared with the traditional leakage detection scheme that requires applying non-0 voltages to at least two signal lines such as word lines and bit lines simultaneously for leakage detection, the control method of this possible implementation is simpler.

[0010] In a possible implementation of the first aspect, the detection circuit is configured to: during the process of continuously applying the first voltage to the first signal line, detect the current of the first signal line as the first electrical signal.

[0011] In this possible implementation, the detection circuit can apply a voltage to the first signal line through a power supply or other means, so that the voltage of the first signal line can be continuously maintained at a relatively stable voltage value (i.e., the first voltage). At this time, during the process of continuously applying the first voltage to the first signal line, by detecting the current of the first signal line, the current of the first signal line can be obtained to determine whether the resistance situation on the first signal line meets the expectation, thereby judging the fault situation of the first signal line.

[0012] In a possible implementation of the first aspect, when the detection circuit determines whether the first signal line is leaking according to the value of the first electrical signal, it is specifically configured to: compare the first electrical signal with a preset current, and when the first electrical signal is greater than the preset current, determine that the first signal line is leaking.

[0013] In this possible implementation, under the first voltage, if the first electrical signal is greater than the preset current, it means that there may be a short circuit leakage or other situations between the first signal line and other signal lines, that is, it is determined that the first signal line is leaking.

[0014] In a possible implementation of the first aspect, the detection circuit is configured to: after stopping applying the first voltage to the first signal line, detect the voltage of the first signal line as the first electrical signal.

[0015] In this possible implementation, after charging the capacitor on the first signal line and controlling the voltage of the first signal line to reach the first voltage, the charging of the capacitor on the first signal line can be stopped. Since the capacitor will start to discharge according to its discharge curve after being charged, after controlling the voltage of the first signal line to reach the first voltage, as the capacitor discharges, the voltage of the first signal line will continuously decrease. At this time, after a specified duration from the moment when the charging of the capacitor on the first signal line is stopped to stop applying the first voltage to the first signal line, it can be determined whether the voltage of the first signal line (specifically, the first capacitor voltage of the capacitor on the first signal line) meets the expectation, so as to judge whether the discharge condition of the capacitor meets the expectation and further judge the leakage condition of the first signal line.

[0016] In a possible implementation of the first aspect, when the detection circuit determines whether the first signal line is leaking according to the value of the first electrical signal, it is specifically configured to: compare the first electrical signal with a preset voltage, and when the first electrical signal is less than the preset voltage, it is determined that the first signal line is leaking.

[0017] In this possible implementation, at the first voltage, if the first electrical signal is less than the preset voltage, it indicates that the capacitor on the first signal line discharges too fast, which means that there may be a short circuit leakage or other situations between the first signal line and other signal lines, that is, it is determined that the first signal line is leaking.

[0018] In a possible implementation of the first aspect, the first voltage applied when the first signal line is a bit line is a voltage opposite to the first voltage applied when the first signal line is a word line.

[0019] In a possible implementation of the first aspect, each memory cell includes a select transistor; the detection circuit is further configured to: apply a third voltage to the first signal line, the absolute value of the third voltage being greater than the absolute value of the first voltage; detect the current of the first signal line, and when the current of the first signal line is greater than a second preset current, it is determined that there is a leakage in the select transistor of the memory cell connected to the first signal line.

[0020] In this possible implementation, the detection circuit may perform the step of applying the third voltage to the first signal line and subsequent steps when it has detected multiple signal lines of the memory chip and there is no leakage current in the multiple signal lines. Or, it can also perform the step of applying the third voltage to the first signal line and subsequent steps when it determines that a certain first signal line is not leaking during the leakage detection of a certain first signal line. In some examples, the third voltage can be applied to the first signal line after determining that the first signal line is not leaking according to the value of the first electrical signal, so that the leakage detection of the signal line itself and the leakage detection of the select transistor of the memory cell can be performed successively, realizing accurate judgment of the leakage type.

[0021] In a possible implementation of the first aspect, a leakage detection instruction is built into the detection circuit of the storage chip, and the leakage detection instruction includes the identifier of the first signal line and the value of the first voltage.

[0022] In this possible implementation, since only a non-zero voltage needs to be applied to the first signal line while other signal lines remain at zero level, therefore, it is not necessary to carry information of other signal lines except the information of the first signal line (such as information of control parameters like address information and voltage), and only the field for recording the address of the first signal line and the control parameter field for recording the voltage corresponding to the first signal line are required.

[0023] It can be seen that in this possible implementation, the field length required for the leakage detection instruction is significantly less than that of the traditional leakage detection instruction, thereby reducing the transmission time and processing time of the leakage detection instruction, etc., and improving the transmission efficiency and processing efficiency of the instruction.

[0024] The second aspect of the present application provides a storage device, which includes a storage controller and a storage chip as described in the above first aspect or any possible implementation of the first aspect. The storage controller is used to read data from the storage chip or write data to the storage chip.

[0025] The third aspect of the present application provides an electronic device, which includes a processor and a storage device as described in the above second aspect or any possible implementation of the second aspect. The processor is used to read data from the storage device or write data to the storage device.

[0026] Among them, the technical effects brought by the second aspect to the third aspect or any possible implementation thereof can refer to the technical effects brought by the first aspect or the related possible implementations of the first aspect, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a is an exemplary schematic diagram of the turn-on voltage of 1S1R when the PCM is in the high-impedance "0" state provided by an embodiment of the present application;

[0028] Figure 1b is an exemplary schematic diagram of the turn-on voltage of 1S1R when the PCM is in the low-impedance "1" state provided by an embodiment of the present application;

[0029] Figure 2 is an exemplary schematic diagram of the threshold transition voltage and read voltage of 1S1R provided by an embodiment of the present application;

[0030] Figure 3 is an exemplary schematic diagram of a storage chip provided by an embodiment of the present application;

[0031] Figure 4 is an exemplary schematic diagram of the operation of a storage cell in the 1S1R array provided by an embodiment of the present application;

[0032] Figure 5a is an exemplary schematic diagram of a storage chip provided by an embodiment of the present application;

[0033] Figure 5b is an exemplary schematic diagram of a storage device provided by an embodiment of the present application;

[0034] Figure 5c is an exemplary schematic diagram of an electronic device provided by an embodiment of the present application;

[0035] Figure 6 is an exemplary schematic diagram of a leakage detection method provided by an embodiment of the present application;

[0036] Figure 7a is an exemplary schematic diagram of leakage of a first signal line when the first signal line is a bit line in an embodiment of the present application;

[0037] Figure 7b is an exemplary schematic diagram of leakage of a first signal line when the first signal line is a word line in an embodiment of the present application;

[0038] Figure 7c is an exemplary schematic diagram of implementing leakage detection of a select transistor for a storage cell on a first signal line when there is no short - circuit leakage in the first signal line in an embodiment of the present application;

[0039] Figure 8 is an exemplary schematic diagram of a first voltage and a third voltage provided by an embodiment of the present application. Detailed implementation manners

[0040] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terms used in the embodiments part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0041] As is known to those of ordinary skill in the art, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0042] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the relationship between associated objects and indicates that three relationships may exist. For example, A and / or B may represent the following three cases: A exists alone, both A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. The terms "first", "second", etc. in the specification, claims, and the above-mentioned drawings of this application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that these terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product, or device comprising a series of units does not have to be limited to those units, but may include other units not explicitly listed or inherent to these processes, methods, products, or devices.

[0043] Before describing a storage chip, a storage device, and an electronic device provided by an embodiment of this application, some concepts related to the embodiments of this application will be described first.

[0044] 1. Phase change memory (PCM):

[0045] PCM is a new type of non-volatile semiconductor memory based on chalcogenide compounds. This memory uses a phase change material to form a storage unit, and the difference in electrical characteristics between the crystalline state and the amorphous state of the phase change material can be used to store "0" / "1" bit information. Specifically, the high-resistance amorphous state (referred to as the high-resistance state in subsequent embodiments) is defined as the RESET ("0") state, and the low-resistance crystalline state (referred to as the low-resistance state in subsequent embodiments) is defined as the SET ("1") state.

[0046] 2. Ovonic threshold switch (OTS):

[0047] OTS is a new type of two-way gated tube also based on chalcogenide compounds. When a read electrical pulse in any direction (positive or negative) and lower than a specific threshold voltage (Vth) is applied to this gated tube, the response current on it is small, generally lower than the nA level, so it presents a high-resistance non-conducting state; when an electrical pulse in any direction and higher than the specific threshold voltage (Vth) is applied to this switch, the response current on it is large, generally higher than the 10uA level, so it presents a low-resistance conducting state. The above switching characteristics of OTS (the ratio of the on-state current to the off-state current) are similar to those of a diode, and in some scenarios, the structure and manufacturing process of the two-terminal OTS are simpler than those of a diode. Therefore, OTS can be integrated with a PCM memory to achieve high-density three-dimensional storage.

[0048] 3. Single gated tube single resistor (1S1R):

[0049] It includes a storage unit integrating an OTS (selector / switch) and a PCM (resistor), namely 1S1R. In this 1S1R, the OTS and the PCM are connected in series and stacked in 3D to obtain a two-dimensional storage array or even a three-dimensional storage array, thus obtaining a storage device.

[0050] For 1S1R, when the PCM is in the high-resistance "0" state, a voltage of Vth-reset (greater than the Vth required for the OTS to turn on itself) needs to be applied across the two ends of the 1S1R to turn on the 1S1R. As Figure 1a shown, Vth-reset is equal to the threshold voltage Vth of the OTS plus the threshold voltage Vth-pcm0 of the high-resistance PCM (generally higher than 1V). According to the voltage division principle of a series circuit: when Vth-reset is applied to the 1S1R device, the high-resistance PCM also bears a certain voltage division. After subtracting this voltage division, the voltage division of the OTS is greater than the Vth of the OTS, then it can be turned on; when the PCM is in the low-resistance "1" state, a voltage of Vth-set needs to be applied across the two ends of the 1S1R to turn on the OTS. As Figure 1b shown, Vth-set is equal to the threshold voltage Vth of the OTS plus the threshold voltage Vth-pcm1 of the low-resistance PCM (generally close to 0V). The reason is similar: when Vth-set is applied to the 1S1R device, the low-resistance PCM also bears a certain voltage division (this voltage division is much lower than that of the high-resistance PCM). After subtracting this voltage division, the voltage division of the OTS is greater than its own Vth, so it can be turned on.

[0051] Based on the above characteristics, in a three-dimensional (3D) structure storage array integrated with OTS and PCM, instead of using the method of distinguishing the high-resistance state or low-resistance state of PCM to store "0" / "1" bit information, "0" / "1" bit information can be stored by identifying the threshold transition voltage of the storage unit including OTS and PCM. When the PCM is in the high-resistance state, the high threshold transition voltage is defined as "0"; when the PCM is in the low-resistance state, the low threshold transition voltage is defined as "1". The difference between the high threshold transition voltage and the low threshold transition voltage is generally greater than 1V, and a read pulse can be applied in this voltage range. For the storage unit storing "0" bit information, since its own threshold voltage is higher than the read voltage Vread of the read pulse, the OTS in the storage unit cannot be turned on, so a relatively small current is detected; for the storage unit storing "1" bit information, since its own threshold voltage is lower than the read voltage Vread, the OTS in the storage unit is turned on, so a relatively large current is detected. The above method of distinguishing the magnitude of the read current can achieve the purpose of distinguishing the storage state of the storage unit.

[0052] As Figure 2 shown in an exemplary schematic diagram of the threshold transition voltage and read voltage of 1S1R, when the PCM is in the high-resistance RESET "0" state, the current response of 1S1R under the action of the read voltage Vread (greater than Vth-set and less than Vth-reset) is small; when the PCM is in the low-resistance SET "1" state, the response current of 1S1R under the action of the read voltage Vread is large. In this way, the storage state of 1S1R can be determined by this read voltage, and thus the information stored on 1S1R can be determined.

[0053] Since the Vth of OTS and the Vth-reset voltage of 1S1R are greater than 3.3V, in actual storage devices, it is generally considered to obtain the required high voltage by applying positive and negative voltages simultaneously, for example, applying a positive voltage through the word line and applying a negative voltage through the bit line.

[0054] In the actual use process, while the 1S1R structure brings high density, it also introduces OTS with relatively weak reliability as a select tube, and the leakage of OTS may cause the failure of the entire row or column of units in the storage array, thus resulting in reliability problems.

[0055] 4. Word line (WL):

[0056] The signal lines required to select a certain physical row in the storage array, in conjunction with the bit lines, can complete the selection of a storage cell. In addition to serving as an address selection function, in storage arrays such as 3D PCM, the word lines often serve as one end of the read / write drive. In the subsequent embodiments of this application, the word lines are used as the positive end, but in actual application scenarios, this is not limited.

[0057] 5. Bit line (BL):

[0058] The signal lines required to select a certain physical column in the storage array, in conjunction with the word lines, can complete the selection of a storage cell. Similar to the word lines, in addition to serving as an address selection function, in storage arrays such as 3D PCM, the bit lines can also serve as one end of the read / write drive. In the subsequent embodiments of this application, the bit lines are used as the negative end, but in actual application scenarios, this is not limited.

[0059] 6. Bit width:

[0060] The number of storage cells read or written by the storage device each time. In a computer system, common bit widths of storage devices are 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0061] 7. Row address and column address:

[0062] Generally, a storage array is usually composed of multiple two-dimensional or even three-dimensional arranged storage cells. Each time the storage array is read or written, generally not just one storage cell is accessed, but multiple storage cells are accessed according to the size of the bit width. These multiple storage cells share a unique address. According to the two-dimensional characteristics of the planar space, the row address and the column address are two parts used to determine this unique address. And due to the aforementioned concept of bit width, generally when a certain row address is selected, actually multiple word lines may be selected; similarly, generally when a certain column address is selected, actually multiple bit lines may be selected.

[0063] With the evolution of semiconductor technology, the storage array has broken through the limitations of the classical two-dimensional layout. For a three-dimensional structure storage array, for the convenience of processing, the address of the third dimension can also be merged into the row address or the column address.

[0064] With the continuous development of technology, high-density storage devices such as 3D structures have been proposed to achieve large-capacity storage. For example, a high-density three-dimensional phase change storage device can be constructed through 1S1R storage cells of a cross bar structure.

[0065] In high-density storage devices, the spacing between the word lines and bit lines used to connect storage cells is usually very small, for example, at the 20 nm scale. The high-difficulty etching problems brought about by high density can cause adjacent word lines and bit lines to leak electricity or even short-circuit due to uneven spacing control or structural collapse. In addition, there is also a certain probability that select transistors such as OTS will experience irreversible performance degradation during use. For example, the leakage current in the subthreshold region increases or it completely becomes low resistance and loses its switching characteristics, etc., which in turn causes the entire word line or bit line to fail.

[0066] Since the storage array generally has a large capacity, the number of storage cells connected to each word line or bit line is counted in the order of k (1024). Therefore, once there is a leakage in the storage array, it will have a greater impact on the reliability of the storage device. In order to reduce the raw bit error rate (RBER), quickly and effectively or even identify the leakage of the word line or bit line in advance is crucial for improving the reliability of the entire storage device.

[0067] Currently, when detecting the leakage of a word line in a storage array, it is usually necessary to apply a voltage to the word line and sequentially apply voltages to multiple bit lines to detect the leakage of the word line; the traditional method for detecting the leakage of a bit line is similar to the above traditional method for detecting the leakage of a word line.

[0068] It can be seen that this traditional signal line leakage detection process requires multiple read and write operations, so it takes a lot of time and the detection efficiency is low. Moreover, this traditional leakage detection process cannot judge the type of leakage. For example, if it is determined that there is a leakage on a certain bit line, it may be a short-circuit leakage in the bit line itself, or it may be the performance degradation of the select transistor in one or more storage cells connected to the bit line that causes the leakage, but the specific reason for the leakage of the bit line cannot be identified.

[0069] It can be seen that the current methods for detecting the leakage of word lines and bit lines in a storage array cannot quickly and effectively identify the leakage of signal lines such as word lines or bit lines in a storage device.

[0070] Based on this, the embodiments of the present application provide a storage chip that can quickly and effectively identify the leakage of word lines or bit lines in a storage array, and in some examples, can distinguish leakage types such as select transistor leakage, word line leakage, and bit line leakage, and can also identify the leakage degree of the select transistor.

[0071] As Figure 3 shown in the example, the storage chip 30 of the embodiment of the present application includes a storage array 301 and a detection circuit 302.

[0072] The storage array 301 includes a plurality of storage cells, and the plurality of storage cells are connected by a plurality of signal lines, and the plurality of signal lines include word lines and bit lines.

[0073] The specific type of the storage array 301 is not limited herein. Exemplarily, the storage array 301 can be of types such as 3D PCM, dynamic random access memory (DRAM), flash memory, static random access memory (SRAM), etc.

[0074] The storage array 301 can be a two-dimensional storage array, or a three-dimensional storage array or a storage array of other structures.

[0075] The plurality of storage cells in the storage array 301 are connected to a plurality of signal lines, and the plurality of signal lines include word lines and bit lines.

[0076] The specific structure of the storage cell and the signal line is not limited herein. For example, each storage cell can include a memory, and in addition, in some examples, each storage cell can further include a selection transistor.

[0077] For example, as Figure 4 In the example shown, each storage cell can include a selection transistor and a memory connected in series.

[0078] Among them, the specific types of the selection transistor and the memory are not limited herein. Specifically, the selection transistor can be an OTS, or other types of selection transistors, and the memory can be a memory such as PCM.

[0079] Any storage cell in the storage array 301 can be connected to a word line and a bit line to be selected through the word line and the bit line and perform read operations and / or write operations.

[0080] For example, as Figure 4 In the example shown, taking a 1S1R array as an example, the operation of the storage cell is introduced.

[0081] In Figure 4In the example shown, a positive voltage V1 (which can be 3.5V) is generally applied to the selected word line, and only one word line is selected under the action of a read instruction or a write instruction, and a zero level V2 is applied to the remaining unselected word lines; a negative voltage V3 (which can be -3V) is generally applied to the selected bit line, and only one bit line is selected under the action of a read instruction or a write instruction, and a zero level V4 is applied to the remaining unselected bit lines. Only the voltage difference caused by the combined action of the positive voltage V1 and the negative voltage V3 can select and possibly turn on the storage unit to be operated. For example, when the voltage difference caused by the combined action of the positive voltage V1 and the negative voltage V3 is greater than Vth-reset, the OTS of the storage unit in the high-impedance state can be turned on. Other storage units that are on the same bit line or the same word line as the storage unit to be operated will not be turned on because only a half-select voltage is applied (that is to say, only a positive voltage or a negative voltage is applied under the action of a read instruction or a write instruction). There is no voltage applied to the storage units that are neither on the same bit line nor on the same word line as the storage unit to be operated, and they will not be turned on either.

[0082] Of course, in some other examples, the storage unit may not include a select transistor. Or, the connection relationship between the storage unit and the signal line may also be different from Figure 4 the example shown. Figure 4 This is only for illustrative purposes and not for limitation.

[0083] Figure 3 The detection circuit 302 shown can be connected to the signal lines in the storage array 301, so as to apply a voltage to one or more signal lines and detect the electrical signals on one or more signal lines, thereby performing leakage detection.

[0084] The specific structure of the detection circuit 302 can be various. For example, the detection circuit 302 can include multiple circuits, such as a word line leakage detection circuit and a bit line leakage detection circuit. Or, the detection circuit 302 can be obtained by improving the read / write circuit of the storage array. The improved read / write circuit can not only apply a read voltage and a write voltage to the storage array, but also apply the first voltage, the second voltage, and the third voltage, etc. during the leakage detection process of the embodiments of the present application, and can detect electrical signals such as current and voltage on the word line and the bit line.

[0085] Next, Figure 5a an exemplary specific structure of the storage chip 30 will be introduced.

[0086] As Figure 5a shown, it is a schematic diagram of an exemplary structure of the storage chip 30 in the embodiments of the present application.

[0087] In Figure 5aIn the example shown, the storage chip 30 may include an IO circuit module, an instruction decoder, a control circuit, a word line leakage detection circuit, a row decoder, a bit line leakage detection circuit, a column decoder, a read / write circuit, and a storage array.

[0088] In Figure 5a the example shown, the leakage detection of the signal lines in the storage array can be implemented through the word line leakage detection circuit and the bit line leakage detection circuit, and the read / write operation on the storage array can be performed through the read / write circuit. Among them, the word line leakage detection circuit and the read / write circuit can control the storage array through the row decoder, and the bit line leakage detection circuit and the read / write circuit can control the storage array through the column decoder. The control circuit can control the word line leakage detection circuit, the bit line leakage detection circuit, and the read / write circuit, etc. In addition, the storage chip 30 can perform information interaction with other devices through the IO circuit module, and decode the instructions (such as leakage detection instructions, etc.) received through the IO circuit module through the instruction decoder, and then control through the control circuit.

[0089] It can be seen that in Figure 5a the example shown, the leakage detection of the signal lines can be implemented through the word line leakage detection circuit and the bit line leakage detection circuit.

[0090] It should be noted that Figure 5a the example shown is only an exemplary structural schematic diagram of the storage chip 30, rather than a limitation. In some other examples, the structure of the storage chip 30 may be other situations.

[0091] For example, in some other examples, the word line leakage detection circuit and the bit line leakage detection circuit can be integrated together. Or, the word line leakage detection circuit or the bit line leakage detection circuit can also be integrated or merged with other circuits. For example, it can be merged with the read / write circuit to implement functions such as controlling the word lines and bit lines of the storage array and reading electrical signals.

[0092] In some examples, as Figure 5b shown, the storage chip 30 can be connected to the storage controller 401, and both the storage chip 30 and the storage controller 401 are included in the storage device 40. The storage controller 401 is used to read data from the storage chip 30 or write data to the storage chip 30.

[0093] The storage controller 401 is a device that performs necessary control on the access to the storage chip 30 according to certain timing rules, including the control of address signals, data signals, and various command signals, so that the device accessing the storage chip 30 (such as a processor, etc.) can use the storage resources on the storage chip 30 according to its own requirements.

[0094] In addition, in some examples, as Figure 5cAs shown, the storage device 40 may also be connected to a processor 501, and both the storage device 40 and the processor 501 are included in the electronic device 50. The processor 501 is used to read data from or write data to the storage device 40.

[0095] The processor 501 may be a central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any combination thereof. The processor 501 may write data (such as a leakage detection instruction) to the storage device 40, or read data (such as a leakage detection result) from the storage device 40.

[0096] In this example, the processor 501 may send the leakage detection instruction to the storage chip 30 through the storage controller 401. After receiving the leakage detection instruction through the IO circuit module, the storage chip 30 may parse the leakage detection instruction through an instruction decoder, and thus may perform leakage detection on signal lines such as word lines or bit lines in the storage array through a word line leakage detection circuit or a bit line leakage detection circuit. Then, the word line leakage detection circuit or the bit line leakage detection circuit may detect an electrical signal, determine the leakage detection situation of the storage chip, and return it to the processor.

[0097] In the embodiments of the present application, leakage detection of a first signal line among multiple signal lines may be implemented through the detection circuit in the storage chip of any of the above embodiments.

[0098] The first signal line may be a bit line or a word line.

[0099] Specifically, as Figure 6 shown, the detection circuit is used to execute steps 601-603.

[0100] Step 601: Apply a first voltage to the first signal line among the multiple signal lines, and apply a second voltage to the signal lines other than the first signal line among the multiple signal lines.

[0101] The first voltage is different from the second voltage.

[0102] In the embodiments of the present application, the first voltage applied when the first signal line is a bit line and the first voltage applied when the first signal line is a word line are opposite voltages.

[0103] For example, when the first signal line is a bit line, the first voltage is a negative voltage, while when the first signal line is a word line, the first voltage is a positive voltage.

[0104] In the embodiments of the present application, there are various ways to apply the first voltage to the first signal line.

[0105] For example, in some examples, the first voltage can be continuously applied to the first signal line through a power supply or the like. In this way, the voltage of the first signal line can be stably maintained at the first voltage.

[0106] In other examples, the first voltage can be applied to the first signal line among the multiple signal lines by charging a capacitor on the first signal line.

[0107] The capacitor on the first signal line can be the parasitic capacitance of the first signal line, which is a capacitance generated due to the structure of the first signal line itself. Or, in some examples, a capacitor can also be connected to the first signal line.

[0108] In this example, charging the capacitor on the first signal line can be to apply the first voltage to one end of the capacitor so that the capacitor voltage reaches the first voltage, and after the capacitor voltage reaches the first voltage, charging the capacitor can be stopped. One end of the capacitor to which the first voltage is applied can be connected to the storage unit through the first signal line.

[0109] The first voltage can be a voltage that does not cause the storage unit connected to the first signal line to turn on in the case of no fault.

[0110] The specific value of the first voltage can be determined based on the specific fault detection scenario. Exemplarily, the first voltage can be a voltage close to 0 to detect whether there is a short circuit leakage on the first signal line.

[0111] In the embodiments of the present application, the second voltage applied to the signal lines other than the first signal line among the multiple signal lines is a voltage that does not affect the leakage detection of the first signal line. In some embodiments, the second voltage makes the signal lines other than the first signal line among the multiple signal lines all at zero level.

[0112] Among them, making the signal lines other than the first signal line among the multiple signal lines at zero level can be to ground the signal lines other than the first signal line among the multiple signal lines, so that the voltage on the signal lines other than the first signal line among the multiple signal lines is 0.

[0113] In this way, when detecting the leakage of the first signal line, only a non-zero voltage needs to be applied to the first signal line, and there is no need to apply a non-zero voltage to other signal lines except the first signal line among the multiple signal lines. Compared with the traditional leakage detection scheme that requires applying non-zero voltages to at least two signal lines such as word lines and bit lines simultaneously for leakage detection, the control method of the embodiment of the present application is simpler.

[0114] Step 602: Detect the first electrical signal on the first signal line.

[0115] In different scenarios, the specific form of the first electrical signal may be different.

[0116] In some examples, during the process of continuously applying the first voltage to the first signal line by the detection circuit, the current of the first signal line is detected as the first electrical signal.

[0117] In this example, the detection circuit can apply a voltage to the first signal line through a power supply or other means, so that the voltage of the first signal line can be continuously maintained at a relatively stable voltage value (i.e., the first voltage). At this time, during the process of continuously applying the first voltage to the first signal line, by detecting the current of the first signal line, the current of the first signal line can be obtained to determine whether the resistance situation on the first signal line meets the expectation, thereby judging the fault situation of the first signal line.

[0118] In other examples, after the detection circuit stops applying the first voltage to the first signal line, the voltage of the first signal line is detected as the first electrical signal.

[0119] In this example, after charging the capacitor on the first signal line to control the voltage of the first signal line to reach the first voltage, the charging of the capacitor on the first signal line can be stopped. Since the capacitor will start to discharge according to the discharge curve of the capacitor after charging, therefore, after controlling the voltage of the first signal line to reach the first voltage, as the capacitor discharges, the voltage of the first signal line will continuously decrease. At this time, after a specified duration from the moment when the charging of the capacitor on the first signal line is stopped to stop applying the first voltage to the first signal line, it can be determined whether the voltage of the first signal line (specifically, the first capacitor voltage of the capacitor on the first signal line) meets the expectation, thereby judging whether the discharge situation of the capacitor meets the expectation to judge the leakage situation of the first signal line.

[0120] Among them, the specified duration can be determined according to the normal discharge curve of the capacitor. Exemplarily, in the normal discharge curve of the capacitor, at the moment 5 ms after the moment when the voltage on the first signal line is controlled to reach the first voltage and the charging of the capacitor stops, the capacitor voltage drops by 20%. Then, at the moment 5 ms after the moment when the application of the first voltage to the first signal line stops, it can be detected whether the first capacitor voltage of the capacitor meets the expectation (for example, it drops by about 20% relative to the first voltage, or the drop amplitude is much greater than 20%), so as to determine the leakage situation of the first signal line.

[0121] Step 603, determine whether the first signal line is leaking according to the value of the first electrical signal.

[0122] In the embodiments of the present application, it can be detected whether the first electrical signal of the first signal line meets the expectation, so as to determine whether the resistance situation on the first signal line or the capacitor charge and discharge situation on the first signal line meets the expectation, etc., so as to efficiently and quickly determine the leakage situation of the first signal line.

[0123] Among them, in some embodiments, the leakage type on the first signal line can be identified by setting the value of the first voltage.

[0124] In this embodiment, the first voltage can be a very small voltage, that is, a voltage with an absolute value close to 0, so as to quickly detect the short-circuit leakage situation of the first signal line itself. Exemplarily, the first voltage can be 0.3V.

[0125] In addition, since the type of the first electrical signal may be different in different situations, therefore, the specific conditions for determining whether the first signal line is leaking according to the value of the first electrical signal can also be determined according to the specific situation.

[0126] In one example, during the process of the detection circuit continuously applying the first voltage to the first signal line, the current of the first signal line is detected as the first electrical signal.

[0127] At this time, when the detection circuit determines whether the first signal line is leaking according to the value of the first electrical signal, it is specifically used for:

[0128] Compare the first electrical signal with a preset current. When the first electrical signal is greater than the preset current, it is determined that the first signal line is leaking.

[0129] In this example, at a small voltage, if the first electrical signal is greater than the preset current, it means that there may be a short-circuit leakage situation between the first signal line and other signal lines, that is, it is determined that the first signal line is leaking.

[0130] In another example, after the detection circuit stops applying the first voltage to the first signal line, the voltage of the first signal line is detected as the first electrical signal.

[0131] At this time, when the detection circuit determines whether the first signal line is leaking electricity according to the value of the first electrical signal, it is specifically used for:

[0132] Compare the first electrical signal with a preset voltage. When the first electrical signal is less than the preset voltage, it is determined that the first signal line is leaking electricity.

[0133] In this example, the voltage of the first signal line can be the first capacitance voltage of the capacitor on the first signal line. At a low voltage, if the first capacitance voltage is less than the preset voltage, it means that the capacitor discharges too fast, indicating that there may be a short circuit and leakage between the first signal line and other signal lines. That is to say, it is determined that the first signal line is leaking electricity.

[0134] Such as Figure 7a shown, it is an exemplary schematic diagram of the first signal line leaking electricity when the first signal line is a bit line.

[0135] Among them, a certain bit line of the storage array is used as the first signal line. At this time, zero levels are applied to the word lines in the storage array and other bit lines except this bit line.

[0136] If, after the voltage of this bit line reaches the first voltage, it is detected that the current of this bit line is greater than the preset current or the voltage of this bit line is less than the preset voltage, it can be determined that there is a situation of bit line short circuit and leakage for this bit line.

[0137] Such as Figure 7b shown, it is an exemplary schematic diagram of the first signal line leaking electricity when the first signal line is a word line.

[0138] Among them, a certain word line of the storage array is used as the first signal line. At this time, zero levels are applied to the bit lines in the storage array and other bit lines except this word line.

[0139] If, after the voltage of this word line reaches the first voltage, it is detected that the current of this word line is greater than the preset current or the voltage of this bit line is less than the preset voltage, it can be determined that there is a situation of word line short circuit and leakage for this word line.

[0140] In some embodiments, if a first voltage is applied to the first signal line among multiple signal lines and the signal lines other than the first signal line among the multiple signal lines are all at zero level, and then the first electrical signal of the first signal line is detected, and according to the first electrical signal, it is determined that the first signal line itself is not leaking electricity, then the leakage situation of the storage unit can be detected. Among them, in many cases, the select tube in the storage unit is more likely to deteriorate in performance and thus lose its switching characteristics. Therefore, usually, the leakage situation of the select tube in the storage unit can be detected to determine the performance of the select tube.

[0141] Next, the leakage detection process of the detection unit will be introduced.

[0142] Specifically, in some embodiments, each memory cell includes a select transistor;

[0143] The detection circuit is further configured to:

[0144] Apply a third voltage to the first signal line, where the absolute value of the third voltage is greater than the absolute value of the first voltage;

[0145] Detect the current of the first signal line. When the current of the first signal line is greater than a second preset current, it is determined that there is a leakage in the select transistor of the memory cell connected to the first signal line.

[0146] In the embodiments of the present application, the detection circuit may perform the step of applying the third voltage to the first signal line and subsequent steps when the detection of multiple signal lines of the memory chip is completed and there is no leakage current in the multiple signal lines. Alternatively, the step of applying the third voltage to the first signal line and subsequent steps may also be performed when the leakage detection of a certain first signal line is completed and it is determined that there is no leakage in the first signal line.

[0147] In addition, in some examples, after stopping applying the first voltage to the first signal line, the voltage of the first signal line may be detected. When the voltage of the first signal line is less than a second preset voltage, it is determined that there is a leakage in the select transistor of the memory cell connected to the first signal line.

[0148] As Figure 7c shown, it is an exemplary schematic diagram for implementing the leakage detection of the select transistor of the memory cell on the first signal line when there is no short-circuit leakage in the first signal line.

[0149] As Figure 7c shown in the example, if a third voltage is applied to the first signal line and it can be detected that the current of the first signal line is greater than a second preset current, it is determined that there is a leakage in the select transistor of the memory cell.

[0150] It can be seen that in the embodiments of the present application, after determining that the first signal line is not leaking according to the value of the first electrical signal, the third voltage can be applied to the first signal line, so that the leakage detection of the signal line itself and the leakage detection of the select transistor of the memory cell can be performed successively, realizing the accurate judgment of the leakage type.

[0151] In addition, in the embodiments of the present application, the number of the third voltages may be one or more, which is not limited herein.

[0152] In some embodiments, the number of the third voltages is multiple;

[0153] After determining that the first signal line is not leaking, the detection circuit is further configured to:

[0154] Apply a plurality of third voltages to the first signal line in a preset order, and detect the current of the first signal line each time a third voltage is applied to the first signal line, until it is detected that the current of the first signal line corresponding to any one of the third voltages is greater than the corresponding second preset current, then it is determined that there is a leakage in the select tube of the memory cell connected to the first signal line, or until all the plurality of third voltages are traversed.

[0155] In the embodiments of the present application, the second preset currents corresponding to different third voltages may be different or the same. Exemplarily, the second preset current corresponding to a smaller third voltage is less than the second preset current corresponding to a larger third voltage. And if it is determined whether there is a leakage in the select tube by detecting the voltage of the first signal line, the second preset voltage corresponding to a smaller third voltage is less than the second preset voltage corresponding to a larger third voltage.

[0156] In the embodiments of the present application, in some examples, the preset order may be an order from small to large. In this way, the voltage of the first signal line can be controlled to gradually increase, the control difficulty is small, and the time consumed in the control process is usually small. Moreover, within the voltage range, the leakage condition of the memory cell can be detected flexibly and comprehensively through a plurality of third voltages, improving the accuracy of leakage detection and facilitating the timely discovery of leakage.

[0157] In some embodiments, the detection circuit is configured to:

[0158] If it is detected that the current of the first signal line corresponding to any one of the third voltages is greater than the corresponding second preset current, then determine the leakage degree of the select tube of the memory cell according to the third voltage.

[0159] In the embodiments of the present application, the leakage condition of the select tube of the memory cell can be detected in segments through a plurality of third voltages, so as to identify the degree of performance deterioration of devices such as the memory cell on the first signal line, providing important information for the detection of the life state of the memory cell.

[0160] For example, if among the plurality of third voltages, it is detected that there is a leakage in the select tube when a smaller third voltage is applied to the first signal line, the leakage condition of devices such as the select tube in the memory cell is relatively serious, indicating that the performance of the memory cell deteriorates relatively seriously and the wear degree is relatively high.

[0161] In the embodiments of the present application, the specific value of the third voltage may be within a specified range.

[0162] Wherein, the absolute value of the third voltage is greater than the absolute value of the first voltage. In addition, in some embodiments, the absolute value of the third voltage is not greater than the second preset voltage.

[0163] The second preset voltage may not be higher than the maximum value of the absolute value of the voltage of the word line connected to the storage cell and the absolute value of the voltage of the bit line connected to the storage cell during a write operation or a read operation on the storage cell.

[0164] Wherein, when the storage array is not faulty, during a write operation or a read operation on the storage cell, the voltage of the word line connected to the storage cell and the voltage of the bit line connected to the storage cell can be regarded as semi-selection voltages. Then, the second preset voltage may not be higher than the semi-selection voltage. When only the semi-selection voltage is applied to the storage cell, generally, the storage cell will not be turned on. At this time, the current of the first signal line should be less than the second preset current. When the current of the first signal line is greater than the second preset current, it is determined that there is a leakage in the selection tube connected to the storage cell of the first signal line.

[0165] Next, in combination with Figure 8 , an exemplary introduction to the values of the first voltage and one or more third voltages will be given.

[0166] For example, Figure 8 in the example shown, the storage cell is 1S1R.

[0167] At this time, by applying a very small voltage (i.e., the first voltage whose absolute value is close to 0), the short-circuit leakage condition of the first signal line itself can be quickly detected.

[0168] Exemplarily, the first voltage may be 0.3V.

[0169] In addition, it can be understood that during normal read and write operations on the storage cell, the differential pressure jointly exerted by the word line and the bit line connected to the storage cell can turn on the storage cell. If only a voltage is applied to the storage cell through the word line and a zero level is applied to the storage cell through the bit line, or only a voltage is applied to the storage cell through the bit line and a zero level is applied to the storage cell through the word line, it can be considered that only the semi-selection voltage is applied to the storage cell.

[0170] In a normal circuit, a storage cell to which only the semi-selection voltage is applied will not be turned on.

[0171] During leakage detection, the second preset voltage corresponding to the storage cell may be greater than the first voltage and is a voltage that will not cause the storage cell to turn on in the case of no fault. Then, the second preset voltage can be regarded as the semi-selection voltage. When there are multiple values of the semi-selection voltage (for example, when the absolute value of the voltage applied to the word line of the storage cell is different from the absolute value of the voltage applied to the bit line of the storage cell), the second preset voltage can be regarded as the maximum value of the absolute values of the semi-selection voltages.

[0172] Specifically, the second preset voltage may not be higher than the maximum value of the absolute value of the voltage of the word line connected to the memory cell and the absolute value of the voltage of the bit line connected to the memory cell during a write operation or a read operation of the memory cell. Moreover, the second preset voltage is less than the turn-on voltage Vth-reset of the 1S1R memory cell when the PCM is in the high-impedance "0" state, the turn-on voltage Vth-set of the 1S1R memory cell when the PCM is in the low-impedance "1" state, and the read voltage Vread of the memory cell.

[0173] At this time, the third voltage in the embodiment of the present application may be in a voltage range greater than the first voltage and not greater than the second preset voltage, and one or more third voltages may be selected within this voltage range for leakage detection.

[0174] For example, in Figure 8 the example shown, the third voltage 1 and the third voltage 2 can be determined, so as to perform segmented detection of the leakage of the memory cell through the third voltage 1 and the third voltage 2, thereby identifying the wear degree of devices such as the memory cell on the first signal line, and providing important information for the life state detection of the memory cell.

[0175] In the embodiment of the present application, there are various ways to trigger the memory chip to execute the above step 601 and subsequent steps. For example, it may be that the user inputs a leakage detection instruction through the processor of the electronic device, and this leakage detection instruction is transmitted to the memory chip through the memory controller to trigger the memory chip to execute the above step 601 and subsequent steps. Or, it may also be that the leakage detection instruction is pre-configured in the memory chip, and the processor can send an indication message to the memory chip to instruct the memory chip to perform leakage detection according to the information in the pre-configured leakage detection instruction; or, it may also be that the memory chip periodically performs leakage detection according to the information in the pre-configured leakage detection instruction.

[0176] It can be seen that in some examples, before the memory chip executes the above step 601, a leakage detection instruction can be built into the detection circuit of the memory chip.

[0177] The leakage detection instruction includes the identifier of the first signal line and the value of the first voltage.

[0178] In this way, the memory chip can execute the above step 601 and subsequent steps according to the leakage detection instruction.

[0179] In the embodiment of the present application, the leakage detection instruction is used to indicate leakage detection of the first signal line.

[0180] The leakage detection instruction may include multiple fields. One field may record the identifier of the first signal line, and another field may record the value of the first voltage.

[0181] The identifier of the first signal line may be the number of the first signal line or the address of the first signal line, etc.

[0182] Among them, according to the field in the leakage detection instruction that records the identifier of the first signal line, the first signal line can be determined, and according to the field that records the value of the first voltage in the leakage detection instruction, the magnitude of the voltage applied to the first signal line can be determined.

[0183] In addition, in some other examples, the leakage detection instruction may further include other fields to record one or more of information such as the identifier of the leakage detection instruction and other control parameters.

[0184] One or more fields in the leakage detection instruction can be sent through one cycle or through multiple cycles.

[0185] Compared with the traditional leakage detection instruction, the leakage detection instruction in the embodiments of the present application can have fewer fields, so that information transmission and processing can be more efficient.

[0186] Specifically, in the traditional leakage detection instruction, the following fields may be included: information such as the identifier of the leakage detection instruction, column address (address of the bit line), row address (address of the bit line), control parameters of the bit line, and control parameters of the word line.

[0187] For example, Table 1 shows the information of the fields in the traditional leakage detection instruction.

[0188] Table 1: Information in the traditional leakage detection instruction

[0189]

[0190] In Table 1, the identifier of the leakage detection instruction is used to indicate the execution of leakage detection. And in the traditional leakage detection instruction, the voltages applied to the word line and the bit line are not 0. Therefore, in the control parameters, the information of the voltage to be applied to the word line and the information of the voltage to be applied to the bit line need to be included.

[0191] In some examples of the present application, the information of the fields of the leakage detection instruction is shown in Table 2.

[0192] Table 2: Information in an exemplary leakage detection instruction of the present application

[0193]

[0194] In the example shown in Table 2, the identifier of the leakage detection instruction is used to indicate the execution of leakage detection. The address of the first signal line is the identifier of the first signal line.

[0195] In this example, since only a non-zero voltage needs to be applied to the first signal line while the other signal lines remain at zero level, compared with the example shown in Table 1, in the example shown in Table 2, there is no need to carry the information of other signal lines except the information of the first signal line (such as information of control parameters such as address information and voltage), and only the field for recording the address of the first signal line and the control parameter field for recording the voltage corresponding to the first signal line are required. In some examples, it may also include an identifier of a leakage detection instruction.

[0196] It can be seen that in the example shown in Table 2, the field length required for the leakage detection instruction is significantly less than that of the traditional leakage detection instruction, thereby reducing the transmission time and processing time of the leakage detection instruction, etc., and improving the transmission efficiency and processing efficiency of the instruction.

[0197] In the embodiment of the present application, after step 601 is executed according to the leakage detection instruction, the detection circuit of the storage chip needs to wait for a certain time delay to obtain the first electrical signal of the first signal line and determine the leakage situation of the first signal line.

[0198] Among them, in one example, after the leakage detection instruction is executed and after a certain time delay to determine the leakage situation of the first signal line, regardless of whether the leakage situation of the first signal line indicates that the first signal line is leaking or not leaking, feedback information is returned to the processor of the electronic device.

[0199] In other examples, since the probability of leakage occurrence is very low, therefore, an early warning method can also be adopted, that is to say, only when the leakage detection instruction is executed and it is determined that the first signal line has a leakage after a certain time delay, feedback information is returned to the processor and it is indicated that the first signal line has a leakage.

[0200] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses, chips, and units can refer to the corresponding processes in the foregoing embodiments, and will not be elaborated herein.

[0201] In several embodiments provided by the present application, it should be understood that the disclosed devices, apparatuses, chips, units, and methods can be implemented in other ways. For example, the above-described embodiments are merely illustrative. For example, the division of units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0202] The unit described as a separating component may or may not be physically separated. The component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed over multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0203] In addition, each functional unit in various embodiments of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0204] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, read-only memory), random access memories (RAM, random access memory), magnetic disks, or optical discs that can store program codes.

Claims

1. A storage chip, the storage chip comprising: A storage array including a plurality of storage units, the plurality of storage units being connected by a plurality of signal lines, the plurality of signal lines including word lines and bit lines; A detection circuit for: Applying a first voltage to a first signal line among the plurality of signal lines, and applying a second voltage to signal lines other than the first signal line among the plurality of signal lines, the first voltage being different from the second voltage; Detecting a first electrical signal on the first signal line; Judging whether the first signal line is leaking electricity according to the value of the first electrical signal.

2. The storage chip according to claim 1, characterized in that, The second voltage causes the signal lines other than the first signal line among the plurality of signal lines to be at zero level.

3. The storage chip according to claim 1, wherein, The detection circuit is used for: During the process of continuously applying the first voltage to the first signal line, detecting the current of the first signal line as the first electrical signal.

4. The memory chip according to claim 3, wherein When the detection circuit judges whether the first signal line is leaking electricity according to the value of the first electrical signal, specifically: Comparing the first electrical signal with a preset current, and when the first electrical signal is greater than the preset current, determining that the first signal line is leaking electricity.

5. The storage chip according to claim 1, wherein The detection circuit is used for: After stopping applying the first voltage to the first signal line, detecting the voltage of the first signal line as the first electrical signal.

6. The storage chip according to claim 5, characterized in that When the detection circuit judges whether the first signal line is leaking electricity according to the value of the first electrical signal, specifically: Comparing the first electrical signal with a preset voltage, and when the first electrical signal is less than the preset voltage, determining that the first signal line is leaking electricity.

7. The storage chip according to any one of claims 1-6, characterized in that, The first voltage applied when the first signal line is a bit line and the first voltage applied when the first signal line is a word line are opposite voltages.

8. The storage chip according to any one of claims 1 to 7, characterized in that, Each of the storage units includes a select tube; the detection circuit is further used for: Applying a third voltage to the first signal line, the absolute value of the third voltage being greater than the absolute value of the first voltage; Detecting the current of the first signal line, and when the current of the first signal line is greater than a second preset current, determining that there is a leaking select tube in the storage unit connected to the first signal line.

9. The storage chip according to any one of claims 1 to 8, characterized in that, A leakage detection instruction is built in the detection circuit of the storage chip, and the leakage detection instruction includes an identifier of the first signal line and a value of the first voltage.

10. A storage device, characterized in that, The storage device includes a storage controller and the storage chip according to any one of claims 1 to 9, and the storage controller is used for reading data from the storage chip or writing data into the storage chip.

11. An electronic device, characterized in that, The electronic device includes a processor and the storage device according to claim 10, and the processor is used for reading data from the storage device or writing data into the storage device.

Images