Memory and operation method thereof, memory system and computer system

Abstract

The embodiment of the invention provides a memory, an operation method thereof, a memory system and a computer system. The memory comprises a test circuit; the test circuit comprises a first selection circuit which comprises a plurality of first input ends, a first selection signal end and a first output end; wherein each first input end in the plurality of first input ends is used for receiving one high-speed periodic signal in the plurality of high-speed periodic signals, and the first selection signal end is used for receiving a first selection signal; the first selection circuit is configured to select one of the plurality of high-speed periodic signals based on a first selection signal, and output the selected high-speed periodic signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a memory and an operation method thereof, a memory system, and a computer system. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. With the continuous progress of semiconductor manufacturing processes, the feature size of semiconductor devices has been continuously reduced, the integration density of memories has become higher and higher, and their performance has become more and more powerful. For example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and NAND memory, etc., are all commonly used semiconductor storage devices in computers.

[0003] Before and after the memory is packaged, it is necessary to output the internal signals in the memory to the outside of the memory and test their levels and timings to verify the functions of the memory. Therefore, how to optimize the design of the circuit for outputting internal signals in the memory has become an urgent problem in the industry. Summary of the Invention

[0004] The present disclosure provides a memory and an operation method thereof, a memory system, and a computer system.

[0005] In a first aspect, the present disclosure provides a memory, the memory includes a test circuit; the test circuit includes:

[0006] A first selection circuit, the first selection circuit includes a plurality of first input terminals, a first selection signal terminal, and a first output terminal; wherein, each of the plurality of first input terminals is used to receive one of a plurality of high-speed periodic signals, and the first selection signal terminal is used to receive a first selection signal;

[0007] The first selection circuit is configured to select one of the plurality of high-speed periodic signals based on the first selection signal and output the selected high-speed periodic signal.

[0008] In some embodiments, the test circuit further includes:

[0009] A second selection circuit, the second selection circuit including a plurality of second input terminals, a second selection signal terminal, and a second output terminal; wherein, each of the plurality of second input terminals is configured to receive one of a plurality of first internal signals, and the second selection signal terminal is configured to receive a second selection signal; the second selection circuit is configured to select one of the plurality of first internal signals based on the second selection signal and output the selected first internal signal;

[0010] A third selection circuit, the third selection circuit including a plurality of third input terminals, a third selection signal terminal, and a third output terminal; wherein, each of the plurality of third input terminals is configured to receive one of a plurality of second internal signals, and the third selection signal terminal is configured to receive a third selection signal; the third selection circuit is configured to select one of the plurality of second internal signals based on the third selection signal and output the selected second internal signal;

[0011] Wherein, the voltage range of the second internal signal is different from the voltage range of the first internal signal.

[0012] In some embodiments, the memory further includes:

[0013] A first test pad, the first test pad being coupled to the second output terminal through a first signal path; wherein, the first test pad is encapsulated inside the memory; the first internal signal output by the second selection circuit is transmitted to the first test pad through the first signal path;

[0014] A second test pad, the second test pad being coupled to the third output terminal through a second signal path; wherein, the second test pad is encapsulated inside the memory; the second internal signal output by the third selection circuit is transmitted to the second test pad through the second signal path.

[0015] In some embodiments, the memory further includes:

[0016] A first data pad, the first data pad being coupled to the second output terminal through a third signal path; wherein, the first internal signal output by the second selection circuit is transmitted to the outside of the memory through the third signal path and the first data pad;

[0017] A second data pad, the second data pad being coupled to the third output terminal through a fourth signal path; wherein, the second internal signal output by the third selection circuit is transmitted to the outside of the memory through the fourth signal path and the second data pad.

[0018] In some embodiments, the test circuit further includes:

[0019] A voltage regulation circuit, coupled to the second selection circuit and the first data pad respectively; the voltage regulation circuit is configured to: based on a voltage regulation signal, regulate the voltage of the first internal signal output by the second selection circuit.

[0020] In some embodiments, the first internal signal has a first voltage range, and the second internal signal has a second voltage range; wherein, the maximum voltage of the second voltage range is less than the maximum voltage of the first voltage range;

[0021] The voltage regulation circuit is specifically configured to:

[0022] Based on the voltage regulation signal, regulate the voltage range of the first internal signal from the first voltage range to the second voltage range.

[0023] In some embodiments, the test circuit includes a plurality of the third selection circuits; wherein, the third output terminals of at least two of the third selection circuits are coupled to a second test pad and share the second test pad; the third output terminals of at least two of the third selection circuits are coupled to a second data pad and share the second data pad.

[0024] In some embodiments, the first internal signal includes at least one of a multi-level analog signal and an indicator signal; the second internal signal includes at least one of a multi-level analog signal and an indicator signal.

[0025] In some embodiments, the test circuit further includes:

[0026] A pull-down circuit, the pull-down circuit includes at least one transistor; the transistor includes a first end, a second end and a control end, the first end is coupled to the first output end, the second end is coupled to a ground end, and the control end is used to receive a control signal;

[0027] The pull-down circuit is configured to turn on the transistor based on the control signal, so that the first output end is grounded through the pull-down circuit.

[0028] In some embodiments, the memory includes a dynamic random access memory.

[0029] In a second aspect, the present disclosure provides an operation method for a memory, the memory includes a test circuit, and the test circuit includes a first selection circuit; the operation method includes:

[0030] The first selection circuit receives a plurality of high-speed cycle signals and a first selection signal;

[0031] The first selection circuit selects one of the plurality of high-speed periodic signals based on the first selection signal and outputs the selected high-speed periodic signal.

[0032] In some embodiments, the test circuit further includes a second selection circuit and a third selection circuit; the operation method further includes:

[0033] The second selection circuit receives a plurality of first internal signals and a second selection signal;

[0034] The third selection circuit receives a plurality of second internal signals and a third selection signal; wherein, the voltage range of the second internal signal is different from the voltage range of the first internal signal;

[0035] The second selection circuit selects one of the plurality of first internal signals based on the second selection signal and outputs the selected first internal signal;

[0036] The third selection circuit selects one of the plurality of second internal signals based on the third selection signal and outputs the selected second internal signal.

[0037] In some embodiments, the memory further includes a first test pad and a second test pad, and the first test pad and the second test pad are encapsulated inside the memory; the operation method further includes:

[0038] The first internal signal output by the second selection circuit is transmitted to the first test pad through a first signal path;

[0039] The second internal signal output by the third selection circuit is transmitted to the second test pad through a second signal path.

[0040] In some embodiments, the memory further includes a first data pad and a second data pad; the operation method further includes:

[0041] The first internal signal output by the second selection circuit is transmitted to the outside of the memory through a third signal path and the first data pad;

[0042] The second internal signal output by the third selection circuit is transmitted to the outside of the memory through a fourth signal path and the second data pad.

[0043] In some embodiments, the test circuit further includes a voltage regulation circuit; the operation method further includes:

[0044] The voltage regulation circuit regulates the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal.

[0045] In some embodiments, the first internal signal has a first voltage range, and the second internal signal has a second voltage range; wherein, the maximum voltage of the second voltage range is less than the maximum voltage of the first voltage range.

[0046] The voltage regulation circuit regulates the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal, including:

[0047] The voltage regulation circuit regulates the voltage range of the first internal signal from the first voltage range to the second voltage range based on the voltage regulation signal.

[0048] In some embodiments, the first internal signal includes at least one of a multi-level analog signal and an indicator signal; the second internal signal includes at least one of a multi-level analog signal and an indicator signal.

[0049] In some embodiments, the test circuit further includes a pull-down circuit; the operation method further includes:

[0050] The pull-down circuit turns on a transistor in the pull-down circuit based on a control signal, so that the first selection circuit is grounded through the pull-down circuit; wherein, the transistor includes a first end, a second end, and a control end, the first end is coupled to the first selection circuit, the second end is coupled to a ground terminal, and the control end is configured to receive the control signal.

[0051] In a third aspect, the present disclosure provides a memory system, including:

[0052] The memory according to any one of the above embodiments;

[0053] A memory controller, coupled to the memory; the memory controller is configured to control the memory.

[0054] In a fourth aspect, the present disclosure provides a computer system, including:

[0055] The memory system according to the above embodiments;

[0056] A host, coupled to the memory system.

[0057] In the embodiments of the present disclosure, the test circuit includes a first selection circuit, and the first selection circuit is configured to select one high-speed cycle signal from a plurality of high-speed cycle signals based on a first selection signal and output the selected high-speed cycle signal. In this way, the test circuit can output the high-speed cycle signal to the outside of the memory for testing, increasing the coverage of various types of signals during testing and improving the test efficiency. Description of the Drawings

[0058] Figure 1 Schematic diagram of a memory provided by an embodiment of the present disclosure;

[0059] Figure 2 Schematic diagram of a first selection circuit in another memory provided by an embodiment of the present disclosure;

[0060] Figure 3 Schematic diagram of a second selection circuit and a third selection circuit in another memory provided by an embodiment of the present disclosure;

[0061] Figure 4 Schematic diagram of a test circuit in another memory provided by an embodiment of the present disclosure;

[0062] Figure 5 Schematic diagram of a pull - down circuit in another memory provided by an embodiment of the present disclosure;

[0063] Figure 6 Schematic diagram of a memory system and a computer system provided by an embodiment of the present disclosure. Detailed implementation manners

[0064] To facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0065] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some well - known technical features are not described; that is, not all features of the actual embodiments are described here, and the well - known functions and structures are not described in detail.

[0066] Generally, terms may be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey either a singular or a plural usage, at least in part, depending on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can alternatively allow for the existence of additional factors that are not necessarily expressly described, again at least in part, depending on the context.

[0067] Unless otherwise defined, the terms used herein are for the purpose of describing particular embodiments only and are not to be construed as limiting the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0068] To fully understand the present disclosure, detailed steps and detailed structures will be set forth in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0069] In some embodiments, such as Figure 1As shown, the memory 100 includes a test circuit 110, and the test circuit 110 includes a plurality of selection circuits 111 and pads 112 corresponding to the selection circuits 111. Among them, the memory 100 includes, but is not limited to, DRAM, SRAM, Ferroelectric Random Access Memory (FRAM), Magnetoresistive Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc. In some embodiments, the memory 100 can also be a non-volatile memory, such as Flash Memory. Preferably, the memory 100 here can be a dynamic random access memory.

[0070] The selection circuit 111 can receive multiple internal signals from the memory array and peripheral circuits of the memory 100, such as analog signals, indicator signals, etc. The selection circuit 111 can also select one internal signal from the multiple internal signals and output it to the corresponding pad 112, so as to output the selected internal signal to the outside of the memory 100 through the pad 112 for testing and debugging. The testing here includes, but is not limited to, testing the characteristics such as the level and timing of the internal signals in the memory 100, so as to verify the functions of the memory 100. Exemplarily, the selection circuit 111 can have multiple low-voltage switches (LV switches) or multiple high-voltage switches (HV switches). Here, the high-voltage switch can be used to conduct and select a high-voltage signal (HV signal) with a relatively high voltage, such as a signal with a voltage range of 0V to 2.2V, while the low-voltage switch can be used to conduct and select a low-voltage signal (LV signal) with a relatively low voltage, such as a signal with a voltage range of 0V to 1.05V. It should be noted that the low-voltage signal (LV signal) can also be controlled and selected by the high-voltage switch (HV switch). For any type of internal signal in the memory 100, such as analog signals, indicator signals, etc., it can be either a high-voltage signal or a low-voltage signal. It should be noted that the resistance value of the high-voltage switch when transmitting signals in a certain voltage range (such as around 1.8V) is lower than the resistance value when the low-voltage switch is conducting. The pad 112 can include test pads such as tst1_nb, tst2_nb, tst3_nb, and tst4_nb, data pads such as dq, and bus pads such as dmi, etc. An electrostatic discharge protection circuit (ESD) can also be connected between each selection circuit 111 and the corresponding pad 112. However, the test circuit 110 cannot select and output the high-speed periodic signal (High Speed Periodical Signal) in the memory 100, and each selection circuit 111 needs to output the selected internal signal through a corresponding pad 112. Therefore, a relatively large number of pads 112 are required in the test circuit 100, occupying a large area and having a low space utilization rate.

[0071] Such as Figure 2 As shown in the figure, the present disclosure provides a memory 200, and the memory 200 includes a test circuit 210; the test circuit 210 includes:

[0072] A first selection circuit 211, the first selection circuit 211 including a plurality of first input terminals, a first selection signal terminal, and a first output terminal; wherein, each of the plurality of first input terminals is configured to receive one of a plurality of high-speed periodic signals period_sig, and the first selection signal terminal is configured to receive a first selection signal sel_sig1;

[0073] The first selection circuit 211 is configured to select one of the plurality of high-speed periodic signals period_sig based on the first selection signal sel_sig1 and output the selected high-speed periodic signal period_sig.

[0074] In some embodiments, the memory includes a dynamic random access memory.

[0075] In the embodiments of the present disclosure, the memory 200 may be a dynamic random access memory. The memory 200 includes a test circuit 210, and the test circuit 210 is configured to output internal signals in the memory 200 to the outside of the memory 200 for testing and debugging. The testing here includes, but is not limited to, testing characteristics such as the level and timing of internal signals in the memory 200, so as to verify the function of the memory 200.

[0076] The test circuit 210 includes a first selection circuit 211. The first selection circuit 211 can receive multiple high-speed periodic signals period_sig from the memory array 201 and the peripheral circuit 202 of the memory 100, as well as a first selection signal sel_sig1, and select and output one of the high-speed periodic signals period_sig according to the first selection signal sel_sig1. Here, the first selection circuit 211 may include circuits such as an arbiter and a multiplexor to select the received multiple high-speed periodic signals period_sig. The first selection signal sel_sig1 can be provided by a decoder in the memory 200. The multiple high-speed periodic signals period_sig can be respective timing signals in the memory 200, and the voltage range of the high-speed periodic signal period_sig can be between 0V and 1.05V. Exemplarily, the first selection circuit 211 may include multiple selection switches, such as the high-voltage switch or the low-voltage switch in the above embodiments. The first selection circuit 211 turns on the corresponding one of the multiple selection switches based on the first selection signal sel_sig1, thereby selecting the corresponding one of the high-speed periodic signals period_sig. Preferably, the selection switch here can be a high-voltage switch HV switch (voltage range between 0V and 2.2V) to reduce the resistance value of the first selection circuit 211. In some embodiments, the test circuit 210 may be located in the peripheral circuit 202. At this time, the first selection circuit 211 can receive the high-speed periodic signals output by other circuits in the peripheral circuit 202 except the test circuit 210.

[0077] It can be understood that the first output terminal of the first selection circuit 211 can also be connected to a pad (such as sel_period_dq), so as to output the selected high-speed periodic signal period_sig to the outside of the memory 200 for testing and debugging. The pad connected to the first output terminal of the first selection circuit 211 can be located at different positions of the memory 200, so as to output the selected high-speed periodic signal period_sig before and / or after the memory 200 is packaged. Exemplarily, the pad connected to the first output terminal of the first selection circuit 211 can be the test pad in the above embodiments, so the selected high-speed periodic signal period_sig can be output before the memory 200 is packaged; the pad connected to the first output terminal of the first selection circuit 211 can also be the data pad in the above embodiments, so that the selected high-speed periodic signal period_sig can be output after the memory 200 is packaged. In some embodiments, a buffer BUF can also be connected between the first output terminal and the pad sel_period_dq to improve the stability and accuracy of the high-speed periodic signal period_sig during transmission.

[0078] In this way, the test circuit 210 can output the high-speed periodic signal period_sig to the outside of the memory 200 for testing and debugging, increasing the coverage of various types of signals during testing and improving the test efficiency.

[0079] In some embodiments, as Figure 3 shown, the test circuit 210 further includes:

[0080] A second selection circuit 212, the second selection circuit 212 includes a plurality of second input terminals, a second selection signal terminal, and a second output terminal; wherein, each of the plurality of second input terminals is used to receive one of the plurality of first internal signals In_sig1, and the second selection signal terminal is used to receive the second selection signal sel_sig2; the second selection circuit 212 is configured to select one of the plurality of first internal signals In_sig1 based on the second selection signal sel_sig2, and output the selected first internal signal In_sig1;

[0081] A third selection circuit 213, the third selection circuit 213 includes a plurality of third input terminals, a third selection signal terminal, and a third output terminal; wherein, each of the plurality of third input terminals is used to receive one of the plurality of second internal signals In_sig2, and the third selection signal terminal is used to receive the third selection signal sel_sig3; the third selection circuit 213 is configured to select one of the plurality of second internal signals In_sig2 based on the third selection signal sel_sig3, and output the selected second internal signal In_sig2;

[0082] Wherein, the voltage range of the second internal signal is different from the voltage range of the first internal signal.

[0083] In some embodiments, the first internal signal In_sig1 includes at least one of a multi-level analog signal and an indicator signal; the second internal signal In_sig2 includes at least one of a multi-level analog signal and an indicator signal.

[0084] In an embodiment of the present disclosure, the test circuit 210 includes a second selection circuit 212. The second selection circuit 212 can receive a plurality of first internal signals In_sig1 from the memory array 201 and the peripheral circuit 202 of the memory 200, as well as a second selection signal sel_sig2, and select and output one of the first internal signals In_sig1 according to the second selection signal sel_sig2. Here, the second selection circuit 212 may include circuits such as an arbiter and a multiplexer to select the received plurality of first internal signals In_sig1. The second selection signal sel_sig2 can be provided by a decoder in the memory 200. The first internal signal In_sig1 can be a multi-level analog signal, an indicator signal, etc. Exemplarily, the multi-level analog signal can include various voltage signals in the memory 200, such as a reference voltage signal, a bit line voltage signal, etc., while the indicator signal can include various enable signals, status indicator signals, etc. in the memory 200. The voltage range of the first internal signal In_sig1 can be from 0V to 2.2V. Exemplarily, the second selection circuit 212 may include a plurality of selection switches, such as the high-voltage switch or the low-voltage switch in the above embodiment. The second selection circuit 212 turns on the corresponding one of the plurality of selection switches based on the second selection signal sel_sig2, thereby selecting the corresponding one of the first internal signals In_sig1. Preferably, the selection switch here can be a high-voltage switch HV switch (voltage range from 0V to 2.2V) to reduce the resistance value of the second selection circuit 212 and improve the transmission quality and stability of the first internal signal In_sig1.

[0085] The test circuit 210 further includes a third selection circuit 213. The third selection circuit 213 can receive a plurality of second internal signals In_sig2 from the memory array 201 and the peripheral circuit 202 of the memory 200, as well as a third selection signal sel_sig3, and select and output one of the second internal signals In_sig2 according to the third selection signal sel_sig3. Here, the third selection circuit 213 may include circuits such as an arbiter and a multiplexer to select the received plurality of second internal signals In_sig2. The third selection signal sel_sig3 can be provided by a decoder in the memory 200. The second internal signal In_sig2 can be a multi-level analog signal, an indicator signal, etc. in the memory 200. The voltage range of the second internal signal In_sig2 can be between 0V and 1.05V. Exemplarily, the third selection circuit 213 may include a plurality of selection switches, such as the high-voltage switch or the low-voltage switch in the above embodiment. The third selection circuit 213 turns on the corresponding one of the plurality of selection switches based on the third selection signal sel_sig3, thereby selecting the corresponding one of the second internal signals In_sig2. Preferably, although the voltage range of the second internal signal In_sig2 can be between 0V and 1.05V, the selection switch in the third selection circuit 213 can still be a high-voltage switch HV switch (voltage range between 0V and 2.2V) to reduce the resistance value of the third selection circuit 213 and improve the transmission quality and stability of the second internal signal In_sig2.

[0086] It can be understood that the second selection circuit 212 and the third selection circuit 213 can be circuits with the same structure. The main difference lies in that the voltage ranges of the internal signals selected for output by the second selection circuit 212 and the third selection circuit 213 are different, that is, the voltage range of the second internal signal In_sig2 is different from the voltage range of the first internal signal In_sig1. The second internal signal In_sig2 and the first internal signal In_sig1 can be internal signals of the same type. For example, both the second internal signal In_sig2 and the first internal signal In_sig1 are multi-level analog signals; the second internal signal In_sig2 and the first internal signal In_sig1 can also be internal signals of different types. For example, the second internal signal In_sig2 is a multi-level analog signal, and the first internal signal In_sig1 is an indicator signal. Exemplarily, the maximum voltage of the second internal signal In_sig2 (such as 1.05V) is less than the maximum voltage of the first internal signal In_sig1 (such as 2.2V). In this way, the circuit structures of the second selection circuit 212 and the third selection circuit 213 are the same, so the design of the test circuit 210 can be simplified, and the test circuit 210 can select and output internal signals of different types and different voltage ranges. In some embodiments, the first selection circuit 211, the second selection circuit 212, and the third selection circuit 213 can all be circuits with the same structure.

[0087] In some embodiments, the test circuit 210 may include multiple second selection circuits 212 and multiple third selection circuits 213, so that the test circuit 210 can output the signals to be tested of all types and all voltage ranges in the memory 200 (such as analog signals, logic signals, and data signals in the data path) to meet the actual test requirements. It should be noted that each second selection circuit 212 or third selection circuit 213 can be used to select and output multiple internal signals with the same voltage range but different types.

[0088] In some embodiments, as Figure 4 shown, the memory 200 further includes:

[0089] A first test pad tst1_nb, the first test pad tst1_nb is coupled to the second output terminal through a first signal path P1; wherein, the first test pad tst1_nb is encapsulated inside the memory 200; the first internal signal In_sig1 output by the second selection circuit 212 is transmitted to the first test pad tst1_nb through the first signal path P1;

[0090] The second test pad tst2_nb is coupled to the third output terminal through a second signal path P2; wherein, the second test pad tst2_nb is encapsulated inside the memory 200; the second internal signal In_sig2 output by the third selection circuit 213 is transmitted to the second test pad tst2_nb through the second signal path P2.

[0091] In the embodiment of the present disclosure, the memory 200 further has a first test pad tst1_nb and a second test pad tst2_nb inside, that is to say, the first test pad tst1_nb and the second test pad tst2_nb are formed before the memory 200 is encapsulated. The second output terminal of the second selection circuit 212 is connected to the first test pad tst1_nb through a first signal path P1, that is, the first internal signal In_sig1 selected by the second selection circuit 212 can be output to the outside of the memory 200 through the first test pad tst1_nb before the memory 200 is encapsulated for testing and troubleshooting; the third output terminal of the third selection circuit 213 is connected to the second test pad tst2_nb through a second signal path P2, that is, the second internal signal In_sig2 selected by the third selection circuit 213 can be output to the outside of the memory 200 through the second test pad tst2_nb before the memory 200 is encapsulated for testing and troubleshooting. In some embodiments, there may also be a switch mon_hvsw controlled by a test enable signal tm_vpp_en on the first signal path P1 and the second signal path P2. It should be noted that Figure 4 This is only a specific circuit example of the test circuit and related circuits in the present disclosure. The test circuit and related circuits in the present disclosure can also be implemented by other combinational circuits including components such as an arbiter, a multiplexer, a high-voltage switch, and a low-voltage switch, and are not limited here.

[0092] In some embodiments, as Figure 4 shown, the memory 200 further includes:

[0093] A first data pad rdqs, the first data pad rdqs is coupled to the second output terminal through a third signal path P3; wherein, the first internal signal In_sig1 output by the second selection circuit 212 is transmitted to the outside of the memory 200 through the third signal path P3 and the first data pad rdqs.

[0094] A second data pad dq1, where the second data pad dq1 is coupled to the third output terminal through a fourth signal path P4; wherein, the second internal signal In_sig2 output by the third selection circuit 213 is transmitted to the outside of the memory 200 through the fourth signal path P4 and the second data pad dq1.

[0095] In the embodiment of the present disclosure, the memory 200 may further include a first data pad rdqs and a second data pad dq1 located on a data path, and the first data pad rdqs and the second data pad dq1 are exposed from the memory 200. Here, the first data pad rdqs and the second data pad dq1 may be data pads (DQpads) in the memory 200 and are used to output and input data signals. It should be noted that the first data pad rdqs and the second data pad dq1 may be formed either before the encapsulation of the memory 200 or after the encapsulation of the memory 200. The second output terminal of the second selection circuit 212 is connected to the first data pad rdqs through a third signal path P3, that is, the first internal signal In_sig1 selected by the second selection circuit 212 can be output to the outside of the memory 200 through the first data pad rdqs before and / or after the encapsulation of the memory 200 for testing and debugging; the third output terminal of the third selection circuit 213 is connected to the second data pad dq1 through a fourth signal path P4, that is, the second internal signal In_sig2 selected by the third selection circuit 213 can be output to the outside of the memory 200 through the second data pad dq1 before and / or after the encapsulation of the memory 200 for testing and debugging. In this way, the test circuit 210 can output the first internal signal In_sig1 and the second internal signal In_sig2 to the outside of the memory 200 through the first data pad rdqs and the second data pad dq1 on the data path respectively, that is, the test circuit 210 shares multiple data pads with the data path, so there is no need to add additional pads after the encapsulation of the memory 200 to output the signals to be tested, reducing the occupied area of the test circuit 210 and improving the integration degree of the memory 200.

[0096] Preferably, the first test pad tst1_nb and the second test pad tst2_nb output the first internal signal In_sig1 and the second internal signal In_sig2 to the outside of the memory 200 respectively for testing and debugging before the encapsulation of the memory 200; the first data pad rdqs and the second data pad dq1 output the first internal signal In_sig1 and the second internal signal In_sig2 to the outside of the memory 200 respectively for testing and debugging after the encapsulation of the memory 200.

[0097] In some embodiments, the third signal path P3 may also have multiple switches S0, S0_0, etc., as well as an electrostatic discharge protection circuit ESD. The fourth signal path P4 may also have multiple switches S8, S0_8, etc., as well as an electrostatic discharge protection circuit ESD.

[0098] In some embodiments, as Figure 4 shown, the test circuit 210 further includes:

[0099] A voltage regulation circuit 214, coupled to the second selection circuit 212 and the first data pad rdq s respectively; the voltage regulation circuit 214 is configured to: based on the voltage regulation signal reg_trim<3:0>, regulate the voltage of the first internal signal In_sig1 output by the second selection circuit 212.

[0100] In the embodiments of the present disclosure, the test circuit 210 may further include a voltage regulation circuit 214 coupled between the second selection circuit 212 and the first data pad rdqs. Since the voltage ranges of the data signals transmitted by the first data pad rdqs and the second data pad dq1 located on the data path are usually the same, and the voltage range of the first internal signal In_sig1 is different from the voltage range of the second internal signal In_sig2, the voltage regulation circuit 214 can regulate the voltage of the first internal signal In_sig1 based on the voltage regulation signal reg_trim<3:0>, so that the voltage range of the first internal signal In_sig1 output by the first data pad rdqs is the same as the voltage range of the second internal signal In_sig2 output by the second data pad dq1, facilitating testing and debugging outside the memory 200.

[0101] In some embodiments, the voltage regulation circuit 214 may also be turned on or off based on the received regulation enable signal reg_div_en to output the first internal signal In_sig1 with regulated voltage, or the first internal signal In_sig1 without voltage regulation. Exemplarily, the regulation enable signal reg_div_en and the voltage regulation signal reg_trim<3:0> here may be provided by the peripheral circuit of the memory 200, the memory controller, or the test control logic circuit outside the memory 200.

[0102] In some embodiments, the first internal signal In_sig1 has a first voltage range, and the second internal signal In_sig2 has a second voltage range; wherein, the maximum voltage of the second voltage range is less than the maximum voltage of the first voltage range;

[0103] The voltage regulation circuit 214 is specifically configured to:

[0104] Based on the voltage regulation signal reg_trim<3:0>, adjust the voltage range of the first internal signal In_sig1 from the first voltage range to the second voltage range.

[0105] In an embodiment of the present disclosure, the voltage regulation circuit 214 may be an adjustable voltage divider. Exemplarily, the first internal signal In_sig1 may have a first voltage range of 0V to 2.2V, and the second internal signal In_sig2 may have a second voltage range of 0V to 1.05V. The voltage regulation circuit 214 may adjust the voltage range of the first internal signal In_sig1 from 0V to 2.2V to 0V to 1.05V based on the received voltage regulation signal reg_trim<3:0>. In this way, the influence of the first internal signal In_sig1 with a higher voltage on the first data pad rdqs can be reduced, and the service life of the first data pad rdqs can be improved.

[0106] In some embodiments, as Figure 4 shown, the test circuit 210 includes a plurality of the third selection circuits 213; wherein, the third output terminals of at least two of the third selection circuits 213 are coupled to the second test pad tst2_nb and share the second test pad tst2_nb; the third output terminals of at least two of the third selection circuits 213 are coupled to the second data pad dq1 and share the second data pad dq1.

[0107] In an embodiment of the present disclosure, the test circuit 210 may include a plurality of third selection circuits 213, and the third output terminals of at least two of the third selection circuits 213 share a second test pad tst2_nb and share a second data pad dq1. Exemplarily, the voltage ranges of the second internal signals In_sig2 received by the plurality of third selection circuits 213 may be the same (e.g., both 0V to 1.05V), but the types of the second internal signals In_sig2 received by each of the plurality of third selection circuits 213 may be the same or different. In this way, compared with the Figure 1 illustrated embodiment, the embodiment of the present disclosure can reduce the number of pads required for the test circuit 210, thereby reducing the occupied area of the test circuit 210 and improving the integration degree of the memory 200.

[0108] In some embodiments, when a plurality of third selection circuits 213 share a second test pad tst2_nb or a second data pad dq1, the plurality of third selection signals sel_sig3 respectively input to the plurality of third selection circuits 213 may be utilized to enable the shared pad to output only the second internal signal In_sig2 selected and output by one of the third selection circuits 213 at a certain time period (or moment), so as to avoid signal interference and errors.

[0109] In some embodiments, as Figure 5 shown, the test circuit 210 further includes:

[0110] A pull-down circuit 215, the pull-down circuit 215 includes at least one transistor; the transistor includes a first end, a second end and a control end, the first end is coupled to the first output end, the second end is coupled to the ground end, and the control end is configured to receive a control signal Pd_sig;

[0111] The pull-down circuit 215 is configured to turn on the transistor based on the control signal Pd_sig, so that the first output end is grounded through the pull-down circuit.

[0112] In the embodiments of the present disclosure, the test circuit further includes a pull-down circuit 215. The pull-down circuit 215 includes at least one transistor (such as an NMOS transistor). The first end of the transistor is coupled to the first output end of the first selection circuit, the second end of the transistor is grounded, and the control end of the transistor is configured to receive a control signal Pd_sig. Here, the control signal Pd_sig can be provided by a peripheral circuit of the memory, a memory controller or a test control logic circuit external to the memory.

[0113] When the first selection circuit is enabled, the first selection circuit outputs the selected high-speed cycle signal period_sig to the outside of the memory through the pad sel_period_dq for testing and debugging. At this time, the pull-down circuit 215 can turn on the transistor based on the control signal Pd_sig, and make the first output end of the first selection circuit grounded through the pull-down circuit 215. Thus, the pull-down circuit 215 can reduce the coupling between the high-speed cycle signal period_sig and other DC signals in the memory, and further reduce the overshoot and undershoot of the high-speed cycle signal period_sig.

[0114] In some embodiments, as Figure 5 shown, another pull-down circuit 216 can also be provided between the buffer BUF and the switch 217. In this way, the leakage caused by the floating of the input end of the buffer BUF after the switch 217 is turned on can be reduced.

[0115] The present disclosure provides an operation method for a memory. The memory includes a test circuit, and the test circuit includes a first selection circuit. The operation method includes:

[0116] The first selection circuit receives a plurality of high-speed cycle signals and a first selection signal;

[0117] The first selection circuit selects one of the multiple high-speed periodic signals based on the first selection signal and outputs the selected high-speed periodic signal.

[0118] In an embodiment of the present disclosure, the memory may be a dynamic random access memory. The memory includes a test circuit for outputting internal signals in the memory to the outside of the memory for testing and debugging. Here, the testing includes, but is not limited to, testing characteristics such as the level and timing of internal signals in the memory, so as to verify the function of the memory.

[0119] The test circuit includes a first selection circuit, which can receive multiple high-speed periodic signals from the memory's storage array and peripheral circuits, as well as a first selection signal, and select and output one of the high-speed periodic signals according to the first selection signal. Here, the first selection signal may be provided by a decoder in the memory. The multiple high-speed periodic signals may be respective timing signals in the memory, and the voltage range of the high-speed periodic signals may be from 0V to 1.05V.

[0120] It can be understood that the first selection circuit may also be connected to one or more pads, so as to output the selected high-speed periodic signal to the outside of the memory for testing and debugging. The pads connected by the first selection circuit may be located at different positions in the memory, so as to output the selected high-speed periodic signal before and / or after the memory is packaged. In this way, the coverage of various types of signals during testing can be increased, and the testing efficiency can be improved.

[0121] In some embodiments, the test circuit further includes a second selection circuit and a third selection circuit; the operation method further includes:

[0122] The second selection circuit receives multiple first internal signals and a second selection signal;

[0123] The third selection circuit receives multiple second internal signals and a third selection signal; wherein, the voltage range of the second internal signals is different from the voltage range of the first internal signals;

[0124] The second selection circuit selects one of the multiple first internal signals based on the second selection signal and outputs the selected first internal signal;

[0125] The third selection circuit selects one of the multiple second internal signals based on the third selection signal and outputs the selected second internal signal.

[0126] In some embodiments, the memory further includes a first test pad and a second test pad, and the first test pad and the second test pad are encapsulated inside the memory; the operation method further includes:

[0127] The first internal signal output by the second selection circuit is transmitted to the first test pad through a first signal path;

[0128] The second internal signal output by the third selection circuit is transmitted to the second test pad through a second signal path.

[0129] In some embodiments, the memory further includes a first data pad and a second data pad; the operation method further includes:

[0130] The first internal signal output by the second selection circuit is transmitted to the outside of the memory through a third signal path and the first data pad;

[0131] The second internal signal output by the third selection circuit is transmitted to the outside of the memory through a fourth signal path and the second data pad.

[0132] In some embodiments, the test circuit further includes a voltage regulation circuit; the operation method further includes:

[0133] The voltage regulation circuit adjusts the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal.

[0134] In some embodiments, the first internal signal has a first voltage range, and the second internal signal has a second voltage range; wherein, the maximum voltage of the second voltage range is less than the maximum voltage of the first voltage range;

[0135] The voltage regulation circuit adjusts the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal, including:

[0136] The voltage regulation circuit adjusts the voltage range of the first internal signal from the first voltage range to the second voltage range based on the voltage regulation signal.

[0137] In some embodiments, the first internal signal includes at least one of a multi-level analog signal and an indicator signal; the second internal signal includes at least one of a multi-level analog signal and an indicator signal.

[0138] In some embodiments, the test circuit further includes a pull-down circuit; the operation method further includes:

[0139] Based on the control signal, the pull-down circuit turns on the transistor in the pull-down circuit, enabling the first selection circuit to be grounded through the pull-down circuit; wherein, the transistor includes a first terminal, a second terminal, and a control terminal, the first terminal is coupled to the first selection circuit, the second terminal is coupled to the ground terminal, and the control terminal is configured to receive the control signal.

[0140] As Figure 6 shown, the present disclosure provides a memory system 300, including:

[0141] The memory 200 described in any one of the above embodiments; a memory controller 301, coupled to the memory 200; the memory controller 301 is configured to control the memory 200.

[0142] In an embodiment of the present disclosure, the memory controller 301 is coupled to the memory 200 and is used to control the memory 200 to perform operations such as reading and writing. The memory controller 301 may include a processor, a microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.

[0143] As Figure 6 shown, the present disclosure provides a computer system 400, including:

[0144] The memory system 300 described in the above embodiment; a host 401, coupled to the memory system 300.

[0145] In an embodiment of the present disclosure, the host 401 may be a processor of an electronic device (for example, a central processing unit (CPU) or a system on chip (SoC) (for example, an application processor (AP))). The host 401 may be configured to send data to the memory system 300 or receive data from the memory system 300.

[0146] It can be understood that, compared with known test circuits, the memory and test circuit provided by the present disclosure have a simpler and more direct circuit structure. For example, the first selection circuit, the second selection circuit, and the third selection circuit can be circuits of the same structure, and can cover a wider range of test conditions (including the tests for high-speed periodic signals, multi-level analog signals, and indicator signals). Moreover, a simplified adjustment code (such as the above-mentioned voltage adjustment signal) can be used to convert an internal signal with a higher maximum voltage into a signal with a suitable voltage range through a voltage divider, so as to reduce the difficulty of testing, improve the test accuracy and test efficiency. In addition, the pull-down circuit and the high-voltage switches with small on-resistance in each selection circuit can also reduce DC coupling, thereby reducing the distortion and DC loss caused by coupling, and maintaining the relative order of the indicator signals.

[0147] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the sequence numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0148] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or any direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that, The memory includes a test circuit; the test circuit includes: A first selection circuit, the first selection circuit including a plurality of first input terminals, a first selection signal terminal, and a first output terminal; wherein, each of the plurality of first input terminals is configured to receive one of a plurality of high-speed periodic signals, and the first selection signal terminal is configured to receive a first selection signal; The first selection circuit is configured to select one of the plurality of high-speed periodic signals based on the first selection signal, and output the selected high-speed periodic signal.

2. The memory according to claim 1, characterized in that, The test circuit further includes: A second selection circuit, the second selection circuit including a plurality of second input terminals, a second selection signal terminal, and a second output terminal; wherein, each of the plurality of second input terminals is configured to receive one of a plurality of first internal signals, and the second selection signal terminal is configured to receive a second selection signal; the second selection circuit is configured to select one of the plurality of first internal signals based on the second selection signal, and output the selected first internal signal; A third selection circuit, the third selection circuit including a plurality of third input terminals, a third selection signal terminal, and a third output terminal; wherein, each of the plurality of third input terminals is configured to receive one of a plurality of second internal signals, and the third selection signal terminal is configured to receive a third selection signal; the third selection circuit is configured to select one of the plurality of second internal signals based on the third selection signal, and output the selected second internal signal; Wherein, the voltage range of the second internal signal is different from the voltage range of the first internal signal.

3. The memory according to claim 2, wherein The memory further includes: A first test pad, the first test pad being coupled to the second output terminal through a first signal path; wherein, the first test pad is encapsulated inside the memory; the first internal signal output by the second selection circuit is transmitted to the first test pad through the first signal path; A second test pad, the second test pad being coupled to the third output terminal through a second signal path; wherein, the second test pad is encapsulated inside the memory; the second internal signal output by the third selection circuit is transmitted to the second test pad through the second signal path.

4. The memory according to claim 2, wherein The memory further includes: A first data pad, the first data pad being coupled to the second output terminal through a third signal path; wherein, the first internal signal output by the second selection circuit is transmitted to the outside of the memory through the third signal path and the first data pad; A second data pad, the second data pad being coupled to the third output terminal through a fourth signal path; wherein, the second internal signal output by the third selection circuit is transmitted to the outside of the memory through the fourth signal path and the second data pad.

5. The memory according to claim 4, wherein The test circuit further includes: A voltage regulation circuit is respectively coupled to the second selection circuit and the first data pad; the voltage regulation circuit is configured to: regulate the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal.

6. The memory according to claim 5, characterized in that, The first internal signal has a first voltage range, and the second internal signal has a second voltage range; wherein, the maximum voltage of the second voltage range is less than the maximum voltage of the first voltage range. The voltage regulation circuit is specifically configured to: Based on the voltage regulation signal, regulate the voltage range of the first internal signal from the first voltage range to the second voltage range.

7. The memory according to claim 2, wherein The test circuit includes a plurality of the third selection circuits; wherein, the third output terminals of at least two of the third selection circuits are coupled to a second test pad and share the second test pad; the third output terminals of at least two of the third selection circuits are coupled to a second data pad and share the second data pad.

8. The memory according to claim 2, wherein The first internal signal includes at least one of a multi-level analog signal and an indicator signal; the second internal signal includes at least one of a multi-level analog signal and an indicator signal.

9. The memory according to claim 1, wherein The test circuit further includes: A pull-down circuit, the pull-down circuit includes at least one transistor; the transistor includes a first end, a second end, and a control end, the first end is coupled to the first output terminal, the second end is coupled to a ground terminal, and the control end is used to receive a control signal. The pull-down circuit is configured to turn on the transistor based on the control signal, so that the first output terminal is grounded through the pull-down circuit.

10. The memory according to claim 1, characterized in that, The memory includes a dynamic random access memory.

11. A method for operating a memory, characterized in that, The memory includes a test circuit, the test circuit includes a first selection circuit; the operation method includes: The first selection circuit receives a plurality of high-speed cycle signals and a first selection signal. The first selection circuit selects one of the plurality of high-speed cycle signals based on the first selection signal and outputs the selected high-speed cycle signal.

12. The operating method according to claim 11, wherein The test circuit further includes a second selection circuit and a third selection circuit; the operation method further includes: The second selection circuit receives a plurality of first internal signals and a second selection signal. The third selection circuit receives a plurality of second internal signals and a third selection signal; wherein, the voltage range of the second internal signal is different from the voltage range of the first internal signal. The second selection circuit selects one of the plurality of first internal signals based on the second selection signal and outputs the selected first internal signal. The third selection circuit selects one of the plurality of second internal signals based on the third selection signal and outputs the selected second internal signal.

13. The operating method according to claim 12, characterized in that, The memory further includes a first test pad and a second test pad, the first test pad and the second test pad are encapsulated inside the memory; the operation method further includes: The first internal signal output by the second selection circuit is transmitted to the first test pad through a first signal path. The second internal signal output by the third selection circuit is transmitted to the second test pad through a second signal path.

14. The operating method according to claim 12, characterized in that, The memory further includes a first data pad and a second data pad; the operation method further includes: The first internal signal output by the second selection circuit is transmitted to the outside of the memory through a third signal path and the first data pad. The second internal signal output by the third selection circuit is transmitted to the outside of the memory through a fourth signal path and the second data pad.

15. The operating method according to claim 14, characterized in that The test circuit further includes a voltage regulation circuit. The operation method further includes: The voltage regulation circuit regulates the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal.

16. The operating method according to claim 15, wherein The first internal signal has a first voltage range, and the second internal signal has a second voltage range; wherein, the maximum voltage of the second voltage range is less than the maximum voltage of the first voltage range. The voltage regulation circuit regulates the voltage of the first internal signal output by the second selection circuit based on a voltage regulation signal, including: The voltage regulation circuit regulates the voltage range of the first internal signal from the first voltage range to the second voltage range based on the voltage regulation signal.

17. The operating method according to claim 12, characterized in that, The first internal signal includes at least one of a multi-level analog signal and an indicator signal; the second internal signal includes at least one of a multi-level analog signal and an indicator signal.

18. The operating method according to claim 11, wherein, The test circuit further includes a pull-down circuit; the operation method further includes: The pull-down circuit turns on a transistor in the pull-down circuit based on a control signal, so that the first selection circuit is grounded through the pull-down circuit; wherein, the transistor includes a first end, a second end, and a control end, the first end is coupled to the first selection circuit, the second end is coupled to a ground terminal, and the control end is used to receive the control signal.

19. A memory system, characterized in that, Comprising: The memory according to any one of claims 1 to 10. A memory controller, coupled to the memory. The memory controller is configured to control the memory.

20. A computer system, characterized in that, Comprising: The memory system according to claim 19. A host, coupled to the memory system.

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