Acceleration unit, storage control chip, solid state disk and physical address reading method

Abstract

The embodiment of the invention provides an acceleration unit, a storage control chip, a solid state disk and a physical address reading method, and the acceleration unit comprises a receiving subunit which is used for receiving a reading request for reading a first mapping table item in a DDR, and a plurality of mapping table items included in the DDR are used for recording physical address information of an IU in an NAND flash memory; the reading subunit is used for reading the first mapping table item according to the reading request to obtain first physical address information and reading a first error correction space corresponding to the first mapping table item in the DDR to obtain a first ECC, and the error correction space is used for storing the ECC of the physical address information in a plurality of corresponding mapping table items; the verification subunit is used for verifying the first physical address information according to the first ECC; and the output subunit is used for outputting the first physical address information after the first physical address information passes the verification. According to the scheme, the high-capacity SSD can be realized on the premise that the DDR capacity is not increased.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of chip technology, and in particular, to an acceleration unit, a storage control chip, a solid-state drive, and a physical address reading method. Background Art

[0002] A solid-state drive (SSD) includes a storage controller and multiple NAND flash memories. A host can read data from the NAND flash memories through the storage controller. The storage controller indexes a global mapping table of the NAND flash physical addresses through a logical block address (LBA) to implement the conversion from the LBA to the flash physical address (FPA), and then reads and writes the NAND flash memories based on the FPA. The mapping table entries indicating the mapping relationship between the LBA and the FPA, and the error correction coding (ECC) used to check the mapping table entries are stored in a double data rate synchronous dynamic random access memory (DDR).

[0003] Currently, a single mapping table entry corresponds to an ECC protection field. When reading a mapping table entry, the physical address information stored in the mapping table entry is checked through the ECC stored in the corresponding ECC protection field.

[0004] However, the mapping table entries and the ECC are stored in the DDR. As the capacity of the SSD increases, the number of mapping table entries and the ECC to be stored increases. To implement an SSD with a larger capacity, a DDR with a larger capacity is required, and the increase in the DDR capacity will lead to an increase in the cost of the SSD. Summary of the Invention

[0005] In view of this, embodiments of the present application provide an acceleration unit, a storage control chip, a solid-state drive, and a physical address reading method to at least solve or alleviate the above problems.

[0006] According to the first aspect of the embodiments of the present application, an acceleration unit is provided, which is applied to a storage control chip in a solid-state drive. The acceleration unit includes: a receiving subunit, configured to receive a read request for reading a first mapping entry in a double data rate synchronous dynamic random access memory. The double data rate synchronous dynamic random access memory includes multiple mapping entries, and the mapping entries are used to record the physical address information of the indirect units in the NAND flash memory. Different mapping entries are used to store the physical address information of different indirect units; a reading subunit, configured to read the first mapping entry according to the read request to obtain first physical address information, and read a first error correction space corresponding to the first mapping entry in the double data rate synchronous dynamic random access memory to obtain a first error correction code. The double data rate synchronous dynamic random access memory includes multiple error correction spaces, one error correction space corresponds to multiple mapping entries, and the error correction space is used to store the error correction codes of the physical address information in the corresponding multiple mapping entries; a verification subunit, configured to verify the first physical address information according to the first error correction code; an output subunit, configured to output the first physical address information after the first physical address information passes the verification.

[0007] According to the second aspect of the embodiments of the present application, a storage control chip is provided, including: a processing unit and the acceleration unit described in the first aspect above; the processing unit is configured to parse a read / write command issued by a host to obtain a first logical address, generate a read request including the first logical address, and send the read request to the acceleration unit. The first logical address points to the first mapping entry; the acceleration unit is configured to send the first physical address information to the processing unit after the first physical address information passes the verification, so that the processing unit performs read / write operations on the NAND flash memory according to the first physical address information.

[0008] According to the third aspect of the embodiments of the present application, a solid-state drive is provided, including: the storage control chip described in the second aspect above, a double data rate synchronous dynamic random access memory, and a NAND flash memory.

[0009] According to a fourth aspect of the embodiments of the present application, a method for reading a physical address is provided, which is applied to an acceleration unit in a storage control chip. The method includes: receiving a read request for reading a first mapping table entry in a double data rate synchronous dynamic random access memory (DDR SDRAM), where the DDR SDRAM includes a plurality of mapping table entries, and the mapping table entries are used to record physical address information of indirect units in a NAND flash memory, and different mapping table entries are used to store physical address information of different indirect units; according to the read request, reading the first mapping table entry to obtain first physical address information, and reading a first error correction space corresponding to the first mapping table entry in the DDR SDRAM to obtain a first error correction code, where the DDR SDRAM includes a plurality of error correction spaces, one error correction space corresponds to a plurality of mapping table entries, and the error correction space is used to store error correction codes of physical address information in the corresponding plurality of mapping table entries; verifying the first physical address information according to the first error correction code; and outputting the first physical address information after the first physical address information passes the verification.

[0010] According to the global mapping table management scheme of LBA index and NAND flash physical address provided by the embodiments of the present application, one mapping table entry in the DDR corresponds to multiple error correction spaces, that is, multiple physical address information is protected by one ECC. Without increasing the capacity of the DDR, the storage space occupied by the ECC can be reduced, so that the DDR can store physical address information with a larger bit width. Increasing the bit width of the physical address information can enable the physical address information to identify a larger number of IUs, so that a larger-capacity SSD can be realized without increasing the DDR capacity and without using other system schemes such as multi-partitioning or large IUs, making the large-capacity SSD have a lower cost and better system QoS. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings.

[0012] Figure 1 is a schematic block diagram of a solid-state drive according to an embodiment of the present application;

[0013] Figure 2 is a schematic block diagram of a storage control chip according to an embodiment of the present application;

[0014] Figure 3 is a schematic block diagram of an acceleration unit according to an embodiment of the present application;

[0015] Figure 4 It is a schematic diagram of a DDR according to an embodiment of the present application;

[0016] Figure 5 It is a schematic diagram of a DDR according to another embodiment of the present application;

[0017] Figure 6 It is a schematic diagram of a DDR according to still another embodiment of the present application;

[0018] Figure 7 It is a schematic diagram of an acceleration unit according to another embodiment of the present application;

[0019] Figure 8 It is a flowchart of a physical address reading method according to an embodiment of the present application. Detailed implementation manners

[0020] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, and procedures are not described in detail. Additionally, the drawings are not necessarily drawn to scale.

[0021] First, some nouns or terms that appear in the process of describing the embodiments of the present application are applicable to the following explanations.

[0022] NAND flash memory: NAND flash memory, also known as NAND flash, is a non-volatile flash memory. NAND flash memory uses tunneling injection for writing and tunneling release for erasing, and the address lines and data lines are multiplexed.

[0023] Solid State Disk: Solid State Disk (SSD), also known as solid state drive, is a hard disk made of a solid-state electronic storage chip array. The solid state disk in the embodiments of the present application refers to a solid state disk composed of NAND flash memory chips.

[0024] Storage control chip: The storage control chip is the SDD controller, also known as the main control chip or main control. It is one of the key components of a solid state disk and is composed of an embedded processor that executes code and several hardware acceleration modules.

[0025] Acceleration unit: In view of the low efficiency of traditional processors in some special-purpose fields (such as data reading, etc.), a processing unit designed to improve the data processing speed in these special-purpose fields. In the embodiments of the present application, it is mainly a special processing unit designed to improve the access speed of DDR.

[0026] Double Data Rate Synchronous Dynamic Random Access Memory: Double Data Rate Synchronous Dynamic Random Access Memory (DDR) is one type of memory, and data is lost when power is off.

[0027] Dynamic Random Access Memory: Dynamic Random Access Memory (DRAM) is a commonly used computer memory. Usually, one transistor and one capacitor are used to represent one bit, and the stored data is lost after the power is cut off.

[0028] Logical Block Address: Logical Block Address (LBA) is a general mechanism used to represent the location of data on a computer data storage device.

[0029] Flash Physical Address: Flash Physical Address (FPA) is used to identify the storage location of user data in flash memory chips, generally including information such as Die, Block, Plane, Page, etc.

[0030] L2P: A global mapping table of LBA index and NAND flash physical location.

[0031] Error Correction Coding: Error Correction Coding (ECC) is an algorithm used to detect and correct errors generated during data transmission or storage. ECC can improve the reliability and integrity of data and prevent data corruption or loss.

[0032] Indirection Unit: The Indirection Unit (IU) is usually 4KiB, and there are also systems with 8KiB, 16KiB, 32KiB, 64KiB, etc. It refers to how large a data segment is allocated to one address in the L2P mapping.

[0033] Application environment of the present application

[0034] The embodiments of this application propose a solution to implement a large - capacity SSD without increasing the cost of DDR. The entire solution is relatively general and can be used in various mapping devices including solid - state drives, such as for data centers, servers, personal computers, Internet of Things (IoT) devices, embedded devices, etc. The physical address reading solution provided by the embodiments of this application is independent of the hardware deployed in the computing device.

[0035] Solid state drive

[0036] Figure 1 A schematic block diagram showing a solid-state drive 100 is presented. A solid-state drive (SSD), also known as a solid-state disk, is a hard disk made of an array of solid-state electronic storage chips. According to different storage media, solid-state drives can be divided into flash-based solid-state drives and dynamic random access memory (DRAM)-based solid-state drives. The solid-state drive 100 in the embodiments of this application refers to a flash-based solid-state drive.

[0037] Solid-state drives have many advantages over traditional mechanical hard disks. For example, they have stronger data storage security. For instance, there is no need to worry about damaging the stored data when shaking the solid-state drive during use, and sudden power outages during use will not cause data loss in the solid-state drive. Based on this, solid-state drives are widely used in various complex working environments, such as highly available servers, and are also ideal storage devices for individual users.

[0038] As Figure 1 shown, the solid-state drive 100 includes a storage control chip 10, a double data rate synchronous dynamic random access memory (DDR) 20, and multiple NAND flash memories 30. As an example, as Figure 1 shown, the solid-state drive 100 includes 3 NAND flash memories 30. However, it should be understood that the number of NAND flash memories 30 is not limited to this. The data in the NAND flash memory 30 is stored in the form of bits in memory cells. One memory cell can store one bit, and multiple memory cells form a bit line, which is the bit width of the NAND flash memory. Multiple bit lines can form a flash page, and multiple flash pages form a flash block. The NAND flash memory 30 reads and writes data in units of flash pages and erases data in units of flash blocks.

[0039] The DDR 20 is used to store the L2P table and ECC. The L2P table stores a global mapping table of LBA indexes and NAND flash physical addresses. The L2P table includes multiple LBAs and multiple mapping table entries. Different LBAs correspond to different mapping table entries, and the mapping table entries are used to store the physical address information mapped to the corresponding LBA. The physical address information identifies the physical address of the indirect unit (IU) in the NAND flash memory. Different physical address information identifies different IUs. When the storage space of the IU is 4 KiB, the physical address information stored in a single mapping table entry identifies a physical storage space of 4 KiB. For an SSD with a capacity of 8 TB, there are 2 G (1 G = 109 ) mapping table entries.

[0040] DDR20 stores multiple ECCs. One ECC corresponds to multiple mapping table entries. Different ECCs correspond to different mapping table entries. The physical address information stored in the mapping table entries can be protected by the corresponding ECC. In one example, DDR20 stores 2G mapping table entries. Every two mapping table entries correspond to one ECC, so DDR20 stores 1G ECCs.

[0041] Since one ECC can protect multiple physical address information, it reduces the storage space occupied by ECCs in DDR20. Without increasing the capacity of DDR20, physical address information with a larger bit width can be stored. The increase in the bit width of the physical address information can identify a larger number of IUs, thus realizing a larger capacity SSD. For example, since the number of blocks and pages of NAND flash memory particles are not powers of 2, 2G physical address information can be indicated by a 32-bit mapping table entry, 4G physical address information can be indicated by a 33-bit mapping table entry, 8G physical address information can be indicated by a 34-bit mapping table entry, 16G physical address information can be indicated by a 35-bit mapping table entry, and 32G physical address information can be indicated by a 36-bit mapping table entry. 2G physical address information can identify an 8TB SSD, 4G physical address information can identify a 16TB SSD, 8G physical address information can identify a 32TB SSD, 16G physical address information can identify a 64TB SSD, and 32G physical address information can identify a 128TB SSD.

[0042] Multiple physical address information is protected by one ECC, enabling the mapping table entries to have a larger bit width, thereby allowing for the identification of a larger capacity SSD. Without increasing the capacity of DDR20 and without using system solutions such as multi-partitioning or large IUs, a larger capacity SSD is achieved. When the IU capacity is 4KiB and the number of mapping table entries is fixed, DDR has a lower cost, thus avoiding an increase in the cost of the SSD due to an increase in the DDR capacity while realizing a large capacity SSD.

[0043] The storage control chip 10 is used to control the read and write operations of the solid state drive 100. When the storage control chip 10 stores data in the NAND flash memory 30, the storage control chip 10 reads the L2P table stored in the DDR20 to determine the physical address information of the IU for storing the data, and reads the ECC corresponding to the read physical address information from the DDR20, and checks the read physical address information through the read ECC. After the physical address information passes the check, the data is stored in the IU identified by the physical address information in the NAND flash memory 30. When the storage control chip 10 reads data from the NAND flash memory 30, the storage control chip 10 reads the L2P table stored in the DDR20 to determine the physical address information of the IU to be read, and reads the ECC corresponding to the read physical address information from the DDR20, and checks the read physical address information through the read ECC. After the physical address information passes the check, the data stored in the IU identified by the physical address information is read.

[0044] One or more application programs 201 are deployed on the host 200. As an example, as Figure 1 shown, application program 1, application program 2, and application program 3 are deployed on the host 200, but it should be understood that the number of application programs 201 should not be limited to this. The application program 201 can send a write command or a read command to the storage control chip 10. The write command carries the LBA of the IU for storing data, and the read command carries the LBA of the IU storing the data to be read. After receiving the write command, the storage control chip 10 reads the FPA (i.e., physical address information) mapped to the LBA from the DDR20 according to the LBA carried in the write command. After passing the ECC check on the FPA, the data to be stored is written into the corresponding one or more IUs in the NAND flash memory 30 according to the read FPA. After receiving the read command, the storage control chip 10 reads the FPA mapped to the LBA from the DDR20 according to the LBA written in the read command. After passing the ECC check on the FPA, the required data is read from the corresponding one or more IUs in the NAND flash memory 30 according to the read FPA, and the read data is sent to the corresponding application program 201.

[0045] The host 200 can be a device with read and write operation functions such as a personal computer (PC) or a server, and the type of the host 200 is not limited in this application. The solid state drive 100 can be connected to the host 200 through a Peripheral Component Interconnect Express (PCIE) interface, and the host 200 and the storage control chip 10 transmit data through the PCIE interface.

[0046] In a possible implementation, the DDR20 includes N memory dies. The mapping table entries are stored in the first memory die to the (N - 1)th memory die among the N memory dies, and the first m columns of the Nth memory die. The error correction space for storing ECC is located in the last n columns of the Nth memory die. The same mapping table entry is located in the same row of the memory die. Multiple mapping table entries corresponding to the same error correction space are aligned with the error correction space in the row direction of the memory die. Herein, N is a positive integer greater than or equal to 3, both m and n are positive integers, and m + n is equal to the bit width of the memory die.

[0047] The memory die can be a DRAM die. The bit width of a single DRAM die can be 8 bit, then the bit width of the DDR20 is 8N bit. Each row of the DDR20 can store a physical address information. The first [8(N - 1) + m] bit of each row of the DDR20 is used to store the physical address information, and the last n bit of each row of the DDR20 is used to store ECC. Since multiple mapping table entries correspond to one error correction space, the error correction space and the multiple mapping table entries corresponding thereto are aligned in the row direction of the DDR20. For example, one error correction space corresponds to M mapping table entries, M is a positive integer greater than or equal to 2, then adjacent M mapping table entries correspond to one error correction space, and the data capacity of the error correction space is M × n. It should be understood that the data length of the physical address information stored in the DDR20 is equal to [8(N - 1) + m] bit, and the data length of the ECC stored in the DDR20 is greater than or equal to n bit. That is to say, the data capacity of the error correction space is greater than the data amount of the ECC, and the ECC cannot fill the error correction space.

[0048] It should be noted that the bit width of a single DRAM die being 8 bit is only an example, and the present application does not limit the bit width of a single memory die. For example, the bit width of a single DRAM die can also be 4 bit, 16 bit, 32 bit, etc.

[0049] In the embodiment of the present application, the first memory die to the (N - 1)th memory die, and the first m columns of the Nth memory die are divided into a physical address storage area. Each row of this physical address storage area serves as a mapping table entry. The last n columns of the Nth memory die are divided into an ECC storage area. Multiple adjacent rows of this ECC storage area serve as an error correction space. The error correction space is aligned with the multiple mapping table entries corresponding thereto in the row direction. Thus, when obtaining the physical address information by reading the mapping table entry, the ECC corresponding to the read physical address information can be obtained by reading the error correction space aligned with the mapping table entry, making it simpler and faster to read the ECC and improving the efficiency of reading and writing the NAND flash memory.

[0050] In a possible implementation, the DDR20 includes 5 memory chips. The bit width of each memory chip is 8 bit. The number of columns m for storing physical address information in the Nth memory chip is greater than or equal to 1 and less than or equal to 7. Among them, the 5 memory chips included in the DDR20 can be DRAM chips.

[0051] When the DDR20 includes 5 memory chips, the sum of the bit widths of the 1st to 4th memory chips is 32 bit. The first m columns of the 5th memory chip are also used to store physical address information. Then, the width of the mapping table entry for storing physical address information is (32 + m) bit. Since 1 ≤ m ≤ 7, the value range of the width of the mapping table entry is [33 bit, 39 bit]. A mapping table entry with a width of 33 bit can indicate 4G physical address information, and 4G physical address information can identify a 16TB SSD. A mapping table entry with a width of 34 bit can indicate 8G physical address information, and 8G physical address information can identify a 32TB SSD. A mapping table entry with a width of 35 bit can indicate 16G physical address information, and 16G physical address information can identify a 64TB SSD. A mapping table entry with a width of 36 bit can indicate 32G physical address information, and 32G physical address information can identify a 128TB SSD. A mapping table entry with a width of 37 bit can indicate 64G physical address information, and 64G physical address information can represent a 256TB SSD. A mapping table entry with a width of 38 bit can indicate 128G physical address information, and 128G physical address information can identify a 512TB SSD. A mapping table entry with a width of 39 bit can indicate 256G physical address information, and 256G physical address information can identify a 1024TB SSD.

[0052] The value of m can be determined according to the capacity of the SSD. When the capacity of the SSD is greater than 8TB and less than or equal to 16TB, m takes the value of 1, that is, the width of the mapping table entry is 33 bit. When the capacity of the SSD is greater than 16TB and less than or equal to 32TB, m takes the value of 2, that is, the width of the mapping table entry is 34 bit. When the capacity of the SSD is greater than 32TB and less than or equal to 64TB, m takes the value of 3, that is, the width of the mapping table entry is 35 bit. When the capacity of the SSD is greater than 64TB and less than or equal to 128TB, m takes the value of 4, that is, the width of the mapping table entry is 36 bit. When the capacity of the SSD is greater than 128TB and less than or equal to 256TB, m takes the value of 5, that is, the width of the mapping table entry is 37 bit. When the capacity of the SSD is greater than 256TB and less than or equal to 512TB, m takes the value of 6, that is, the width of the mapping table entry is 38 bit. When the capacity of the SSD is greater than 512TB and less than or equal to 1024TB, m takes the value of 7, that is, the width of the mapping table entry is 39 bit.

[0053] The number of bits in the error correction space needs to ensure that the ECC of its corresponding multiple mapping table entries can be stored. In one ECC algorithm, data of 4 to 11 bits requires 5-bit ECC for protection, data of 12 to 26 bits requires 6-bit ECC for protection, data of 27 to 57 bits requires 7-bit ECC for protection, data of 58 to 120 bits requires 8-bit ECC for protection, data of 121 to 247 bits requires 9-bit ECC for protection, data of 248 to 502 bits requires 10-bit ECC for protection, data of 503 to 1013 bits requires 11-bit ECC for protection, data of 1014 to 2036 bits requires 12-bit ECC for protection, data of 2037 to 4083 bits requires 13-bit ECC for protection, and data of 4084 to 8178 bits requires 14-bit ECC for protection.

[0054] In the embodiment of the present application, the DDR20 includes 5 memory chips. The bit width of a single memory chip is 8 bits. The width of the mapping table entry can be 33 bits, 34 bits, 35 bits, 36 bits, 37 bits, 38 bits, and 39 bits. The capacities of the SSDs that can be identified are 16TB, 32TB, 64TB, 128TB, 256TB, 512TB, and 1024TB in sequence. That is, an SSD with a size of 1024TB can be identified by 5 memory chips, without adding extra memory chips on the basis of meeting the large-capacity SSD, avoiding the increase in the cost of the SSD due to the addition of memory chips.

[0055] The embodiment of the present application mainly focuses on the process of the storage control chip 10 reading and writing the DDR20, and the structure of the storage control chip 10 and the process of reading and writing the DDR20 will be described in detail later.

[0056] Storage control chip

[0057] Figure 2 is a schematic block diagram of a storage control chip according to an embodiment of the present application. As Figure 2As shown in the figure, the storage control chip 10 includes a processing unit 110 and an acceleration unit 120. The processing unit 110 can parse the read and write commands issued by the host 200, obtain the first logical address, generate a read request including the first logical address, and then send the read request to the acceleration unit 120. Among them, in the DDR 20, the first logical address points to the first mapping entry. After receiving the read request, the acceleration unit 120 reads the first mapping entry in the DDR 20 according to the first logical address included in the first mapping entry, obtains the first physical address information, reads the error correction space corresponding to the first mapping entry in the DDR 20, obtains the first ECC, and uses the first ECC to check the first physical address information. After the first physical address information passes the check, the first physical address information is sent to the processing unit 110, so that the processing unit 110 can perform read and write operations on the NAND flash 30 according to the first physical address information.

[0058] The host 200 performs read and write operations on the NAND flash 30 by issuing read and write commands to realize reading the data stored in the NAND flash 30 or storing data in the NAND flash 30. When reading and writing the NAND flash 30, it is necessary to determine the FPA to be read and written. However, the read and write commands issued by the host 200 include the LBA, and the NAND flash 30 cannot be correctly read and written directly according to the LBA. Therefore, it is necessary to first map the LBA to the corresponding FPA through L2P, and then read and write the NAND flash 30 according to the FPA.

[0059] After receiving the read and write commands issued by the host 200, the processing unit 110 parses the first logical address included in the read and write commands, generates a read request including the first logical address, and then sends the read request to the acceleration unit 120. After receiving the read request, the acceleration unit 120 reads the first mapping entry corresponding to the first logical address in the DDR 20 according to the first logical address included in the read request, obtains the first physical address information, reads the first ECC from the first error correction space corresponding to the first mapping entry, and after passing the check of the first physical address information according to the first ECC, sends the first physical address information to the processing unit 110, so that the processing unit 110 can perform read and write operations on the NAND flash 30 according to the first physical address information, that is, the processing unit 110 performs read and write operations on the NAND flash 30 according to the FPA.

[0060] In an embodiment of the present application, after the processing unit 110 receives a read / write command issued by the host 200, it sends the first logical address parsed from the read / write command to the acceleration unit 120. The acceleration unit 120 reads the corresponding first physical address information from the DDR 20 according to the first logical address, and reads the first ECC corresponding to the first physical address information from the DDR 20. After verifying that the first physical address information passes through the first ECC, the acceleration unit 120 sends the first physical address information to the processing unit 110, so that the processing unit 110 reads and writes the NAND flash memory 30 according to the first physical address information. Since multiple physical address information in the DDR 20 is protected by one ECC, the mapping table entry can have a larger bit width, so that the DDR 20 can identify a larger capacity SSD without increasing the capacity of the DDR 20. Therefore, when implementing a large-capacity SSD, it is possible to avoid an increase in the cost of the SSD due to an increase in the DDR capacity.

[0061] The processing unit 110 may construct a Flash Translation Layer (FTL). The FTL is a software intermediate layer or a combination of software and hardware. The FTL is the connection relationship between the storage medium (NAND flash memory) and the storage control chip 10. The acceleration unit 120 includes a DDR controller. The DDR controller communicates with the DDR 20 through the DDR port physical layer (PHY). The FTL is connected to the DDR controller through a bus.

[0062] After the read / write command issued by the host 200 is received by the FTL, the FTL can parse the first logical address included in the read / write command, and send a read request including the first logical address to the DDR controller. The DDR controller reads the first physical address information and the ECC from the DDR 20 according to the first logical address, and after verifying that the first physical address information passes through the ECC, the DDR controller sends the first physical address information to the FTL. After receiving the first physical address information sent by the DDR controller, the FTL reads and writes the NAND flash memory 30 based on the received first physical address information.

[0063] The acceleration unit 120 needs to verify the first physical address information through ECC, and also needs to generate ECC according to the physical address information stored in the mapping table entry. As a general component, the DDR controller itself has a general ECC algorithm for physical address information verification and ECC generation. Since in the embodiments of the present application, one physical address information does not correspond to one ECC, the DDR controller cannot complete the verification of physical address information and the generation of ECC. The acceleration unit 120 includes an ECC function module, which can replace the DDR controller to verify and generate ECC for the physical address information. The ECC function module is deployed between the FTL and the DDR controller, and bypasses the functions of the DDR controller for physical address information verification and ECC generation, so that the acceleration unit 120 can verify physical address information and generate ECC through the ECC function module, and at the same time, there is no need to re-design the DDR controller to achieve the IP (Intellectual Property) reuse of the DDR controller.

[0064] It should be noted that the acceleration unit 120 may also be located within the DDR controller, and the present application does not limit the attribution relationship between the acceleration unit 120 and the DDR controller.

[0065] The embodiments of the present application mainly focus on the process of the acceleration unit 120 reading and writing the DDR20, and the structure of the acceleration unit 120 and the process of reading and writing the DDR20 will be described in detail later.

[0066] Acceleration unit

[0067] Figure 3 is a schematic block diagram of an acceleration unit according to an embodiment of the present application. As Figure 3 shown, the acceleration unit 120 includes a receiving subunit 121, a reading subunit 122, a verifying subunit 123, and an output subunit 124.

[0068] The receiving subunit 121 can receive a read request for reading the first mapping table entry in the DDR20. Among them, the DDR20 includes multiple mapping table entries, and the mapping table entries are used to record the physical address information of the IUs in the NAND flash memory 30, and different mapping table entries are used to store the physical address information of different IUs.

[0069] The reading subunit 122 can read the first mapping table entry according to the read request to obtain the first physical address information, and read the first error correction space corresponding to the first mapping table entry in the DDR20 to obtain the first ECC. Among them, the DDR20 includes multiple error correction spaces, one error correction space corresponds to multiple mapping table entries, and the error correction space is used to store the ECC of the physical address information in the corresponding multiple mapping table entries.

[0070] The syndrome unit 123 can verify the first physical address information according to the first ECC and send the verification result to the output unit 124.

[0071] After the output unit 124 determines that the first physical address information passes the verification according to the verification result, the first physical address information is output.

[0072] The receiving unit 121 can receive the read request sent by the FTL. The read request includes a first logical address. The DDR 20 includes multiple mapping entries, and different mapping entries correspond to different logical addresses. After receiving the read request, the receiving unit 121 can determine the first mapping entry corresponding to the first logical address included in the read request.

[0073] Figure 4 is a schematic diagram of the DDR according to an embodiment of the present application. As Figure 4 shown, the DDR 20 includes 5 DRAMs, namely DRAM0 to DRAM4. x+0(a), x+1(b), x+2(c), x+3(d), x+4(e), x+5(f), x+6(g), x+7(h), and x+t are all logical addresses. The storage area corresponding to the logical address in the row direction is the mapping entry corresponding to the logical address. For example, the storage area storing L2P a[31:24], L2P a[23:16], L2P a[15:08], L2P a[07:00], and L2P a[y:32] is the mapping entry corresponding to the logical address x+0(a), and the storage area storing L2P e[31:24], L2P e[23:16], L2P e[15:08], L2P e[07:00], and L2P e[y:32] is the mapping entry corresponding to the logical address x+4(e).

[0074] The physical address information is stored in the mapping entry. The physical address information identifies the IU in the NAND flash 30. For example, L2P a[31:24], L2P a[23:16], L2P a[15:08], L2P a[07:00], and L2P a[y:32] stored in the mapping entry corresponding to the logical address x+0(a) is a physical address information, and this physical address information identifies an IU in the NAND flash 30. L2P e[31:24], L2P e[23:16], L2P e[15:08], L2P e[07:00], and L2P e[y:32] stored in the mapping entry corresponding to the logical address x+4(e) is a physical address information, and this physical address information identifies another IU in the NAND flash 30. The physical address information stored in different mapping entries identifies different IUs in the NAND flash 30.

[0075] When it is determined that the first mapping entry needs to be read, the reading subunit 122 reads the first physical address information from the first mapping entry. As Figure 4 shown, if the first mapping entry is the mapping entry corresponding to the logical address x + 4(e), the reading subunit 122 reads L2P e[31:24], L2P e[23:16], L2P e[15:08], L2P e[07:00], and L2P e[y:32] as the first physical address information.

[0076] DDR20 includes multiple error correction spaces. One error correction space corresponds to multiple mapping entries. Different error correction spaces correspond to different mapping entries. The error correction space stores the ECC of the physical address information in the corresponding multiple mapping entries. As Figure 4 shown, the mapping entries corresponding to the logical addresses x + 0(a), x + 1(b), x + 2(c), x + 3(d), x + 4(e), x + 5(f), x + 6(g), x + 7(h), and x + t correspond to the same error correction space ECC bits. The ECC of the physical address information in these 8 mapping entries is stored in the error correction space ECC bits. For example, when the mapping entry corresponding to the logical address x + 4(e) is the first mapping entry, the first ECC is read from the ECC bits. It should be understood that if the mapping entry corresponding to any one of the logical addresses x + 0(a), x + 1(b), x + 2(c), x + 3(d), x + 4(e), x + 5(f), x + 6(g), x + 7(h), and x + t is the first mapping entry, the reading subunit 122 reads the first ECC from the error correction space ECC bits.

[0077] The first ECC is used to protect multiple physical address information including the first physical address information in the first mapping entry. After the reading subunit 122 reads the first physical address information and the first ECC, the verification subunit 123 verifies the first physical address information according to the first ECC through a preset ECC algorithm to detect and correct the errors generated during the storage of the first physical address information. After the first physical address information passes the verification, the output subunit 124 sends the verified physical address information to the processing unit 110, so that the processing unit 110 reads and writes the NAND flash 30 according to the verified first physical address information.

[0078] It should be noted that the embodiments of the present application do not limit the ECC algorithm. The verification subunit 123 can verify the first physical address information through various suitable ECC algorithms.

[0079] In an embodiment of the present application, one mapping table entry in DDR20 corresponds to multiple error correction spaces, that is, multiple physical address information is protected by one ECC. Without increasing the capacity of DDR20, the storage space occupied by ECC can be reduced, so that DDR20 can store physical address information with a larger bit width. Increasing the bit width of the physical address information can make the physical address information identify a larger number of IUs, so that a larger capacity SSD can be realized without increasing the DDR capacity, making the large capacity SSD have a lower cost.

[0080] In a possible implementation manner, when the reading subunit 122 reads DDR20, it reads DDR20 in units of mapping blocks. DDR20 includes multiple mapping blocks, and a mapping block includes at least two mapping table entries and corresponding error correction spaces. Multiple mapping table entries corresponding to the same error correction space are located in the same mapping block. A mapping block may include one or more error correction spaces. Since one error correction space corresponds to multiple mapping table entries, a mapping block includes at least two mapping table entries.

[0081] Figure 5 and Figure 6 are schematic diagrams of two types of DDRs in an embodiment of the present application. As Figure 4 and Figure 5 shown, the mapping block includes 8 mapping table entries corresponding to logical addresses x+0(a), x+1(b), x+2(c), x+3(d), x+4(e), x+5(f), x+6(g), and x+7(h), and this mapping table entry includes that these 8 mapping table entries correspond to the same error correction space ECC bits. As Figure 6 shown, the mapping block includes 8 mapping table entries corresponding to logical addresses x+0(a), x+1(b), x+2(c), x+3(d), x+4(e), x+5(f), x+6(g), and x+7(h). The error correction space ECC ab corresponding to the two mapping table entries corresponding to logical addresses x+0(a) and x+1(b) is also located in this mapping block. The error correction space ECC cd corresponding to the two mapping table entries corresponding to logical addresses x+2(c) and x+3(d) is also located in this mapping block. The error correction space ECCef corresponding to the two mapping table entries corresponding to logical addresses x+4(e) and x+5(f) is also located in this mapping block. The error correction space ECC ef corresponding to the two mapping table entries corresponding to logical addresses x+4(e) and x+5(f) is also located in this mapping block. The error correction space ECC gh corresponding to the two mapping table entries corresponding to logical addresses x+6(g) and x+7(h) is also located in this mapping block.

[0082] As Figure 5As shown, the mapping block includes 8 mapping entries, and the width of each mapping entry is 38 bits. When the IU in the NAND flash 30 is 4 KiB, an SSD with a maximum capacity of 512 TB can be identified. The 8 mapping entries are uniformly protected by an ECC with a 16-bit width. To improve the read / write reliability of the DRAM, the size of the mapping block can be increased, that is, a single mapping block can contain more mapping entries. At this time, there will be a larger error correction space for data protection. Or the width of the mapping entry can be appropriately reduced to provide more ECC protection fields.

[0083] As Figure 6 shown, the mapping block includes 8 mapping entries, and the width of each mapping entry is 36 bits. When the IU in the NAND flash 30 is 4 KiB, an SSD with a maximum capacity of 128 TB can be identified. The 8 mapping entries are no longer uniformly protected by a single ECC, but two mapping entries correspond to one ECC for protection.

[0084] It should be noted that Figures 4 to 6 the mapping block shown is only an example. The mapping block can include any number of error correction spaces and corresponding mapping entries. For example, the number of error correction spaces included in the mapping block can be 1, 2, 3, 4, 8 or any other value.

[0085] When the read subunit 122 reads the first physical address information, it reads the first mapping block where the first mapping entry and the first error correction space are located, and obtains the physical address information stored in each mapping entry in the first mapping block, including the first physical address information stored in the first mapping entry, and obtains the ECC stored in each error correction space in the first mapping block, including the first ECC stored in the first error correction space.

[0086] In the embodiment of the present application, when reading the first physical address information and the first ECC, the read subunit 122 reads the mapping block where the first mapping entry and the first error correction space are located, and obtains the physical address information stored in each mapping entry in the mapping block, and the ECC stored in each error correction space in the mapping block, so that the first physical address information can be selected from the read physical address information, and the first ECC can be selected from the read ECCs. The read subunit 122 reads the DDR20 in units of mapping blocks, avoiding frequent reading of the DDR20 and improving the efficiency of reading the DDR20.

[0087] Figure 7 is a schematic block diagram of an acceleration unit according to another embodiment of the present application. As Figure 7As shown in the figure, on the basis of including a receiving subunit 121, a reading subunit 122, a verification subunit 123, and an output subunit 124, the acceleration unit 120 may further include a replacement subunit 125, an update subunit 126, and a writing subunit 127.

[0088] The receiving subunit 121 may receive a writing request for writing a second mapping entry in the DDR20. When the host 200 needs to update the L2P stored in the DDR20, the host 200 sends an update command to the processing unit 110. The update command includes the logical address corresponding to the physical address information to be updated. After receiving the update command, the processing unit 110 generates a writing request indicating the logical address and sends the generated writing request to the acceleration unit 120. The receiving subunit 121 in the acceleration unit 120 may receive the writing request.

[0089] After the receiving subunit 121 receives the writing request, it sends the writing request to the replacement subunit 125. The replacement subunit 125 may determine the second mapping entry for which the stored physical address information needs to be updated according to the writing request, and then read the second mapping block where the second mapping entry is located to obtain the first mapping block data, and replace the physical address information stored by the second mapping entry in the first mapping block data with the second physical address information carried in the writing request to obtain the second mapping block data.

[0090] The second mapping block not only includes the second mapping entry, but also at least includes other mapping entries corresponding to the same error correction space as the second mapping entry, and the second mapping block also at least includes the error correction space corresponding to the second mapping entry. Therefore, the first mapping block data not only includes the physical address information stored in the second mapping entry, but also at least includes the third ECC stored in the error correction space corresponding to the second mapping entry. The replacement subunit 125 replaces the physical address information stored by the second mapping entry in the first mapping block data with the second physical address information carried in the writing request and keeps other data in the first mapping block data unchanged to obtain the second mapping block data.

[0091] The verification subunit 123 may generate a second ECC according to the second physical address information and the physical address information stored by a third mapping entry in the second mapping block data through a preset ECC algorithm, where the third mapping entry is a mapping entry corresponding to the same error correction space as the second mapping entry. It should be understood that the third ECC in the second mapping block data is generated by the verification subunit 123 according to the physical address information stored by the second mapping entry in the first mapping block data and the physical address information stored by each third mapping entry corresponding to the same error correction space as the second mapping entry.

[0092] After the syndrome unit 123 generates the second ECC, the update unit 126 replaces the third ECC in the second mapped block data with the second ECC and keeps other data in the second mapped block data unchanged to obtain the third mapped block data.

[0093] After the update unit 126 obtains the third mapped block data, the write unit 127 writes the third mapped block data into the second mapped block to replace the first mapped block data previously stored in the second mapped block.

[0094] In the embodiment of the present application, when updating the L2P in the DDR20, after the receiving unit 121 receives a write request, the replacement unit 125 reads the mapped block where the second mapped table entry to be updated is located to obtain the first mapped block data, and replaces the physical address information stored by the second mapped table entry in the first mapped block data with the second physical address information to obtain the second mapped block data. The syndrome unit 123 can then generate the second ECC according to the second physical address information and the physical address information stored in each mapped table entry corresponding to the same error correction space as the second mapped table entry. The update unit 126 replaces the third ECC stored in the error correction space corresponding to the second mapped table entry in the second mapped block data with the second ECC to obtain the third mapped block data. Further, the write unit 127 replaces the original first mapped block data in the second mapped block with the third mapped block data, thereby realizing the update of the physical address information stored by the second mapped table entry and the ECC in the error correction space corresponding to the second mapped table entry. On the premise that one ECC corresponds to multiple physical address information, the reliability of the ECC to protect the physical address information is ensured.

[0095] In a possible implementation manner, the mapped block includes at least one error correction space and each mapped table entry corresponding to the included error correction space. The number of mapped table entries included in the mapped block can be determined based on the access efficiency of the DDR20 and the granularity of the ECC protection. If it is necessary to improve the access efficiency of the DDR20, the mapped block can include a larger number of mapped table entries. If it is necessary to improve the reliability of the ECC to protect the physical address information, the mapped block can include a smaller number of mapped table entries. Since different mapped table entries have the same data capacity, the data volume of the mapped block is positively correlated with the number of included mapped table entries.

[0096] In an example, the data volume of the mapped block is an integer multiple of the access granularity of the DDR20. For example, when the bit width of the DDR20 is 40bit, if the DDR20 is a fourth-generation double data rate synchronous dynamic random access memory (DDR4), the mapped block includes 8 mapped table entries (such as Figure 4 and Figure 5As shown, to match the DDR4 interface access burst size. If DDR20 is the fifth-generation double data rate synchronous dynamic random access memory (DDR5), the mapping block includes 16 mapping table entries to match the DDR5 interface access burst size.

[0097] In the embodiments of the present application, the data capacity of the mapping block is equal to an integer multiple of the access granularity of DDR20, so that when the reading subunit 122 reads the mapping block, the complete mapping block can be read by reading DDR20 one or more times, and the data read each time is the data in the same mapping block, ensuring the efficiency of reading DDR20.

[0098] In a possible implementation, DDR20 includes N memory dies. The mapping table entries are stored in the first memory die to the (N - 1)th memory die among the N memory dies, and the first m columns of the Nth memory die. The error correction space for storing ECC is located in the last n columns of the Nth memory die. The same mapping table entry is located in the same row of the memory die. Multiple mapping table entries corresponding to the same error correction space are aligned with the error correction space in the row direction of the memory die. Wherein, N is a positive integer greater than or equal to 3, and both m and n are positive integers, and m + n is equal to the bit width of the memory die.

[0099] The mapping block may include one or more error correction spaces, such as Figure 4 and Figure 5 As shown, the mapping block includes one error correction space and includes 8 mapping table entries corresponding to this error correction space. As Figure 6 shown, the mapping block includes 4 error correction spaces and includes 2 mapping table entries corresponding to each of these 4 error correction spaces.

[0100] In the embodiments of the present application, the first memory die to the (N - 1)th memory die, and the first m columns of the Nth memory die are divided into a physical address storage area. Each row of this physical address storage area serves as a mapping table entry. The last n columns of the Nth memory die are divided into an ECC storage area. Multiple adjacent rows of this ECC storage area serve as an error correction space. The error correction space is aligned with the multiple mapping table entries corresponding to it in the row direction. Thus, when obtaining physical address information by reading the mapping table entry, the ECC corresponding to the physical address information read can be obtained by reading the error correction space aligned with the mapping table entry, making it simpler and faster to read the ECC and improving the efficiency of reading and writing to the NAND flash memory.

[0101] In a possible implementation, DDR20 includes 5 memory dies, the bit width of the memory die is 8 bit, and the number of columns m for storing physical address information in the Nth memory die is greater than or equal to 1 and less than or equal to 7. Among them, the 5 memory dies included in DDR20 may be DRAM dies.

[0102] As Figure 4 shown, when designing a large-capacity SSD, the mapping table entry will exceed 4 bytes, and the upper limit of the width of the mapping table entry can reach 39 bits, that is Figure 4 in which the value range of y is [32, 38], and the value of y can be determined according to actual requirements. For example, the value of y is determined according to the capacity size that the system needs to support. For an SSD with a capacity not greater than 32 TB, the width of the mapping table entry is 34 bits, and at this time y is equal to 33. When the system needs a wider mapping table entry, the width of the mapping table entry can reach 39 bits, and at this time y is equal to 38.

[0103] The width of the mapping table entry can be flexibly defined according to requirements to meet the personalized needs of different users and improve the applicability of the acceleration unit. The SSD controller is designed according to a single partition, the controller solution is simple, and the resource consumption is small. Under a large-capacity SSD, reserved space (Over Provision, OP) can be increased, and the quality of service (Quality of Service, QoS) of the system can be improved. Among them, the reserved space is equal to the ratio of the difference between the total capacity of the SSD and the user-visible capacity to the user-visible capacity.

[0104] In the embodiment of the present application, DDR20 includes 5 memory particles, the bit width of a single memory particle is 8 bits, and the width of the mapping table entry can be 33 bits, 34 bits, 35 bits, 36 bits, 37 bits, 38 bits, and 39 bits. The capacities of the SSDs that can be identified are 16 TB, 32 TB, 64 TB, 128 TB, 256 TB, 512 TB, and 1024 TB in sequence. That is, an SSD with a size of 1024 TB can be identified by 5 memory particles, and no additional memory particles need to be added on the basis of meeting the large-capacity SSD, avoiding the increase in the cost of the SSD due to the addition of memory particles.

[0105] Physical address reading method

[0106] Figure 8 is the physical address reading method of an embodiment of the present application, and this physical address reading method can be executed by the acceleration unit 120 in any of the above quantities. As Figure 8 shown, this physical address reading method may include the following steps:

[0107] Step 801, receive a read request for reading the first mapping table entry in the double data rate synchronous dynamic random access memory.

[0108] The double data rate synchronous dynamic random access memory includes multiple mapping table entries for recording the physical address information of indirect cells in the NAND flash memory. Different mapping table entries are used to store the physical address information of different indirect cells.

[0109] Step 802: According to the read request, read the first mapping table entry to obtain the first physical address information, and read the first error correction space corresponding to the first mapping table entry in the double data rate synchronous dynamic random access memory to obtain the first error correction code.

[0110] The double data rate synchronous dynamic random access memory includes multiple error correction spaces. One error correction space corresponds to multiple mapping table entries, and the error correction space is used to store the error correction codes of the physical address information in the corresponding multiple mapping table entries.

[0111] Step 803: Verify the first physical address information according to the first error correction code.

[0112] Step 804: After the first physical address information passes the verification, output the first physical address information.

[0113] In the embodiment of the present application, one mapping table entry in the DDR20 corresponds to multiple error correction spaces, that is, multiple physical address information is protected by one ECC. Without increasing the capacity of the DDR20, the storage space occupied by the ECC can be reduced, so that the DDR20 can store physical address information with a larger bit width. The increase in the bit width of the physical address information can enable the physical address information to identify a larger number of IUs, so that a larger-capacity SSD can be realized without increasing the DDR capacity, making the large-capacity SSD have a lower cost.

[0114] Since the process of reading the physical address information from the DDR has been described in detail in the above embodiments of the storage control chip and the acceleration unit in conjunction with the structural schematic diagrams, the specific process can be referred to the descriptions in the above embodiments of the storage control chip and the acceleration unit, and will not be elaborated here.

[0115] Commercial value of the embodiments of the present application

[0116] In the embodiment of the present application, one mapping table entry corresponds to multiple error correction spaces. Without using system solutions such as multi-partitioning or large IUs and with a certain number of mapping table entries, without increasing the cost of the DDR, managing the mapping table entries in the form of mapping blocks increases the width of the mapping table entries, thereby realizing a large-capacity SSD. When a single mapping table entry identifies a 4KiB physical space, an SSD with a capacity of up to 1024TB can be supported, so that a large-capacity SSD can be realized without increasing the DDR cost, making the large-capacity SSD have a lower cost and improving the competitiveness of storage control chip products and solid-state drive products.

[0117] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data that have been authorized by the user or fully authorized by all parties. Moreover, the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entrances are provided for the user to choose to authorize or reject.

[0118] It should be understood that the various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, reference can be made to each other. The embodiments mainly illustrate the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and reference can be made to the relevant parts of other embodiments for the relevant content.

[0119] It should be understood that the specific embodiments of this specification have been described above. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0120] It should be understood that an element described herein in the singular form or shown as only one in the drawings does not represent limiting the quantity of the element to one. In addition, a module or element described or shown herein as separate may be combined into a single module or element, and a module or element described or shown herein as a single one may be split into multiple modules or elements.

[0121] It should also be understood that the terms and expressions used herein are only for description, and one or more embodiments of this specification should not be limited to these terms and expressions. Using these terms and expressions does not mean excluding any equivalent features of the illustration and description (or parts thereof). It should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Correspondingly, the claims should be regarded as covering all such equivalents.

Claims

1. An acceleration unit is applied to a storage control chip in a solid-state drive. The acceleration unit includes: A receiving subunit, configured to receive a read request for reading a first mapping entry in a double data rate synchronous dynamic random access memory. The double data rate synchronous dynamic random access memory includes a plurality of mapping entries, and the mapping entries are used to record physical address information of indirect cells in a NAND flash memory. Different mapping entries are used to store physical address information of different indirect cells; A reading subunit, configured to read the first mapping entry according to the read request to obtain first physical address information, and read a first error correction space corresponding to the first mapping entry in the double data rate synchronous dynamic random access memory to obtain a first error correction code. The double data rate synchronous dynamic random access memory includes a plurality of error correction spaces, one error correction space corresponds to a plurality of mapping entries, and the error correction space is used to store error correction codes of physical address information in the corresponding plurality of mapping entries; A verification subunit, configured to verify the first physical address information according to the first error correction code; An output subunit, configured to output the first physical address information after the first physical address information passes the verification.

2. The acceleration unit according to claim 1, wherein The reading subunit is configured to read a first mapping block where the first mapping entry and the first error correction space are located according to the read request, obtain physical address information stored in the mapping entries in the first mapping block, and obtain error correction codes stored in the error correction space in the first mapping block. The double data rate synchronous dynamic random access memory includes a plurality of mapping blocks, and each mapping block includes at least two mapping entries and a corresponding error correction space. The plurality of mapping entries corresponding to the same error correction space are located in the same mapping block.

3. The acceleration unit according to claim 2, wherein the acceleration unit further comprises: A replacement subunit, an update subunit, and a write subunit; The receiving subunit is configured to receive a write request for writing a second mapping entry in the double data rate synchronous dynamic random access memory; The replacement subunit is configured to read a second mapping block where the second mapping entry is located according to the write request to obtain first mapping block data, replace the physical address information stored by the second mapping entry in the first mapping block data with second physical address information carried by the write request to obtain second mapping block data; The verification subunit is configured to generate a second error correction code according to the physical address information stored by a third mapping entry in the second mapping block data and the second physical address information, wherein the third mapping entry corresponds to the same error correction space as the second mapping entry; The update subunit is configured to replace the third error correction code in the second mapping block data with the second error correction code to obtain third mapping block data, wherein the error correction space storing the third error correction code is the error correction space corresponding to the second mapping entry; The write subunit is configured to write the third mapping block data into the second mapping block to replace the first mapping block data stored in the second mapping block.

4. The acceleration unit according to claim 2 or 3, wherein, The data capacity of the mapping block is equal to an integer multiple of the access granularity of the double data rate synchronous dynamic random access memory.

5. The acceleration unit according to claim 1, wherein, The double data rate synchronous dynamic random access memory includes N memory dies. The multiple mapping entries are located in the first memory die to the (N - 1)th memory die among the N memory dies, and the first m columns of the Nth memory die. The multiple error correction spaces corresponding to the multiple mapping entries are located in the last n columns of the Nth memory die. The same mapping entry is located in the same row of the N memory dies. The multiple mapping entries corresponding to the same error correction space are aligned with the error correction space in the row direction of the memory die. N is a positive integer greater than or equal to 3, and both n and m are positive integers, and m + n is equal to the bit width of the memory die.

6. The acceleration unit according to claim 5, wherein, The double data rate synchronous dynamic random access memory includes 5 memory dies, the bit width of the memory die is 8 bit, and 1 ≤ m ≤ 7.

7. A storage control chip, comprising: A processing unit and an acceleration unit as described in any one of claims 1-6; The processing unit is configured to parse a read / write command issued by a host to obtain a first logical address, generate a read request including the first logical address, and send the read request to the acceleration unit. The first logical address points to the first mapping entry. The acceleration unit is configured to, after the first physical address information passes the verification, send the first physical address information to the processing unit, so that the processing unit performs read / write operations on the NAND flash according to the first physical address information.

8. A solid state drive, comprising: A storage control chip, a double data rate synchronous dynamic random access memory, and a NAND flash as described in any one of claims 1-6.

9. The solid state drive according to claim 8, wherein, The double data rate synchronous dynamic random access memory includes N memory dies. The multiple mapping entries are located in the first memory die to the (N - 1)th memory die among the N memory dies, and the first m columns of the Nth memory die. The multiple error correction spaces corresponding to the multiple mapping entries are located in the last n columns of the Nth memory die. The same mapping entry is located in the same row of the N memory dies. The multiple mapping entries corresponding to the same error correction space are aligned with the error correction space in the row direction of the memory die. N is a positive integer greater than or equal to 3, and both m and n are positive integers, and m + n is equal to the bit width of the memory die.

10. The solid state drive according to claim 9, wherein, The double data rate synchronous dynamic random access memory includes 5 memory dies, the bit width of the memory die is 8 bit, and 1 ≤ m ≤ 7.

11. A physical address reading method applied to an acceleration unit in a storage control chip. The method includes: Receiving a read request for reading a first mapping entry in a double data rate synchronous dynamic random access memory. The double data rate synchronous dynamic random access memory includes multiple mapping entries, and the mapping entries are used to record physical address information of indirect units in the NAND flash. Different mapping entries are used to store physical address information of different indirect units. According to the read request, read the first mapping table entry to obtain first physical address information, and read a first error correction space corresponding to the first mapping table entry in the double data rate synchronous dynamic random access memory, where the double data rate synchronous dynamic random access memory includes a plurality of error correction spaces, one error correction space corresponds to a plurality of mapping table entries, and the error correction space is used to store error correction codes of physical address information in the corresponding plurality of mapping table entries; Verify the first physical address information according to the first error correction code; After the verification of the first physical address information passes, output the first physical address information.

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