Relay control circuit and control method

Abstract

The invention provides a relay control circuit and a control method. The circuit comprises a driving switch circuit and a peak absorption and follow current circuit. The driving switch circuit is connected with the peak absorption and follow current circuit and a target relay. The peak absorption and follow current circuit is connected with the target relay; the driving switch circuit is used for switching on or switching off an MOS transistor in the driving switch circuit in response to a received logic level signal, so that a contact of a target relay is closed or switched off, or the average voltage of the target relay is reduced to be smaller than or equal to a preset maintaining voltage in a pulse maintaining mode; and the peak absorption and follow current circuit is used for discharging the peak voltage of the target relay in response to the turn-off of the target relay, and carrying out follow current on the inductive current of the target relay. Through the circuit, the effects of reducing the use cost and the circuit complexity are realized, the loss and the temperature of the relay are reduced, and the working efficiency and the stability of the relay are further improved.

Description

Technical Field

[0001] This application relates to the fields of circuits and power electronics technologies, and particularly to a relay control circuit and a control method thereof. Background Art

[0002] When a relay is in the process of pulling in and maintaining voltage reduction, a power resistor is usually connected in series with the relay coil. The relay coil is maintained at a reduced voltage by means of voltage division by the power resistor, so as to reduce the coil loss of the relay, and further achieve the effects of reducing the power consumption and temperature of the relay.

[0003] In the method of reducing the holding voltage of the relay by voltage division of the power resistor, since the power resistor itself also has losses and there will be heat generation of the resistor, the overall heat generation of the application product where the relay is located does not decrease, reducing the working efficiency of the relay and increasing the use cost of the relay; in addition, when controlling the pulling in and maintaining voltage reduction of the relay, an external single-chip microcomputer is required to control the relay, increasing the redundancy complexity and instability of the relay. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a relay control circuit and a control method. Based on the received logic level signal, the driving switch circuit conducts or disconnects the MOS transistor in the driving switch circuit, so that the contacts of the target relay are pulled in or turned off, and the target relay is maintained at a reduced voltage by means of pulse maintenance. When the target relay is turned off, the spike absorption and freewheeling circuit discharges the spike voltage generated by the target relay and freewheels the inductive current of the target relay to protect the relay control circuit and the target relay, achieving the effects of reducing the use cost and circuit complexity, reducing the loss and temperature of the relay, and further improving the working efficiency and stability of the relay.

[0005] Based on the above purpose, in the first aspect of this application, a relay control circuit is provided. The circuit includes a driving switch circuit and a spike absorption and freewheeling circuit:

[0006] The driving switch circuit is respectively connected to the spike absorption and freewheeling circuit and the target relay; the spike absorption and freewheeling circuit is connected to the target relay;

[0007] The driving switch circuit is used to conduct or disconnect the MOS transistor in the driving switch circuit in response to receiving a logic high level signal or a logic low level signal, so that the contacts of the target relay are pulled in or turned off; in response to receiving a logic alternating level signal, the average voltage of the target relay is reduced to be less than or equal to a preset holding voltage by means of pulse maintenance;

[0008] The spike absorption and freewheeling circuit is configured to discharge the spike voltage generated by the turning-off of the target relay and freewheel the inductive current of the target relay in response to the turning-off of the target relay, so as to protect the relay control circuit and the target relay.

[0009] Further, the relay control circuit further includes a filter capacitor:

[0010] The filter capacitor is respectively connected to the drive switch circuit, the spike absorption and freewheeling circuit, and the target relay;

[0011] The filter capacitor is configured to discharge the charge input to the filter capacitor to the target relay in response to a change in the voltage of the target relay, and regulate the external positive power supply of the spike absorption and freewheeling circuit.

[0012] Further, the drive switch circuit includes a MOS transistor, a second resistor, and a third resistor:

[0013] The first end of the third resistor is connected to the logic level signal input terminal; the second end of the third resistor and the first end of the second resistor are respectively connected to the gate of the MOS transistor; the second end of the second resistor and the source of the MOS transistor are respectively connected to the spike absorption and freewheeling circuit and grounded; the drain of the MOS transistor is respectively connected to the spike absorption and freewheeling circuit and the target relay;

[0014] The MOS transistor is configured to turn on or off the source and drain in the MOS transistor in response to receiving a logic high level signal or a logic low level signal, so as to make the contact of the target relay close or open; in response to receiving a logic alternating level signal, by means of pulse maintenance, the average voltage of the target relay is reduced to be less than or equal to a preset maintenance voltage;

[0015] The third resistor is configured to receive the logic high level signal sent by the logic level signal input terminal, so that the current in the relay control circuit flows to the gate of the MOS transistor and the second resistor respectively, to charge the gate capacitance of the MOS transistor;

[0016] The second resistor is configured to flow the current flowing through the third resistor to the source of the MOS transistor to charge the gate capacitance.

[0017] Further, when the gate voltage of the MOS transistor is greater than or equal to a preset turn-on voltage, the MOS transistor is turned on to close the contacts of the target relay; when the gate voltage of the MOS transistor is less than or equal to a preset turn-off voltage, the MOS transistor is turned off to turn off the contacts of the target relay; when the gate voltage of the MOS transistor is less than the preset turn-on voltage and greater than the preset turn-off voltage, the MOS transistor performs pulse maintenance on the target relay.

[0018] Further, the third resistor is also used to limit the current of the MOS transistor; the second resistor is also used to divide the voltage of the MOS transistor and provide a discharge path for the gate capacitance of the MOS transistor.

[0019] Further, the second resistor is also used to ensure that when the target relay is turned off, the input of the gate of the MOS transistor is a logic low-level signal output by the logic level signal input terminal, so as to improve the reliability of the MOS transistor.

[0020] Further, the spike absorption and freewheeling circuit includes a first resistor, a diode and a first capacitor:

[0021] The first end of the first capacitor and the first end of the diode are respectively connected to the drive switch circuit and the second end of the target relay; the first end of the first resistor is connected to the second end of the diode; the second end of the first capacitor and the second end of the first resistor are respectively connected to the drive switch circuit and the first end of the target relay; the second end of the first capacitor and the second end of the first resistor are respectively connected to an external positive power supply.

[0022] Further, the first resistor and the first capacitor are used to form an RC buffer to absorb the energy of the spike voltage generated by the turn-off of the target relay and smooth the voltage fluctuation of the target relay.

[0023] Further, the diode is used to provide a freewheeling path for the target relay by forward biasing when the power supply of the target relay is cut off and the inductor of the target relay tries to continue to flow current, so that the inductor current of the target relay circulates back to the power supply of the target relay and protects the relay control circuit.

[0024] In a second aspect of the present application, a relay control method is provided, and the method includes:

[0025] In response to the drive switch circuit receiving a logic high-level signal, the MOS transistor in the drive switch circuit is turned on to make the contacts of the target relay attract;

[0026] In response to the drive switch circuit receiving a logic alternating level signal, the average voltage of the target relay is reduced to be less than or equal to a preset holding voltage by means of pulse maintenance;

[0027] In response to the drive switch circuit receiving a logic low level signal, the MOS transistor in the drive switch circuit is turned off to turn off the contacts of the target relay;

[0028] In response to the target relay being turned off, the spike absorption and freewheeling circuit discharges the spike voltage generated by the turning off of the target relay and freewheels the inductive current of the target relay to protect the relay control circuit and the target relay.

[0029] As can be seen from the above, the relay control circuit and control method provided by the embodiments of the present application, through the drive switch circuit based on the received logic level signal, turns on or off the MOS transistor in the drive switch circuit to make the contacts of the target relay attract or turn off, and makes the target relay be in a step-down holding state by means of pulse maintenance. When the target relay is turned off, through the spike absorption and freewheeling circuit, the spike voltage generated by the target relay is discharged and the inductive current of the target relay is freewheeled to protect the relay control circuit and the target relay.

[0030] Compared with the prior art method of connecting a power resistor in series with the coil of the relay, reducing the voltage of the relay coil by means of power resistor voltage division and externally connecting a single-chip microcomputer to control the relay, the effects of reducing the usage cost and circuit complexity are achieved, the loss and temperature of the relay are reduced, and thus the working efficiency and stability of the relay are improved.

[0031] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1 Shows one of the schematic structural diagrams of an exemplary relay control circuit according to an embodiment of the present application;

[0034] Figure 2Shows the second schematic diagram of the structure of an exemplary relay control circuit according to an embodiment of the present application;

[0035] Figure 3 Shows the third schematic diagram of the structure of an exemplary relay control circuit according to an embodiment of the present application;

[0036] Figure 4 Shows the schematic diagram of the logic level signal of an exemplary target relay according to an embodiment of the present application;

[0037] Figure 5 Shows the flowchart of an exemplary relay control method according to an embodiment of the present application. Detailed implementation manners

[0038] To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0039] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meanings understood by those of ordinary skill in the art to which the present application belongs. The "first", "second", and similar terms used in the embodiments of the present application do not indicate any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0040] After research, it is found that currently, when a relay is in the process of pulling in and voltage-reducing maintenance, a power resistor is usually connected in series with the relay coil, and the relay coil is voltage-reduced and maintained by the voltage-dividing method of the power resistor to reduce the coil loss of the relay, thereby achieving the effects of reducing the power consumption and temperature of the relay.

[0041] Among them, in the method of reducing the holding voltage of the relay by voltage division of the power resistor, since the power resistor itself also has losses and there will be a situation of resistance heating, the overall heat generation of the application product where the relay is located does not decrease, the working efficiency of the relay is reduced, and the use cost of the relay is increased.

[0042] In the existing control circuit for the pulling-in and step-down maintenance of a relay, to perform step-down maintenance on the relay coil, devices such as a power resistor, a transistor, and a driver need to be added, increasing the application cost and being unfavorable for the large-scale application of the relay.

[0043] In addition, when controlling the pulling-in and step-down maintenance of the relay, an external microcontroller needs to be connected to control the relay, increasing the redundancy complexity and instability of the relay.

[0044] Based on this, the embodiment of the present application provides a relay control circuit. By driving the switch circuit to conduct or disconnect the MOS transistor in the driving switch circuit based on the received logic level signal, the contact of the target relay is pulled in or turned off, and the target relay is maintained in a step-down state through a pulse maintenance method. When the target relay is turned off, the spike absorption and freewheeling circuit is used to discharge the spike voltage generated by the target relay and freewheel the inductor current of the target relay to protect the relay control circuit and the target relay, achieving the effects of reducing the usage cost and circuit complexity, reducing the loss and temperature of the relay, and further improving the working efficiency and stability of the relay.

[0045] Figure 1 FIG. 10 shows one of the schematic structural diagrams of an exemplary relay control circuit according to an embodiment of the present application.

[0046] As Figure 1 shown in FIG. 15, the relay control circuit 10 provided by the embodiment of the present application can be applied to any device or system using a relay. The relay control circuit 10 may include a driving switch circuit 110 and a spike absorption and freewheeling circuit 120.

[0047] The driving switch circuit 110 is respectively connected to the spike absorption and freewheeling circuit 120 and the target relay 20; the spike absorption and freewheeling circuit 120 is connected to the target relay 20.

[0048] In the embodiment of the present application, the target relay 20 is an electrical control device. The target relay 20 uses a smaller current to control a larger current or circuit. In essence, it is a switch driven by an electromagnet and can achieve remote control, automated operation, and isolation between circuits.

[0049] The target relay 20 includes a coil, an armature, a contact K1, and a spring; among them, the coil generates a magnetic field when current passes through; the armature is the part attracted or repelled by the magnetic field generated by the coil; the contact K1 is open when the coil is not powered on and closed when the coil is powered on; the spring is used to restore the contact to the original position when no current flows through the coil.

[0050] Specifically, when an appropriate voltage is applied to the coil of the target relay 20, a current is generated in the coil, and thus a magnetic field is formed. This magnetic field attracts the armature, causing mechanical movement and changing the state of the contact K1; once the voltage on the coil is removed, the action of the spring causes the armature to return to its initial position, thereby returning the contact K1 to the default open state.

[0051] Figure 2 FIG. 4 shows a second schematic structural diagram of an exemplary relay control circuit according to an embodiment of the present application.

[0052] As Figure 2 shown in FIG. 5, the relay control circuit 10 further includes a filter capacitor C2.

[0053] The filter capacitor C2 is respectively connected to the drive switch circuit 110, the spike absorption and freewheeling circuit 120, and the target relay 20.

[0054] Among them, the filter capacitor C2 is used to discharge the charge input to the filter capacitor C2 to the target relay 20 in response to a change in the voltage of the target relay 20, and to stabilize the external positive power supply of the spike absorption and freewheeling circuit 120.

[0055] Here, the filter capacitor C2 is connected in parallel with the external positive power supply, which can filter out high-frequency noise on the power line of the external positive power supply, ensuring the stability of the source voltage of the MOS transistor in the drive switch circuit 110. This voltage stabilizing effect helps to reduce voltage fluctuations on the power line and improve the overall stability of the circuit.

[0056] Specifically, when the MOS transistor in the drive switch circuit 110 is turned off, the charge on the drain of the MOS transistor and the charge on the target relay 20 will be quickly discharged to a fixed level through the filter capacitor C2, which helps to quickly discharge the high spike voltage generated by the self-inductance of the relay coil when the relay is turned off, enabling the MOS transistor to enter the cut-off state faster; during the switching process of the MOS transistor, the transient current on the power line will also be absorbed by the filter capacitor C2, preventing voltage spikes from affecting other circuit components.

[0057] Further, as Figure 1 shown in FIG. 6, the drive switch circuit 110 is configured to turn on or off the MOS transistor in the drive switch circuit 110 in response to receiving a logic high level signal or a logic low level signal, so as to make the contact of the target relay 20 attract or turn off; in response to receiving a logic alternating level signal, by means of pulse maintenance, the average voltage of the target relay 20 is reduced to be less than or equal to a preset maintenance voltage.

[0058] Figure 3FIG. 3 shows a schematic diagram of an exemplary relay control circuit according to an embodiment of the present application.

[0059] As Figure 3 shown in FIG. 3, the drive switch circuit 110 includes a MOS transistor Q1, a second resistor R2, and a third resistor R3.

[0060] The first end of the third resistor R3 is connected to the logic level signal input terminal RLY_CONT; the second end of the third resistor R3 and the first end of the second resistor R2 are respectively connected to the gate G of the MOS transistor Q1; the second end of the second resistor R2 and the source S of the MOS transistor Q1 are respectively connected to the spike absorption and freewheeling circuit 120 and grounded; the drain D of the MOS transistor Q1 is respectively connected to the spike absorption and freewheeling circuit 120 and the target relay 20.

[0061] Further, the second end of the second resistor R2 and the source of the MOS transistor Q1 are respectively connected to the filter capacitor C2 and grounded.

[0062] Wherein, the MOS transistor Q1 is configured to turn on or off the source S and the drain D in the MOS transistor Q1 in response to receiving a logic high level signal or a logic low level signal, so that the contact K1 of the target relay 20 is attracted or turned off; in response to receiving a logic alternating level signal, by means of pulse maintenance, the average voltage of the target relay 20 is reduced to be less than or equal to a preset maintenance voltage.

[0063] In an embodiment of the present application, the MOS transistor Q1 is an N-channel metal oxide semiconductor field effect transistor (N-channel MOSFET, N-MOS), and the MOS transistor Q1 is composed of three main terminals: the gate (Gate, G) is used for receiving the input of the control signal; the source (Source, S) refers to the end where the current flows out; the drain (Drain, D) refers to the end where the current flows in.

[0064] Wherein, when a positive voltage of a logic level signal that appears as a positive voltage is applied to the gate G of the MOS transistor Q1 relative to the source S, and this positive voltage exceeds a preset turn-on voltage, a conductive N-type channel (i.e., an inversion layer) will be formed on the P-type substrate under the gate G, and this channel connects the two N-type regions between the source S and the drain D, allowing current to flow from the drain D to the source S; if the positive voltage is less than or equal to the preset turn-on voltage, there is not enough charge to form a conductive channel, and at this time, the MOS transistor Q1 is in the off state and no current flows through.

[0065] Here, the preset turn-on voltage can be specifically calibrated according to the performance parameters and factory setting parameters of the MOS transistor Q1; the preset holding voltage can be specifically calibrated according to the performance parameters and factory setting parameters of the target relay 20.

[0066] Further, the MOS transistor includes a gate capacitance GS.

[0067] When the voltage of the gate capacitance GS is greater than or equal to the preset turn-on voltage, the MOS transistor Q1 is turned on to close the contact K1 of the target relay 20; when the voltage of the gate capacitance GS is less than or equal to the preset turn-off voltage, the MOS transistor Q1 is turned off to turn off the contact K1 of the target relay 20; when the voltage of the gate capacitance GS is less than the preset turn-on voltage and greater than the preset turn-off voltage, the MOS transistor Q1 performs pulse holding on the target relay 20.

[0068] Among them, when the signal at the logic level signal input terminal RLY_CONT is a logic high level signal, the gate voltage of the MOS transistor Q1 is greater than or equal to the preset turn-on voltage; when the signal at the logic level signal input terminal RLY_CONT is a logic low level signal, the gate voltage of the MOS transistor Q1 is less than or equal to the preset turn-off voltage; when the signal at the logic level signal input terminal RLY_CONT is a logic alternating level signal, the voltage of the gate of the MOS transistor Q1 is less than the preset turn-on voltage and greater than the preset turn-off voltage.

[0069] Specifically, when the signal at the logic level signal input terminal RLY_CONT is a logic high level signal, current flows through the third resistor R3 and the second resistor R2 to charge the gate capacitance GS of the MOS transistor Q1; when the gate voltage of the MOS transistor Q1 reaches the turn-on voltage, the MOS transistor Q1 is turned on, and the coil of the target relay 20 forms a closed-loop circuit, and an induced current is generated in the coil of the target relay 20, and the magnetic field generated by the induced current closes the contact K1.

[0070] Figure 4 Shows a schematic diagram of the logic level signal of an exemplary target relay according to an embodiment of the present application.

[0071] As Figure 4 shown, when the target relay 20 is in the state where the contact K1 is attracted (OPEN), the signal at the logic level signal input terminal RLY_CONT is a logic high level signal (1); when the target relay 20 is in the step-down holding (HOLD) state, the signal at the logic level signal input terminal RLY_CONT is a logic alternating level signal; when the target relay 20 is in the state where the contact K1 is turned off (CLOSE), the signal at the logic level signal input terminal RLY_CONT is a logic low level signal (0).

[0072] In the embodiment of the present application, it takes 10 ms for the contact K1 of the target relay 20 to complete half of the suction, and the duration of the closure of the contact K1 of the target relay 20 will be specifically set according to the actual performance parameters and working requirements of the target relay 20. For example, the duration of the closure of the contact K1 of the target relay 20 is generally set within the range of 1 - 2 s.

[0073] Here, after the duration of the closure of the contact K1 of the target relay 20 reaches the set time, the signal at the logic level signal input terminal RLY_CONT is a logic alternating level signal, so that the gate voltage of the MOS transistor Q1 is less than the preset turn-on voltage and greater than the preset turn-off voltage. By means of pulse maintenance, the average voltage across the coil of the target relay 20 is reduced to less than or equal to the preset maintenance voltage, so as to reduce the loss and temperature of the coil of the target relay 20 and improve the working efficiency of the target relay 20.

[0074] Specifically, performing pulse maintenance on the target relay 20 can ensure that the target relay 20 is in a step-down maintenance state, that is, triggering the action of the target relay 20 through a short pulse signal to keep the target relay 20 in a working state. This method can be used in application scenarios where it is necessary to keep the target relay 20 in a working state for a long time but without expecting continuous high power consumption.

[0075] Further, as Figure 3 shown in, the third resistor R3 is used to receive the logic high level signal sent by the logic level signal input terminal RLY_CONT, so that the current in the relay control circuit 10 flows to the gate G of the MOS transistor Q1 and the second resistor R2 respectively to charge the gate capacitance GS of the MOS transistor Q1.

[0076] Among them, the third resistor R3 is also used to limit the current of the MOS transistor Q1.

[0077] Further, as Figure 3 shown in, the second resistor R2 is used to flow the current flowing through the third resistor R3 to the source S of the MOS transistor Q1 to charge the gate capacitance GS.

[0078] Among them, the second resistor R2 is also used to divide the voltage of the MOS transistor Q1 and provide a discharge loop for the gate capacitance GS of the MOS transistor Q1.

[0079] The second resistor R2 is further configured to ensure that when the target relay 20 is turned off, the input of the gate G of the MOS transistor Q1 is the logic low-level signal output by the logic level signal input terminal RLY_CONT, so as to improve the reliability of the MOS transistor Q1.

[0080] Further, as Figure 3 shown in

[0081] The first end of the first capacitor C1 and the first end of the diode D1 are respectively connected to the driving switch circuit 110 and the second end of the target relay 20; the first end of the first resistor R1 is connected to the second end of the diode D1; the second end of the first capacitor C1 and the second end of the first resistor R1 are respectively connected to the driving switch circuit 110 and the first end of the target relay 20; the second end of the first capacitor C1 and the second end of the first resistor R1 are respectively connected to the external positive power supply VCC+ (12V).

[0082] Further, the second end of the first capacitor C1 and the second end of the first resistor R1 are respectively connected to the second end of the filter capacitor C2.

[0083] Wherein, the first resistor R1 and the first capacitor C1 are used to form an RC buffer to absorb the energy of the spike voltage generated by the turning-off of the target relay 20 and smooth the voltage fluctuation of the target relay 20.

[0084] The diode D1 is configured to provide a freewheeling path for the target relay 20 by forward biasing when the power supply POWER_IN / POWER_OUT of the target relay 20 is cut off and the inductor of the target relay 20 attempts to continue to flow current, so that the inductor current of the target relay 20 circulates back to the power supply POWER_IN / POWER_OUT of the target relay 20 and protects the relay control circuit 10.

[0085] The relay control circuit provided by the embodiment of the present application turns on or off the MOS transistor in the driving switch circuit based on the received logic level signal through the driving switch circuit, so that the contact of the target relay is attracted or turned off, and the target relay is in the step-down maintenance state through the pulse maintenance method. When the target relay is turned off, the spike absorption and freewheeling circuit is used to discharge the spike voltage generated by the target relay and freewheel the inductor current of the target relay, so as to protect the relay control circuit and the target relay, achieving the effects of reducing the use cost and circuit complexity, reducing the loss and temperature of the relay, and further improving the working efficiency and stability of the relay.

[0086] Based on the same inventive concept, corresponding to the circuits of any of the above embodiments, the present application further provides a relay control method 500.

[0087] Figure 5 Shows a flowchart of an exemplary relay control method according to an embodiment of the present application.

[0088] As Figure 5 shown, for the relay control method provided by the embodiment of the present application, the method may be executed by a relay control circuit 10 (for example, Figure 1 the relay control circuit 10 in

[0089] In step S501, in response to the drive switch circuit receiving a logic high level signal, turn on the MOS transistor in the drive switch circuit to cause the contacts of the target relay to close.

[0090] In step S502, in response to the drive switch circuit receiving a logic alternating level signal, by means of pulse maintenance, reduce the average voltage of the target relay to be less than or equal to a preset maintenance voltage.

[0091] In step S503, in response to the drive switch circuit receiving a logic low level signal, turn off the MOS transistor in the drive switch circuit to cause the contacts of the target relay to open.

[0092] In step S504, in response to the target relay being turned off, the spike absorption and freewheeling circuit discharges the spike voltage generated by the turn-off of the target relay and freewheels the inductor current of the target relay to protect the relay control circuit and the target relay.

[0093] For the relay control method provided by the embodiment of the present application, by the drive switch circuit based on the received logic level signal, turn on or off the MOS transistor in the drive switch circuit to cause the contacts of the target relay to close or open, and by means of pulse maintenance, make the target relay in a step-down maintenance state. When the target relay is turned off, through the spike absorption and freewheeling circuit, discharge the spike voltage generated by the target relay and freewheel the inductor current of the target relay to protect the relay control circuit and the target relay, achieving the effects of reducing the usage cost and circuit complexity, reducing the loss and temperature of the relay, and further improving the working efficiency and stability of the relay.

[0094] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the above embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0095] The methods of the above embodiments are used to implement the corresponding circuits in any of the foregoing embodiments and have the beneficial effects of the corresponding circuit embodiments, which will not be elaborated herein.

[0096] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; within the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0097] In addition, for the sake of simplicity of description and discussion, and so as not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Further, the devices may be shown in block diagram form so as not to make the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In cases where specific details (such as circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application may be implemented without these specific details or with variations of these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0098] Although the present application has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0099] Embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A relay control circuit, characterized in that, The circuit includes a driving switch circuit and a spike absorption and freewheeling circuit: The driving switch circuit is respectively connected to the spike absorption and freewheeling circuit and the target relay; the spike absorption and freewheeling circuit is connected to the target relay; The driving switch circuit is configured to turn on or off the MOS transistor in the driving switch circuit in response to receiving a logic high level signal or a logic low level signal, so as to make the contacts of the target relay close or open; In response to receiving a logic alternating level signal, by means of pulse maintenance, the average voltage of the target relay is reduced to be less than or equal to a preset maintenance voltage; The spike absorption and freewheeling circuit is configured to discharge the spike voltage generated by the turn-off of the target relay and freewheel the inductor current of the target relay in response to the turn-off of the target relay, so as to protect the relay control circuit and the target relay.

2. The circuit according to claim 1, wherein The relay control circuit further includes a filter capacitor: The filter capacitor is respectively connected to the driving switch circuit, the spike absorption and freewheeling circuit and the target relay; The filter capacitor is configured to discharge the charge input to the filter capacitor to the target relay in response to a change in the voltage of the target relay, and regulate the external positive power supply of the spike absorption and freewheeling circuit.

3. The circuit according to claim 1, wherein The driving switch circuit includes a MOS transistor, a second resistor and a third resistor: The first end of the third resistor is connected to the logic level signal input terminal; the second end of the third resistor and the first end of the second resistor are respectively connected to the gate of the MOS transistor; the second end of the second resistor and the source of the MOS transistor are respectively connected to the spike absorption and freewheeling circuit and grounded; the drain of the MOS transistor is respectively connected to the spike absorption and freewheeling circuit and the target relay; The MOS transistor is configured to turn on or off the source and drain in the MOS transistor in response to receiving a logic high level signal or a logic low level signal, so as to make the contacts of the target relay close or open; In response to receiving a logic alternating level signal, by means of pulse maintenance, the average voltage of the target relay is reduced to be less than or equal to a preset maintenance voltage; The third resistor is configured to receive the logic high level signal sent by the logic level signal input terminal, so that the current in the relay control circuit flows to the gate of the MOS transistor and the second resistor respectively, to charge the gate capacitance of the MOS transistor; The second resistor is configured to flow the current flowing through the third resistor to the source of the MOS transistor to charge the gate capacitance.

4. The circuit according to claim 3, wherein When the gate voltage of the MOS transistor is greater than or equal to a preset turn-on voltage, the MOS transistor is turned on to make the contacts of the target relay close; when the gate voltage of the MOS transistor is less than or equal to a preset turn-off voltage, the MOS transistor is turned off to make the contacts of the target relay open; When the gate voltage of the MOS transistor is less than the preset turn-on voltage and greater than the preset turn-off voltage, the MOS transistor performs pulse maintenance on the target relay.

5. The circuit according to claim 3, wherein The third resistor is further configured to limit the current of the MOS transistor; the second resistor is further configured to divide the voltage of the MOS transistor and provide a discharge path for the gate capacitance of the MOS transistor.

6. The circuit according to claim 3, wherein The second resistor is further configured to ensure that when the target relay is turned off, the input of the gate of the MOS transistor is a logic low-level signal output by the logic level signal input terminal, so as to improve the reliability of the MOS transistor.

7. The circuit according to claim 1, characterized in that, The spike absorption and flyback circuit includes a first resistor, a diode, and a first capacitor: The first end of the first capacitor and the first end of the diode are respectively connected to the drive switch circuit and the second end of the target relay; the first end of the first resistor is connected to the second end of the diode; the second end of the first capacitor and the second end of the first resistor are respectively connected to the drive switch circuit and the first end of the target relay; the second end of the first capacitor and the second end of the first resistor are respectively connected to an external positive power supply.

8. The circuit according to claim 7, wherein The first resistor and the first capacitor are used to form an RC buffer to absorb the energy of the spike voltage generated by the turn-off of the target relay and smooth the voltage fluctuation of the target relay.

9. The circuit according to claim 7, wherein The diode is configured to provide a flyback path for the target relay through forward biasing when the power supply of the target relay is cut off and the inductor of the target relay attempts to continue to conduct current, so that the inductor current of the target relay circulates back to the power supply of the target relay and protects the relay control circuit.

10. A relay control method, characterized in that, The method includes: In response to the drive switch circuit receiving a logic high-level signal, turning on the MOS transistor in the drive switch circuit to make the contacts of the target relay close; In response to the drive switch circuit receiving a logic alternating level signal, by means of pulse maintenance, reducing the average voltage of the target relay to be less than or equal to a preset maintenance voltage; In response to the drive switch circuit receiving a logic low-level signal, turning off the MOS transistor in the drive switch circuit to make the contacts of the target relay open; In response to the target relay being turned off, the spike absorption and flyback circuit discharges the spike voltage generated by the turn-off of the target relay and continues to conduct the inductor current of the target relay to protect the relay control circuit and the target relay.

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